A shift register, a driving circuit, a display panel, and a display device.
By setting a sustaining unit in the shift register, the output fluctuation problem was solved, the stability of the signal output was achieved, and the display effect was ensured.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- WUHAN TIANMA MICRO ELECTRONICS CO LTD
- Filing Date
- 2024-01-23
- Publication Date
- 2026-05-26
Smart Images
Figure CN118053370B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of display technology, and more particularly to a shift register, a driving circuit, a display panel, and a display device. Background Technology
[0002] With the development of display technology, high-resolution, narrow-bezel display panels have become one of the mainstream development trends in the display field, leading to the emergence of gate driver on array (GOA) circuits. GOA circuits refer to circuits that directly integrate the gate driver circuit of the display panel into the non-display area of the array substrate. They can replace external driver chips on the array substrate and have advantages such as low cost, fewer processes, and high production capacity. In existing gate driver circuits, the output of the shift register can fluctuate, affecting the display effect. Summary of the Invention
[0003] This invention provides a shift register, a driving circuit, a display panel, and a display device to solve the technical problem that fluctuations in the output of the shift register affect the display effect.
[0004] In a first aspect, embodiments of the present invention provide a shift register, which includes a first input unit, a second input unit, a first output unit, a second output unit, and a sustaining unit;
[0005] The first input unit is coupled to the first node and is used to write signals to the first node; the control terminal of the first output unit is coupled to the first node, the first terminal of the first output unit receives the first voltage signal, and the second terminal of the first output unit is coupled to the signal output terminal.
[0006] The second input unit is coupled to the second node and is used to write signals to the second node; the control terminal of the second output unit is coupled to the second node, the first terminal of the second output unit receives the first clock signal, and the second terminal of the second output unit is coupled to the signal output terminal.
[0007] The output of the sustaining unit is coupled to the second node, and the sustaining unit is used to maintain the potential of the second node at least during the period when the first output unit is off and the second output unit is on.
[0008] Secondly, based on the same inventive concept, embodiments of the present invention also provide a driving circuit, including a shift register provided in any embodiment of the present application, wherein multiple shift registers are cascaded.
[0009] Thirdly, based on the same inventive concept, embodiments of the present invention also provide a display panel, including the driving circuit provided in any embodiment of this application.
[0010] Fourthly, based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any embodiment of this application.
[0011] The shift register, driving circuit, display panel, and display device provided in this invention have the following beneficial effects: A sustaining unit is provided in the shift register, and the output terminal of the sustaining unit is coupled to the second node. The sustaining unit can write signals to the second node at least during the period when the first output unit is off and the second output unit is on. By directly writing signals to the second node, the potential fluctuations of the second node are smoothed out, thereby maintaining the potential stability of the second node and ensuring that the potential of the second node is maintained during the period when the enable signal is output at the signal output terminal, thus ensuring the output state of the signal output terminal. When applied to a display panel, it can prevent display abnormalities. Attached Figure Description
[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0013] Figure 1 This is a schematic diagram of a shift register in related technologies;
[0014] Figure 2 This is a schematic diagram of another shift register in related technologies;
[0015] Figure 3 for Figure 2 A timing diagram of a shift register is provided;
[0016] Figure 4 A schematic diagram of a shift register provided in an embodiment of the present invention;
[0017] Figure 5 This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0018] Figure 6 for Figure 5 An example timing diagram of a shift register provided in the embodiment;
[0019] Figure 7 This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0020] Figure 8 This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0021] Figure 9This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0022] Figure 10 This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0023] Figure 11 This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0024] Figure 12 Another timing diagram of the shift register provided in an embodiment of the present invention;
[0025] Figure 13 This is a schematic diagram of another shift register provided in an embodiment of the present invention;
[0026] Figure 14 A schematic diagram of a driving circuit provided in an embodiment of the present invention;
[0027] Figure 15 A schematic diagram of a display panel provided in an embodiment of the present invention;
[0028] Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0030] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.
[0031] It should be understood that although the terms "first" and "second" may be used to describe XX in the embodiments of the present invention, these XX should not be limited to these terms. These terms are only used to distinguish XX from each other. For example, without departing from the scope of the embodiments of the present invention, the first XX may also be referred to as the second XX, and similarly, the second XX may also be referred to as the first XX.
[0032] Figure 1 This is a schematic diagram of a shift register in related technologies, such as... Figure 1As shown, the shift register includes a first input unit 01, a second input unit 02, a first output unit 03, and a second output unit 04. The first input unit 01 is used to write signals to the first node N1'; the control terminal of the first output unit 03 is coupled to the first node N1', the first terminal of the first output unit 03 receives a first voltage signal V1', and the second terminal of the first output unit 03 is coupled to the signal output terminal out'; the second input unit 02 is used to write signals to the second node N2'; the control terminal of the second output unit 04 is coupled to the second node N2', the first terminal of the second output unit 04 receives a first clock signal CK', and the second terminal of the second output unit 04 is coupled to the signal output terminal out'. The first output unit 03 includes a first output transistor TFT1' and a first capacitor C1', and the second output unit 04 includes a second output transistor TFT2' and a second capacitor C2'. For example, when the first node N1' is at a low potential, the first output transistor TFT1' is turned on; when the second node N2' is at a low potential, the second output transistor TFT2' is turned on. Since the first clock signal CK′ is a signal that frequently switches between high and low levels, the potential of the second node N2′ will fluctuate due to the parasitic capacitance of the second output transistor TFT2′, which in turn affects the output of the signal output terminal out′.
[0033] In another related technology, Figure 2 This is a schematic diagram of another shift register in related technologies. Figure 3 for Figure 2 A timing diagram for a shift register is provided. For example... Figure 2 As shown, the shift register also includes a voltage regulator unit 05, which is coupled to the second node N2'. The voltage regulator unit 05 is used to maintain the potential of the second node N2'. The voltage regulator unit 05 includes a first transistor 051 and a second transistor 052. The control terminal of the first transistor 051 is coupled to the first node N1', receiving a first voltage signal V1', and its second terminal is connected to the third node N3'. The control terminal of the second transistor 052 receives a first clock signal CK', with its first terminal connected to the third node N3' and its second terminal connected to the second node N2'. (Combined...) Figure 3During the period when the first node N1′ is low and the first clock signal CK′ is low, such as during period t2′, both the first transistor 051 and the second transistor 052 are turned on, writing the high level of the first voltage signal V1′ to the second node N2′, maintaining the high level of the second node N2′, causing the second output transistor TFT2′ to turn off, and keeping the signal output terminal out′ outputting a high level. During the period when the first clock signal CK′ is high, such as during period t3′, the second transistor 052 is turned off, locking the high potential of the second node N2′, so that the second node N2′ maintains a high level. When the first node N1′ is high, the third node N3′ is locked. When the first clock signal CK′ is low, the high level of the floating state of the third node N3′ will affect the second node N2′. For example, during period t1′, that is, when the signal output terminal out′ outputs a low level, the low potential of the second node N2′ will fluctuate, thus affecting the output. The low level output by the signal output terminal out′ serves as the enable signal for the transistor it controls. Furthermore, in this scheme, the control terminal of the second transistor 052 receives the first clock signal CK′. The first clock signal CK′ is a signal that frequently switches between high and low levels. The potential of the second node N2′ will also fluctuate due to the parasitic capacitance of the second transistor 052. The potential fluctuation of the second node N2′ will affect the working state of the second output transistor TFT2′, thereby affecting the output state of the signal output terminal out′. After setting the voltage regulation unit 05 in the shift register, the effect of maintaining the low potential of the second node N2′ is poor during the period when the second output transistor TFT2′ is turned on and the first output transistor TFT1′ is turned off (time period t1′).
[0034] To address the problems existing in the related technologies, this application provides a shift register with a sustaining unit. During the period when the first output unit is off and the second output unit is on, the shift register outputs an enable signal at its signal output terminal. The sustaining unit can maintain the potential of the second node at least during the period when the enable signal is output at the signal output terminal, thus ensuring the output state of the signal output terminal.
[0035] Figure 4 A schematic diagram of a shift register provided for an embodiment of the present invention, as shown below. Figure 4As shown, the shift register includes a first input unit 10, a second input unit 20, a first output unit 30, a second output unit 40, and a sustaining unit 50. The first input unit 10 is coupled to a first node N1 and is used to write signals to the first node N1. The control terminal of the first output unit 30 is coupled to the first node N1, the first terminal of the first output unit 30 receives a first voltage signal V1, and the second terminal of the first output unit 30 is coupled to a signal output terminal out. The second input unit 20 is coupled to a second node N2 and is used to write signals to the second node N2. The control terminal of the second output unit 40 is coupled to the second node N2, the first terminal of the second output unit 40 receives a first clock signal CK, and the second terminal of the second output unit 40 is coupled to a signal output terminal out. The output terminal of the sustaining unit 50 is coupled to the second node N2, and the sustaining unit 50 is used to maintain the potential of the second node N2 at least during the period when the first output unit 30 is off and the second output unit 40 is on.
[0036] Optional, such as Figure 4 As shown, the first output unit 30 includes a first output transistor T1 and a first capacitor C1, and the second output unit 40 includes a second output transistor T2 and a second capacitor C2. Figure 4 Taking a scenario where both the first output transistor T1 and the second output transistor T2 are p-type transistors as an example. The potential of the first node N1 controls the first output transistor T1 to turn on, providing a high level of the first voltage signal V1 to the signal output terminal out. The potential of the second node N2 controls the second output transistor T2 to turn on, providing a level of the first clock signal CK to the signal output terminal out. During the period when the first output unit 30 is off and the second output unit 40 is on, the signal output terminal out outputs a low level provided by the first clock signal CK, acting as an enable signal to control the transistor coupled to the signal output terminal out to turn on. That is, during the period when the first output unit 30 is off and the second output unit 40 is on, the potential stability of the second node N2 is crucial.
[0037] The shift register provided in this embodiment of the invention includes a sustaining unit 50. The output of the sustaining unit 50 is coupled to the second node N2. The sustaining unit 50 can write signals to the second node N2 at least during the period when the first output unit 30 is off and the second output unit 40 is on. During this period, the potential fluctuation of the second node N2 can be smoothed out by directly writing signals to the second node N2, thereby maintaining the potential stability of the second node N2 and ensuring that the potential of the second node N2 is maintained during the period when the signal output terminal out outputs an enable signal, thus ensuring the output state of the signal output terminal out. When applied to a display panel, this can prevent display abnormalities.
[0038] In some implementations... Figure 5This is a schematic diagram of another shift register provided in an embodiment of the present invention. Figure 6 for Figure 5 An example timing diagram of a shift register provided in the embodiment. For example... Figure 5 As shown, the sustaining unit 50 includes a first transistor M1 and a first sub-unit 51. The control terminal of the first transistor M1 receives a first clock signal CK. The first terminal of the first transistor M1 and the output terminal of the first sub-unit 51 are coupled to the third node N3, and the second terminal of the first transistor M1 is coupled to the second node N2. During the period when the first output unit 30 is off and the second output unit 40 is on: the first sub-unit 51 inputs a second voltage signal V2 to the third node N3. When the first transistor M1 is on, it writes the second voltage signal V2 to the second node N2 to maintain the potential of the second node N2. In this embodiment, during the period when the signal output terminal out needs to output an enable signal, the first sub-unit 51 in the sustaining unit 50 directly writes the second voltage signal V2 to the second node N2. The second voltage signal V2 can smooth out the potential fluctuation of the second node N2, thereby stabilizing the potential of the second node N2 and ensuring the on state of the second output unit 40, thus ensuring the output of the signal output terminal out. By directly writing the voltage signal to the second node N2, the influence of the first clock signal CK signal jump on the second node N2 can be reduced.
[0039] Taking a first voltage signal V1 as a high-level signal and a second voltage signal V2 as a low-level signal as an example. Combined with... Figure 6 During time period t2, the first node N1 is at a high level, controlling the first output transistor T1 to turn off, and the second node N2 is at a low level, controlling the second output transistor T2 to turn on. That is, time period t2 is the period when the first output unit 30 is off and the second output unit 40 is on. During time period t2, the first sub-unit 51 inputs the second voltage signal V2 to the third node N3. The first transistor M1 turns on under the control of the low level of the first clock signal CK, writing the second voltage signal V2 into the second node N2. By writing a low level into the second node N2, the low potential of the second node N2 is maintained, thus effectively maintaining the low potential of the second node N2.
[0040] In some implementations... Figure 7 Another schematic diagram of a shift register provided in an embodiment of the present invention is shown below. Figure 7 As shown, the control terminal of the first subunit 51 is coupled to the control terminal of the first output unit 30. Figure 7 The diagram illustrates the coupling of the control terminal of the first subunit 51 to the first node N1. The first terminal of the first subunit 51 receives the second voltage signal V2, and the second terminal of the first subunit 51 is coupled to the third node N3. (Combined with...) Figure 6From the timing diagram, during time period t2, the first node N1 is at a low level, controlling the first sub-unit 51 to turn on and write the low level of the second voltage signal V2 to the third node N3. The first transistor M1, under the control of the low level of the first clock signal CK, turns on and writes a low level to the second node N2. This effectively maintains the low potential of the second node N2, ensuring the on-state of the second output unit 40, and thus ensuring the output of the signal output terminal out. Furthermore, in this embodiment, using the potential of the first node N1 to control the first sub-unit 51 avoids the use of the clock signal, preventing the voltage jumps of the clock signal from affecting the potential of the third node N3. This is more beneficial for the stability of the third node N3 potential, and thus improves the overall circuit output stability.
[0041] like Figure 7 As shown, the first sub-unit 51 includes a second transistor M2. The control terminal of the second transistor M2 is coupled to the control terminal of the first output unit 30. The first terminal of the second transistor M2 receives a second voltage signal V2, and the second terminal of the second transistor M2 is coupled to a third node N3. The first sub-unit 51 includes a single transistor, has a simple structure, and in application, the second transistor M2 can reuse the manufacturing process of transistors in the display panel.
[0042] In one embodiment, the second transistor M2 is an n-type transistor, and the other transistors in the shift register are p-type transistors. Combined with... Figure 6 From a timing perspective, during period t2, the first node N1 is at a high level, and the first clock signal CK is at a low level. Under the control of the potential of the first node N1, the second transistor M2 turns on and writes the low level of the second voltage signal V2 to the third node N3. Under the control of the first clock signal CK, the first transistor M1 turns on and writes the low level to the second node N2. This achieves the stabilization of the potential of the second node N2 by writing signals to it. The potential fluctuations of the second node N2 can be smoothed out by the written signals, thus effectively maintaining the low potential of the second node N2. Furthermore, during period t1, the first clock signal CK is at a high level, so the first transistor M1 is off, and the third node N3 is locked, meaning the third node N3 will not affect the potential of the second node N2. And in periods after t2, the first node N1 is at a low level, so the second transistor M2 is off, and the second transistor M2 will not write signals to the third node N3 to affect the high potential state of the second node N2.
[0043] In some implementations... Figure 8 Another schematic diagram of a shift register provided in an embodiment of the present invention is shown below. Figure 8 As shown, the control terminal of the first subunit 51 is coupled to the control terminal of the second output unit 40. Figure 8The diagram illustrates the coupling of the control terminal of the first subunit 51 to the second node N2. The first terminal of the first subunit 51 receives the second voltage signal V2, and the second terminal of the first subunit 51 is coupled to the third node N3. (Combined...) Figure 6 From the timing diagram, during time period t2, the second node N2 is at a low level, controlling the first sub-unit 51 to turn on and write the low level of the second voltage signal V2 to the third node N3. The first transistor M1, under the control of the low level of the first clock signal CK, turns on and writes a low level to the second node N2. This effectively maintains the low potential of the second node N2, ensuring the on-state of the second output unit 40, and thus ensuring the output of the signal output terminal out. Furthermore, in this embodiment, using the potential of the second node N2 to control the first sub-unit 51 avoids the use of the clock signal, preventing the voltage jumps of the clock signal from affecting the potential of the third node N3. This is more beneficial for the stability of the third node N3 potential, and thus improves the overall circuit output stability.
[0044] like Figure 8 As shown, the first subunit 51 includes a second transistor M2. The control terminal of the second transistor M2 is coupled to the control terminal of the second output unit 40. The first terminal of the second transistor M2 receives a second voltage signal V2, and the second terminal of the second transistor M2 is coupled to a third node N3. The first subunit 51 includes a single transistor, has a simple structure, and in application, the second transistor M2 can reuse the manufacturing process of transistors in the display panel.
[0045] In one embodiment, the second transistor M2 and the other transistors in the shift register are all p-type transistors. Figure 6 From a timing perspective, during period t2, the second node N2 is at a low level, and the first clock signal CK is also at a low level. Under the control of the potential of the second node N2, the second transistor M2 turns on and writes the low level of the second voltage signal V2 to the third node N3. Under the control of the first clock signal CK, the first transistor M1 turns on and writes the low level to the second node N2. This achieves the stabilization of the potential of the second node N2 by writing a signal to it. The potential fluctuations of the second node N2 are smoothed out by the written signal, effectively maintaining the low potential of the second node N2. Furthermore, during period t1, the first clock signal CK is at a high level, so the first transistor M1 is off, and the third node N3 is locked, meaning the third node N3 does not affect the potential of the second node N2. And in periods after t2, when the second node N2 is at a high level, the second transistor M2 is off, and it will not write a signal to the third node N3 to affect the high potential state of the second node N2.
[0046] In some implementations... Figure 9 Another schematic diagram of a shift register provided in an embodiment of the present invention is shown below. Figure 9 As shown, the shift register includes a third transistor M3. The first terminal of the third transistor M3 is coupled to the second node N2, and the second terminal of the third transistor M3 is coupled to the control terminal of the second output unit 40. The control terminal of the third transistor M3 receives a second voltage signal V2. The second voltage signal V2 controls the third transistor M3 to be normally open. The second input unit 20 writes a signal to the second node N2, and then writes the signal down to the fourth node N4 via the third transistor M3. Therefore, there is a voltage difference between the second node N2 and the fourth node N4. In addition, since the control terminal of the second output transistor T2 is electrically connected to the fourth node N4, when the first clock signal CK transitions from high to low, the potential of the fourth node N4 will be coupled low. When the third transistor M3 is normally open, the fourth node N4 will leak current to the second node N2, and the potential of the fourth node N4 is lower than the potential of the second node N2.
[0047] Figure 9 The diagram illustrates the electrical connection between the maintenance unit 50 and the second node N2, and the second output unit 40 is coupled to the second node N2 through the third transistor M3.
[0048] In this embodiment of the invention, the control terminal of the second transistor M2 in the first subunit 51 is coupled to the control terminal of the second output unit 40. This coupling can be either with the second node N2 or with the fourth node N4. Since the potential of the fourth node N4 is lower than that of the second node N2, coupling the control terminal of the second transistor M2 to the fourth node N4 ensures that the on-state of the second transistor M2 is sufficiently large during time period t2, allowing the second transistor M2 to effectively write the low-level signal to the third node N3.
[0049] Figure 9 The diagram only illustrates the coupling between the control terminal of the second transistor M2 in the first subunit 51 and the control terminal of the second output unit 40. Figure 7 In the embodiment where the control terminal of the first subunit 51 is coupled to the control terminal of the first output unit 30, the same approach of setting the third transistor M3 is also applicable.
[0050] In some implementations... Figure 10 Another schematic diagram of a shift register provided in an embodiment of the present invention is shown below. Figure 10As shown, the maintenance unit 50 is also used to maintain the potential of the second node N2 during the period when the first output unit 30 is on and the second output unit 40 is off; the maintenance unit 50 also includes a second sub-unit 52, the output terminal of which is coupled to the third node N3. During the period when the first output unit 30 is on and the second output unit 40 is off: the second sub-unit 52 inputs a first voltage signal V1 to the third node N3, and when the first transistor M1 is on, it writes the first voltage signal V1 into the second node N2 to maintain the potential of the second node N2.
[0051] Wherein, the first voltage signal V1 is a high-level signal, and the second voltage signal V2 is a low-level signal, meaning the voltage value of the first voltage signal V1 is greater than the voltage value of the second voltage signal V2. The first node N1 is at a low potential to control the first output unit 30 to turn on, and the second node N2 is at a low potential to control the second output unit 40 to turn on. Combined with... Figure 6 As can be seen, during period t4, the first output unit 30 is turned on and the second output unit 40 is turned off. Period t4 is after period t2, that is, after the enable signal is output from the signal output terminal OUT. During period t4, the low potential of the first node N1 controls the second sub-unit 52 to turn on, writing the high level of the first voltage signal V1 to the third node N3. The low level of the first clock signal CK controls the first transistor M1 to turn on, writing the high level signal to the second node N2. When the second node N2 is at a high potential, the first sub-unit 51 is in a turned-off state. In period t5, which follows period t4, the first clock signal CK is at a high potential, so the first transistor M1 is in a turned-off state, and the potential of the third node N3 is locked. The frequent high and low level transitions of the first clock signal CK mean that periods t4 and t5 will alternate after period t2. Since a high level signal can be written to the second node N2 during period t4, the fluctuations in the potential of the second node N2 caused by the voltage transitions of the first clock signal CK will be improved, thus maintaining the high potential state of the second node N2 well.
[0052] In this embodiment, the maintenance unit 50 includes a first transistor M1, a first sub-unit 51, and a second sub-unit 52. During time period t1, the first input unit 10 is turned on, the first node N1 is written with a low level, the second input unit 20 is turned on, and the second node N2 is written with a low level. During time period t1, the first clock signal CK is high, controlling the first transistor M1 to turn off, thus locking the third node N3, which does not affect the potential of the second node N2. During time period t2, the first sub-unit 51 is off, the second sub-unit 52 is turned on, and the low level of the second voltage signal V2 is written to the third node N3. The first transistor M1 is turned on under the control of the first clock signal CK, and the low level is written to the second node N2. The low level of the second node N2 is maintained by directly writing a signal to the second node N2. During time period t3 after time period t2, the first input unit 10 is turned on, the first node N1 is written with a low level, the second input unit 20 is turned on, and the second node N2 is written with a high level. During time period t4, the low potential of the first node N1 controls the second sub-unit 52 to turn on, writing the high level of the first voltage signal V1 to the third node N3. The first clock signal CK controls the first transistor M1 to turn on, writing the high-level signal to the second node N2. During time period t5, the first clock signal CK is at a high potential, so the first transistor M1 is off, and the potential of the third node N3 is locked. The high and low levels of the first clock signal CK frequently change, alternating between time periods t4 and t5. Because a high-level signal can be written to the second node N2 during time period t4, the fluctuations in the potential of the second node N2 caused by the voltage changes of the first clock signal CK are mitigated, thus effectively maintaining the high potential state of the second node N2. This implementation not only effectively maintains the high potential of the second node N2 but also effectively maintains its low potential, making the second node N2 unaffected by the high-frequency changes of the clock signal, more effectively maintaining the stability of the second node N2, thereby ensuring stable output at the signal output terminal and guaranteeing display performance in applications.
[0053] Figure 10 The first subunit 51 is illustrated by including a second transistor M2, the control terminal of which is coupled to the control terminal of the second output unit 40. In a scheme where the maintenance unit 50 includes a second subunit 52, the control terminal of the first subunit 51 in the maintenance unit 50 can also be coupled to the control terminal of the first output unit 30 (e.g., ...). Figure 7 (Example), which will not be illustrated in the accompanying drawings.
[0054] like Figure 10 As shown, the second sub-unit 52 includes a fourth transistor M4. The control terminal of the fourth transistor M4 is coupled to the first node N1, the first terminal of the fourth transistor M4 receives a first voltage signal V1, and the second terminal of the fourth transistor M4 is coupled to the third node N3. (Combined with...) Figure 6During time period t4, the fourth transistor M4 is turned on under the potential control of the first node N1 to write the high level of the first voltage signal V1 to the third node N3. At the same time, the first transistor M1 is turned on under the control of the first clock signal CK to write the high level to the second node N2, so as to maintain the high level state of the second node N2.
[0055] In some implementations... Figure 11 Another schematic diagram of a shift register provided in an embodiment of the present invention is shown below. Figure 11 As shown, the first input unit 10 includes a fifth transistor M5 and a sixth transistor M6; the control terminal of the fifth transistor M5 is coupled to the second node N2, the first terminal of the fifth transistor M5 receives the second clock signal XCK, and the second terminal of the fifth transistor M5 is coupled to the first node N1; the control terminal of the sixth transistor M6 receives the second clock signal XCK, the first terminal of the sixth transistor M6 receives the second voltage signal V2, and the second terminal of the sixth transistor M6 is coupled to the first node N1.
[0056] like Figure 11 As shown, the second input unit 20 includes a seventh transistor M7; the control terminal of the seventh transistor M7 receives a second clock signal XCK, the first terminal of the seventh transistor M7 is coupled to the signal input terminal IN, and the second terminal of the seventh transistor M7 is coupled to the second node N2. In some embodiments, the seventh transistor M7 can be a dual-gate transistor.
[0057] Figure 12 Another timing diagram of the shift register provided in an embodiment of the present invention. Figure 12 Timing diagrams are applicable Figure 11 The shift register provided in the embodiment. Combined with... Figure 11 and Figure 12 Let's take a look at how the shift register works.
[0058] During time period t11, the first clock signal CK is high, and the second clock signal XCK is low. The second clock signal XCK controls the sixth transistor M6 in the first input unit 10 to turn on, writing the low level of the second voltage signal V2 to the first node N1. The second clock signal XCK also controls the seventh transistor M7 in the second input unit 20 to turn on, writing the low level of the signal input terminal IN to the second node N2. The third transistor M3 is normally open under the control of the second voltage signal V2, and the fourth node N4 is written with a low potential. The fourth node N4 controls the second output transistor T2 in the second output unit 40 to turn on, providing a high-level signal to the signal output terminal out. Simultaneously, the second node N2 controls the fifth transistor M5 in the first input unit 10 to turn on, writing the low level of the second clock signal XCK to the first node N1. The first node N1 is at a low potential, controlling the first output transistor T1 in the first output unit 30 to turn on, providing the high level of the first voltage signal V1 to the signal output terminal out. During time period t11, the signal output terminal out outputs a high-level signal. Additionally, during time period t11, the low potential of the first node N1 controls the fourth transistor M4 in the second sub-unit 52 to turn on and write the high level of the first voltage signal V1 to the third node N3. However, since the first clock signal CK is at a high level, the first transistor M1 in the maintenance unit 50 is in a closed state, and the potential of the third node N3 is locked. Therefore, the maintenance unit 50 has no effect on the potential of the second node N2.
[0059] During time period t12, the first clock signal CK is low and the second clock signal XCK is high. The second clock signal XCK controls the sixth transistor M6 in the first input unit 10 and the seventh transistor M7 in the second input unit 20 to turn off. The second node N2 maintains a low potential, so the fourth node N4 also maintains a low potential, and the fourth node N4 controls the second output unit 40 to be on. The low potential of the second node N2 controls the fifth transistor M5 in the first input unit 10 to turn on, writing the high level of the second clock signal XCK to the first node N1, making the first node N1 high. The high potential of the first node N1 controls the first output unit 30 to turn off. During this time period, the first output unit 30 is off and the second output unit 30 is on, and the signal output terminal OUT outputs the low level of the first clock signal CK. Simultaneously, during this time period, the first clock signal CK transitions from high to low, and due to coupling, pulls the potential of the fourth node N4 low. Figure 12 As can be seen, the potential of the fourth node N4 during the t12 period is lower than that of the second node N2.
[0060] Additionally, during time period t12, the high potential of the first node N1 controls the fourth transistor M4 in the second sub-unit 52 to turn off, and the low potential of the fourth node N4 controls the second transistor M2 in the first sub-unit 51 to turn on, writing the low level of the second voltage signal V2 to the third node N3. During this period, the third node N3 is not in a floating state, but changes from a high level to a low level after the signal is written. Simultaneously, the first transistor M1 turns on under the control of the first clock signal CK, writing the low level of the third node N3 to the second node N2. This achieves the stabilization of the potential of the second node N2 by writing a signal to it. The potential fluctuations of the second node N2 can be smoothed out by the written signal, effectively maintaining the low potential of the second node N2, and thus also maintaining the potential of the fourth node N4, ensuring the on state of the second output unit 40 and ensuring stable output at the signal output terminal out.
[0061] During time period t13, the first clock signal CK is high and the second clock signal XCK is low. The second clock signal XCK controls the sixth transistor M6 in the first input unit 10 to turn on, writing the low level of the second voltage signal V2 to the first node N1. The first node N1 controls the first output unit 30 to turn on. The second clock signal XCK controls the seventh transistor M7 in the second input unit 20 to turn on, writing the high level of the signal input terminal IN to the second node N2. The third transistor M3, normally open, writes a high potential to the fourth node N4. The fourth node N4 controls the second output unit 40 to turn off. During this time period, the first output unit 30 is on and the second output unit 40 is off, and the signal output terminal out outputs the high level of the first voltage signal V1. During this time period, the second sub-unit 52 in the sustaining unit 50 writes a high-level signal to the third node N3, and the first transistor M1 is in the off state.
[0062] During time period t14, the first clock signal CK is low and the second clock signal XCK is high. The second clock signal XCK controls the sixth transistor M6 in the first input unit 10 and the seventh transistor M7 in the second input unit 20 to turn off. The second node N2 maintains the high potential of the first time period, so the fifth transistor M5 in the first input unit 10 is also turned off. Therefore, the first node N1 maintains the low potential of the previous time period, and the fourth node N4 also maintains the high potential of the previous time period. During this time period, the first output unit 30 is turned on and the second output unit 40 is turned off. During this time period, the low potential of the first node N1 controls the second sub-unit 52 to turn on and write the high level of the first voltage signal V1 to the third node N3. The low level of the first clock signal CK controls the first transistor M1 to turn on and write the high level signal to the second node N2. When the second node N2 is high, the first sub-unit 51 is turned off. Thus, the high potential of the second node N2 can be maintained during this time period, and the high potential of the fourth node N4 can also be maintained, keeping the second output unit 40 off.
[0063] During time period t15, the first node N1 is at a low potential, and the second node N2 is at a high potential. During this period, the first output unit 30 is turned on and the second output unit 40 is turned off. During this period, the first clock signal CK is at a high potential, so the first transistor M1 is turned off, and the potential of the third node N3 is locked. Furthermore, during time periods t14 and t15, the first sub-unit 51 remains in the off state. The frequent high and low level transitions of the first clock signal CK mean that time periods t14 and t15 will alternate after time period t13. Since a high-level signal can be written to the second node N2 during time period t14, the fluctuations in the potential of the second node N2 caused by the voltage transitions of the first clock signal CK will be mitigated, thus effectively maintaining the high potential state of the second node N2.
[0064] In this embodiment of the invention, the maintenance unit 50 can write a low level to the second node N2 during time period t12, ensuring that the second node N2 maintains a low potential state. Simultaneously, the maintenance unit 50 can also write a high level to the second node N2 during time period t14, ensuring that the second node N2 maintains a high potential state after time period t12. This ensures the stability of the shift register output and guarantees the display effect in applications.
[0065] Figure 11 In the embodiment, the sustaining unit 50 includes a first transistor M1, a first sub-unit 51, and a second sub-unit 52. The first sub-unit 51 includes a second transistor M2, and the second sub-unit 52 includes a fourth transistor M4. The control terminal of the second transistor M2 is coupled to the control terminal of the second output unit 40. All transistors in the shift register are p-type transistors.
[0066] In another embodiment, Figure 13Another schematic diagram of a shift register provided in an embodiment of the present invention is shown below. Figure 13 As shown, the first input unit 10 includes a fifth transistor M5 and a sixth transistor M6, and the second input unit 20 includes a seventh transistor M7. The sustaining unit 50 includes a first transistor M1, a first sub-unit 51, and a second sub-unit 52. The first sub-unit 51 includes a second transistor M2, and the second sub-unit 52 includes a fourth transistor M4. The control terminal of the second transistor M2 is coupled to the control terminal of the first output unit 30. The second transistor M2 is an n-type transistor, and the remaining transistors are p-type transistors.
[0067] Figure 11 Timing diagrams can also be applied to Figure 13 The shift register provided in this embodiment. During time period t12, the high potential of the first node N1 controls the fourth transistor M4 in the second sub-unit 52 to turn off. The first node N1 also controls the second transistor M2 in the first sub-unit 51 to turn on, writing the low level of the second voltage signal V2 to the third node N3. During this time period, the third node N3 is not in a floating state, but changes from a high level to a low level after the signal is written. Simultaneously, the first transistor M1, under the control of the first clock signal CK, turns on and writes the low level of the third node N3 to the second node N2. This achieves stabilization of the potential of the second node N2 by writing a signal to it. The potential fluctuations of the second node N2 can be smoothed out by the written signal, effectively maintaining the low potential of the second node N2. This also helps to maintain the potential of the fourth node N4, ensuring the second output unit 40 is in the on state and guaranteeing stable output from the signal output terminal OUT. Additionally, during period t14, the low potential of the first node N1 controls the second sub-unit 52 to turn on and the first sub-unit 51 to turn off. After the second sub-unit 52 turns on, it writes the high level of the first voltage signal V1 to the third node N3. The low level of the first clock signal CK controls the first transistor M1 to turn on and write the high-level signal to the second node N2. The second node N2 is at a high potential, thus maintaining the high potential state of the second node N2 during this period, and consequently maintaining the high potential state of the fourth node N4, keeping the second output unit 40 off. During period t15, the first transistor M1 is off, the first sub-unit 51 remains off, and the potential of the third node N3 is locked. The frequent high and low level transitions of the first clock signal CK mean that periods t14 and t15 will alternate after period t13. Since a high-level signal can be written to the second node N2 during period t14, the fluctuations in the potential of the second node N2 caused by the voltage transitions of the first clock signal CK are mitigated, thus effectively maintaining the high potential state of the second node N2.
[0068] Combination Figure 11 and Figure 12The shift register's operating cycle consists of a first output stage and a second output stage, with the first output stage preceding the second output stage.
[0069] In the first output stage: the second input unit 20 starts writing signals to the second node N2, and the first input unit 10 starts writing signals to the first node N1; the first output unit 30 starts under the potential control of the first node N1, and the second output unit 40 starts under the potential control of the second node N2. The first output stage is... Figure 12 During the t11 period, the first output stage is equivalent to the signal writing stage to the shift register.
[0070] In the second output stage: the first input unit 10 is turned on to write a signal to the first node N1, and the first output unit 30 is turned off under the potential control of the first node N1; the second input unit 20 is turned off, the maintenance unit 50 is turned on to maintain the potential of the second node N2, and the second output unit 40 is turned on under the potential control of the second node N2. The second output stage is... Figure 12 In the t12 period, the second output stage is equivalent to the signal output stage of the shift register. A signal is written during the t11 period and output during the t12 period, thus achieving the signal shifting function. Furthermore, the second output stage is the period when the first output unit 30 is off and the second output unit 40 is on. The maintenance unit 50 is on during the t12 period, writing a low level to the second node N2 to maintain the potential of the second node N2, ensuring the output stability of the signal output terminal out.
[0071] The shift register provided in this embodiment of the invention further includes a third output stage in its operating cycle, which follows the second output stage; combined with Figure 11 and Figure 12 As can be seen, time period t14 is the third output stage. In the third output stage: the first input unit 10 is off, and the first output unit 30 is on under the potential control of the first node N1; the second input unit 20 is off, the maintenance unit 50 is on, maintaining the potential of the second node N2, and the second output unit 40 is off under the potential control of the second node N2. The third output stage is the period when the first output unit 30 is on and the second output unit 40 is off. During time period t14, the maintenance unit 50 writes a high level to the second node N2 to maintain its potential. This improves the stability of the second node N2's potential caused by the voltage jump of the first clock signal CK, thus effectively maintaining the high potential state of the second node N2 and ensuring the output stability of the signal output terminal out.
[0072] Based on the same inventive concept, embodiments of the present invention also provide a driving circuit. Figure 14 A schematic diagram of a driving circuit provided for an embodiment of the present invention, such as... Figure 14As shown, the driving circuit includes multiple shift registers 100, which are cascaded together. Each shift register 100 includes a signal input terminal IN and a signal output terminal out. The signal input terminal IN of the next-stage shift register 100 is connected to the signal output terminal out of the previous-stage shift register 100, and the signal input terminal IN of the first-stage shift register 100 is connected to the start signal STV. The structure of the shift register 100 has been described in the above embodiments and will not be repeated here. With the design of this embodiment, the output state of the signal output terminal out of each stage of the shift register 100 is more stable in various time periods, ensuring the overall performance stability of the driving circuit.
[0073] Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 15 This is a schematic diagram of a display panel provided in an embodiment of the present invention, such as... Figure 15 As shown, the display panel includes a driving circuit 200, which can be any of the types provided in the embodiments of the present invention. The display panel includes a display area AA and a non-display area NA, and the driving circuit 200 is located in the non-display area NA. Figure 15 The diagram illustrates that driving circuits 200 are respectively arranged on both sides of the display area AA. In some other embodiments, the driving circuit provided in the embodiments of the present invention is arranged on one side of the display area AA, which will not be shown in the accompanying drawings.
[0074] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 16 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 16 As shown, the display device includes a display panel 300, which can be any of the types provided in the embodiments of the present invention. The display device may be, for example, an electronic device such as a mobile phone, tablet, laptop, television, or watch.
[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
[0076] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A shift register, characterized in that, The shift register includes a first input unit, a second input unit, a first output unit, a second output unit, and a sustain unit; The first input unit is coupled to the first node, and the first input unit is used to write signals to the first node; The control terminal of the first output unit is coupled to the first node, the first terminal of the first output unit receives the first voltage signal, and the second terminal of the first output unit is coupled to the signal output terminal. The second input unit is coupled to the second node, and the second input unit is used to write signals to the second node; The control terminal of the second output unit is coupled to the second node, the first terminal of the second output unit receives the first clock signal, and the second terminal of the second output unit is coupled to the signal output terminal. The output terminal of the sustaining unit is coupled to the second node, and the sustaining unit is used to maintain the potential of the second node at least during the period when the first output unit is off and the second output unit is on; The working cycle of the shift register also includes a second output stage and a third output stage, wherein the third output stage is after the second output stage; In the second output stage: the first input unit starts writing a signal to the first node, and the first output unit is turned off under the potential control of the first node; the second input unit is turned off, the sustaining unit is turned on to maintain the potential of the second node, and the second output unit is turned on under the potential control of the second node; In the third output stage: the first input unit is turned off, the first output unit is turned on under the potential control of the first node; the second input unit is turned off, the sustaining unit is turned on to maintain the potential of the second node, and the second output unit is turned off under the potential control of the second node.
2. The shift register according to claim 1, characterized in that, The sustaining unit includes a first transistor and a first sub-unit; The control terminal of the first transistor receives the first clock signal, the first terminal of the first transistor and the output terminal of the first sub-unit are coupled to the third node, and the second terminal of the first transistor is coupled to the second node. During the period when the first output unit is off and the second output unit is on: the first sub-unit inputs a second voltage signal to the third node, and when the first transistor is on, it writes the second voltage signal to the second node to maintain the potential of the second node.
3. The shift register according to claim 2, characterized in that, The control terminal of the first sub-unit is coupled to the control terminal of the first output unit or the control terminal of the second output unit. The first terminal of the first sub-unit receives the second voltage signal, and the second terminal of the first sub-unit is coupled to the third node.
4. The shift register according to claim 3, characterized in that, The first sub-unit includes a second transistor, a first terminal of which receives the second voltage signal, and a second terminal of which is coupled to the third node; The control terminal of the second transistor is coupled to the control terminal of the first output unit, or the control terminal of the second transistor is coupled to the control terminal of the second output unit.
5. The shift register according to claim 4, characterized in that, The control terminal of the second transistor is coupled to the control terminal of the first output unit. The second transistor is an n-type transistor, and the other transistors in the shift register are p-type transistors.
6. The shift register according to claim 4, characterized in that, The control terminal of the second transistor is coupled to the control terminal of the second output unit, and each transistor in the shift register is a p-type transistor.
7. The shift register according to claim 2, characterized in that, The shift register includes a third transistor, the first terminal of which is coupled to the second node, and the second terminal of which is coupled to the control terminal of the second output unit. The control terminal of the third transistor receives the second voltage signal.
8. The shift register according to claim 2, characterized in that, The sustaining unit is also used to maintain the potential of the second node during the period when the first output unit is turned on and the second output unit is turned off; The maintenance unit further includes a second sub-unit, the output of which is coupled to a third node; During the period when the first output unit is on and the second output unit is off: the second sub-unit inputs the first voltage signal to the third node, and when the first transistor is on, it writes the first voltage signal to the second node to maintain the potential of the second node.
9. The shift register according to claim 8, characterized in that, The second sub-unit includes a fourth transistor, the control terminal of which is coupled to the first node, the first terminal of which receives the first voltage signal, and the second terminal of which is coupled to the third node.
10. The shift register according to claim 1, characterized in that, The first input unit includes a fifth transistor and a sixth transistor; The control terminal of the fifth transistor is coupled to the second node, the first terminal of the fifth transistor receives the second clock signal, and the second terminal of the fifth transistor is coupled to the first node; The control terminal of the sixth transistor receives the second clock signal, the first terminal of the sixth transistor receives the second voltage signal, and the second terminal of the sixth transistor is coupled to the first node.
11. The shift register according to claim 1, characterized in that, The second input unit includes a seventh transistor; The control terminal of the seventh transistor receives a second clock signal, the first terminal of the seventh transistor is coupled to the signal input terminal, and the second terminal of the seventh transistor is coupled to the second node.
12. The shift register according to claim 1, characterized in that, The shift register's operating cycle includes a first output stage, which precedes the second output stage; During the first output phase: the second input unit activates the write signal to the second node, and the first input unit activates the write signal to the first node; The first output unit is turned on under the potential control of the first node, and the second output unit is turned on under the potential control of the second node.
13. A driving circuit, characterized in that, It includes the shift register as described in any one of claims 1 to 12, wherein a plurality of the shift registers are cascaded.
14. A display panel, characterized in that, Includes the driving circuit as described in claim 13.
15. A display device, characterized in that, Includes the display panel as described in claim 14.