A shift register, a gate driving circuit and a display device

Abstract

Embodiments of the present application provide a shift register, a gate drive circuit and a display device, by setting an anti-leakage module, when the gate signal output end needs to output the signal provided by the second clock signal end, the high potential accumulated by leakage at the third node can be released to the fourth power supply end through the anti-leakage module, so that the potential at the third node will not leak into the potential of the second power supply end due to leakage, so that the potential of the second node will not be affected, and the fourth node can be self-boosted to ensure that the second output module normally outputs the signal provided by the second clock signal end to the gate signal output end. Therefore, the embodiments of the present application solve the problem that the PMOS tube leakage causes the gate signal output end to output abnormally, optimize the shift register output problem caused by the damage of external factors to the PMOS tube, and realize more stable LED display products.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display device. Background Technology

[0002] The gate driver on array (GOA) circuit is an important component of a display device. A GOA circuit can include multiple cascaded shift registers, each of which can be electrically connected to at least one line in the display device. The GOA circuit can sequentially input scan signals to multiple lines (e.g., gate lines or light-emitting control signal lines) in the display device, enabling the display device to display an image. Summary of the Invention

[0003] This invention provides a shift register, a gate driving circuit, and a display device, the specific solutions of which are as follows:

[0004] This invention provides a shift register, comprising: an input module, a first node control module, a second node control module, a first output module, a second output module, and a leakage protection module; wherein...

[0005] The input module is electrically connected to a signal input terminal, a first clock signal terminal, and a second node. The input module is configured to write the signal provided by the signal input terminal to the second node in response to the control of the signal provided by the first clock signal terminal.

[0006] The first node control module is electrically connected to the first power supply terminal, the first clock signal terminal, the second node, and the first node. The first node control module is configured to write the first voltage of the first power supply terminal to the first node in response to the control of the signal provided by the first clock signal terminal, and to write the signal provided by the first clock signal terminal to the first node in response to the control of the voltage at the second node.

[0007] The second node control module is electrically connected to the first node, the second node, the second clock signal terminal, and the second power supply terminal. The second node control module is configured to write the second voltage of the second power supply terminal to the third node in response to the control of the voltage at the first node, and to write the voltage at the third node to the second node in response to the control of the signal provided by the second clock signal terminal.

[0008] The first output module is electrically connected to the first node, the third power supply terminal, and the gate signal output terminal. The first output module is configured to write the third voltage of the third power supply terminal into the gate signal output terminal in response to the control of the voltage at the first node.

[0009] The second output module is electrically connected to the second node, the first power supply terminal, the second clock signal terminal and the gate signal output terminal. The second output module is configured to write the signal provided by the second clock signal terminal to the gate signal output terminal in response to voltage control at the second node.

[0010] The leakage protection module is electrically connected to the third clock signal terminal, the fourth power supply terminal, and the third node. The leakage protection module is configured to release the voltage at the third node to the fourth power supply terminal in response to the control of the signal provided by the third clock signal terminal.

[0011] Optionally, in the shift register provided in the embodiments of the present invention, the leakage protection module includes a first switching transistor, the gate of the first switching transistor is electrically connected to the third clock signal terminal, the first terminal of the first switching transistor is electrically connected to the third node, and the second terminal of the first switching transistor is electrically connected to the fourth power supply terminal.

[0012] Optionally, in the shift register provided in the embodiments of the present invention, the input module includes a second switching transistor, the gate of the second switching transistor is electrically connected to the first clock signal terminal, the first terminal of the second switching transistor is electrically connected to the signal input terminal, and the second terminal of the second switching transistor is electrically connected to the second node.

[0013] Optionally, in the shift register provided in the embodiments of the present invention, the first node control module includes a third switching transistor and a fourth switching transistor; wherein,

[0014] The gate of the third switching transistor is electrically connected to the first clock signal terminal, the first terminal of the third switching transistor is electrically connected to the first power supply terminal, and the second terminal of the third switching transistor is electrically connected to the first node.

[0015] The gate of the fourth switching transistor is electrically connected to the second node, the first terminal of the fourth switching transistor is electrically connected to the first clock signal terminal, and the second terminal of the fourth switching transistor is electrically connected to the first node.

[0016] Optionally, in the shift register provided in the embodiments of the present invention, the second node control module includes a fifth switching transistor and a sixth switching transistor; wherein,

[0017] The gate of the fifth switching transistor is electrically connected to the first node, the first terminal of the fifth switching transistor is electrically connected to the second power supply terminal, and the second terminal of the fifth switching transistor is electrically connected to the third node.

[0018] The gate of the sixth switching transistor is electrically connected to the second clock signal terminal, the first terminal of the sixth switching transistor is electrically connected to the third node, and the second terminal of the sixth switching transistor is electrically connected to the second node.

[0019] Optionally, in the shift register provided in the embodiments of the present invention, the first output module includes a seventh switching transistor and a first capacitor; wherein,

[0020] The gate of the seventh switching transistor is electrically connected to the first node, the first terminal of the seventh switching transistor is electrically connected to the third power supply terminal, and the second terminal of the seventh switching transistor is electrically connected to the gate signal output terminal.

[0021] The first terminal of the first capacitor is electrically connected to the third power supply terminal, and the second terminal of the first capacitor is electrically connected to the gate of the seventh switching transistor.

[0022] Optionally, in the shift register provided in the embodiments of the present invention, the second output module includes an eighth switching transistor, a ninth switching transistor, and a second capacitor; wherein,

[0023] The gate of the eighth switching transistor is electrically connected to the first power supply terminal, the first terminal of the eighth switching transistor is electrically connected to the second node, and the second terminal of the eighth switching transistor is electrically connected to the gate of the ninth switching transistor.

[0024] The first terminal of the ninth switching transistor is electrically connected to the second clock signal terminal, and the second terminal of the ninth switching transistor is electrically connected to the gate signal output terminal.

[0025] The first terminal of the second capacitor is electrically connected to the gate of the ninth switching transistor, and the second terminal of the second capacitor is electrically connected to the gate signal output terminal.

[0026] Optionally, in the shift register provided in the embodiments of the present invention, the third clock signal terminal and the first clock signal terminal are the same signal terminal, the first switching transistor is an N-type transistor, and the second to the ninth switching transistors are all P-type transistors.

[0027] Optionally, in the shift register provided in the embodiments of the present invention, the third clock signal terminal and the second clock signal terminal are the same signal terminal, and the first to the ninth switching transistors are all P-type transistors.

[0028] Optionally, in the shift register provided in the embodiments of the present invention, both the second power supply terminal and the third power supply terminal are high-voltage signal terminals, and the second power supply terminal and the third power supply terminal are different signal terminals;

[0029] Both the first power supply terminal and the fourth power supply terminal are low-voltage signal terminals, and the first power supply terminal and the fourth power supply terminal are different signal terminals.

[0030] Accordingly, embodiments of the present invention also provide a gate driving circuit, including multiple cascaded shift registers as described in any of the above embodiments of the present invention.

[0031] Accordingly, embodiments of the present invention also provide a display device, including the gate driving circuit described above in embodiments of the present invention.

[0032] The beneficial effects of the embodiments of the present invention are as follows:

[0033] This invention provides a shift register, gate drive circuit, and display device. By incorporating a leakage protection module, when the gate signal output terminal needs to output the signal provided by the second clock signal terminal, the high potential accumulated at the third node due to leakage can be released to the fourth power supply terminal through the leakage protection module. This ensures that the potential at the third node does not leak to the level of the second power supply terminal, thus preventing any impact on the potential of the second node. This ensures the bootstrapping of the fourth node and guarantees that the second output module outputs the signal provided by the second clock signal terminal normally to the gate signal output terminal. Therefore, this invention solves the problem of abnormal gate signal output caused by PMOS transistor leakage, optimizes the shift register output problem caused by external factors damaging the PMOS transistor, and achieves a more stable LED display product. Attached Figure Description

[0034] Figure 1 This is a frontal plan view of the panel;

[0035] Figure 2 for Figure 1 A schematic diagram of the metal fanout traces on the back of the middle panel;

[0036] Figure 3 This is a schematic diagram of the PMOS transistor structure;

[0037] Figure 4A The IV characteristic curves of the PMOS transistor before laser etching on the back of the panel;

[0038] Figure 4B The IV characteristic curves of the PMOS transistor after laser etching on the back of the panel;

[0039] Figure 5 This refers to a GOA circuit structure in an LED display screen provided in related technologies;

[0040] Figure 6 To Figure 5The simulation waveforms of node2, node4, and gate signal output terminal OUT obtained by driving GOA are shown below.

[0041] Figure 7 This is a schematic diagram of the shift register provided in an embodiment of the present invention;

[0042] Figure 8 This is a schematic diagram of a specific structure of a shift register provided in an embodiment of the present invention;

[0043] Figure 9 A schematic diagram illustrating yet another specific structure of the shift register provided in an embodiment of the present invention;

[0044] Figure 10 A schematic diagram illustrating yet another specific structure of the shift register provided in an embodiment of the present invention;

[0045] Figure 11 A schematic diagram illustrating yet another specific structure of the shift register provided in an embodiment of the present invention;

[0046] Figure 12 for Figure 10 and Figure 11 The timing diagram of the shift register shown is shown below;

[0047] Figure 13 To Figure 10 and Figure 11 The simulation waveforms of the second node (node2), the fourth node (node4), and the gate signal output terminal (OUT) obtained by driving the shift register are shown below.

[0048] Figure 14 for Figure 8 and Figure 9 The timing diagram of the shift register shown is shown below;

[0049] Figure 15 To Figure 8 and Figure 9 The simulation waveforms of the second node (node2), the fourth node (node4), and the gate signal output terminal (OUT) obtained by driving the shift register are shown. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Furthermore, the embodiments and features in the embodiments of the present invention can be combined with each other without conflict. Based on the described embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Unless otherwise defined, the technical or scientific terms used in this invention shall have the ordinary meaning understood by one of ordinary skill in the art to which this invention pertains. The terms "comprising" or "including," and similar terms used in this invention, mean that the element or object preceding the term encompasses the element or object listed following the term and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Terms such as "inner," "outer," "upper," and "lower" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0052] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of the invention. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0053] LED displays are currently emerging as a leading technology in outdoor and central control screen displays, becoming a highly sought-after display medium in the industry. LED applications are primarily for long-distance viewing, requiring a relatively large pitch (pixel size). Currently, a small-screen panel design is used, followed by seamless splicing of multiple panels to achieve a large-screen display. To achieve seamless splicing, the panel ultimately only has a display area (AA area). ICs, FPCs, and other structures must be placed on the back of the panel. The wiring in the AA area and the connection between the ICs and FPCs on the back of the panel are achieved through side pads 01 led out from the bottom of the front of the panel. A sidewring process is used on the bottom sidewall of the panel glass (substrate) to transfer the side pads 01 from the front to the back. Figure 1 As shown.

[0054] The GOA, Data, VDD, and VSS signal lines on the front of the panel are connected to the back of the panel via Side Pad 01. The back of the panel requires metal fanout traces which are then bonded to the FPC. Currently, a backsputter and laser etching process is used. First, Cu metal is plated, and then a high-energy laser is used to etch the Cu metal to form the metal fanout traces. Figure 2 As shown, Figure 2 This is a schematic diagram of the metal fanout routing on the back of the panel. Then, FPC is bonded to the pin, and the IC signal can enter the AA area through the back fanout and side pad to drive the panel, ultimately achieving seamless splicing.

[0055] In the back-side etching process of the panel, very high-intensity ultraviolet light is required. To ensure that the Cu metal can be etched, the light passes through the glass and hits the front side of the panel. Due to the high intensity of the light, a significant amount of energy remains after passing through the glass. The circuitry on the front side of the panel is built using LTPS PMOS transistors. The structure of a MOS transistor is generally a top-gate structure. Light shining from the back of the glass can directly hit the channel of the MOS transistor, thus affecting the characteristics of the PMOS transistor.

[0056] In LED active-matrix displays, the circuit is built using PMOS transistors, and the structure of one of the PMOS transistors is as follows: Figure 3 As shown, the panel includes a buffer layer 2, an active layer 3, a gate insulating layer 4, a gate 5, a source 6, a drain 7, and an interlayer insulating layer 8, all sequentially stacked on a substrate 1. A laser (indicated by the arrow) shines from the back of the panel, directly illuminating the PMOS transistor channel (active layer 3). The active layer 3 is made of p-Si. The laser will disrupt the original structure of the p-Si, breaking the crystallization of the channel and causing unstable characteristic shifts in the PMOS transistor. Current testing shows that this will cause a shift in the threshold voltage V of the PMOS transistor. th The problems of negative bias and increased off-state leakage current (Ioff), such as Figure 4A and Figure 4B As shown, Figure 4A The image shows the IV characteristic curves of the PMOS transistor before laser etching on the back of the panel. Figure 4B The I / O characteristic curves of the PMOS transistor after laser etching on the back of the panel show that when the gate voltage Vg is 0V, the I / O characteristic curve is as follows: off Increased by 3 to 4 orders of magnitude.

[0057] Since the damage to PMOS transistors caused by laser etching is irreversible, the resulting increase in Ioff has a significant impact on the LED GOA circuit. Because there are critical nodes in the GOA circuit that require a 0V off state, such as... Figure 5 As shown, Figure 5 This invention relates to a GOA circuit structure for an LED display screen, which is a 9T2C structure where all transistors are P-type transistors. When the gate signal output terminal OUT requires a low-level signal from the CB terminal, the gate-source voltage Vgs of transistor M5 is Vnode1 - VGH = 0V when node1 is high. Normally, the PMOS transistor is off at 0V, and Ioff is approximately 1 × 10⁻¹⁰. -12 Order of magnitude. At this point, node 3 is low, transistor M6 is on, node 2 can remain low, node 4 bootstraps, transistor M9 is on, the second clock signal terminal CB outputs a low level, and thus the gate signal output terminal OUT outputs a low level; however, our PMOS transistors have a problem where Ioff is too high when the gate voltage Vg is 0V, and transistor M5 cannot be completely turned off when Vgs = 0V, node 3 gradually rises because transistor M6 is on at this time, causing node 2 to also go high. At this time, node 4 also leaks and goes high, so node 4 cannot bootstrap, transistor M9 cannot turn on, the low level of CB cannot be output, OUT remains high, and there is no output from OUT. Figure 6 As shown, Figure 6 To Figure 5 The simulation waveforms of node2, node4, and gate signal output terminal OUT obtained by driving GOA are shown below. When Ioff reaches 1×10 -9 At this point, node2 begins to leak current, and the bootstrap waveform at node4 also begins to leak current, failing to reach the VGL voltage. It slowly leaks to a high level. At this point, because the bootstrap voltage still exists, the output voltage can barely guarantee normal output. However, as the GOA cascade process continues, the GOA output will become high and fail during transmission. When Ioff reaches 1×10... -7 At that time, Node4 had severe leakage current. Before it could bootstrap, it had already leaked to a high level VGH. The OUT output could not be pulled low and remained at a high level, causing the first line of GOA to fail.

[0058] When the GOA experiences leakage and has no output, our LED display will malfunction, resulting in large areas of non-lighting and poor dark lines. Therefore, we need to solve the GOA leakage problem to ensure that the potential at the nodes in the GOA can be maintained.

[0059] In view of this, embodiments of the present invention provide a shift register, such as Figure 7As shown, it includes: an input module 10, a first node control module 20, a second node control module 30, a first output module 40, a second output module 50, and a leakage protection module 60; wherein,

[0060] The input module 10 is electrically connected to the signal input terminal STV, the first clock signal terminal CK, and the second node node2. The input module 10 is configured to write the signal provided by the signal input terminal STV into the second node node2 in response to the control of the signal provided by the first clock signal terminal CK.

[0061] The first node control module 20 is electrically connected to the first power supply terminal VGL1, the first clock signal terminal CK, the second node node2, and the first node node1. The first node control module 20 is configured to write the first voltage of the first power supply terminal VGL1 into the first node node1 in response to the control of the signal provided by the first clock signal terminal CK, and to write the signal provided by the first clock signal terminal CK into the first node node1 in response to the control of the voltage at the second node node2.

[0062] The second node control module 30 is electrically connected to the first node node1, the second node node2, the second clock signal terminal CB, and the second power supply terminal VGH1. The second node control module 30 is configured to write the second voltage of the second power supply terminal VGH1 to the third node node3 in response to the control of the voltage at the first node node1, and to write the voltage at the third node node3 to the second node node2 in response to the control of the signal provided by the second clock signal terminal CB.

[0063] The first output module 40 is electrically connected to the first node node1, the third power supply terminal VGH2 and the gate signal output terminal OUT. The first output module 40 is configured to write the third voltage of the third power supply terminal VGH2 into the gate signal output terminal OUT in response to the control of the voltage at the first node node1.

[0064] The second output module 50 is electrically connected to the second node 2, the first power supply terminal VGL1, the second clock signal terminal CB, and the gate signal output terminal OUT. The second output module 50 is configured to write the signal provided by the second clock signal terminal CB to the gate signal output terminal OUT in response to the control of the voltage at the second node 2.

[0065] The leakage protection module 60 is electrically connected to the third clock signal terminal CL, the fourth power supply terminal VGL2, and the third node 3. The leakage protection module 60 is configured to release the voltage at the third node 3 to the fourth power supply terminal VGL2 in response to the control of the signal provided by the third clock signal terminal CL.

[0066] The shift register provided in this embodiment of the invention, by setting an anti-leakage module 60, ensures that when the gate signal output terminal OUT needs to output the signal provided by the second clock signal terminal CB, the high potential (VGH1) accumulated at the third node 3 due to leakage can be released to the fourth power supply terminal VGL2 through the anti-leakage module 60. This ensures that the potential at the third node 3 will not leak to the potential of the second power supply terminal VGH1 due to leakage, thus not affecting the potential of the second node 2, ensuring the bootstrapping of the fourth node 4, and ensuring that the second output module 50 outputs the signal provided by the second clock signal terminal CB normally to the gate signal output terminal OUT. Therefore, this embodiment of the invention solves the problem of abnormal output at the gate signal output terminal OUT due to PMOS transistor leakage, optimizes the problem of no output of the shift register caused by external factors damaging the PMOS transistor, and achieves a more stable LED display product.

[0067] It should be noted that the specific circuit structures of the above-mentioned input module, first node control module, second node control module, first output module, second output module, and leakage protection module are not limited, as long as they meet the corresponding functions.

[0068] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9 As shown, the leakage protection module 60 may include a first switching transistor M1. The gate of the first switching transistor M1 is electrically connected to the third clock signal terminal CL, the first terminal of the first switching transistor M1 is electrically connected to the third node 3, and the second terminal of the first switching transistor M1 is electrically connected to the fourth power supply terminal VGL2. Thus, when leakage current accumulates at the third node 3 to the potential of the second power supply terminal VGH1, the effective level provided by the third clock signal terminal CL can control the first switching transistor M1 to turn on. The voltage at the third node 3 is then released to the fourth power supply terminal VGL2 through the first switching transistor M1, ensuring that the voltage at the third node 3 is normal and does not affect the voltage at the second node 2.

[0069] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9 As shown, the input module 10 may include a second switching transistor M2. The gate of the second switching transistor M2 is electrically connected to the first clock signal terminal CK, the first terminal of the second switching transistor M2 is electrically connected to the signal input terminal STV, and the second terminal of the second switching transistor M2 is electrically connected to the second node node2. Specifically, the second switching transistor M2 can be turned on when the first clock signal terminal CK provides an effective level, providing the signal from the signal input terminal STV to the second node node2.

[0070] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9 As shown, the first node control module 20 may include a third switching transistor M3 and a fourth switching transistor M4; wherein,

[0071] The gate of the third switching transistor M3 is electrically connected to the first clock signal terminal CK, the first terminal of the third switching transistor M3 is electrically connected to the first power supply terminal VGL1, and the second terminal of the third switching transistor M3 is electrically connected to the first node node1. Specifically, the third switching transistor M3 can be turned on when the first clock signal terminal CK provides an effective level, and provide the first voltage of the first power supply terminal VGL1 to the first node node1.

[0072] The gate of the fourth switching transistor M4 is electrically connected to the second node node2, the first terminal of the fourth switching transistor M4 is electrically connected to the first clock signal terminal CK, and the second terminal of the fourth switching transistor M4 is electrically connected to the first node node1. Specifically, the fourth switching transistor M4 can be turned on when the second node node2 provides an effective level, and provide the first clock signal terminal CK to the first node node1.

[0073] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9 As shown, the second node control module 30 may include a fifth switching transistor M5 and a sixth switching transistor M6; wherein,

[0074] The gate of the fifth switching transistor M5 is electrically connected to the first node node1, the first terminal of the fifth switching transistor M5 is electrically connected to the second power supply terminal VGH1, and the second terminal of the fifth switching transistor M5 is electrically connected to the third node node3. Specifically, the fifth switching transistor M5 can be turned on when the first node node1 provides an effective level, and provide the second voltage of the second power supply terminal VGH1 to the third node node3.

[0075] The gate of the sixth switching transistor M6 is electrically connected to the second clock signal terminal CB, the first terminal of the sixth switching transistor M6 is electrically connected to the third node node3, and the second terminal of the sixth switching transistor M6 is electrically connected to the second node node2. Specifically, the sixth switching transistor M6 can be turned on when the second clock signal terminal CB provides an effective level, and provide the voltage at the third node node3 to the second node node2.

[0076] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9As shown, the first output module 40 may include a seventh switching transistor M7 and a first capacitor C1; wherein,

[0077] The gate of the seventh switching transistor M7 is electrically connected to the first node node1, the first terminal of the seventh switching transistor M7 is electrically connected to the third power supply terminal VGH2, and the second terminal of the seventh switching transistor M7 is electrically connected to the gate signal output terminal OUT. Specifically, the seventh switching transistor M7 can be turned on when the first node node1 provides an effective level, and provide the third voltage of the third power supply terminal VGH2 to the gate signal output terminal OUT.

[0078] The first terminal of the first capacitor C1 is electrically connected to the third power supply terminal VGH2, and the second terminal of the first capacitor C1 is electrically connected to the gate of the seventh switching transistor M7.

[0079] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9 As shown, the second output module 50 may include an eighth switching transistor M8, a ninth switching transistor M9, and a second capacitor C2; wherein,

[0080] The gate of the eighth switching transistor M8 is electrically connected to the first power supply terminal VGL1, the first terminal of the eighth switching transistor M8 is electrically connected to the second node node2, and the second terminal of the eighth switching transistor M8 is electrically connected to the gate of the ninth switching transistor M9. Specifically, the eighth switching transistor M8 can be turned on under the control of the first voltage of the first power supply terminal VGL1 to provide the voltage at the second node node2 to the gate (fourth node node4) of the eighth switching transistor M8.

[0081] The first terminal of the ninth switching transistor M9 is electrically connected to the second clock signal terminal CB, and the second terminal of the ninth switching transistor M9 is electrically connected to the gate signal output terminal OUT. Specifically, the ninth switching transistor M9 can be turned on when the fourth node4 provides an effective level, and provide the signal of the second clock signal terminal CB to the gate signal output terminal OUT.

[0082] The first terminal of the second capacitor C2 is electrically connected to the gate of the ninth switching transistor M9, and the second terminal of the second capacitor C2 is electrically connected to the gate signal output terminal OUT.

[0083] It should be noted that the embodiments of the present invention do not limit the type of transistor, which can be a thin film transistor, such as a low-temperature polycrystalline silicon thin film transistor or an oxide thin film transistor, etc.

[0084] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8As shown, the third clock signal terminal CL and the first clock signal terminal CK can be the same signal terminal. The first switching transistor M1 can be an N-type transistor, and the second switching transistors M2 to the ninth switching transistor M9 can all be P-type transistors. In this way, when the second clock signal terminal CB is low, the first switching transistor M1 can be turned on, and the high voltage accumulated at the third node 3 due to the leakage current of the fifth switching transistor M5 can be released to the fourth power supply terminal VGL2 through the turned-on first switching transistor M1.

[0085] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 9 As shown, the third clock signal terminal CL and the second clock signal terminal CB can be the same signal terminal, and the first switching transistor M1 to the ninth switching transistor M9 can all be P-type transistors. In this way, when the second clock signal terminal CB is at a low level, the first switching transistor M1 can be turned on, and the high voltage accumulated at the third node3 due to the leakage current of the fifth switching transistor M5 can be released to the fourth power supply terminal VGL2 through the turned-on first switching transistor M1.

[0086] Specifically, a P-type transistor conducts at low potentials and is cut off at high potentials; an N-type transistor conducts at high potentials and is cut off at low potentials.

[0087] In specific implementation, in the shift register provided in the embodiments of the present invention, such as Figure 8 and Figure 9 As shown, both the second power supply terminal VGH1 and the third power supply terminal VGH2 are high-voltage signal terminals, and the second power supply terminal VGH1 and the third power supply terminal VGH2 can be the same signal terminal; as Figure 10 and Figure 11 As shown, VGH is directly used to represent the high voltage of the second and third power supply terminals;

[0088] Both the first power supply terminal VGL1 and the fourth power supply terminal VGL2 are low-voltage signal terminals, and the first power supply terminal VGL1 and the fourth power supply terminal VGL2 can be the same signal terminal; for example Figure 10 and Figure 11 As shown, VGL is directly used to represent the low voltage of the first power supply terminal and the fourth power supply terminal.

[0089] The following is combined with Figure 12 The signal timing diagram shown is for Figure 10 and Figure 11 The operation of the shift register is explained below. One working cycle of the shift register can include multiple time periods: the first time period (T1), the second time period (T2), and the third time period (T3).

[0090] In the first time period T1: the signal input terminal STV provides a low-level signal, the signal input terminal CB provides a low-level signal, and the signal input terminal CB provides a high-level signal. The second switching transistor M2 and the third switching transistor M3 are turned on, the potentials at the first node (node1) and the second node (node2) are both low, the fourth switching transistor M4 is turned on, the first switching transistor M1 is turned off, the fifth switching transistor M5 is turned on, the potential at the third node (node3) is high, the sixth switching transistor M6 is turned off, the eighth switching transistor M8 is turned on, the seventh switching transistor M7 is turned on, the ninth switching transistor M9 is turned on, and the gate signal output terminal OUT outputs a high level.

[0091] During the second time period T2: the signal input terminal STV provides a high-level signal, the first clock signal terminal provides a high-level signal, and the second clock signal terminal CB provides a low-level signal. The second switching transistor M2 and the third switching transistor M3 are off, the potential at node2 remains low, the fourth switching transistor M4 is on, the potential at node1 becomes high, the fifth switching transistor M5 and the seventh switching transistor M7 are both off, the sixth switching transistor M6 is on, the potential at node3 becomes the same as the potential at node2 (both are low), the eighth switching transistor M8 and the ninth switching transistor M9 are both on, and the gate signal output terminal OUT outputs a low level. However, during this stage, due to leakage of the fifth switching transistor M5, the potential at the third node (node3) accumulates and becomes a high voltage (VGH). Because the sixth switching transistor M6 is turned on, the potential at the second node (node2) becomes high, causing the potential at the third node (node3) to also become high. Consequently, the ninth switching transistor M9 cannot be turned on, and the gate signal output terminal OUT cannot output the low-level signal of the second clock signal terminal CB, resulting in the gate signal output terminal OUT failing to output normally. However, the leakage protection module 60 provided in this embodiment of the invention, because the first switching transistor M1 is turned on during this stage, even if the potential at the third node (node3) accumulates and becomes a high voltage (VGH), the high-level signal at the third node (node3) is released to the fourth power supply terminal VGL2 through the first switching transistor M1, thus ensuring that the potential at the third node (node3) remains low during this stage. This does not affect the potential at the second node (node2), and therefore does not affect the potential at the fourth node (node4), ensuring that the ninth switching transistor M9 is turned on normally, thereby ensuring that the gate signal output terminal OUT outputs a low level.

[0092] In the third period: the signal provided by the signal input terminal STV is a high-level signal, the signal provided by the first clock signal terminal is a low-level signal, and the signal provided by the second clock signal terminal CB is a high-level signal. The second switching transistor M2 and the third switching transistor M3 are turned on, the potential at the first node 1 is low, the potential at the second node 2 is high, the fourth switching transistor M4 is turned off, the first switching transistor M1 is turned off, the fifth switching transistor M5 is turned on, the potential at the third node 3 is high, the sixth switching transistor M6 is turned off, the eighth switching transistor M8 is turned on, the seventh switching transistor M7 is turned on, and the ninth switching transistor M9 is turned off. The gate signal output terminal OUT outputs a high level.

[0093] like Figure 13 As shown, Figure 13 To Figure 10 and Figure 11 The simulation waveforms of the second node (node2), the fourth node (node4), and the gate signal output terminal (OUT) obtained by driving the shift register are shown below. Ioff starts from 10. -12 Change to 10 -7 It can be seen that the waveform of the second node2 can basically remain at a low level in the second period without leakage. This is because the leakage at the third node3 mentioned above is released to VGL through the conducting first switching transistor M1. Thus, the bootstrap phenomenon of the fourth node4 is not affected. When the second clock signal terminal CB input is low, the waveform of the gate signal output terminal OUT can remain normal.

[0094] but, Figure 13 In the dashed box on the right, we can see that the waveforms at nodes 2, 4, and OUT all exhibit downward coupling noise. This noise is caused by the leakage protection path of the first switching transistor M1. Figure 9 and Figure 10 There is only one VGH and one VGL, meaning VGH and VGL are shared. The two ends of the third node (node3) are VGH and VGL, forming a single current path. The current flow direction of VGH at the gate signal output terminal OUT is affected by the first switching transistor M1. When OUT outputs VGH, there is a risk that the OUT level may not reach the VGH voltage, and there is also a risk of noise. Therefore, it affects the output of VGH, and consequently affects the potential of VGH / VGL at the output and node. Therefore, in the shift register provided in the above embodiment of the present invention, as... Figure 8 and Figure 9 As shown, the second power supply terminal VGH1 and the third power supply terminal VGH2 are both high-voltage signal terminals, and the second power supply terminal VGH1 and the third power supply terminal VGH2 are different signal terminals.

[0095] Both the first power supply terminal VGL1 and the fourth power supply terminal VGL2 are low-voltage signal terminals, and they are different signal terminals. Thus, the two ends of the third node (node3) are VGH1 and VGL2, which has no impact on VGH2 of the gate signal output terminal OUT, resulting in a more stable circuit structure.

[0096] Figure 8 and Figure 9 The timing diagram of the shift register shown is as follows: Figure 14 As shown, the working principle is the same as Figure 10 and Figure 11 The working principle is the same, so I will not go into details here.

[0097] like Figure 15 As shown, Figure 15 To Figure 8 and Figure 9 The simulation waveforms of the second node (node2), the fourth node (node4), and the gate signal output terminal (OUT) obtained by driving the shift register are shown below. Figure 8 and Figure 9 Based on the shared VGH / VGL, it can be seen that the output functions of VGH and VGL and the voltage holding functions of other nodes are not affected. The output waveforms of the second node Node2, the fourth node 4, and the gate signal output terminal OUT show no coupled noise (within the dashed box); and Ioff from 10 -12 Change to 10 -7 While maintaining the low level of the second node (node2) and the bootstrap effect of the fourth node (node4), the gate signal output (OUT) did not attenuate; Figure 10 and Figure 11 In comparison, while improving the leakage current issue of the third node (node3), the third node (node3) has no impact on the VGH output at the gate signal output terminal OUT, resulting in a more stable circuit structure. Figure 10 and Figure 11 It also reduces the risk of coupling noise and can be applied to improve the solution of leakage current in the third node (node3).

[0098] Based on the same inventive concept, embodiments of the present invention also provide a gate driving circuit, including multiple cascaded shift registers provided in the embodiments of the present invention. Since the principle by which this gate driving circuit solves the problem is similar to that of the aforementioned shift register, the implementation of this gate driving circuit can refer to the implementation of the aforementioned shift register, and repeated details will not be described again.

[0099] The aforementioned gate driving circuit can be connected to the pixel driving circuit of the display substrate to provide various control signals to the pixel driving circuit, such as: line scanning signals, light emission control signals, etc.

[0100] Alternatively, the display substrate can be a Mini LED display substrate, an OLED display substrate, or the like.

[0101] Based on the same inventive concept, embodiments of the present invention also provide a display device, including multiple cascaded gate driving circuits provided in the embodiments of the present invention. Since the principle by which this display device solves the problem is similar to that of the aforementioned shift register, the implementation of this display device can refer to the implementation of the aforementioned shift register, and repeated details will not be elaborated further.

[0102] The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Implementation of this display device can refer to the embodiments of the display panel described above; repeated details will not be repeated.

[0103] This invention provides a shift register, a gate drive circuit, and a display device. By incorporating a leakage protection module, when the gate signal output terminal needs to output the signal provided by the second clock signal terminal, the high potential accumulated at the third node due to leakage can be released to the fourth power supply terminal through the leakage protection module. This ensures that the potential at the third node does not leak to the level of the second power supply terminal, thus preventing any impact on the potential of the second node. This ensures the bootstrapping of the fourth node and guarantees that the second output module outputs the signal provided by the second clock signal terminal normally to the gate signal output terminal. Therefore, this invention solves the problem of abnormal gate signal output caused by PMOS transistor leakage, optimizes the shift register output problem caused by external factors damaging the PMOS transistor, and achieves a more stable LED display product.

[0104] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0105] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A shift register, characterized in that, include: The system includes an input module, a first node control module, a second node control module, a first output module, a second output module, and a leakage protection module; among which, The input module is electrically connected to a signal input terminal, a first clock signal terminal, and a second node. The input module is configured to write the signal provided by the signal input terminal to the second node in response to the control of the signal provided by the first clock signal terminal. The first node control module is electrically connected to the first power supply terminal, the first clock signal terminal, the second node, and the first node. The first node control module is configured to write the first voltage of the first power supply terminal to the first node in response to the control of the signal provided by the first clock signal terminal, and to write the signal provided by the first clock signal terminal to the first node in response to the control of the voltage at the second node. The second node control module is electrically connected to the first node, the second node, the second clock signal terminal, and the second power supply terminal. The second node control module is configured to write the second voltage of the second power supply terminal to the third node in response to the control of the voltage at the first node, and to write the voltage at the third node to the second node in response to the control of the signal provided by the second clock signal terminal. The first output module is electrically connected to the first node, the third power supply terminal, and the gate signal output terminal. The first output module is configured to write the third voltage of the third power supply terminal into the gate signal output terminal in response to the control of the voltage at the first node. The second output module is electrically connected to the second node, the first power supply terminal, the second clock signal terminal and the gate signal output terminal. The second output module is configured to write the signal provided by the second clock signal terminal to the gate signal output terminal in response to voltage control at the second node. The leakage protection module is electrically connected to the third clock signal terminal, the fourth power supply terminal, and the third node. The leakage protection module is configured to release the voltage at the third node to the fourth power supply terminal in response to the control of the signal provided by the third clock signal terminal.

2. The shift register as described in claim 1, characterized in that, The leakage protection module includes a first switching transistor, the gate of which is electrically connected to the third clock signal terminal, the first terminal of which is electrically connected to the third node, and the second terminal of which is electrically connected to the fourth power supply terminal.

3. The shift register as described in claim 2, characterized in that, The input module includes a second switching transistor, the gate of which is electrically connected to the first clock signal terminal, the first terminal of which is electrically connected to the signal input terminal, and the second terminal of which is electrically connected to the second node.

4. The shift register as described in claim 3, characterized in that, The first node control module includes a third switching transistor and a fourth switching transistor; wherein, The gate of the third switching transistor is electrically connected to the first clock signal terminal, the first terminal of the third switching transistor is electrically connected to the first power supply terminal, and the second terminal of the third switching transistor is electrically connected to the first node. The gate of the fourth switching transistor is electrically connected to the second node, the first terminal of the fourth switching transistor is electrically connected to the first clock signal terminal, and the second terminal of the fourth switching transistor is electrically connected to the first node.

5. The shift register as described in claim 4, characterized in that, The second node control module includes a fifth switching transistor and a sixth switching transistor; wherein, The gate of the fifth switching transistor is electrically connected to the first node, the first terminal of the fifth switching transistor is electrically connected to the second power supply terminal, and the second terminal of the fifth switching transistor is electrically connected to the third node. The gate of the sixth switching transistor is electrically connected to the second clock signal terminal, the first terminal of the sixth switching transistor is electrically connected to the third node, and the second terminal of the sixth switching transistor is electrically connected to the second node.

6. The shift register as described in claim 5, characterized in that, The first output module includes a seventh switching transistor and a first capacitor; wherein, The gate of the seventh switching transistor is electrically connected to the first node, the first terminal of the seventh switching transistor is electrically connected to the third power supply terminal, and the second terminal of the seventh switching transistor is electrically connected to the gate signal output terminal. The first terminal of the first capacitor is electrically connected to the third power supply terminal, and the second terminal of the first capacitor is electrically connected to the gate of the seventh switching transistor.

7. The shift register as described in claim 6, characterized in that, The second output module includes an eighth switching transistor, a ninth switching transistor, and a second capacitor; wherein, The gate of the eighth switching transistor is electrically connected to the first power supply terminal, the first terminal of the eighth switching transistor is electrically connected to the second node, and the second terminal of the eighth switching transistor is electrically connected to the gate of the ninth switching transistor. The first terminal of the ninth switching transistor is electrically connected to the second clock signal terminal, and the second terminal of the ninth switching transistor is electrically connected to the gate signal output terminal. The first terminal of the second capacitor is electrically connected to the gate of the ninth switching transistor, and the second terminal of the second capacitor is electrically connected to the gate signal output terminal.

8. The shift register as described in claim 7, characterized in that, The third clock signal terminal is the same as the first clock signal terminal. The first switching transistor is an N-type transistor, and the second to the ninth switching transistors are all P-type transistors.

9. The shift register as described in claim 7, characterized in that, The third clock signal terminal is the same as the second clock signal terminal, and the first to the ninth switching transistors are all P-type transistors.

10. The shift register as described in any one of claims 1-9, characterized in that, Both the second power supply terminal and the third power supply terminal are high-voltage signal terminals, and the second power supply terminal and the third power supply terminal are different signal terminals; Both the first power supply terminal and the fourth power supply terminal are low-voltage signal terminals, and the first power supply terminal and the fourth power supply terminal are different signal terminals.

11. A gate driving circuit, characterized in that, Includes multiple cascaded shift registers as described in any one of claims 1-10.

12. A display device, characterized in that, Includes the gate drive circuit as described in claim 11.

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