Variable double modular multiplication operator, method of operation and related apparatus

Abstract

The application discloses a variable double modulus multiplication operation device, an operation method and related devices. The variable double modulus multiplication operation device comprises double operation modules and modulus operation modules which are connected in sequence. The constant in the modulus operation module comprises a modulus. The double operation module is used for determining the double of input data to be multiplied. The modulus operation module is used for calculating the modulus operation result of the double of the data to be multiplied and the modulus. The variable double modulus multiplication operation device is beneficial to realizing the double modulus multiplication operation of input data in quantum computation.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a variable double modular multiplication operator, operation method and related device. Background Technology

[0002] A quantum computer is a physical device that performs high-speed mathematical and logical operations, stores and processes quantum information in accordance with the laws of quantum mechanics. When a device processes and calculates quantum information and runs quantum algorithms, it is a quantum computer. Because of its ability to process mathematical problems more efficiently than ordinary computers—for example, reducing the time to crack RSA keys from hundreds of years to hours—quantum computers have become a key technology under research.

[0003] Modular operations have wide applications in number theory and cryptography, from parity and prime number determination to the Caesar cipher, from finite fields to the implementation of block ciphers and field towers, and from elliptic curves over finite fields to elliptic curve-based public-key cryptography. Modular operations are ubiquitous in these applications. Therefore, modular operations are the most commonly used function in computational units, and this is also true for quantum computing. How to implement the modular multiplication of variables twice is a technical problem that urgently needs to be solved in quantum computing. Summary of the Invention

[0004] The purpose of this invention is to provide a variable double modular multiplication operator, operation method and related device, which aims to realize double modular multiplication of input data in quantum computing.

[0005] An embodiment of the present invention provides a variable doubling modular multiplication operator, which includes a doubling operation module and a modulus operation module cascaded in sequence. The constant in the modulus operation module includes a modulus. The doubling operation module is used to determine twice the input data to be multiplied, and the modulus operation module is used to calculate the modulus operation result of twice the data to be multiplied and the modulus.

[0006] Optionally, the double operation module includes one of the following operations: data misalignment storage, adder, or SWAP gate.

[0007] Optionally, one input terminal of the variable doubling modular multiplication operator is connected to the input terminal of the doubling operation module, the output terminal of the doubling operation module is connected to one input terminal of the modular multiplication module, and the other input terminal of the variable doubling modular multiplication operator is connected to the other input terminal of the modular multiplication module. One input terminal of the variable doubling modular multiplication operator is used to input the quantum state corresponding to the data to be multiplied, and the other input terminal of the variable doubling modular multiplication operator is used to input the quantum state corresponding to the initial auxiliary data.

[0008] Optionally, the modular arithmetic module includes a constant subtractor, a first CNOT gate, and a controlled constant adder cascaded together, wherein the constant in the constant subtractor and the controlled constant adder is the modulus.

[0009] Optionally, the output of the constant subtractor includes a data output and a sign output, one of the inputs of the controlled constant adder includes a data input and a sign input, the data output of the constant subtractor is connected to the data input of the controlled constant adder, the sign output of the constant subtractor is connected to one of the inputs of the first CNOT gate, and the two outputs of the first CNOT gate are respectively connected to the sign input and the other input of the controlled constant adder.

[0010] Optionally, the two outputs of the controlled constant adder are used to output the quantum state corresponding to twice the data to be multiplied and the result of the modulus operation, and the quantum state corresponding to the intermediate auxiliary data, respectively.

[0011] Optionally, the two outputs of the controlled constant adder are respectively connected to the two outputs of the variable double modular multiplication operator.

[0012] Optionally, the constant subtractor, the first CNOT gate, and the controlled constant adder constitute a first operation submodule. The modular arithmetic module further includes a second operation submodule cascaded with the first operation submodule. The second operation submodule is used to reset the intermediate auxiliary data to the initial auxiliary data.

[0013] Optionally, the second sub-operation module includes a first NOT gate, a second CNOT gate, and a second NOT gate cascaded in sequence. One output terminal of the controlled constant adder includes a low-order output terminal and a non-low-order output terminal. The low-order output terminal of the controlled constant adder is connected to the input terminal of the first NOT gate, and the other output terminal of the controlled constant adder is connected to one input terminal of the second CNOT gate.

[0014] Optionally, the output of the first NOT gate is connected to another input of the second CNOT gate, and the other output of the second CNOT gate is connected to the input of the second NOT gate.

[0015] Optionally, the output of the second NOT gate and the non-low-order output of the controlled constant adder are used to output the quantum state corresponding to twice the data to be multiplied and the modulus operation result, and one of the outputs of the second CNOT gate is used to output the quantum state corresponding to the initial auxiliary data.

[0016] Optionally, the output of the second NOT gate and the non-low-order output of the controlled constant adder are connected to one of the outputs of the variable double modular multiplication operator, and one of the outputs of the second CNOT gate is connected to the other output of the variable double modular multiplication operator.

[0017] Another embodiment of the present invention provides a method for performing a variable double modular multiplication, the method comprising:

[0018] Obtain the variable double modular multiplication operator and the data to be doubled as described in the above embodiments;

[0019] The data to be multiplied is input into the variable doubling modular multiplication operator, and the variable doubling modular multiplication operator is run to obtain the quantum state corresponding to the modular operation result of the data to be multiplied twice and the modulus;

[0020] Based on the quantum state corresponding to the modulus operation result, determine the result of the modulus operation between twice the data to be multiplied and the modulus.

[0021] Another embodiment of the present invention provides a variable double modular multiplication operation device, the device comprising:

[0022] The acquisition unit is used to acquire the variable double modular multiplication operator and the data to be multiplied as described in the above embodiments;

[0023] The computing unit is used to input the data to be multiplied into the variable double modular multiplication operator, and to run the variable double modular multiplication operator to obtain the quantum state corresponding to the modular operation result of the data to be multiplied twice and the modulus;

[0024] A determining unit is used to determine the result of the modulo operation between twice the data to be multiplied and the modulus, based on the quantum state corresponding to the modulo operation result.

[0025] Another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute the methods described above when running.

[0026] Another embodiment of the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the methods described above.

[0027] Compared with the prior art, the present invention provides a variable doubling modular multiplication operator, a calculation method and related apparatus. The variable doubling modular multiplication operator includes a doubling operation module and a modulus operation module cascaded in sequence. The constant in the modulus operation module includes the modulus. The doubling operation module is used to determine the doubling of the input data to be multiplied. The modulus operation module is used to calculate the modulus operation result of the doubling of the data to be multiplied and the modulus. For the input data to be multiplied, the doubling operation module can be used to calculate the doubling of the data, and then the modulus operation module can be used to calculate the modulus result of the doubling of the data and the preset modulus. Attached Figure Description

[0028] Figure 1 A hardware structure block diagram of a computer terminal for a variable double modular multiplication operation method provided in an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of the structure of a variable double modular multiplication operator provided in an embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of another variable double modular multiplication operator provided in an embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of the structure of a modular arithmetic module provided in an embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of another modular arithmetic module provided in an embodiment of the present invention;

[0033] Figure 6 A flowchart illustrating a variable double modular multiplication method provided in an embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of a variable double modular multiplication operation device provided in an embodiment of the present invention. Detailed Implementation

[0035] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0036] This invention first provides a method for performing a variable double modular multiplication, which can be applied to electronic devices, such as computer terminals, specifically ordinary computers, quantum computers, etc.

[0037] The following detailed explanation uses a computer terminal as an example. Figure 1 This is a hardware structure block diagram of a computer terminal for a variable double modular multiplication operation method provided in an embodiment of the present invention. Figure 1 As shown, a computer terminal may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing the method of performing a two-times modular multiplication operation on variables are also shown. Optionally, the computer terminal may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1 The structure shown is for illustrative purposes only and does not limit the structure of the computer terminal described above. For example, the computer terminal may also include components that are more complex than those described above. Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0038] The memory 104 can be used to store software programs and modules of application software, such as the program instructions / modules corresponding to the variable double modular multiplication operation method in this embodiment. The processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, thereby implementing the above-described method. The memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include memory remotely located relative to the processor 102, and these remote memories can be connected to a computer terminal via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0039] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the computer terminal. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module, used for wireless communication with the Internet.

[0040] It's important to note that a true quantum computer has a hybrid structure, comprising two main parts: a classical computer responsible for performing classical computations and control, and a quantum device responsible for running quantum programs to achieve quantum computation. A quantum program is a sequence of instructions written in a quantum language such as QRunes that can run on a quantum computer, supporting operations on quantum logic gates and ultimately enabling quantum computing. Specifically, a quantum program is a sequence of instructions that operates on quantum logic gates according to a specific timing order.

[0041] In practical applications, due to limitations in the development of quantum device hardware, quantum computing simulations are often required to verify quantum algorithms, quantum applications, and so on. Quantum computing simulation is the process of simulating the execution of a quantum program corresponding to a specific problem using a virtual architecture (i.e., a quantum virtual machine) built with the resources of a regular computer. Typically, it is necessary to construct a quantum program corresponding to a specific problem. The quantum program referred to in this embodiment of the invention is a program written in a classical language that represents qubits and their evolution, wherein qubits, quantum logic gates, etc., related to quantum computing all have corresponding classical code representations.

[0042] Quantum circuits, also known as quantum logic circuits, are a manifestation of quantum programming and are the most commonly used general-purpose quantum computing model. They represent circuits that operate on qubits under an abstract concept. They consist of qubits, circuits (timelines), and various quantum logic gates. Finally, the results are often read out through quantum measurement operations.

[0043] Unlike traditional circuits that use metal wires to transmit voltage or current signals, in quantum circuits, the circuits can be seen as being connected by time. That is, the state of a quantum bit evolves naturally over time, following the instructions of the Hamiltonian operator until it encounters a logic gate and is operated on.

[0044] A quantum program corresponds to a single quantum circuit. The quantum program described in this invention refers to this single quantum circuit, where the total number of qubits in the single quantum circuit is the same as the total number of qubits in the quantum program. This can be understood as follows: a quantum program can consist of a quantum circuit, measurement operations on the qubits within the quantum circuit, registers storing the measurement results, and control flow nodes (jump instructions). A single quantum circuit can contain dozens, hundreds, or even thousands of quantum logic gate operations. The execution of a quantum program is the process of executing all the quantum logic gates in a specific timing order. It should be noted that the timing order refers to the chronological sequence in which individual quantum logic gates are executed.

[0045] It should also be noted that this invention relates to quantum computers. In conventional silicon-based computing devices, the processing chip units are CMOS transistors. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, currently, the number of such computing units in silicon chips is sufficient; that is, the number of computing units in a single chip is currently in the tens of thousands. The sufficient number of computing units and the fixed selectable computing logic of CMOS transistors, such as AND logic, allow for computational efficiency through a combination of numerous CMOS transistors and limited logic functions.

[0046] Unlike the logical units in ordinary computing devices, the basic computing unit in current quantum computers is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its usage time and is not always available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is a crucial challenge. The number of qubits is also one of the representative indicators of a quantum computer's performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), RX gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum logic gates are generally represented using unitary matrices. A unitary matrix is ​​not only a matrix form but also a type of operation and transformation. In general, the action of a quantum logic gate on a quantum state is calculated by left-multiplying a unitary matrix by the matrix corresponding to the right vector of the quantum state. In quantum computing, a finite number of qubits combined with diverse logical functions achieves computational effects.

[0047] Given these differences in quantum computers, the design of logical functions applied to qubits (including the design of whether qubits are used and the design of the efficiency of each qubit's use) is crucial for improving the computational performance of quantum computers and requires specialized design. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to address. Therefore, this invention proposes a variable double modular multiplication operator, a computation method, and related devices to realize double modular multiplication of input data in quantum computing.

[0048] See Figure 2 , Figure 2 This is a schematic diagram of a variable doubling modular multiplication operator provided in an embodiment of the present invention. The variable doubling modular multiplication operator 200 includes a doubling operation module 210 and a modulus operation module 220 cascaded together. The constant in the modulus operation module 220 includes a modulus. The doubling operation module 210 is used to determine the doubling of the input data to be multiplied, and the modulus operation module 220 is used to calculate the modulus operation result of doubling the data to be multiplied and the modulus.

[0049] In this system, the inputs and outputs of the variable doubling modular multiplication unit 200, the doubling operation module 210, and the modular number operation module 220 are all qubits. Classical data is encoded onto the quantum states of the qubits, and the encoding method can be angle encoding, amplitude encoding, ground state encoding, etc. The doubling operation module 210 and the modular number operation module 220 can include quantum logic gates, which act on the quantum states to cause them to evolve.

[0050] For example, the data to be multiplied x is encoded into the quantum state |x> of the qubit, and then used as the input of the variable doubling modular multiplication operator, that is, the input of the doubling operation module 210; after the action of the doubling operation module 210, the quantum state evolves into |2x>, which is then input to the modular multiplication module 220. After the action, it evolves to obtain |2x mod p>, that is, the output of the variable doubling modular multiplication operator 200, where p is the modulus; finally, |2x mod p> is converted into classical data, that is, the modular multiplication result 2x mod p of the data to be multiplied x (2x) and the modulus p can be obtained.

[0051] Wherein, the modulus p is an odd prime number, that is, p is both odd and prime. The number of qubits is as follows. x∈[0, p-1].

[0052] The double operation module 210 includes one of the following operations: data misalignment storage, adder, and SWAP gate.

[0053] For example, data is encoded using n+1 qubits, where the binary representation is x = |x0>|x1>...|x... n-1 >, then 2x = |0>|x0>|x1>···|x n-1 >

[0054] The data is stored in a staggered manner, that is, the 0th qubit is skipped, and x0 is directly stored in the 1st qubit, x1 is stored in the 2nd qubit, and so on. n-1 Storing it on the nth qubit, we eventually get |0>|x0>|x1>···|x n-1 >;

[0055] Alternatively, x and x can be added together using an adder, ultimately resulting in |0>|x0>|x1>···|x n-1 >;

[0056] Alternatively, the first n qubits can be stored as |x0>|x1>...|x n-1The last qubit stores |0>. Using n SWAP gates, the stored |0> is shifted to the 0th qubit. The |x0> on the 0th qubit is shifted to the 1st qubit, and so on, until the |x0> on the (n-2)th qubit... n-1 Shifting to the last qubit, we can ultimately obtain |0>|x0>|x1>···|x n-1 >

[0057] See Figure 3 , Figure 3 This is a schematic diagram of another variable doubling modular multiplication operator provided in an embodiment of the present invention. One input terminal 200a1 of the variable doubling modular multiplication operator 200 is connected to the input terminal 210a of the doubling module 210, the output terminal 210b of the doubling module 210 is connected to one input terminal 220a1 of the modular multiplication module 220, and the other input terminal 200a2 of the variable doubling modular multiplication operator 200 is connected to the other input terminal 220a2 of the modular multiplication module 220. One input terminal 200a1 of the variable doubling modular multiplication operator 200 is used to input the quantum state |x> corresponding to the data to be multiplied x, and the other input terminal 200a2 of the variable doubling modular multiplication operator 200 is used to input the quantum state corresponding to the initial auxiliary data.

[0058] The initial auxiliary data can be, for example, 0, 1, or other values.

[0059] See Figure 4 , Figure 4 This is a schematic diagram of a modular arithmetic module provided in an embodiment of the present invention. The modular arithmetic module 220 includes a constant subtractor 221, a first CNOT gate 222, and a controlled constant adder 223 cascaded together, wherein the constant in the constant subtractor 221 and the controlled constant adder 223 is the modulus.

[0060] The constant subtractor 221 has an output terminal 221b including a data output terminal 221bm and a sign output terminal 221bn. One of the input terminals 223a1 of the controlled constant adder 223 includes a data input terminal 223a1m and a sign input terminal 223a1n. The data output terminal 221bm of the constant subtractor 221 is connected to the data input terminal 223a1m of the controlled constant adder 223. The sign output terminal 221bn of the constant subtractor 221 is connected to one of the input terminals 222a1 of the first CNOT gate 222. The two output terminals 222b1 and 222b2 of the first CNOT gate 222 are respectively connected to the sign input terminal 223a1n and the other input terminal 223a2 of the controlled constant adder 223.

[0061] Among them, the two output terminals 223b1 and 223b2 of the controlled constant adder 223 are respectively used to output the quantum state |2x mod p> corresponding to the modulus operation result of twice the data to be multiplied and the quantum state corresponding to the intermediate auxiliary data.

[0062] Among them, the two output terminals 223b1 and 223b2 of the controlled constant adder 223 are respectively connected to the two output terminals 200b1 and 200b2 of the variable double modulo multiplier 200.

[0063] In some embodiments of the present invention, the initial auxiliary data is 0, and the corresponding quantum state is |0>. After passing through the constant subtractor 221, the quantum state evolves into |2x - p>, and then the magnitudes of 2x and p are compared through the first CNOT gate 222.

[0064] If 2x ≥ p, the quantum state of the quantum bit representing the sign of 2x - p is |0>, the first CNOT gate 222 and the controlled constant adder 223 will not be executed, and the quantum state corresponding to the modulus operation result of twice the data to be multiplied output is |2x - p>, and the quantum state corresponding to the intermediate auxiliary data is |0>;

[0065] On the contrary, if 2x < p, the quantum state of the quantum bit representing the sign of 2x - p is |1>, both the first CNOT gate 222 and the controlled constant adder 223 will be executed, and the quantum state corresponding to the modulus operation result of twice the data to be multiplied output is |2x>, and the quantum state corresponding to the intermediate auxiliary data is |1>.

[0066] It can be seen that in the design of the quantum circuit in the embodiments of the present invention, whether 2x is greater than or equal to or less than p, 2x mod p can be calculated. However, if 2x < p, the quantum state of the auxiliary quantum bit used to encode the initial auxiliary data will evolve from |0> to |1>, resulting in the inability to reuse this quantum bit in subsequent other calculations.

[0067] To solve the problem that the auxiliary quantum bit used to encode the initial auxiliary data cannot be reused, the present invention provides another specific embodiment.

[0068] See Figure 5 , Figure 5This is a schematic diagram of another modular arithmetic module provided in an embodiment of the present invention. The constant subtractor 221, the first CNOT gate 222, and the controlled constant adder 223 constitute a first arithmetic submodule 220A. The modular arithmetic module 220 further includes a second arithmetic submodule 220B cascaded with the first arithmetic submodule 220A. The second arithmetic submodule 220B is used to reset the intermediate auxiliary data to the initial auxiliary data.

[0069] The second sub-operation module 220B includes a first NOT gate 224, a second CNOT gate 225, and a second NOT gate 226 cascaded in sequence. One output terminal 223b1 of the controlled constant adder 223 includes a low-order output terminal 223b1m and a non-low-order output terminal 223b1n. The low-order output terminal 223b1m of the controlled constant adder 223 is connected to the input terminal 224a of the first NOT gate 224. The other output terminal 223b2 of the controlled constant adder 223 is connected to one of the input terminals 225a1 of the second CNOT gate 225.

[0070] Specifically, the output terminal 224b of the first NOT gate 224 is connected to the other input terminal 225a2 of the second CNOT gate 225, and the other output terminal 225b2 of the second CNOT gate 225 is connected to the input terminal 226a of the second NOT gate 226.

[0071] Wherein, the output terminal 226b of the second NOT gate 226 and the non-low-order output terminal 223b1n of the controlled constant adder 223 are used to output the quantum state corresponding to the result of the modulo operation of twice the data to be multiplied, and one of the output terminals 225b1 of the second CNOT gate 225 is used to output the quantum state corresponding to the initial auxiliary data.

[0072] Specifically, the output terminal 226b of the second NOT gate 226 and the non-low-order output terminal 223b1n of the controlled constant adder 223 are connected to one of the output terminals 200b1 of the variable double modular multiplication operator 200, and one of the output terminals 225b1 of the second CNOT gate 225 is connected to the other output terminal 400b2 of the variable double modular multiplication operator 400.

[0073] It can be seen that if 2x≥p, the output |2x-p> is odd. Therefore, the quantum state output by the low-order output terminal 223b1m is |1>. After the first NOT gate 224 is activated, it evolves into |0>. The second CNOT gate 225 will not be executed. After the second NOT gate 226 is activated again, it evolves back into |1>. Finally, the quantum state corresponding to the result of the modulo operation between the doubled data to be multiplied and the modulus is still |2x-p>. At the same time, the quantum state corresponding to the auxiliary qubit is |0>.

[0074] If 2x < p, the output |2x> is an even number. Therefore, the quantum state output by the low - order output terminal 223b1m is |0>. After the first NOT gate 224 acts on it, it evolves into |1>. The second CNOT gate 225 will be executed, and the quantum state corresponding to the auxiliary qubit is reset from |1> to |0>. The second NOT gate 226 evolves the obtained |1> into |0> again. Thus, the quantum state corresponding to the result of the modulo operation of twice the data to be multiplied and the modulus is still |2x>, but the quantum state corresponding to the auxiliary qubit is reset to |0>.

[0075] It can be seen that in the design of the quantum circuit in the embodiment of the present invention, whether 2x is greater than or equal to or less than p, 2x mod p can be calculated. At the same time, the quantum state of the auxiliary qubit used to encode the initial auxiliary data is also reset and can be used for other calculations later.

[0076] The constant subtractor and the controlled constant adder can be implemented by the adder in the Chinese patent document with the application number "202211114262.1" and the application name "Constant Adder, Operation Method and Related Device Based on Quantum Fourier Transform". There can also be other implementation manners, which are not limited herein.

[0077] See Figure 6 , Figure 6 is a schematic flowchart of a method for variable double - modulo multiplication provided by an embodiment of the present invention. The method includes:

[0078] Step 601: Obtain the variable double - modulo multiplier and the data to be multiplied in the above - mentioned embodiment;

[0079] Step 602: Input the data to be multiplied into the variable double - modulo multiplier and run the variable double - modulo multiplier to obtain the quantum state corresponding to the result of the modulo operation of twice the data to be multiplied and the modulus;

[0080] Step 603: Determine the result of the modulo operation of twice the data to be multiplied and the modulus based on the quantum state corresponding to the modulo operation result.

[0081] See Figure 7 , Figure 7 is a schematic structural diagram of a variable double - modulo multiplication device provided by an embodiment of the present invention. The device includes:

[0082] An obtaining unit 701, configured to obtain the variable double - modulo multiplier and the data to be multiplied in the above - mentioned embodiment;

[0083] The computing unit 702 is used to input the data to be multiplied into the variable double modular multiplication operator, and to run the variable double modular multiplication operator to obtain the quantum state corresponding to the modular operation result of the data to be multiplied twice and the modulus;

[0084] The determining unit 703 is used to determine the result of the modulo operation between twice the data to be multiplied and the modulus based on the quantum state corresponding to the modulo operation result.

[0085] Another embodiment of the present invention provides a storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the method embodiments above when running.

[0086] Specifically, in this embodiment, the storage medium can be configured to store a computer program for performing the following steps:

[0087] Obtain the variable double modular multiplication operator and the data to be doubled as described in the above embodiments;

[0088] The data to be multiplied is input into the variable doubling modular multiplication operator, and the variable doubling modular multiplication operator is run to obtain the quantum state corresponding to the modular operation result of the data to be multiplied twice and the modulus;

[0089] Based on the quantum state corresponding to the modulus operation result, determine the result of the modulus operation between twice the data to be multiplied and the modulus.

[0090] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.

[0091] Another embodiment of the present invention provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the method embodiments described above.

[0092] Specifically, the aforementioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the aforementioned processor, and the input / output device is connected to the aforementioned processor.

[0093] Specifically, in this embodiment, the processor can be configured to perform the following steps via a computer program:

[0094] Obtain the variable double modular multiplication operator and the data to be doubled as described in the above embodiments;

[0095] The data to be multiplied is input into the variable doubling modular multiplication operator, and the variable doubling modular multiplication operator is run to obtain the quantum state corresponding to the modular operation result of the data to be multiplied twice and the modulus;

[0096] Based on the quantum state corresponding to the modulus operation result, determine the result of the modulus operation between twice the data to be multiplied and the modulus.

[0097] The above description, based on the embodiments shown in the figures, details the structure, features, and effects of the present invention. The above description is only a preferred embodiment of the present invention, but the present invention is not limited to the scope of implementation shown in the figures. Any changes made in accordance with the concept of the present invention, or equivalent embodiments modified to have equivalent changes, that do not exceed the spirit covered by the specification and figures, should be within the protection scope of the present invention.

Claims

1. A variable double modular multiplication operator, characterized by, The variable double modulo multiplication operator comprises a double operation module and a modulus operation module connected in sequence, constants in the modulus operation module comprise a modulus, the double operation module is used for determining double of input data to be multiplied, and the double operation module comprises one of the following operations: an operation of storing data in a staggered manner, an adder, and a SWAP gate; the modulus operation module is used for calculating a modulus operation result of the double of the data to be multiplied and the modulus, and the modulus operation module comprises a constant subtractor, a first CNOT gate, and a controlled constant adder connected in sequence, and constants in the constant subtractor and the controlled constant adder are the modulus; one input end of the variable double modulo multiplication operator is connected with an input end of the double operation module, an output end of the double operation module is connected with one input end of the modulus operation module, another input end of the variable double modulo multiplication operator is connected with another input end of the modulus operation module, one input end of the variable double modulo multiplication operator is used for inputting a quantum state corresponding to the data to be multiplied, and another input end of the variable double modulo multiplication operator is used for inputting a quantum state corresponding to initial auxiliary data.

2. The variable double modulo multiplier as described in claim 1, wherein, An output end of the constant subtractor comprises a data output end and a symbol output end, one input end of the controlled constant adder comprises a data input end and a symbol input end, the data output end of the constant subtractor is connected with the data input end of the controlled constant adder, the symbol output end of the constant subtractor is connected with one input end of the first CNOT gate, and two output ends of the first CNOT gate are respectively connected with the symbol input end and another input end of the controlled constant adder.

3. The variable double modulo multiplier as described in claim 2, wherein, Two output ends of the controlled constant adder are respectively used for outputting quantum states corresponding to a modulus operation result of the double of the data to be multiplied and the modulus and quantum states corresponding to intermediate auxiliary data.

4. The variable double modulo multiplier as described in claim 3, wherein, The two output ends of the controlled constant adder are respectively connected with two output ends of the variable double modulo multiplication operator.

5. The variable double modulo multiplier as described in claim 3, wherein, The constant subtractor, the first CNOT gate, and the controlled constant adder are a first operation sub-module, the modulus operation module further comprises a second operation sub-module connected with the first operation sub-module in sequence, and the second operation sub-module is used for resetting the intermediate auxiliary data to the initial auxiliary data.

6. The variable double modulo multiplier as described in claim 5, wherein, The second operation sub-module comprises a first NOT gate, a second CNOT gate, and a second NOT gate connected in sequence, one output end of the controlled constant adder comprises a low-bit output end and a non-low-bit output end, the low-bit output end of the controlled constant adder is connected with an input end of the first NOT gate, and another output end of the controlled constant adder is connected with one input end of the second CNOT gate.

7. The variable double modulo multiplier as described in claim 6, wherein, An output end of the first NOT gate is connected with another input end of the second CNOT gate, and another output end of the second CNOT gate is connected with an input end of the second NOT gate.

8. The variable double modulo multiplier as described in claim 7, wherein, An output end of the second NOT gate is connected with a non-low bit output end of the controlled constant adder, and an output end of the second CNOT gate is used for outputting a quantum state corresponding to the initial auxiliary data.

9. The variable double modulo multiplier as described in claim 8, wherein, An output end of the second NOT gate, a non-low bit output end of the controlled constant adder and one output end of the variable double modulus multiplication operator are connected, and one output end of the second CNOT gate is connected with the other output end of the variable double modulus multiplication operator.

10. A method of variable double modular multiplication, characterized in that, The method comprises: obtaining the variable double modulus multiplication operator and the data to be multiplied according to any one of claims 1-9; inputting the data to be multiplied into the variable double modulus multiplication operator, and running the variable double modulus multiplication operator to obtain a quantum state corresponding to a result of modulus operation of a double of the data to be multiplied and the modulus; determining the result of modulus operation of the double of the data to be multiplied and the modulus based on the quantum state corresponding to the result of modulus operation.

11. A variable double modular multiplication device, characterized by comprising: The device comprises: an obtaining unit configured to obtain the variable double modulus multiplication operator and the data to be multiplied according to any one of claims 1-9; a calculating unit configured to input the data to be multiplied into the variable double modulus multiplication operator, and run the variable double modulus multiplication operator to obtain a quantum state corresponding to a result of modulus operation of a double of the data to be multiplied and the modulus; a determining unit configured to determine the result of modulus operation of the double of the data to be multiplied and the modulus based on the quantum state corresponding to the result of modulus operation.

12. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the method in claim 10 when running. 13.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to execute the computer program to execute the method in claim 10.

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