Solar cell and preparation method thereof

Abstract

The present application relates to the field of solar cell technology, and in particular to a solar cell and its preparation method, which can reduce process steps, thereby meeting the increasing demand for simplified process steps and reducing costs. A method for preparing a solar cell includes: forming a first silicon glass film on a silicon substrate layer having a PN junction, on a surface of the PN junction facing away from the silicon substrate layer; removing a portion of the first silicon glass film corresponding to a first region to form a first silicon glass pattern; forming a first tunneling oxide layer on the first surface and located in the first region; using a deposition process and a plasma etching process, depositing first doped silicon on the first silicon glass pattern and on a surface of the first tunneling oxide layer facing away from the silicon substrate layer, such that the first doped silicon is deposited only on the surface of the first tunneling oxide layer; removing the first silicon glass pattern; and sequentially forming a first passivation layer and a first gate line pattern on a portion of the PN junction corresponding to a second region and on the surface of the first doped silicon.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] N-type TOPCon (Tunnel Oxide Passivated Contact) solar cell technology is favored by many cell manufacturers due to its high compatibility with PERC (Passivated Emitter and Rear Cell) (it can be upgraded based on existing PERC production lines). For example, N-type TOPCon cells add a tunnel oxide layer and N-type doped polysilicon layer to PERC cells, enabling the rear structure of the N-type TOPCon cell to form a good passivation contact. However, the front passivation of the N-type TOPCon cell has not been significantly improved compared with the previous generation technology.

[0003] Currently, there is a solution to further improve the passivation effect of the N-type TOPCon cell and reduce the parasitic absorption of the P-type doped polysilicon layer by preparing a tunneling oxide layer and a P-type doped polysilicon layer on the front of the N-type TOPCon cell and removing the P-type doped polysilicon layer and the tunneling oxide layer in the non-gate line area.

[0004] However, the current process requires removing portions of the P-type doped polysilicon layer and the tunnel oxide layer corresponding to the non-gate line area after preparing the P-type doped polysilicon layer. The removal process is complex and involves many steps, which cannot meet the growing demand for simplifying process steps. Summary of the Invention

[0005] Based on this, it is necessary to provide a solar cell and a method for preparing the same, which can reduce the number of steps, thereby meeting the increasing demand for simplifying process steps and reducing costs.

[0006] In a first aspect, a method for preparing a solar cell is provided, comprising:

[0007] Providing a silicon substrate layer, the silicon substrate layer comprising a first surface and a second surface disposed opposite to each other along a thickness direction thereof, a PN junction formed on the first surface, and a first silicon glass thin film formed on a surface of the PN junction facing away from the silicon substrate layer, wherein the first silicon glass thin film is doped with a first doping element and an oxygen element;

[0008] Removing a portion of the first silicon glass film corresponding to a first area to form a first silicon glass pattern, wherein the first silicon glass pattern covers a portion of the PN junction corresponding to a second area, while exposing a portion of the PN junction corresponding to the first area, wherein the first area is an area where a grid line pattern of the solar cell is located, and the second area is a remaining area of the first surface excluding the area where the grid line pattern is located, wherein the grid line pattern includes a first grid line pattern located on the first surface and a second grid line pattern located on the second surface;

[0009] forming a first tunneling oxide layer on the first surface and in the first region;

[0010] Depositing first doped silicon on surfaces of the first silicon glass pattern and the first tunnel oxide layer facing away from the silicon base layer using a deposition process and a plasma etching process, and utilizing the difference between the deposition rate and etching rate of the first doped silicon on the first silicon glass pattern and the first tunnel oxide layer so that the first doped silicon is deposited on the surface of the first tunnel oxide layer, while exposing the first silicon glass pattern;

[0011] removing the first silicon glass pattern to expose a portion of the PN junction corresponding to the second region;

[0012] A first passivation layer and a first gate line pattern are sequentially stacked on a portion of the PN junction corresponding to the second region and a surface of the first doped silicon. The first gate line pattern passes through the first passivation layer and is electrically connected to the first doped polysilicon layer.

[0013] Optionally, the first doping element is a P-type doping element, and the first silicon glass film is a borosilicate glass film.

[0014] Optionally, removing a portion of the first silicon glass film corresponding to the first area to form a first silicon glass pattern includes:

[0015] Laser ablation is used to remove a portion of the first silicon glass film corresponding to the first area to form the first silicon glass pattern.

[0016] Optionally, a deposition process and a plasma etching process are used to deposit first doped silicon on surfaces of the first silicon glass pattern and the first tunnel oxide layer facing away from the silicon base layer, comprising:

[0017] In the same chamber, chemical vapor deposition and plasma etching are cyclically performed, utilizing the fact that a deposition rate of the first doped silicon on the first silicon glass pattern is less than a deposition rate of the first doped silicon on the first tunnel oxide layer, while an etching rate of the first doped silicon on the first silicon glass pattern is greater than an etching rate of the first doped silicon on the first tunnel oxide layer, so that the deposition of the first doped silicon on the first tunnel oxide layer is at least partially retained, while the deposition of the first doped silicon on the first silicon glass pattern is removed.

[0018] Optionally, a ratio of a deposition rate of the first doped silicon on the first tunnel oxide layer to a deposition rate of the first doped silicon on the first silicon glass pattern is 1:1~1.5:1, and a ratio of an etching rate of the first doped silicon on the first tunnel oxide layer to an etching rate of the first doped silicon on the first silicon glass pattern is 0.05:1~0.2:1.

[0019] Optionally, the number of cycles is 5 to 20 times, and in each cycle, the ratio of the chemical vapor deposition time to the plasma etching time is 3:1 to 12:1.

[0020] Optionally, in each cycle, the chemical vapor deposition time is 24s to 36s, and the plasma etching time is 3s to 8s.

[0021] Optionally, while forming the first tunneling oxide layer on the first surface and in the first region, the preparation method further includes:

[0022] A second tunneling oxide layer is formed on the second surface and located in the first region and the second region by the same preparation process as that of the first tunneling oxide layer.

[0023] Optionally, the first doped silicon is first doped amorphous silicon; after depositing the first doped silicon on surfaces of the first silicon glass pattern and the first tunneling oxide layer facing away from the silicon base layer using a deposition process and a plasma etching process, the preparation method further comprises:

[0024] forming a second doped amorphous silicon on a surface of the second tunnel oxide layer facing away from the silicon base layer; and

[0025] The first doped amorphous silicon is converted into first doped polysilicon, and the second doped amorphous silicon is converted into second doped polysilicon by annealing.

[0026] Optionally, in the deposition process, the reaction gases used include: a silicon source, a hydrogen source, and a boron source;

[0027] In the plasma etching process, the reaction gases used include: a plasma gas source and a fluorine-containing gas source, wherein the plasma gas source is used to generate plasma to etch the first doped silicon deposited on the first silicon glass pattern and the first tunneling oxide layer, and the fluorine-containing gas source is used to form silicon fluoride gas with the etched first doped silicon, and the etched first doped silicon is removed by the silicon fluoride gas being extracted.

[0028] Optionally, in the deposition process, the pressure in the reaction chamber is 200 MPa to 400 MPa, the power of the power supply is 8000 W to 14000 W, and the sum of the flow rates of the silicon source, the hydrogen source, and the boron source is 10700 sccm to 18800 sccm;

[0029] In the plasma etching process, the pressure in the chamber is 100 MPa~250 MPa, the power of the power supply is 6000 W~10000 W, the sum of the flow rates of the non-reactive plasma gas source and the fluorine-containing gas source is 300 sccm~3800 sccm, and the molar ratio of the plasma element in the non-reactive plasma gas source to the fluorine element in the fluorine-containing gas source is 2:1~5:1.

[0030] Optionally, removing the first silicon glass pattern to expose a portion of the PN junction corresponding to the second region includes:

[0031] The first silicon glass pattern is dissolved and removed by using hydrofluoric acid to expose a portion of the PN junction corresponding to the second region.

[0032] In a second aspect, a solar cell is provided, which is prepared by the preparation method described in the first aspect.

[0033] The solar cell and its preparation method provided by this application have the following beneficial technical effects:

[0034] By forming a first silicon glass film on the surface of the PN junction facing away from the silicon base layer, on the one hand, the first silicon glass film can protect the PN junction during alkali polishing of the back side, and on the other hand, by patterning the first silicon glass film, that is, forming the first silicon glass pattern only in the remaining areas of the first surface except the area where the first gate line pattern is located, and utilizing the different deposition rates and etching rates of the first doped silicon on the first silicon glass pattern and the first tunneling oxide layer, the first doped silicon can be formed only on the first tunneling oxide layer and not deposited on the first silicon glass pattern. By controlling the large difference in properties between the first silicon glass pattern and the first tunneling oxide layer, the first silicon glass pattern formed in the second area can be removed while retaining the first tunneling oxide layer formed in the first area (that is, the area where the first gate line pattern is located), thereby forming a passivation structure on the front side of the solar cell while achieving partial coverage of the first doped silicon, that is, the first doped silicon is formed only in the first area, thereby reducing parasitic absorption. Compared with the related art that requires forming a first tunneling oxide film and a first doped polysilicon film that fully covers the PN junction, and requires an additional patterning process to remove the portion of the first doped polysilicon film located in the second region, this patterning process utilizes the first silicon glass pattern as a mask, and completes the local deposition of the first doped silicon by taking advantage of the different deposition rates and etching rates of the first doped silicon on different materials. On the one hand, it can reduce the number of steps and does not introduce additional developer to achieve the patterning of the first doped silicon. On the other hand, it does not require setting an additional mask, avoiding the introduction and removal of other mask materials. In summary, the method for preparing a solar cell provided in the embodiment of the present application can reduce the number of steps, thereby meeting the increasing demand for simplifying process steps and reducing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic diagram of a process for preparing a first tunneling oxide layer and a second tunneling oxide layer in a solar cell provided in an embodiment of the present application;

[0036] Figure 2 A schematic diagram of a process for forming a first doped polysilicon layer, a first passivation layer, and a first gate line pattern on a first silicon glass pattern and a first tunnel oxide layer is provided in an embodiment of the present application. DETAILED DESCRIPTION

[0037] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below with reference to the accompanying drawings. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar improvements without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0038] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0039] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0040] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0041] As used herein, unless otherwise specified, "one or more" means one or more than two.

[0042] Herein, terms such as "for example," "such as," "example," and "for instance" are used for descriptive purposes to indicate a connection between the preceding and following technical solutions. However, they should not be construed as limiting the preceding technical solution or the scope of protection herein. Unless otherwise specified, "A (such as B)" means that B is a non-limiting example of A, and it should be understood that A is not limited to B.

[0043] As used herein, "optionally," "optional," and "optional" mean optional or dispensable, meaning that the option is selected from either of two parallel options: "optional" or "optional." If a technical solution contains multiple "optional" clauses, each "optional" clause is considered independent unless otherwise specified and there are no conflicts or constraints.

[0044] Herein, descriptions such as “optionally contain” and “optionally include” mean “contain or not contain”. “Optional component X” means component X is present or not, or contains or not contains the component X.

[0045] In this document, the terms "first" and "second" in "the first aspect" and "the second aspect" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or quantity, nor can they be understood as implicitly indicating the importance or quantity of the indicated technical features.

[0046] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intermediate element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be an intermediate element. The terms "vertical," "horizontal," "upper," "lower," "left," "right," and similar expressions used herein are for illustrative purposes only and do not represent the only implementation methods.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0048] In this article, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features.

[0049] In this document, "at least one" means more than one, such as one, two, or more than two. "Multiple" or "several" means at least two, such as two, three, etc., and "multi-layer" means at least two layers, such as two, three, etc., unless otherwise specifically defined. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0050] As used herein, when referring to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values within the numerical interval is deemed to be continuous and includes the two numerical endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between the two numerical endpoints. Unless otherwise specified, when a numerical interval refers only to integers within the numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe a feature or characteristic, these numerical ranges can be combined. In other words, unless otherwise specified, the numerical ranges disclosed herein should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. "Numerical interval" allows for a broad range of numerical interval types including percentage intervals, ratio intervals, and ratio intervals.

[0051] In this article, unless otherwise specified, the percentage content refers to mass percentage for solid-liquid mixing and solid-solid mixing, and refers to volume percentage for liquid-liquid mixing.

[0052] In this article, percentage concentrations, unless otherwise specified, refer to final concentrations, which are the percentage of an added ingredient in the system after the ingredient is added.

[0053] As used herein, %(w / w) and wt% both refer to weight percentage, %(v / v) refers to volume percentage, and %(w / v) refers to mass volume percentage.

[0054] In this article, when it comes to temperature parameters, unless otherwise specified, both constant temperature treatment and treatment within a certain temperature range are permitted. The constant temperature treatment allows the temperature to fluctuate within the precision range controlled by the instrument.

[0055] Herein, the term "room temperature" or "normal temperature" generally refers to 4°C to 35°C, for example, 20°C ± 5°C. In some embodiments herein, "room temperature" or "normal temperature" refers to 10°C to 30°C. In some embodiments herein, "room temperature" or "normal temperature" refers to 20°C to 30°C.

[0056] As used herein, fill factor (FF) is the ratio of the maximum practically achievable power (Pm or Vmp * Jmp) to the theoretical (not practically achievable) power (Jsc * Voc). Therefore, FF can be determined by the following formula:

[0057] FF = (Vmp * Jmp) / (Jsc * Voc)

[0058] Where Jmp and Vmp represent the current density and voltage at the maximum power point (Pm), respectively. This point is achieved by varying the resistance in the circuit until J * V reaches its maximum value. Jsc and Voc represent the short-circuit current and open-circuit voltage, respectively. Fill factor is a key parameter for evaluating solar cells. Commercial solar cells typically have a fill factor of approximately 60% or higher.

[0059] As used herein, open circuit voltage (Voc) is the potential difference between the anode and cathode of a device with no external load connected.

[0060] The power conversion efficiency (PCE) of a solar cell used in this article refers to the percentage of power converted from absorbed light to electrical energy. The power conversion efficiency (PCE) of a solar cell can be measured by the incident light irradiance (E: W / m 2 ) and the surface area of the solar cell (Ac:m 2) divided by the maximum power point (Pm). STC usually refers to the temperature of 25℃ and the irradiance of 1000 W / m 2 , the spectrum of air mass 1.5 (AM1.5).

[0061] In view of the situation in which a tunnel oxide layer and a doped polysilicon layer are also prepared on the front side of the TOPCon battery in related technologies, it is crucial to achieve patterning of the doped polysilicon layer when preparing the tunnel oxide layer and the doped polysilicon layer, reduce parasitic absorption while reducing the number of steps, and meet the growing demand for simplifying process steps.

[0062] Based on the above technical problems, in the first aspect, some embodiments of the present application provide a method for preparing a solar cell 1, such as Figure 1 and Figure 2 As shown, the preparation method includes the following steps S11) to S16):

[0063] S11), providing a silicon substrate layer 11, the silicon substrate layer 11 including a first surface 11a and a second surface 11b opposite to each other along a thickness direction thereof, a PN junction formed on the first surface 11a, and a first silicon glass film 100 formed on a surface of the silicon substrate layer away from the PN junction, wherein the first silicon glass film 100 is doped with a first doping element and oxygen;

[0064] Among them, the solar cell can be a P-type Topcon cell or an N-type Topcon cell. When the solar cell is a P-type Topcon cell, the silicon base layer 11 is a P-type silicon base. At this time, the first doping element can be a P element, and the first silicon glass film 100 is phosphorus silicon glass; when the solar cell is an N-type Topcon cell, the silicon base layer 11 is an N-type silicon base. At this time, the first doping element can be a P-type doping element, and the first silicon glass film 100 is a borosilicate glass film.

[0065] In the following embodiments, the silicon substrate layer 11 is an N-type silicon substrate, the first doping element is a P-type doping element, and the first silicon glass film 100 is a borosilicate glass film.

[0066] In some embodiments, either ion implantation or thermal diffusion can be used to dope the first surface 11a of the silicon base layer 11 with B elements, forming a PN junction on the silicon base layer 11, and forming a borosilicate glass film doped with B elements and oxygen elements on the surface of the PN junction away from the silicon base layer 11.

[0067] In some embodiments, the sheet resistance of the P region in the PN junction is 100Ω / sqr to 200Ω / sqr, and the sheet resistance of the first silicon glass film 100 is 200Ω / sqr to 300Ω / sqr.

[0068] In these embodiments, the square resistance of the P region is 100Ω / sqr to 200Ω / sqr, which can meet the carrier transport requirements of the solar cell. The square resistance of the first silicon glass film 100 is 200Ω / sqr to 300Ω / sqr, which can reduce carrier recombination in the solar cell while maximizing the difference in properties between the first silicon glass film 100 and the first tunneling oxide layer mentioned below. This allows the subsequently formed first silicon glass pattern 101 to be completely removed while minimizing damage to the first tunneling oxide layer.

[0069] S12), removing the portion of the first silicon glass film 100 corresponding to the first area A to form a first silicon glass pattern 101, the first silicon glass pattern 101 covers the portion of the PN junction corresponding to the second area B, and exposes the portion of the PN junction corresponding to the first area A, the first area A is the area where the grid line pattern of the solar cell is located, the second area B is the remaining area of the first surface except the area where the grid line pattern is located, and the grid line pattern includes a first grid line pattern L1 located on the first surface 11a and a second grid line pattern located on the second surface.

[0070] Removing a portion of the first silicon glass film 100 corresponding to the first region A to form the first silicon glass pattern 101 may include:

[0071] Laser ablation is used to remove the portion of the first silicon glass film 100 corresponding to the first region A to form a first silicon glass pattern 101 .

[0072] In these embodiments, laser ablation is used to selectively remove the portion of the first silicon glass film 100 corresponding to the first region A, while retaining the portion of the first silicon glass film 100 corresponding to the second region B, thereby forming the first silicon glass pattern 101 .

[0073] The first silicon glass pattern 101 covers a portion of the PN junction corresponding to the second region B, while exposing a portion of the PN junction corresponding to the first region A.

[0074] Since the first region A is where the gridline patterns of the solar cell are located, and the gridline patterns include the first gridline pattern L1 located on the first surface 11a and the second gridline pattern located on the second surface, the first gridline pattern L1 and the second gridline pattern can both be located in the first region A.

[0075] S13), forming a first tunnel oxide layer 12 on the first surface 11a and located in the first area A;

[0076] The surface of the portion of the PN junction corresponding to the first region A exposed by the first silicon glass pattern 101 may be oxidized to form a first tunneling oxide layer 12 .

[0077] For example, a thermal oxidation process may be used to oxidize a portion of the surface of the first region A corresponding to the PN junction exposed by the first silicon glass pattern 101 to form the first tunneling oxide layer 12 .

[0078] In some embodiments, while forming the first tunnel oxide layer 12 on the first surface 11 a and in the first region A, the preparation method may further include:

[0079] The second tunnel oxide layer 13 is formed on the second surface 11 b and located in the first region A and the second region B by the same preparation process as that of the first tunnel oxide layer 12 .

[0080] In these embodiments, the first tunnel oxide layer 12 and the second tunnel oxide layer 13 may be formed simultaneously by a one-step process.

[0081] It should be noted that, in step S11), the first surface 11a and the second surface 11b of the silicon substrate layer 11 may also be formed with a velvet structure. This is because, by forming a velvet structure on the first surface 11a of the silicon substrate layer 11, the anti-reflection performance of the solar cell can be improved, thereby improving the utilization rate of sunlight; and during the velvet treatment, a velvet structure is usually formed on both the first surface 11a and the second surface 11b of the silicon substrate layer 11, and when the first silicon glass film 100 is formed on the surface of the PN junction away from the silicon substrate layer 11, a wrap-around plating is also formed on the second surface 11b.

[0082] Based on this, before forming the second tunnel oxide layer 13 on the second surface 11 b and located in the first region A and the second region B by the same preparation process as that of the first tunnel oxide layer 12, the preparation method may further include:

[0083] S101 ), removing the first silicon glass film 100 plated on the second surface 11 b , and performing alkali polishing on the second surface 11 b of the silicon base layer 11 .

[0084] For example, the first silicon glass film plated on the second surface 11b can be removed by contacting the second surface 11b with hydrofluoric acid, and the suede structure of the second surface 11b of the silicon base layer 11 can be alkaline polished using an alkaline polishing solution.

[0085] In some embodiments of the present application, Figure 1 As shown, step S101) can occur before step S12). Thus, when the suede structure of the second surface 11b of the silicon substrate layer 11 is alkaline-polished using an alkaline polishing solution, the first silicon glass film 100 completely covers the PN junction, thereby protecting the PN junction.

[0086] S14) Figure 2As shown, a deposition process and a plasma etching process are used to deposit the first doped silicon 14 on the surface of the first silicon glass pattern 101 and the first tunneling oxide layer 12 away from the silicon base layer 11. The deposition rate and etching rate of the first doped silicon 14 on the first silicon glass pattern 101 and the first tunneling oxide layer 12 are different, so that the first doped silicon 14 is deposited on the surface of the first tunneling oxide layer 12, while the first silicon glass pattern 101 is exposed.

[0087] The deposition rate and etching rate of the first doped silicon 14 on the first silicon glass pattern 101 and the first tunnel oxide layer 12 are different. For example, the deposition rate of the first doped silicon 14 on the first silicon glass pattern 101 is lower, while the deposition rate on the first tunnel oxide layer 12 is higher. The etching rate of the first doped silicon 14 on the first silicon glass pattern 101 is higher, while the etching rate on the first tunnel oxide layer 12 is lower. By controlling the deposition process time and the plasma etching process time, the portion of the first doped silicon 14 deposited on the surface of the first tunnel oxide layer 12 is not completely etched away, while the first doped silicon deposited on the first silicon glass pattern 101 is almost completely removed. As a result, the first doped silicon 14 is deposited on the surface of the first tunnel oxide layer 12, but no deposition is formed on the first silicon glass pattern 101 (i.e., the first silicon glass pattern 101 is exposed).

[0088] In some embodiments, a deposition process and a plasma etching process are used to deposit the first doped silicon 14 on the surface of the first silicon glass pattern 101 and the first tunnel oxide layer 12 facing away from the silicon base layer 11, including:

[0089] In the same chamber, chemical vapor deposition and plasma etching are cyclically performed, utilizing the fact that the deposition rate of the first doped silicon 14 on the first silicon glass pattern 101 is lower than the deposition rate of the first doped silicon 14 on the first tunnel oxide layer 12, while the etching rate of the first doped silicon 14 on the first silicon glass pattern 101 is higher than the etching rate of the first doped silicon 14 on the first tunnel oxide layer 12, so that the deposition of the first doped silicon 14 on the first tunnel oxide layer 12 is at least partially retained, while the deposition of the first doped silicon 14 on the first silicon glass pattern 101 is removed.

[0090] In these embodiments, chemical vapor deposition and plasma etching can be used to achieve deposition and etching of the first doped silicon 14 in the same chamber. By cyclically performing chemical vapor deposition and plasma etching, the thickness of the first doped silicon 14 ultimately formed on the first tunnel oxide layer 12 can be effectively controlled. For example, in one cycle, the deposition thickness of the first doped silicon 14 on the first tunnel oxide layer 12 is equal to the difference between the deposition rate difference of the first doped silicon 14 on the first tunnel oxide layer 12 and the first silicon glass pattern 101 multiplied by the deposition time, minus the difference between the etching rate difference of the first doped silicon 14 on the first silicon glass pattern 101 and the first tunnel oxide layer 12 multiplied by the etching time. As the number of cycles increases, the thickness of the first doped silicon 14 ultimately formed on the first tunnel oxide layer 12 also increases.

[0091] In some embodiments, a ratio of a deposition rate of the first doped silicon 14 on the first tunnel oxide layer 12 to a deposition rate of the first doped silicon 14 on the first silicon glass pattern 101 is 1:1 to 1.5:1, and a ratio of an etching rate of the first doped silicon 14 on the first tunnel oxide layer 12 to an etching rate of the first doped silicon 14 on the first silicon glass pattern 101 is 0.05:1 to 0.2:1.

[0092] In these embodiments, by controlling the deposition time and etching time, the first doped silicon 14 can be formed to a desired thickness on the first tunnel oxide layer 12 , and the first doped silicon 14 deposited on the first silicon glass pattern 101 can be removed as completely as possible.

[0093] In some embodiments, the number of cycles is 5 to 20, and in each cycle, the ratio of chemical vapor deposition time to plasma etching time is 3:1 to 12:1.

[0094] In these embodiments, the thickness of the first doped silicon 14 ultimately formed on the first tunnel oxide layer 12 can be effectively controlled.

[0095] In some embodiments, the chemical vapor deposition time is 24s-36s, and the plasma etching time is 3s-8s.

[0096] In these embodiments, the thickness of the first doped silicon 14 finally formed on the first tunnel oxide layer 12 can be limited to a suitable range, thereby achieving a better passivation effect.

[0097] S15), removing the first silicon glass pattern 101 to expose a portion of the PN junction corresponding to the second region B.

[0098] The first silicon glass pattern 101 is removed to expose a portion of the PN junction corresponding to the second region B, which may include:

[0099] The first silicon glass pattern 101 is dissolved and removed by using hydrofluoric acid, exposing a portion of the PN junction corresponding to the second region B.

[0100] In these embodiments, hydrofluoric acid can be used to dissolve and remove the first silicon glass pattern 101. When the sheet resistance of the first silicon glass pattern 101 is maintained at 200Ω / sqr to 300Ω / sqr, the large difference in properties between the first silicon glass pattern 101 and the first tunnel oxide layer 12 is utilized. The hydrofluoric acid will not cause significant damage to the first tunnel oxide layer 12 and the second tunnel oxide layer 13, so that the first tunnel oxide layer 12 and the second tunnel oxide layer 13, especially the second tunnel oxide layer 13, can be preserved.

[0101] In some embodiments, the preparation method may further include:

[0102] A second doped polysilicon 15 is formed on a surface of the second tunneling oxide layer 13 facing away from the silicon base layer 11 .

[0103] The formation of the second doped polysilicon 15 on the surface of the second tunneling oxide layer 13 facing away from the silicon base layer 11 may occur after or before the above S15), which is not specifically limited here.

[0104] In some embodiments, the first doped silicon 14 is first doped amorphous silicon; S13), after depositing the first doped silicon 14 on the surface of the first silicon glass pattern 101 and the first tunneling oxide layer 12 away from the silicon base layer 11 using a deposition process and a plasma etching process, the preparation method further includes:

[0105] forming a second doped amorphous silicon on a surface of the second tunneling oxide layer 13 facing away from the silicon base layer 11; and

[0106] The first doped amorphous silicon is converted into first doped polysilicon, and the second doped amorphous silicon is converted into second doped polysilicon by annealing.

[0107] In these embodiments, the first doped amorphous silicon and the second doped amorphous silicon can be first formed by chemical vapor deposition, and then the first doped polysilicon and the second doped polysilicon can be formed by a one-step annealing. Furthermore, by first forming the first doped polysilicon and the second doped polysilicon and then dissolving and removing the first silicon glass pattern 101 using hydrofluoric acid, the first doped polysilicon and the second doped polysilicon can be used to protect the first tunneling oxide layer 12 and the second tunneling oxide layer 13, respectively, thereby preventing damage to the first tunneling oxide layer 12 and the second tunneling oxide layer 13.

[0108] In some embodiments, in the above deposition process, the reaction gases used may include: a silicon source, a hydrogen source, and a boron source;

[0109] In the plasma etching process, the reaction gases used include: a plasma gas source and a fluorine-containing gas source, wherein the plasma gas source is used to generate plasma to etch the first doped silicon 14 deposited on the first silicon glass pattern 101 and the first tunneling oxide layer 12, and the fluorine-containing gas source is used to form silicon fluoride gas with the etched first doped silicon 14, and the etched first doped silicon 14 is removed by the silicon fluoride gas being extracted.

[0110] The silicon source may include one or more of monosilane (SiH4) and disilane (Si2H6), the hydrogen source may include hydrogen, and the boron source may include diborane (B2H6) and tetraborane (B4H 10 ) one or more; the plasma gas source may include argon (Ar2), nitrogen (N2) and helium (He), and the fluorine-containing gas source may include: one or more of CF4, SF6 and C4F8.

[0111] In some embodiments, during the deposition process, the pressure in the chamber is 200 MPa to 400 MPa, the power of the power supply is 8000 W to 14000 W, and the sum of the flow rates of the silicon source, the hydrogen source, and the boron source is 10700 sccm to 18800 sccm;

[0112] In the plasma etching process, the pressure in the reaction chamber is 100MPa~250MPa, the power of the power supply is 6000W~10000W, the sum of the flow rates of the plasma gas source and the fluorine-containing gas source is 300sccm~3800sccm, and the molar ratio of the plasma element in the plasma gas source to the fluorine element in the fluorine-containing gas source is 2:1~5:1.

[0113] In these embodiments, by limiting the pressure in the chamber, the power of the power supply, the sum of the flow rates of the plasma gas source and the fluorine-containing gas source, and the molar ratio of the plasma gas source and the fluorine-containing gas source to the above ranges, it is convenient to etch the first doped silicon 14 located above the first silicon glass pattern in a shorter time, and it is possible to prevent the etching rate of the first doped silicon 14 located above the first tunnel oxide layer from being too fast, thereby affecting the passivation effect.

[0114] In some embodiments, taking the silicon source as SiH4, the hydrogen source as hydrogen, the boron source as BH3, the plasma gas source as argon, and the fluorine-containing gas source as CF4 as an example, the flow rate of SiH4 is 2500 sccm ~4000 sccm, the flow rate of hydrogen is 8000 sccm ~12000 sccm, the flow rate of BH3 is 200 sccm ~2800 sccm, the flow rate of argon is 100 sccm ~3000 sccm, and the flow rate of the fluorine-containing gas source is 200 sccm ~800 sccm.

[0115] S16 ), a first passivation layer 16 and a first gate line pattern L1 are sequentially stacked on the portion of the PN junction corresponding to the second region B and the surface of the first doped silicon 14 . The first gate line pattern L1 passes through the first passivation layer 16 and is electrically connected to the first doped silicon 14 .

[0116] The first passivation layer 16 may be a front passivation layer, and the first gate line pattern L1 may be a front gate line pattern. In some embodiments, the preparation method may further include:

[0117] A second passivation layer 17 and a second gate line pattern L2 are sequentially stacked on the surface of the second doped polysilicon layer 16 . The second gate line pattern L2 passes through the second passivation layer 17 and is electrically connected to the second doped polysilicon layer 16 .

[0118] In these embodiments, the second passivation layer 17 may be a back passivation layer, and the second gate line pattern L2 may be a back gate line pattern.

[0119] In some embodiments, the formation of the first passivation layer 16 on the portion of the PN junction corresponding to the second region B and the surface of the first doped polysilicon layer 14 and the formation of the second passivation layer 17 on the surface of the second doped polysilicon layer 16 can be performed simultaneously, such as Figure 2 S161); and / or

[0120] The first gate line pattern L1 is formed on the portion of the PN junction corresponding to the first region A and the surface of the first doped polysilicon layer 14, and the second gate line pattern L2 is formed on the surface of the second doped polysilicon layer 16 simultaneously. Figure 2 (S162 in Figure 5)

[0121] In summary, in the method for preparing a solar cell provided in an embodiment of the present application, the first silicon glass film 100 is formed on the surface of the PN junction facing away from the silicon base layer 11. On the one hand, the first silicon glass film 100 can protect the PN junction during backside alkali polishing. On the other hand, the first silicon glass film 100 is patterned, that is, the first silicon glass pattern 101 is formed only in the second region B (that is, the remaining region of the first surface 11a except the region where the first gate line pattern L1 is located). By utilizing the different deposition rates and etching rates of the first doped silicon 14 on the first silicon glass pattern 101 and the first tunneling oxide layer 12, The first doped silicon 14 can be formed only on the first tunneling oxide layer 12 without being deposited on the first silicon glass pattern 101. By controlling the significant difference in properties between the first silicon glass pattern 101 and the first tunneling oxide layer 12, the first silicon glass pattern 101 formed in the second region B can be removed while retaining the first tunneling oxide layer 12 formed in the first region A (i.e., the region where the first gate line pattern L1 is located). This allows a passivation structure to be formed on the front side of the solar cell while achieving partial coverage of the first doped silicon 14. That is, the first doped silicon 14 is formed only in the first region A, thereby reducing parasitic absorption. Compared with the related art that requires forming a first tunneling oxide film and a first doped polysilicon film covering the entire PN junction, and requiring an additional patterning process to remove the portion of the first doped polysilicon film located in the second region, this patterning process utilizes the first silicon glass pattern 101 as a mask, and completes the local deposition of the first doped silicon 14 by taking advantage of the different deposition rates and etching rates of the first doped silicon 14 on different materials. On the one hand, it can reduce the number of steps and does not introduce additional developer to achieve the patterning of the first doped silicon 14. On the other hand, it does not require the provision of an additional mask, avoiding the introduction and removal of other mask materials. In summary, the method for preparing a solar cell provided in the embodiment of the present application can reduce the number of steps, thereby meeting the increasing demand for simplifying process steps and reducing costs.

[0122] It should be noted here that the above only shows the case where the solar cell is an N-type Topcon cell. Those skilled in the art will understand that when the solar cell is a P-type Topcon cell, the above preparation method is also applicable. The only difference is that the silicon base layer 11 is a P-type silicon base, the first doping element can be an N-type doping element, such as a P element, and the first silicon glass film 100 can be a phosphorus silicon glass. At this time, the reaction gas used in chemical vapor deposition can include: a silicon source, a hydrogen source and a phosphorus source, and the phosphorus source can include: PH3.

[0123] In a second aspect, some embodiments of the present application provide a solar cell, which is prepared by the preparation method described in the first aspect.

[0124] In a third aspect, some embodiments of the present application provide a photovoltaic assembly, the photovoltaic assembly comprising: a plurality of solar cells connected in series and / or in parallel;

[0125] At least one of the solar cells is the solar cell according to the second aspect.

[0126] In a fourth aspect, some embodiments of the present application provide a photovoltaic system comprising the photovoltaic assembly as described in the third aspect.

[0127] Photovoltaic systems can be used in photovoltaic power stations, such as ground power stations, rooftop power stations, water-surface power stations, etc. They can also be used in equipment or devices that use solar energy to generate electricity, such as user solar power supplies, solar street lights, solar cars, solar buildings, etc. Of course, it is understandable that the application scenarios of photovoltaic systems are not limited to this, that is, photovoltaic systems can be used in all fields that require solar energy to generate electricity. Taking the photovoltaic power generation system network as an example, the photovoltaic system may include a photovoltaic array, a junction box and an inverter. The photovoltaic array can be an array combination of multiple solar cells. For example, multiple solar cells can form multiple photovoltaic arrays. The photovoltaic array is connected to the junction box, which can converge the current generated by the photovoltaic array. The converged current flows through the inverter to be converted into the AC power required by the mains power grid and then connected to the mains power network to achieve solar power supply.

[0128] In order to objectively evaluate the technical effects of the embodiments of the present application, the present application will be described in detail and exemplarily through the following examples and comparative examples.

[0129] In the following examples and comparative examples, all raw materials can be purchased commercially, and in order to maintain the reliability of the experiments, the raw materials used in the following examples and comparative examples have the same physical and chemical parameters or are prepared by the same processing method.

[0130] Example 1

[0131] The method for preparing the solar cell provided in Example 1 is as follows:

[0132] Step S1), cleaning and texturing the N-type silicon wafer;

[0133] Step S2), boron diffusion is performed on the front surface of the cleaned and textured N-type silicon wafer, and oxidation is performed to prepare a PN junction and a borosilicate glass layer. According to the test, before oxidation, the surface resistance of the P region of the PN junction is 160Ω / sqr, and after oxidation, the surface resistance of the borosilicate glass layer is 280Ω / sqr;

[0134] Step S3), removing the borosilicate glass on the back of the silicon wafer and performing alkali polishing on the back;

[0135] Step S4), using a laser to remove the borosilicate glass layer in the area where the first gate line pattern is located;

[0136] Step S5), thermally oxidizing the front and back sides of the silicon wafer simultaneously to grow a first tunneling oxide layer on the front side and a second tunneling oxide layer on the back side.

[0137] Step S6), use PECVD (Plasma Enhanced Chemical Vapor Deposition, plasma enhanced chemical vapor deposition) and plasma etching to cyclically perform step A and step B on the front side to deposit a boron-doped amorphous silicon layer; wherein, in step A, SiH4, H2 and BH3 are introduced into the reaction furnace tube so that the pressure in the reaction furnace tube is maintained at 350Mpa, and a power supply is turned on to carry out chemical vapor deposition, the power of the power supply is 11000W, the flow rate of SiH4 is 3250sccm, the flow rate of H2 is 10000sccm, and the flow rate of BH3 is 600sccm; in step B, plasma is adopted to carry out etching, and during etching, CF4 and Ar2 are first introduced into the reaction furnace tube so that the pressure of the reaction furnace tube is maintained at 160MPa, the flow rate of CF4 is 400sccm, the flow rate of Ar2 is 2000sccm, and the power of the power supply is 8000W. Taking advantage of the differences in deposition and etching rates of the amorphous silicon layer on different surfaces, a boron-doped amorphous silicon layer is selectively deposited in the area where the first gate line pattern is located. Step A reacts for 30 seconds, and step B reacts for 5 seconds, which constitutes one cycle. Deposition is completed after repeating 10 cycles.

[0138] Step S7), wet etching the front surface, using HF to etch the borosilicate glass layer in the light-receiving area of the front surface;

[0139] Step S8), growing and depositing a P-doped amorphous silicon layer on the back side of the silicon wafer, the deposition conditions are: introducing SiH4, H2 and PH3 into the reaction furnace tube to maintain the pressure of the reaction furnace tube at 350MPa, turning on the power supply, performing chemical vapor deposition, the power of the power supply is 11000W, the flow rate of SiH4 is 3250sccm, the flow rate of H2 is 10000sccm, the flow rate of PH3 is 600sccm, and the deposition time is 780s;

[0140] Step S9), performing high temperature annealing on the silicon wafer having the B-doped amorphous silicon layer and the P-doped amorphous silicon layer formed thereon, wherein the annealing temperature is 900° C. and the time is 45 minutes;

[0141] Step S10), a passivation anti-reflection film is deposited on both the front and back sides of the silicon wafer. AlO is first deposited on the front side by ALD. x The film layer is 16nm, and then SiN is deposited by PECVD x The film layer is 75nm, and SiN is deposited on the back x Film layer 75nm;

[0142] Step S11 ), metallization screen printing is performed on the silicon wafer, and sintering and light injection are performed to form a first gate line pattern and a second gate line pattern.

[0143] Example 2

[0144] The method for preparing the solar cell in Example 2 is substantially the same as the method for preparing the solar cell in Example 1, except that:

[0145] In step S6), step A reacts for 25 seconds, and step B reacts for 3 seconds, which constitutes one cycle. The deposition is completed after 10 cycles are repeated.

[0146] Example 3

[0147] The method for preparing the solar cell in Example 3 is substantially the same as the method for preparing the solar cell in Example 1, except that:

[0148] In step S6), the reaction time of step A is 35 seconds, and the reaction time of step B is 8 seconds, which constitutes one cycle. The deposition is completed after 10 cycles are repeated.

[0149] Example 4

[0150] The method for preparing the solar cell in Example 4 is substantially the same as the method for preparing the solar cell in Example 1, except that:

[0151] In step S6), the flow rate of SiH4 in step A is 2500 sccm, the flow rate of H2 is 8000 sccm, and the flow rate of BH3 is 200 sccm. The flow rate of CF4 in step B is 200 sccm, and the flow rate of Ar2 is 800 sccm.

[0152] Example 5

[0153] The method for preparing the solar cell in Example 5 is substantially the same as the method for preparing the solar cell in Example 1, except that:

[0154] In step S6), the flow rate of SiH4 in step A is 4000 sccm, the flow rate of H2 is 12000 sccm, and the flow rate of BH3 is 2800 sccm. The flow rate of CF4 in step B is 412 sccm, and the flow rate of Ar2 is 2888 sccm.

[0155] Example 6

[0156] The method for preparing the solar cell in Example 6 is substantially the same as the method for preparing the solar cell in Example 5, except that:

[0157] In step S6), the flow rate of CF4 in step B is 660 sccm, and the flow rate of Ar2 is 2640 sccm.

[0158] Example 7

[0159] The method for preparing the solar cell in Example 7 is substantially the same as the method for preparing the solar cell in Example 5, except that:

[0160] In step S6), the flow rate of CF4 in step B is 300 sccm, and the flow rate of Ar2 is 3000 sccm.

[0161] Comparative Example 1

[0162] The preparation method of the solar cell in Comparative Example 1 is substantially the same as that in Example 1, except that:

[0163] Step S2) also includes the step of removing the borosilicate glass layer on the front side, and therefore does not include step S4);

[0164] In step S5) and step S6), a tunnel oxide film is formed to cover the entire surface on both the front and back surfaces, a boron-doped amorphous silicon film is formed to cover the entire surface on the tunnel oxide film on the front surface, and a phosphorus-doped amorphous silicon film is formed to cover the entire surface on the tunnel oxide film on the back surface;

[0165] In step 7), a silicon dioxide mask is deposited on the front boron-doped amorphous silicon film and in the non-gate line area, and the boron-doped polysilicon layer and the tunnel oxide layer in the area not covered by the silicon dioxide mask are removed by multiple wet etching steps. Then, the silicon dioxide mask is cleaned and removed.

[0166] Test Case

[0167] The solar cells provided in Examples 1 to 7 and Comparative Example 1 were subjected to performance tests. The specific test results are shown in Table 1 below:

[0168] Table 1

[0169]

[0170] As shown in Table 1, the open-circuit voltage, short-circuit current, fill factor, and efficiency of the solar cells provided by the embodiments of the present application are substantially equivalent to those of the solar cells provided by Comparative Example 1, and even exhibit superior performance. Example 1 exhibits the best efficiency, while Examples 2 and 3 exhibit slightly lower efficiency due to variations in deposition and etching times compared to Example 1. Examples 4 and 5 exhibit slightly lower efficiency due to variations in gas flow rates compared to Example 1. The use of borosilicate glass as a mask throughout the entire preparation process allows for localized deposition of the boron-doped polysilicon layer. This reduces the number of steps required to pattern the boron-doped polysilicon thin film without the need for an additional developer. Furthermore, the absence of an additional mask prevents the introduction and removal of other mask materials.

[0171] Comparing Example 5 with Examples 6 to 7, it can be seen that in the present application, by controlling the molar ratio of the element in the plasma gas source to the fluorine element in the fluorine-containing gas in the plasma etching step within the range of 2:1 to 5:1, the etching can be selectively performed, thereby facilitating improved performance of the solar cell.

[0172] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0173] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A method for preparing a solar cell, characterized in that: include: Providing a silicon substrate layer, the silicon substrate layer comprising a first surface and a second surface disposed opposite to each other along a thickness direction thereof, a PN junction formed on the first surface, and a first silicon glass thin film formed on a surface of the PN junction facing away from the silicon substrate layer, wherein the first silicon glass thin film is doped with a first doping element and an oxygen element; Removing a portion of the first silicon glass film corresponding to a first area to form a first silicon glass pattern, wherein the first silicon glass pattern covers a portion of the PN junction corresponding to a second area, while exposing a portion of the PN junction corresponding to the first area, wherein the first area is an area where a grid line pattern of the solar cell is located, and the second area is a remaining area of the first surface excluding the area where the grid line pattern is located, wherein the grid line pattern includes a first grid line pattern located on the first surface and a second grid line pattern located on the second surface; forming a first tunneling oxide layer on the first surface and in the first region; Depositing first doped silicon on surfaces of the first silicon glass pattern and the first tunnel oxide layer facing away from the silicon base layer using a deposition process and a plasma etching process; removing the first silicon glass pattern to expose a portion of the PN junction corresponding to the second region; forming a first passivation layer and a first gate line pattern in sequence on a portion of the PN junction corresponding to the second region and on a surface of the first doped silicon, wherein the first gate line pattern passes through the first passivation layer and is electrically connected to the first doped silicon; Depositing first doped silicon on surfaces of the first silicon glass pattern and the first tunnel oxide layer facing away from the silicon base layer using a deposition process and a plasma etching process, comprising: Deposition and plasma etching are performed cyclically, utilizing the fact that a deposition rate of the first doped silicon on the first silicon glass pattern is less than a deposition rate of the first doped silicon on the first tunnel oxide layer, while an etching rate of the first doped silicon on the first silicon glass pattern is greater than an etching rate of the first doped silicon on the first tunnel oxide layer, so that the deposition of the first doped silicon on the first tunnel oxide layer is at least partially retained, while the deposition of the first doped silicon on the first silicon glass pattern is removed.

2. The preparation method according to claim 1, characterized in that The first doping element is a P-type doping element, and the first silicon glass film is a borosilicate glass film.

3. The preparation method according to claim 1, characterized in that Removing a portion of the first silicon glass film corresponding to the first area to form a first silicon glass pattern, comprising: Laser ablation is used to remove a portion of the first silicon glass film corresponding to the first area to form the first silicon glass pattern.

4. The preparation method according to claim 1, characterized in that Deposition and plasma etching are performed cyclically in the same chamber.

5. The preparation method according to claim 1, characterized in that The ratio of the deposition rate of the first doped silicon on the first tunnel oxide layer to the deposition rate of the first doped silicon on the first silicon glass pattern is 1:1 to 1.5:1, and the ratio of the etching rate of the first doped silicon on the first tunnel oxide layer to the etching rate of the first doped silicon on the first silicon glass pattern is 0.05:1 to 0.2:

1.

6. The preparation method according to claim 1, characterized in that The deposition is chemical vapor deposition, the number of cycles is 5 to 20 times, and in each cycle, the ratio of the chemical vapor deposition time to the plasma etching time is 3:1 to 12:

1.

7. The preparation method according to claim 6, characterized in that In each cycle, the chemical vapor deposition time is 24s to 36s, and the plasma etching time is 3s to 8s.

8. The preparation method according to claim 1, characterized in that While forming a first tunneling oxide layer on the first surface and in the first region, the preparation method further includes: A second tunneling oxide layer is formed on the second surface and located in the first region and the second region by the same preparation process as that of the first tunneling oxide layer.

9. The preparation method according to claim 8, characterized in that The first doped silicon is first doped amorphous silicon; after depositing the first doped silicon on the surface of the first silicon glass pattern and the first tunnel oxide layer away from the silicon base layer using a deposition process and a plasma etching process, the preparation method further includes: forming a second doped amorphous silicon on a surface of the second tunnel oxide layer facing away from the silicon base layer; and The first doped amorphous silicon is converted into first doped polysilicon, and the second doped amorphous silicon is converted into second doped polysilicon by annealing.

10. The preparation method according to any one of claims 1 to 9, characterized in that: In the deposition process, the reaction gases used include: silicon source, hydrogen source and boron source; In the plasma etching process, the reaction gases used include: a plasma gas source and a fluorine-containing gas source, wherein the plasma gas source is used to generate plasma to etch the first doped silicon deposited on the first silicon glass pattern and the first tunneling oxide layer, and the fluorine-containing gas source is used to form silicon fluoride gas with the etched first doped silicon, and the etched first doped silicon is removed by the silicon fluoride gas being extracted.

11. The preparation method according to claim 10, characterized in that: In the deposition process, the pressure in the reaction chamber is 200 MPa to 400 MPa, the power of the power supply is 8000 W to 14000 W, and the sum of the flow rates of the silicon source, the hydrogen source, and the boron source is 10700 sccm to 18800 sccm; In the plasma etching process, the pressure in the chamber is 100 MPa to 250 MPa, the power of the power supply is 6000 W to 10000 W, the sum of the flow rates of the plasma gas source and the fluorine-containing gas source is 300 sccm to 3800 sccm, and the molar ratio of the plasma element in the plasma gas source to the fluorine element in the fluorine-containing gas source is 2:1 to 5:

1.

12. The preparation method according to any one of claims 1 to 9, characterized in that: The step of removing the first silicon glass pattern to expose a portion of the PN junction corresponding to the second region includes: The first silicon glass pattern is dissolved and removed by using hydrofluoric acid to expose a portion of the PN junction corresponding to the second region.

Images