Pixel driving circuit, driving method thereof, and display panel

Abstract

The present application proposes a pixel driving circuit, a driving method thereof, and a display panel, which belong to the technical field of display devices. The pixel driving circuit includes a data line, a scan line, and at least one sub-pixel driving circuit. The sub-pixel driving circuit includes a first capacitor, and the first capacitor includes a first electrode and a second electrode arranged opposite to each other. Correspondingly, the pixel driving circuit is provided with a first switching transistor and a second switching transistor. Through circuit design, the second electrode can be connected to the data line or to the common voltage terminal, that is, the second electrode can be controlled to be connected to the data line based on the first signal when driving at high frequency, and the second electrode can be controlled to be connected to the common voltage terminal based on the second signal when driving at low frequency, so that the capacitance value of the storage capacitor does not change when driving at high frequency, and the capacitance value of the storage capacitor is increased when driving at low frequency. The capacitance value of the storage capacitor can be adapted to the switching of the driving frequency, and the display effect when the driving frequency is switched can be improved.

Description

Technical Field

[0001] The present application relates to the technical field of display devices, and in particular to a pixel driving circuit and a driving method thereof, and a display panel. Background Art

[0002] When the display panel is driven at a low frequency, a frame needs to be maintained for a long time, requiring a large storage capacitor Cst to maintain the deflection state of the liquid crystal. When the display panel is driven at a high frequency, the displayed image is maintained for a short time, and the pixel unit needs to reach the predetermined voltage within a short time. Therefore, a large storage capacitor Cst is not required. Excessively large storage capacitor Cst will affect the charging rate of the pixel unit.

[0003] Then, at present, the pixel driving circuit of the display panel only has a storage capacitor with a fixed capacitance value, and the capacitance value of the storage capacitor cannot be adjusted according to the change of the driving frequency of the display panel, that is, it cannot adapt to the switching of the driving frequency, which will affect the display effect of the display panel when switching between high and low driving frequencies. Summary of the Invention

[0004] The main purpose of the embodiments of the present application is to provide a pixel driving circuit, a driving method thereof, and a display panel. By providing a first capacitor in each sub-pixel driving circuit of the pixel driving circuit and correspondingly providing a first switching transistor and a second switching transistor in the pixel driving circuit, the capacitance value of the storage capacitor can be adjusted according to the driving frequency, thereby adapting the capacitance value of the storage capacitor to the switching of the driving frequency and improving the display effect when the driving frequency is switched.

[0005] To achieve the above objectives, a first aspect of an embodiment of the present application provides a pixel driving circuit, comprising:

[0006] Data lines, scan lines and at least one sub-pixel driving circuit;

[0007] The sub-pixel driving circuit includes a driving transistor, a pixel electrode, a common electrode, and a storage capacitor, wherein a control terminal of the driving transistor is connected to a scan line, a first terminal of the driving transistor is connected to a data line, a second terminal of the driving transistor is connected to the pixel electrode, the common electrode is arranged opposite to the pixel electrode and is connected to a common voltage terminal, one terminal of the storage capacitor is connected to the pixel electrode, and the other terminal of the storage capacitor is connected to the common voltage terminal;

[0008] The sub-pixel driving circuit further includes a first capacitor, the first capacitor including a first electrode and a second electrode disposed opposite to each other, the pixel driving circuit further including at least one first switching transistor and at least one second switching transistor, the first electrode being connected to the pixel electrode, the second electrode being connected to a first end of the first switching transistor, and the second electrode being further connected to a first end of the second switching transistor;

[0009] The second end of the first switching transistor is connected to the data line, and the third end of the first switching transistor is used to access the first signal that controls the switching of the first switching transistor; the second end of the second switching transistor is connected to the common voltage end, and the third end of the second switching transistor is used to access the second signal that controls the switching of the second switching transistor.

[0010] In one embodiment of the present application, the sub-pixel driving circuit also includes a third switching transistor, the first end of the third switching transistor is connected to the second electrode, the second end of the third switching transistor is used to connect the first end of the first switching transistor and the first end of the second switching transistor, and the third end of the third switching transistor is used to connect the scan line.

[0011] In one embodiment of the present application, the sub-pixel driving circuit further includes a diode, a first end of the diode is connected between the first end of the third switch transistor and the second electrode, and a second end of the diode is connected to the pixel electrode.

[0012] In one embodiment of the present application, the pixel driving circuit further includes a first signal line and a second signal line;

[0013] The first signal line and the second signal line are arranged along a row direction, the first signal line is used to receive the first signal sent by the source driver module, and the second signal line is used to receive the second signal sent by the source driver module;

[0014] The third terminal of the first switching transistor is used to connect to the first signal line to receive the first signal for controlling the switching of the first switching transistor;

[0015] The third terminal of the second switch transistor is used to connect to the second signal line to receive the second signal for controlling the switching of the second switch transistor.

[0016] In one embodiment of the present application, the sub-pixel driving circuit also includes a fourth switching transistor, the first end of the fourth switching transistor is connected between the first end of the third switching transistor and the second electrode, the second end of the fourth switching transistor is connected to the pixel electrode, and the third end of the fourth switching transistor is connected to the third signal for controlling the switching of the fourth switching transistor.

[0017] In one embodiment of the present application, the pixel driving circuit further includes a third signal line, the third signal line is arranged along a row direction, and the third signal line is used to receive the third signal sent by the source driving module;

[0018] The third terminal of the fourth switch transistor is connected to the third signal line to receive the third signal for controlling the switching of the fourth switch transistor.

[0019] To achieve the above-mentioned object, a second aspect of the embodiments of the present application provides a driving method for driving the pixel driving circuit provided by any embodiment of the present application, the method comprising:

[0020] By detecting the length of the vertical blank gap area, the driving frequency of the current frame is obtained;

[0021] When the driving frequency exceeds a preset threshold, a first signal for controlling the first switch transistor to turn on and a second signal for controlling the second switch transistor to turn off are generated, and the first signal is transmitted to the third terminal of the first switch transistor and the second signal is transmitted to the third terminal of the second switch transistor, so that the second electrode and the data line are electrically connected;

[0022] When the driving frequency does not exceed the preset threshold, a first signal for controlling the first switching transistor to turn off and a second signal for controlling the second switching transistor to turn on are generated, and the first signal is transmitted to the third end of the first switching transistor and the second signal is transmitted to the third end of the second switching transistor, so that the second electrode and the common voltage end are connected.

[0023] In one embodiment of the present application, after obtaining the driving frequency of the current frame by detecting the length of the vertical blank gap area, the method further includes:

[0024] When the driving frequency exceeds the preset threshold, a third signal for controlling the fourth switch transistor to turn on is generated, and the third signal is transmitted to the third terminal of the fourth switch transistor, so that the pixel electrode is connected to the data line through the fourth switch transistor;

[0025] When the driving frequency does not exceed the preset threshold, a third signal for controlling the fourth switch transistor to be turned off is generated, and the third signal is transmitted to the third end of the fourth switch transistor, so that the pixel electrode is not connected to the data line.

[0026] To achieve the above-mentioned purpose, a third aspect of an embodiment of the present application provides a display panel, which includes a gate driving circuit and a pixel driving circuit, wherein:

[0027] The pixel driving circuit is the pixel driving circuit provided by any embodiment of the present application; and / or

[0028] The gate drive circuit includes a plurality of shift registers, which are used to provide a plurality of scan signals to a plurality of scan lines respectively and sequentially during a frame period of the display panel. Each of the shift registers includes a pre-charging unit and a pull-up unit. The output end of the pre-charging unit is electrically connected to a control node for pre-charging the control node. The pull-up unit includes a first transistor and an energy storage capacitor. The first end of the first transistor is connected to the control node, the second end of the first transistor is connected to a clock signal input end, and the third end of the first transistor is connected to a scan signal output end. The first end of the energy storage capacitor is connected to the control node, and the second end of the energy storage capacitor is connected to the scan signal output end.

[0029] The gate drive circuit further includes a second capacitor, a fifth switching transistor, and a sixth switching transistor, the second capacitor including a third electrode and a fourth electrode disposed opposite to each other, the third electrode being connected to the control node, the fourth electrode being connected to the first terminal of the fifth switching transistor, and the fourth electrode being further connected to the first terminal of the sixth switching transistor;

[0030] The second end of the fifth switching transistor is connected to the control node, and the third end of the fifth switching transistor is used to access the fourth signal for controlling the switching of the fifth switching transistor; the second end of the sixth switching transistor is connected to the scan signal output end, and the third end of the sixth switching transistor is used to access the fifth signal for controlling the switching of the sixth switching transistor.

[0031] In one embodiment of the present application, the frame period includes a plurality of display phases and a plurality of touch sensing phases, and the display phases and the touch sensing phases are switched alternately. Based on the fact that the gate driving circuit includes a second capacitor, a fifth switching transistor, and a sixth switching transistor,

[0032] Before entering the touch sensing phase, controlling the fifth switch transistor to be turned off based on the fourth signal, and controlling the sixth switch transistor to be turned on based on the fifth signal, so that conduction is achieved between the fourth electrode and the scan signal output terminal;

[0033] After the touch sensing phase ends, the fifth switch transistor is controlled to be turned on based on the fourth signal, and the sixth switch transistor is controlled to be turned off based on the fifth signal, so that the fourth electrode is conductively connected to the control node.

[0034] In the technical solution provided in the embodiments of the present application, a pixel driving circuit includes a data line, a scan line, and at least one sub-pixel driving circuit, wherein the sub-pixel driving circuit includes a first capacitor, the first capacitor including a first electrode and a second electrode disposed opposite each other. Correspondingly, the pixel driving circuit is provided with a first switching transistor and a second switching transistor, wherein the first electrode is connected to the pixel electrode, the second electrode is connected to the first end of the first switching transistor, and the second electrode is also connected to the first end of the second switching transistor. The second end of the first switching transistor is connected to the data line, and the third end of the first switching transistor is used to receive a first signal for controlling the switching of the first switching transistor; the second end of the second switching transistor is connected to a common voltage terminal, and the third end of the second switching transistor is used to receive a second signal for controlling the switching of the second switching transistor. That is, the second electrode can be controlled to be connected to the data line based on the first signal during high-frequency driving, and the second electrode can be controlled to be connected to the common voltage terminal based on the second signal during low-frequency driving. This allows the capacitance value of the storage capacitor to remain unchanged during high-frequency driving, while increasing the capacitance value of the storage capacitor during low-frequency driving. This allows the capacitance value of the storage capacitor to adapt to the switching of the driving frequency, thereby improving the display effect when the driving frequency switches display. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a structural block diagram of a pixel driving circuit provided in an embodiment of the present application;

[0036] Figure 2 is another structural block diagram of the pixel driving circuit provided in an embodiment of the present application;

[0037] Figure 3 is another structural block diagram of the pixel driving circuit provided in an embodiment of the present application;

[0038] Figure 4 is another structural block diagram of the pixel driving circuit provided in an embodiment of the present application;

[0039] Figure 5 This is a timing diagram of high and low brush drive switching provided by an embodiment of the present application;

[0040] Figure 6is another structural block diagram of a pixel driving circuit provided in an embodiment of the present application;

[0041] Figure 7 is another structural block diagram of a pixel driving circuit provided in an embodiment of the present application;

[0042] Figure 8 is a flowchart of the driving method provided in an embodiment of the present application;

[0043] Figure 9 This is a flowchart of the steps after obtaining the driving frequency of the current frame image by detecting the length of the vertical blank gap area provided by an embodiment of the present application;

[0044] Figure 10 is a structural block diagram of a shift register provided in an embodiment of the present application;

[0045] Figure 11 1 is a schematic diagram of the working timing of the gate drive circuit provided in an embodiment of the present application;

[0046] Figure 12 This is an example diagram of the operation timing of the gate drive circuit provided in an embodiment of the present application.

[0047] Description of reference numerals:

[0048] Data line 10; scan line 20; sub-pixel driving circuit 30; driving transistor 310; pixel electrode 311; common electrode 312; storage capacitor 313; common voltage terminal 40; first capacitor 320; first electrode 321; second electrode 322; first switching transistor 330; second switching transistor 340; third switching transistor 350; diode 360; fourth switching transistor 370; pre-charging unit 1010; pull-up unit 1020; control node 50; first transistor 1021; energy storage capacitor 1022; second capacitor 1030; fifth switching transistor 1040; sixth switching transistor 1050; third electrode 1031; fourth electrode 1032. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solutions and advantages of this application more clear, the following further describes this application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0050] It should be noted that although the device schematics illustrate functional module divisions and the flowcharts illustrate logical sequences, in certain circumstances, the steps illustrated or described may be performed in a sequence that differs from the module divisions in the device or the sequence in the flowcharts. The terms "first," "second," and the like in the specification, claims, and drawings are used to distinguish similar objects and are not necessarily used to describe a specific sequence or precedence.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0052] The screen refresh rate refers to how many times per second the screen updates the displayed information. High-refresh monitors display images more quickly. The higher the refresh rate, the less flickering the image appears, and the more stable it is. On the other hand, a lower refresh rate can cause the image to flicker and jitter more easily, leading to eye fatigue after prolonged viewing. Furthermore, while high-refresh-rate screens allow for smoother gaming, they consume more power, and because more images need to be displayed per unit time, the screen's lifespan is reduced.

[0053] In different application scenarios, if the appropriate refresh rate can be achieved for adaptive switching, the goal of both good visual appreciation and reduced power consumption can be achieved. However, in the process of switching the refresh rate of the actual display, it is often affected by the pixel structure, such as the storage capacitor Cst. The function of the storage capacitor Cst is to maintain the charged pixel voltage to the next frame of the picture, reducing the pixel voltage drop caused by the change of the liquid crystal capacitance. When the panel is driven at a low frequency, a frame of the picture needs to be maintained for a long time, and a large storage capacitor Cst is required to maintain the deflection state of the liquid crystal; when the panel is driven at a high frequency, the display image is maintained for a short time, and the pixel unit needs to reach a predetermined voltage in a short time, so a large storage capacitor Cst is not required. If the storage capacitor Cst is too large, it will affect the charging rate of the pixel unit.

[0054] Then, at present, the pixel driving circuit of the display panel only has a storage capacitor with a fixed capacitance value, and the capacitance value of the storage capacitor cannot be adjusted according to the change of the driving frequency of the display panel, that is, it cannot adapt to the switching of the driving frequency, which will affect the display effect of the display panel when switching between high and low driving frequencies.

[0055] Based on this, an embodiment of the present application proposes a pixel driving circuit. By setting a first capacitor, a first switching transistor and a second switching transistor in each sub-pixel driving circuit in the pixel driving circuit, the capacitance value of the storage capacitor can be adjusted according to the driving frequency, so that the capacitance value of the storage capacitor can be adapted to the switching of the driving frequency, thereby improving the display effect when the driving frequency switches the display.

[0056] Reference Figure 1 , Figure 1 : is a structural block diagram of a pixel driving circuit provided by an embodiment of the present application. Figure 1 As shown, the pixel driving circuit includes a data line 10, a scan line 20 and at least one sub-pixel driving circuit 30. The sub-pixel driving circuit 30 includes a driving transistor 310, a pixel electrode 311, a common electrode 312 and a storage capacitor 313. The control terminal of the driving transistor 310 is used to connect to the scan line 20, the first terminal of the driving transistor 310 is used to connect to the data line 10, the second terminal of the driving transistor 310 is connected to the pixel electrode 311, the common electrode 312 is arranged opposite to the pixel electrode 311 and is used to connect to the common voltage terminal 40, one end of the storage capacitor 313 is connected to the pixel electrode 311, and the other end of the storage capacitor 313 is used to connect to the common voltage terminal 40. The sub-pixel driving circuit 30 also includes a first capacitor 320, which includes a first electrode 321 and a second electrode 322 arranged opposite to each other. The pixel driving circuit also includes at least one first switching transistor 330 and at least one second switching transistor 340. The first electrode 321 is connected to the pixel electrode 311, the second electrode 322 is connected to the first terminal of the first switching transistor 330, and the second electrode 322 is also connected to the first terminal of the second switching transistor 340. The second terminal of the first switching transistor 330 is connected to the data line 10, and the third terminal of the first switching transistor 330 is used to receive a first signal for controlling the switching of the first switching transistor 330. The second terminal of the second switching transistor 340 is connected to the common voltage terminal 40, and the third terminal of the second switching transistor 340 is used to receive a second signal for controlling the switching of the second switching transistor 340.

[0057] In the embodiment of the present application, since one end of the storage capacitor 313 is connected to the pixel electrode 311, and the first electrode 321 in the first capacitor 320 is also connected to the pixel electrode 311, the potential of the first electrode 321 is the pixel electrode potential. Since the first end of the driving transistor 310 is connected to the data line 10, and the second end of the driving transistor 310 is connected to the pixel electrode 311, the voltage of the pixel electrode 311 is determined by the data voltage transmitted by the data line 10. During high-frequency driving, the second electrode 322 can be controlled to be connected to the data line 10 based on the first signal, so that the second electrode 322 also has the pixel electrode potential. As a result, there is no potential difference between the electrode plates on both sides of the first capacitor 320, that is, no additional charge is accumulated, and the capacitance value of the storage capacitor 313 is not changed. During low-frequency driving, the second electrode 322 can be controlled to be connected to the common voltage terminal 40 based on the second signal, so that the second electrode 322 has a common potential. Thus, the first capacitor 320 is connected in parallel with the storage capacitor 313, which is equivalent to increasing the electrode area, so that the capacitance value of the storage capacitor 313 is twice the capacitance value of the original storage capacitor 313, that is, the capacitance value of the storage capacitor 313 is increased, which can improve the picture retention.

[0058] In the embodiment of the present application, the capacitance value of the storage capacitor is not changed during high-frequency driving, and is increased during low-frequency driving. This allows the capacitance value of the storage capacitor to adapt to the switching of the driving frequency, thereby improving the display effect when the driving frequency is switched.

[0059] In one embodiment of the present application, referring to Figure 2 , Figure 2 is another structural block diagram of the pixel driving circuit provided by the embodiment of the present application. Figure 2 As shown, the sub-pixel driving circuit 30 also includes a third switching transistor 350, the first end of the third switching transistor 350 is connected to the second electrode 322, the second end of the third switching transistor 350 is used to connect the first end of the first switching transistor 330 and the first end of the second switching transistor 340, and the third end of the third switching transistor 350 is used to connect the scan line 20.

[0060] In the embodiment of the present application, a third switch transistor 350 is provided in each sub-pixel driver circuit 30, with a first end of the third switch transistor 350 connected to the second electrode 322, a second end of the third switch transistor 350 connected to the first end of the first switch transistor 330 and the first end of the second switch transistor 340, and a third end of the third switch transistor 350 connected to the scan line 20. Thus, the row drive signal received by the scan line 20 can be used to control the selective input of the adjustable potential of the second electrode of the first capacitor 320 in each row of the sub-pixel driver circuit 30. Thus, the storage capacitor 313 in each row of the sub-pixel driver circuit 30 can be adjusted simultaneously.

[0061] In one embodiment of the present application, referring to Figure 3 , Figure 3 is another structural block diagram of the pixel driving circuit provided by the embodiment of the present application. Figure 3 As shown, the sub-pixel driving circuit 30 further includes a diode 360 ​​, a first end of the diode 360 ​​is connected between the first end of the third switch transistor 350 and the second electrode 322 , and a second end of the diode 360 ​​is connected to the pixel electrode 311 .

[0062] In an embodiment of the present application, by adding a diode 360 ​​between the second electrode 322 and the pixel electrode 311, combined with the control of the first signal and the second signal, dual-channel charging can be performed during the high-brush forward charging process, thereby improving the charging efficiency of the high-brush display. Specifically, considering that the time for displaying a frame of picture is short during high-brush driving, the charging time of the pixel unit is insufficient, and there may be a risk of insufficient pixel charging rate. Therefore, during high-frequency driving, the second electrode 322 can be controlled to be connected to the data line 10 based on the first signal and the second signal, so that the second electrode 322 is also the pixel electrode potential, that is, the capacitance value of the storage capacitor is not changed. At the same time, when the pixel unit is forward charged, the scan signal simultaneously turns on the driving transistor 310 and the third switching transistor 350. At this time, the data line 10 can charge the pixel electrode simultaneously through the second electrode of the first capacitor 320 and the first end of the driving transistor 310, thereby realizing dual-channel charging, thereby improving the charging efficiency of the high-brush display.

[0063] In one embodiment of the present application, referring to Figure 4 , Figure 4 is another structural block diagram of the pixel driving circuit provided by the embodiment of the present application. Figure 4 As shown, the pixel driving circuit further includes a first signal line L1 and a second signal line L2. The first signal line L1 and the second signal line L2 are arranged along the row direction. The first signal line L1 is used to receive a first signal sent by the source driver module, and the second signal line L2 is used to receive a second signal sent by the source driver module. The third terminal of the first switching transistor 330 is used to connect to the first signal line L1 to receive a first signal for controlling the switching of the first switching transistor 330. The third terminal of the second switching transistor 340 is used to connect to the second signal line L2 to receive a second signal for controlling the switching of the second switching transistor 340.

[0064] In the embodiment of the present application, the third terminal of the first switch transistor 330 is used to connect to the first signal line L1, and the third terminal of the second switch transistor 340 is used to connect to the second signal line L2. Therefore, the source driver module can transmit a first signal to the first switch transistor 330 via the first signal line L1 to control the on and off of the first switch transistor 330. At the same time, the source driver module can transmit a second signal to the second switch transistor 340 via the second signal line L2 to control the on and off of the second switch transistor 340.

[0065] For example, during high-frequency driving, the source driver module can send a high-level signal to the first signal line L1 and a low-level signal to the second signal line L2 to control the first switch transistor 330 to turn on and the second switch transistor 340 to turn off, thereby connecting the second electrode 322 to the data line 10, so that the second electrode 322 is also the pixel electrode potential, that is, the capacitance value of the storage capacitor is not changed. During low-frequency driving, the source driver module can send a low-level signal to the first signal line L1 and a high-level signal to the second signal line L2 to control the first switch transistor 330 to turn off and the second switch transistor 340 to turn on, thereby connecting the second electrode 322 to the common voltage terminal 40, so that the second electrode 322 is the common potential, which can increase the capacitance value of the storage capacitor. Thus, by adapting the capacitance value of the storage capacitor to the switching of the driving frequency, the display effect when the driving frequency is switched can be improved. At the same time, by providing the first signal line L1 and the second signal line L2 in the pixel driving circuit, each sub-pixel driving circuit can share the first signal line L1 and the second signal line L2, without occupying additional area, thus saving wiring space.

[0066] Reference Figure 5 , Figure 5 This is the high and low brush drive switching timing diagram provided by the embodiment of the present application, Figure 5 As shown, when a frame is normally displayed, the frame start signal STV is input to the first row, and then the gate scanning signal is output through the clock signal CLK, so that the driving transistor 310 that controls the pixel electrode 311 is turned on to transmit the electrode signal on the data line 10 to the corresponding pixel electrode 311. Different time constants (H and h) correspond to different high and low brushing modes, and the first signal line L1 and the second signal line L2 have different potential states. Figure 5As shown, when high-frequency driving is used, the first signal line L1 is at a high level and the second signal line L2 is at a low level, thereby controlling the first switch transistor 330 to turn on and the second switch transistor 340 to turn off, so that the second electrode 322 is connected to the data line 10, so that the second electrode 322 also has the pixel electrode potential, and the capacitance value of the storage capacitor does not change. When switching from high-frequency driving to low-frequency driving, the first signal line L1 is at a low level and the second signal line L2 is at a high level, thereby controlling the first switch transistor 330 to turn off and the second switch transistor 340 to turn on, so that the second electrode 322 is connected to the common voltage terminal 40, so that the second electrode 322 has the common potential, and the capacitance value of the storage capacitor can be increased. At this time, the time constant in the two driving modes changes from H to h, and H = 2h. The time constant is calculated as: time constant = 1 / refresh rate / (number of resolution lines + number of redundant lines). For example, if the refresh rate is 60 Hz, the resolution is 1200*1920, and the number of redundant lines is 30, the time constant is 1 / 60 / (1200+30)=13.55 μs. Thus, the switching time for switching the signals between the first signal line L1 and the second signal line L2 can be determined based on the time constant.

[0067] In one embodiment of the present application, referring to Figure 6 , Figure 6 is another structural block diagram of the pixel driving circuit provided by the embodiment of the present application. Figure 6 As shown, the sub-pixel driving circuit 30 also includes a fourth switching transistor 370, the first end of the fourth switching transistor 370 is connected between the first end of the third switching transistor 350 and the second electrode 322, the second end of the fourth switching transistor 370 is connected to the pixel electrode 311, and the third end of the fourth switching transistor 370 is connected to the third signal for controlling the switching of the fourth switching transistor 370.

[0068] In the embodiment of the present application, considering that the diode 360 ​​has unidirectional conductivity, the charging channel established by the diode 360 ​​has certain limitations. That is, because the diode has directionality and can only go from a high potential to a low potential, when the pixel unit changes from positive polarity to negative polarity or the pixel potential of the current frame is lower than the pixel potential of the previous frame, after the scan line simultaneously turns on the drive transistor 310 and the third switch transistor 350, the diode 360 ​​does not conduct, and the charging channel established by the diode 360 ​​cannot achieve the charging effect. Similarly, when driving at a low frequency, the charging channel established by the diode 360 ​​cannot achieve the charging effect. Based on this, the embodiment of the present application replaces the diode 360 ​​with a fourth switch transistor 370, and the opening and closing of the fourth switch transistor 370 is controlled by a third signal. Specifically, when driving at a high frequency, the second electrode 322 can be controlled to be connected to the data line 10 based on the first signal and the second signal, so that the second electrode 322 also has the pixel electrode potential, thereby eliminating the need to increase the storage capacitor 313. At this time, the fourth switch transistor 370 can be controlled to turn on by the third signal, so that the data line 10 can simultaneously charge the pixel electrode through the second electrode of the first capacitor 320 and the first end of the driving transistor 310, thereby realizing dual-channel charging. During low-frequency driving, the second electrode 322 can be controlled to be connected to the common voltage terminal based on the first signal and the second signal, so that the second electrode 322 is at a common potential, thereby increasing the capacitance value of the storage capacitor 313. At this time, the fourth switch transistor 370 can be controlled to turn off by the third signal to prevent the common potential from interfering with the pixel charging.

[0069] In one embodiment of the present application, referring to Figure 7 , Figure 7 is another structural block diagram of the pixel driving circuit provided by the embodiment of the present application. Figure 7 As shown, the pixel driving circuit further includes a third signal line L3, which is arranged in the row direction and is used to receive a third signal sent by the source driver module. A third terminal of the fourth switching transistor 370 is connected to the third signal line L3 to receive the third signal for controlling the switching of the fourth switching transistor 370.

[0070] In the embodiment of the present application, the third end of the fourth switch transistor 370 is connected to the third signal line L3. Thus, the source driver module can transmit the third signal to the fourth switch transistor 370 through the third signal line L3 to control the opening and closing of the fourth switch transistor 370.

[0071] For example, during high-frequency driving, the source driver module can send a high-level signal to the first signal line L1 and a low-level signal to the second signal line L2 to control the first switch transistor 330 to turn on and the second switch transistor 340 to turn off, thereby connecting the second electrode 322 to the data line 10, so that the second electrode 322 is also at the pixel electrode potential, that is, the capacitance value of the storage capacitor is not changed. At the same time, the source driver module sends a high-level signal to the third signal line L3 to control the fourth switch transistor 370 to turn on, so that the data line 10 can charge the pixel electrode simultaneously through the second electrode of the first capacitor 320 and the first end of the drive transistor 310, thereby achieving dual-channel charging. During low-frequency driving, the source driver module can send a low-level signal to the first signal line L1 and a high-level signal to the second signal line L2 to control the first switch transistor 330 to turn off and the second switch transistor 340 to turn on, thereby connecting the second electrode 322 to the common voltage terminal 40, so that the second electrode 322 is at the common potential, which can increase the capacitance value of the storage capacitor. At the same time, the source driver module sends a low-level signal to the third signal line L3 to control the fourth switching transistor 370 to turn off, thereby preventing the common potential from interfering with the pixel charging. Thus, by adapting the capacitance of the storage capacitor to the switching of the drive frequency, and by adapting the pixel charging to the switching of the drive frequency, the display effect during the drive frequency switching display can be improved. Furthermore, by providing the third signal line L3 in the pixel driver circuit, each sub-pixel driver circuit can share the third signal line L3, eliminating the need for additional area and saving wiring space.

[0072] Reference Figure 8 , Figure 8 This is a flowchart of the driving method provided in an embodiment of the present application, which is used to drive the pixel driving circuit provided in any embodiment of the present application, including but not limited to steps S810 to S830.

[0073] In step S810 , the driving frequency of the current frame is obtained by detecting the length of the vertical blank gap area.

[0074] In this embodiment of the present application, frequency switching is achieved by adjusting the length of the vertical blank gap area. The lower the frame rate, the longer the vertical blank gap area. Therefore, the timing control module can obtain the driving frequency of the current frame by detecting the length of the vertical blank gap area.

[0075] In step S820, when the driving frequency exceeds a preset threshold, a first signal for controlling the first switching transistor to turn on and a second signal for controlling the second switching transistor to turn off are generated, and the first signal is transmitted to the third end of the first switching transistor and the second signal is transmitted to the third end of the second switching transistor, so that the second electrode and the data line are conductive.

[0076] In the embodiment of the present application, when the driving frequency exceeds a preset threshold, it indicates that the display panel is in a high-frequency driving mode, at which point a large storage capacitor is not required. Therefore, the timing control module can generate a first signal for controlling the first switching transistor to turn on and a second signal for controlling the second switching transistor to turn off. Thus, the first signal can be used to control the first switching transistor 330 to turn on, and the second signal can be used to control the second switching transistor 340 to turn off, thereby connecting the second electrode 322 to the data line 10 and setting the second electrode 322 to the pixel electrode potential, i.e., the capacitance value of the storage capacitor remains unchanged.

[0077] In step S830, when the driving frequency does not exceed the preset threshold, a first signal for controlling the first switching transistor to turn off and a second signal for controlling the second switching transistor to turn on are generated, and the first signal is transmitted to the third end of the first switching transistor and the second signal is transmitted to the third end of the second switching transistor, so that the second electrode and the common voltage end are conductive.

[0078] In the embodiment of the present application, when the driving frequency does not exceed the preset threshold, it indicates that the display panel is in a low-frequency driving mode, and a large storage capacitor is required. Therefore, the timing control module can generate a first signal for controlling the first switching transistor to be turned off and a second signal for controlling the second switching transistor to be turned on. The first signal can control the first switching transistor 330 to be turned off, and the second signal can control the second switching transistor 340 to be turned on, thereby connecting the second electrode 322 to the common voltage terminal 40, so that the second electrode 322 is at a common potential, thereby increasing the capacitance value of the storage capacitor.

[0079] In the embodiment of the present application, by adapting the capacitance value of the storage capacitor to the switching of the driving frequency, the display effect when the driving frequency is switched can be improved.

[0080] Reference Figure 9 , Figure 9 This is a flowchart of the steps provided by an embodiment of the present application after the driving frequency of the current frame image is obtained by detecting the length of the vertical blank gap area, including but not limited to steps S910 to S920.

[0081] In step S910, when the driving frequency exceeds the preset threshold, a third signal for controlling the fourth switch transistor to turn on is generated and the third signal is transmitted to the third terminal of the fourth switch transistor, so that the pixel electrode is connected to the data line through the fourth switch transistor.

[0082] In an embodiment of the present application, when the driving frequency exceeds a preset threshold, it indicates that the display panel is in a high-frequency driving mode, and a large storage capacitor is not required at this time. The display time of a frame is short, and the charging time of the pixel unit is insufficient, and there may be a risk of insufficient pixel charging rate. Therefore, the timing control module can also generate a third signal for controlling the opening of the fourth switching transistor, so that the fourth switching transistor 370 can be controlled to be turned on by the third signal, so that the data line 10 can charge the pixel electrode simultaneously through the second electrode of the first capacitor 320 and through the first end of the driving transistor 310, thereby realizing dual-channel charging to increase the charging rate.

[0083] In step S920, when the driving frequency does not exceed the preset threshold, a third signal for controlling the fourth switch transistor to be turned off is generated, and the third signal is transmitted to the third terminal of the fourth switch transistor so that the pixel electrode is not connected to the data line.

[0084] In the embodiment of the present application, when the drive frequency does not exceed the preset threshold, it indicates that the display panel is in a low-frequency drive mode. In this case, a large storage capacitor is required, but there is no problem of insufficient charging, and the common potential will still charge interfering pixels. Therefore, the timing control module can also generate a third signal for controlling the fourth switch transistor to be turned off. This third signal can control the fourth switch transistor 370 to be turned off, thereby preventing the common potential from interfering with the pixel charging.

[0085] In the embodiment of the present application, by adapting the capacitance value of the storage capacitor to the switching of the driving frequency and adapting the pixel charging to the switching of the driving frequency, the display effect when the driving frequency is switched can be improved.

[0086] An embodiment of the present application further provides a display panel, wherein the display panel includes a gate driving circuit and a pixel driving circuit provided by any embodiment of the present application.

[0087] In the embodiments of the present application, since the display panel includes the pixel driving circuit provided by any embodiment of the present application, wherein the pixel driving circuit can improve the display effect when the driving frequency switches by adapting the capacitance value of the storage capacitor to the switching of the driving frequency. Therefore, the display panel provided by the embodiments of the present application can also improve the display effect when the driving frequency switches.

[0088] The embodiment of the present application also includes a display panel, wherein the display panel includes a gate driving circuit and a pixel driving circuit, the gate driving circuit includes a plurality of shift registers, and the shift registers are used to provide a plurality of scanning signals to a plurality of scanning lines respectively and sequentially during a frame period of the display panel. Figure 10 , Figure 10 This is a structural block diagram of the shift register provided by the embodiment of the present application. Figure 10As shown, each shift register includes a pre-charging unit 1010 and a pull-up unit 1020. The output end of the pre-charging unit 1010 is electrically connected to the control node 50 for pre-charging the control node 50. The pull-up unit 1020 includes a first transistor 1021 and a storage capacitor 1022. The first end of the first transistor 1021 is connected to the control node 50, the second end of the first transistor 1021 is connected to the clock signal CLK input end, the third end of the first transistor 1021 is connected to the scan signal output end Gout(n), the first end of the storage capacitor 1022 is connected to the control node 50, and the second end of the storage capacitor 1022 is connected to the scan signal output end Gout(n). The gate drive circuit also includes a second capacitor 1030, a fifth switching transistor 1040, and a sixth switching transistor 1050. The second capacitor 1030 includes a third electrode 1031 and a fourth electrode 1032 disposed opposite each other. The third electrode 1031 is connected to the control node 50, and the fourth electrode 1032 is connected to the first terminal of the fifth switching transistor 1040. The fourth electrode 1032 is also connected to the first terminal of the sixth switching transistor 1050. The second terminal of the fifth switching transistor 1040 is connected to the control node 50, and the third terminal of the fifth switching transistor 1040 is used to receive a fourth signal for controlling the switching of the fifth switching transistor 1040. The second terminal of the sixth switching transistor 1050 is connected to the scan signal output terminal Gout(n), and the third terminal of the sixth switching transistor 1050 is used to receive a fifth signal for controlling the switching of the sixth switching transistor 1050.

[0089] In the embodiment of the present application, the energy storage capacitor 1022 in the gate drive circuit mainly plays the role of the user line interface circuit function (borst) and the maintenance control node 50 (PU). For the current numerous displays with touch function, the timing of realizing the touch function mainly includes LongH and LongV, and the difference between the two is that LongH is to insert the TP signal within the frame, while LongV is to insert the TP signal between frames. The difference in the insertion position of the TP signal puts forward different requirements for the structure of the gate drive circuit. Among them, the characteristics of the LongH timing require that the energy storage capacitor 1022 in the gate drive circuit be large enough to maintain the potential of the control node 50 (PU) during the time of inserting the TP signal. However, the increase in the capacitance of the energy storage capacitor 1022 will occupy a large space on the display panel, which will increase the non-display area ratio of the product. Therefore, the second capacitor 1030, the fifth switch transistor 1040 and the sixth switch transistor 1050 can be used to achieve the adaptation of the capacitance, which can also save a certain amount of space.

[0090] In the present application, refer to Figure 10Thin-film transistor T1 and the signal sources VGH and Gout_n-2 acting around it constitute the pre-charge unit 1010 of the gate drive circuit. The previous stage pre-charges the control node 50 (PU) of this stage. Thin-film transistor T1A is the signal that resets the control node 50 (PU) of this row and is triggered by the output signal Gout_n+2 of the next stage. Thin-film transistors T2 and T2A constitute a reset unit that resets the control node 50 (PU). Thin-film transistors T5 and T5A constitute another reset unit that resets the output signal Gout. Thin-film transistor T6 is the first transistor 1021, which outputs the gate signal. Thin-film transistor T7 is the source of the PD signal. T4 resets the PD signal. The touch signal (TP) and the touch signal source (TPE) constitute the touch triggering part. The energy storage capacitor 1022 provides the user line interface circuit function (borst) and maintenance for the PU potential, allowing T6 to open more fully.

[0091] In the present application, refer to Figure 11 , Figure 11 : is a schematic diagram of the working timing of the gate drive circuit provided by the embodiment of the present application. Figure 11 As shown, the signal source VGH and the signal source VGL are respectively a DC high level and a DC low level. The clock signal CLKB is a signal with an opposite phase to the output of the clock signal CLK. A frame of the picture contains display timing and non-display timing, wherein the display timing controls the normal display of the display area, and the non-display timing is used to insert reset and touch signals. The touch signal will be inserted between the display pictures. When the touch signal is inserted, the touch signal source (TPE) will turn on the touch signal (TP) and turn off the current row output terminal Gout. At this time, the potential of the control node 50 (PU) is in a hold state. As the touch time is inserted, the holding time of the control node 50 (PU) of the next-level gate drive circuit is prolonged, which will cause the control node 50 (PU) to leak due to the leakage of the thin film transistor T1, thereby causing a difference in the output of the output terminal Gout, thereby causing the problem of displaying horizontal stripes.

[0092] Therefore, the present application provides a second capacitor 1030, a fifth switch transistor 1040, and a sixth switch transistor 1050 in the gate drive circuit. The second capacitor 1030 includes a third electrode 1031 and a fourth electrode 1032 arranged opposite to each other. The third electrode 1031 is connected to the control node 50, the fourth electrode 1032 is connected to the first end of the fifth switch transistor 1040, and the fourth electrode 1032 is also connected to the first end of the sixth switch transistor 1050. The second end of the fifth switch transistor 1040 is connected to the control node 50. The third end of the fifth switch transistor 1040 is used to receive a fourth signal for controlling the switching of the fifth switch transistor 1040. The second end of the sixth switch transistor 1050 is connected to the scan signal output terminal Gout(n), and the third end of the sixth switch transistor 1050 is used to receive a fifth signal for controlling the switching of the sixth switch transistor 1050. Thus, when touch display is not in progress, the fifth switching transistor 1040 is controlled to be turned on by the fourth signal, and the sixth switching transistor 1050 is controlled to be turned off by the fifth signal, so that the fourth electrode 1032 of the second capacitor 1030 is connected to the control node 50, so that there is no potential difference between the third electrode 1031 and the fourth electrode 1032, that is, the energy storage capacitor 1022 in the gate drive circuit is not changed. When touch display is in progress, the fifth switching transistor 1040 is controlled to be turned off by the fourth signal, and the sixth switching transistor 1050 is controlled to be turned on by the fifth signal, so that the fourth electrode 1032 of the second capacitor 1030 is connected to the scan signal output terminal Gout(n), so that there is a potential difference between the third electrode 1031 and the fourth electrode 1032, which is equivalent to connecting the second capacitor 1030 in parallel with the energy storage capacitor 1022, that is, increasing the capacitance value of the energy storage capacitor 1022 in the gate drive circuit. Thus, the capacitance value of the energy storage capacitor can be adjusted according to whether touch display is in progress, thereby improving the display stripe problem caused by touch display.

[0093] In one embodiment of the present application, referring to Figure 12 , Figure 12This is an example diagram of the operation timing of the gate driver circuit provided by an embodiment of the present application. Each frame period of the display panel includes an interlaced display phase and a touch sensing phase. At the beginning of a new frame period, a synchronization signal generates a downward pulse signal, and then the frame period officially begins. During the frame period, during the display phase, some shift registers in the gate driver circuit output scan signals to some pixel rows in the display area, causing the corresponding pixel units to display corresponding grayscales. Then, during the touch sensing phase, the gate driver circuit pauses outputting scan signals, and the source and touch driver circuit output touch sensing signals to the touch sensing electrodes in the display area, causing the touch sensing electrodes to perform touch sensing functions. Subsequently, when transitioning from the touch sensing phase to the display phase, the source and touch driver circuit stop outputting touch sensing signals to suspend touch sensing, and some shift registers in the gate driver circuit subsequent to the shift register that has output the scan signal output scan signals to some pixel rows in the display area, causing the corresponding pixel units to display corresponding grayscales. The subsequent touch sensing phase and display phase are also carried out in the same manner as above until the frame period ends. Figure 12 The illustration is limited. In each frame period, the number of display phases can be 2, 3, or more, and the number of touch sensing phases can be less than, equal to, or greater than the number of display phases. Furthermore, all touch sensing phases in the same frame period can have substantially the same duration.

[0094] In the embodiment of the present application, considering that when performing touch display, as the touch time is inserted, the holding time of the control node 50 (PU) of the next-level gate drive circuit is prolonged, the leakage of the thin film transistor T1 will cause the control node 50 (PU) to leak, thereby causing a difference in the output of the output terminal Gout, thereby causing the problem of display horizontal stripes. Therefore, before entering the touch sensing stage, the fifth switch transistor 1040 can be controlled to be closed based on the fourth signal, and the sixth switch transistor 1050 can be controlled to be turned on based on the fifth signal to make the fourth electrode 1032 and the scan signal output terminal Gout (n) conductive. Therefore, before entering the touch sensing stage, the fourth electrode 1032 of the second capacitor 1030 can be connected to the scan signal output terminal Gout (n), so that there is a potential difference between the fourth electrode 1032 and the third electrode 1031 (connected to the control node 50), thereby connecting the second capacitor 1030 in parallel with the energy storage capacitor 1022, thereby increasing the capacitance of the energy storage capacitor 1022. Thus, charging can be completed before entering the touch sensing phase, thereby overcoming the display streak problem caused by leakage of the control node 50 (PU) due to leakage of the thin film transistor T1. After the touch sensing phase ends, the fifth switch transistor 1040 is controlled to turn on based on the fourth signal, and the sixth switch transistor 1050 is controlled to turn off based on the fifth signal, so that the fourth electrode 1032 and the control node 50 are conductive. After the touch sensing phase ends, the fourth electrode 1032 of the second capacitor 1030 can be connected to the control node 50, so that there is no potential difference between the fourth electrode 1032 and the third electrode 1031 (connected to the control node 50), thereby not changing the capacitance of the energy storage capacitor 1022.

[0095] An embodiment of the present application also includes a display panel, wherein the display panel includes the gate driving circuit provided by any embodiment of the present application and the pixel driving circuit provided by any embodiment of the present application.

[0096] In an embodiment of the present application, since the display panel includes the gate driving circuit provided by any embodiment of the present application and the pixel driving circuit provided by any embodiment of the present application, the display panel can improve the display effect when the driving frequency switches the display, and improve the display horizontal stripe problem caused by touch display.

[0097] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0098] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0099] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0100] Those skilled in the art will appreciate that all or some of the steps in the methods, systems, and functional modules / units in the devices disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0101] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0102] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0103] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0104] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0105] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0106] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk, and other media that can store programs.

[0107] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A pixel driving circuit, characterized in that: include: Data lines, scan lines and at least one sub-pixel driving circuit; The sub-pixel driving circuit includes a driving transistor, a pixel electrode, a common electrode, and a storage capacitor, wherein a control terminal of the driving transistor is connected to a scan line, a first terminal of the driving transistor is connected to a data line, a second terminal of the driving transistor is connected to the pixel electrode, the common electrode is arranged opposite to the pixel electrode and is connected to a common voltage terminal, one terminal of the storage capacitor is connected to the pixel electrode, and the other terminal of the storage capacitor is connected to the common voltage terminal; The sub-pixel driving circuit further includes a first capacitor, the first capacitor including a first electrode and a second electrode disposed opposite to each other, the pixel driving circuit further including at least one first switching transistor and at least one second switching transistor, the first electrode being connected to the pixel electrode, the second electrode being connected to a first end of the first switching transistor, and the second electrode being further connected to a first end of the second switching transistor; The second end of the first switching transistor is connected to the data line, and the third end of the first switching transistor is used to access the first signal that controls the switching of the first switching transistor; the second end of the second switching transistor is connected to the common voltage end, and the third end of the second switching transistor is used to access the second signal that controls the switching of the second switching transistor.

2. The pixel driving circuit according to claim 1, wherein: The sub-pixel driving circuit also includes a third switching transistor, a first end of the third switching transistor is connected to the second electrode, a second end of the third switching transistor is used to connect the first end of the first switching transistor and the first end of the second switching transistor, and a third end of the third switching transistor is used to connect the scan line.

3. The pixel driving circuit according to claim 2, wherein: The sub-pixel driving circuit further includes a diode, a first end of the diode is connected between the first end of the third switch transistor and the second electrode, and a second end of the diode is connected to the pixel electrode.

4. The pixel driving circuit according to claim 2 or 3, characterized in that: The pixel driving circuit further includes a first signal line and a second signal line; The first signal line and the second signal line are arranged along a row direction, the first signal line is used to receive the first signal sent by the source driver module, and the second signal line is used to receive the second signal sent by the source driver module; The third terminal of the first switching transistor is used to connect to the first signal line to receive the first signal for controlling the switching of the first switching transistor; The third terminal of the second switch transistor is used to connect to the second signal line to receive the second signal for controlling the switching of the second switch transistor.

5. The pixel driving circuit according to claim 2, wherein: The sub-pixel driving circuit also includes a fourth switching transistor, a first end of the fourth switching transistor is connected between the first end of the third switching transistor and the second electrode, a second end of the fourth switching transistor is connected to the pixel electrode, and a third end of the fourth switching transistor is connected to a third signal for controlling the switching of the fourth switching transistor.

6. The pixel driving circuit according to claim 5, wherein: The pixel driving circuit further includes a third signal line, the third signal line is arranged along a row direction, and the third signal line is used to receive the third signal sent by the source driving module; The third terminal of the fourth switch transistor is connected to the third signal line to receive the third signal for controlling the switching of the fourth switch transistor.

7. A driving method for driving the pixel driving circuit according to any one of claims 1 to 6, characterized in that: The method comprises: By detecting the length of the vertical blank gap area, the driving frequency of the current frame is obtained; When the driving frequency exceeds a preset threshold, a first signal for controlling the first switch transistor to turn on and a second signal for controlling the second switch transistor to turn off are generated, and the first signal is transmitted to the third terminal of the first switch transistor and the second signal is transmitted to the third terminal of the second switch transistor, so that the second electrode and the data line are electrically connected; When the driving frequency does not exceed the preset threshold, a first signal for controlling the first switching transistor to turn off and a second signal for controlling the second switching transistor to turn on are generated, and the first signal is transmitted to the third end of the first switching transistor and the second signal is transmitted to the third end of the second switching transistor, so that the second electrode and the common voltage end are connected.

8. The method according to claim 7, characterized in that After obtaining the driving frequency of the current frame by detecting the length of the vertical blank gap area, the method further includes: When the driving frequency exceeds the preset threshold, a third signal for controlling the fourth switch transistor to turn on is generated, and the third signal is transmitted to the third terminal of the fourth switch transistor, so that the pixel electrode is connected to the data line through the fourth switch transistor; When the driving frequency does not exceed the preset threshold, a third signal for controlling the fourth switch transistor to be turned off is generated, and the third signal is transmitted to the third end of the fourth switch transistor, so that the pixel electrode is not connected to the data line.

9. A display panel, characterized in that: The display panel includes a gate driving circuit and a pixel driving circuit, wherein: The pixel driving circuit is the pixel driving circuit according to any one of claims 1 to 6; and / or The gate drive circuit includes a plurality of shift registers, which are used to provide a plurality of scan signals to a plurality of scan lines respectively and sequentially during a frame period of the display panel. Each of the shift registers includes a pre-charging unit and a pull-up unit. The output end of the pre-charging unit is electrically connected to a control node for pre-charging the control node. The pull-up unit includes a first transistor and an energy storage capacitor. The first end of the first transistor is connected to the control node, the second end of the first transistor is connected to a clock signal input end, and the third end of the first transistor is connected to a scan signal output end. The first end of the energy storage capacitor is connected to the control node, and the second end of the energy storage capacitor is connected to the scan signal output end. The gate drive circuit further includes a second capacitor, a fifth switching transistor, and a sixth switching transistor, the second capacitor including a third electrode and a fourth electrode disposed opposite to each other, the third electrode being connected to the control node, the fourth electrode being connected to the first terminal of the fifth switching transistor, and the fourth electrode being further connected to the first terminal of the sixth switching transistor; The second end of the fifth switching transistor is connected to the control node, and the third end of the fifth switching transistor is used to access the fourth signal for controlling the switching of the fifth switching transistor; the second end of the sixth switching transistor is connected to the scan signal output end, and the third end of the sixth switching transistor is used to access the fifth signal for controlling the switching of the sixth switching transistor.

10. The display panel according to claim 9, wherein: The frame period includes a plurality of display phases and a plurality of touch sensing phases, and the display phases and the touch sensing phases are switched alternately. Based on the fact that the gate driving circuit includes a second capacitor, a fifth switching transistor, and a sixth switching transistor, Before entering the touch sensing phase, controlling the fifth switch transistor to be turned off based on the fourth signal, and controlling the sixth switch transistor to be turned on based on the fifth signal, so that conduction is achieved between the fourth electrode and the scan signal output terminal; After the touch sensing phase ends, the fifth switch transistor is controlled to be turned on based on the fourth signal, and the sixth switch transistor is controlled to be turned off based on the fifth signal, so that the fourth electrode is conductively connected to the control node.

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