Information processing method and device, resource allocation method and device, and electronic equipment

Abstract

An information processing method and device, a resource allocation method and device, an electronic device, and a storage medium. The information processing method includes: collecting performance data generated by a processor in the process of executing a task, wherein the processor runs multiple threads to execute the task at the same time, and the performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads; generating compilation instruction information corresponding to the task according to the performance data; inserting the compilation instruction information into the compiler of the task to obtain the optimized compiler corresponding to the task, wherein the compilation instruction information is used to allocate the hardware resources of the processor when the processor runs the optimized compiler. The information processing method can control or divide the resources used by the threads in a targeted manner according to the characteristics of the program itself, so that the resource allocation is more reasonable and the performance of the processor is effectively improved.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an information processing method, a resource allocation method, an information processing device, a resource allocation device, an electronic device, and a non-transitory computer-readable storage medium. Background Art

[0002] Simulate Multi-Threading (SMT) technology is an important technology to improve the overall performance of the processor. It uses the multi-issue and out-of-order execution mechanisms of high-performance processing cores (such as central processing unit cores, CPU cores) to execute instructions of multiple threads simultaneously, so that a physical core is presented to the software and operating system as multiple virtual processing cores. When a modern multi-issue high-performance processing core executes a single thread, its internal multiple execution units and hardware resources cannot be fully utilized most of the time; when the thread is paused for some reason (such as L2 cache miss), the hardware execution unit can only run idle, which causes a waste of hardware resources and reduces the performance-power ratio. In SMT mode, when a thread is paused, other threads can still run, which improves the utilization of hardware resources, thereby improving the multi-threaded throughput, overall performance and performance-power ratio of the processor. Summary of the invention

[0003] At least one embodiment of the present disclosure provides an information processing method, comprising: collecting performance data generated by a processor during the execution of a task, wherein the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand of each of the multiple threads for different hardware resources in the processor; generating compilation instruction information corresponding to the task based on the performance data; inserting the compilation instruction information into a compiler of the task to obtain an optimized compiler corresponding to the task, wherein the compilation instruction information is used for allocating hardware resources of the processor when the processor runs the optimized compiler.

[0004] For example, in the information processing method provided by at least one embodiment of the present disclosure, the performance data includes the occupancy of the different hardware resources by the processor in the process of running the task, and the compilation instruction information corresponding to the task is generated according to the performance data, including: determining the criticality of each hardware resource to each thread according to the occupancy of the different hardware resources by the processor in the process of running the task; and generating the compilation instruction information in combination with the criticality of each hardware resource to each thread, wherein the compilation instruction information is used to adjust the occupancy ratio and / or dynamic usage range of each thread to each hardware resource according to the criticality of each hardware resource to each thread when running the optimization compiler.

[0005] For example, in the information processing method provided by at least one embodiment of the present disclosure, for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to reduce the allocation ratio of any hardware resource allocated to the N threads, or to limit the dynamic usage range of any hardware resource by the N threads, wherein M and N are positive integers.

[0006] For example, in the information processing method provided by at least one embodiment of the present disclosure, any one of the hardware resources includes a cache, and the occupation of the different hardware resources by the processor in the process of running the task includes the number of times each thread occupies the cache, and the criticality of each hardware resource to each thread is determined according to the occupation of the different hardware resources by the processor in the process of running the task, including: for each thread: determining the criticality of the cache to the thread according to the number of times the thread occupies the cache, wherein, in response to fewer times the thread occupies the cache, the criticality of the cache to the thread is lower; wherein the compilation instruction information is used to instruct to reduce the allocation ratio of the cache allocated to the N threads when running the optimization compiler, or to restrict the N threads to select a cache line from the cache lines occupied by the N threads for cache replacement when cache replacement occurs.

[0007] For example, in the information processing method provided by at least one embodiment of the present disclosure, any one of the hardware resources includes a branch target table, each branch target table entry in the branch target table is used to store relevant information of branch jumps, the occupation of the different hardware resources by the processor in the process of running the task includes the branch prediction accuracy of each branch in each thread, and the criticality of each hardware resource to each thread is determined according to the occupation of the different hardware resources by the processor in the process of running the task, including: for each thread: according to the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, determining the criticality of the branch target table to the thread, wherein, in response to the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, the more branches are, the lower the criticality of the branch target table to the thread; wherein, the compilation instruction information is used to indicate to reduce the allocation ratio of the branch target table to the N threads when running the optimization compiler, or to restrict the N threads to select a branch target table entry from the branch target table entries occupied by the N threads for replacement when applying for a branch target table entry.

[0008] For example, in the information processing method provided by at least one embodiment of the present disclosure, the occupation of the different hardware resources by the processor in the process of running the task includes the total occupation of each hardware resource by each thread within a preset time period of running the task, and the criticality of each hardware resource to each thread is determined based on the occupation of the different hardware resources by the processor in the process of running the task, including: determining the criticality of each hardware resource to each thread based on the total occupation of each hardware resource by the multiple threads.

[0009] For example, in the information processing method provided by at least one embodiment of the present disclosure, the criticality of each hardware resource to each thread is determined according to the total amount of occupation of each hardware resource by the multiple threads, including: for a first hardware resource among the different hardware resources: for each thread, in response to the total amount of occupation of the first hardware resource by the thread being less than B / b, determining that the criticality of the first hardware resource to the thread is not critical, wherein the first hardware resource is a hardware resource exclusively used by the multiple threads, B represents the total amount of resources of the first hardware resource, b is the total number of the multiple threads, and B and b are integers greater than 1; wherein, in response to the criticality of the first hardware resource to at least one thread among the multiple threads being not critical, the compilation instruction information is used to indicate, when running the optimization compiler, that the first hardware resource is allocated to each thread among the at least one thread according to the total amount of occupation of the first hardware resource by each thread.

[0010] For example, in the information processing method provided by at least one embodiment of the present disclosure, the criticality of each hardware resource to each thread is determined according to the total amount of occupation of each hardware resource by the multiple threads, including: for any hardware resource, according to the total amount of occupation of the any hardware resource by each thread, determining the sum of the total amount of occupation of the any hardware resource by the multiple threads; in response to the sum of the total amount of occupation being greater than the total amount of resources of the any hardware resource: determining the total duration of pipeline stagnation of each thread when the any hardware resource is missing; determining the criticality of the any hardware resource to each thread according to the total duration of pipeline stagnation of each thread, wherein the total duration of pipeline stagnation is positively correlated with the criticality; wherein the compilation instruction information is used to indicate, when running the optimization compiler, to increase the allocation ratio of threads with higher criticality to the any hardware resource and reduce the allocation ratio of threads with lower criticality to the any hardware resource.

[0011] For example, in the information processing method provided by at least one embodiment of the present disclosure, for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to increase the allocation ratio of any hardware resource to the M threads.

[0012] For example, in the information processing method provided by at least one embodiment of the present disclosure, the criticality of each hardware resource to each thread is determined according to the occupation of the different hardware resources by the processor in the process of running the task, including: determining the total duration of pipeline stagnation of the thread due to the lack of any hardware resource or the proportion of the stagnation time in the total running time based on the duration of pipeline interruption or stagnation of the thread when the thread lacks any one of the hardware resources and the number of times the thread lacks any one of the hardware resources; determining the criticality of the thread to any one of the hardware resources based on the total duration or the proportion.

[0013] For example, in the information processing method provided by at least one embodiment of the present disclosure, the occupation of the different hardware resources by the processor in the process of running the task includes any combination of the following parameters: the number of times each thread occupies each hardware resource, the number of times each thread stalls in the pipeline when each hardware resource is lacking, the duration of the pipeline stall when each thread is lacking each hardware resource, the total amount of occupation of each hardware resource by each thread, and the branch prediction accuracy of each branch in each thread.

[0014] For example, in the information processing method provided by at least one embodiment of the present disclosure, the performance data includes the time distribution of the multiple threads occupying each hardware resource when the processor runs the task, and the compilation instruction information corresponding to the task is generated according to the performance data, including: generating the compilation instruction information in combination with the time distribution of the multiple threads occupying each hardware resource when the processor runs the task, wherein the compilation instruction information is used to control the occupation timing of each hardware resource by each thread according to the time distribution of the multiple threads occupying each hardware resource when running the optimization compiler.

[0015] For example, in the information processing method provided by at least one embodiment of the present disclosure, the compilation instruction information is used to reserve the target hardware resources for the thread when the thread is close to using the target hardware resources according to the time distribution of the multiple threads occupying each hardware resource when running the optimization compiler.

[0016] For example, in the information processing method provided by at least one embodiment of the present disclosure, the performance data includes the dependency relationship between the hardware resources used by each thread of the processor when running the task, and the compilation instruction information corresponding to the task is generated according to the performance data, including: generating the compilation instruction information in combination with the dependency relationship between the hardware resources used by each thread, wherein the compilation instruction information is used to control the occupation timing or resource occupation priority of the thread according to the dependency relationship between the hardware resources used by each thread when running the optimization compiler.

[0017] For example, in the information processing method provided by at least one embodiment of the present disclosure, in response to the existence of a dependency relationship between P hardware resources used by the thread to perform a first operation, the P hardware resources include a target hardware resource, and P is a positive integer greater than 1. The compilation instruction information is used to indicate, when running the optimization compiler, that after the remaining P-1 hardware resources other than the target hardware resource return the usage data required to perform the first operation, the occupancy right of the target hardware resource is allocated to the thread, or the occupancy priority of the thread for the target hardware resource is increased.

[0018] For example, in the information processing method provided by at least one embodiment of the present disclosure, the dependency relationship between the hardware resources used by each thread is obtained through the occupancy of multiple hardware resources when the pipeline of each thread is stalled, wherein the multiple hardware resources include other hardware resources among the different hardware resources except the hardware resources that directly cause the pipeline of the thread to be stalled.

[0019] For example, in the information processing method provided in at least one embodiment of the present disclosure, the hardware resources in the processor include computing resources and storage resources, the computing resources include computing logic units and address calculation units, and the storage resources include cache, memory, queues, and registers.

[0020] For example, in the information processing method provided by at least one embodiment of the present disclosure, the processor includes at least one physical core, and the multiple threads run in the same physical core.

[0021] At least one embodiment of the present disclosure provides a resource allocation method, comprising: allocating hardware resources of a processor used when the processor executes a task according to compilation instruction information, wherein the compilation instruction information is generated according to performance data generated by the processor in the process of running a compilation program corresponding to the task, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand of different hardware resources in the processor by each of the multiple threads.

[0022] For example, in the resource allocation method provided in at least one embodiment of the present disclosure, the hardware resources of the processor used when the processor executes a task are allocated according to the compilation instruction information, including: determining the criticality of each hardware resource to each thread according to the compilation instruction information; and adjusting the occupancy ratio and / or dynamic usage range of each thread for each hardware resource according to the criticality of each hardware resource to each thread.

[0023] For example, in the resource allocation method provided in at least one embodiment of the present disclosure, the occupancy ratio and / or dynamic usage range of each thread for each hardware resource is adjusted according to the criticality of each hardware resource to each thread, including: for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, reducing the allocation ratio of any hardware resource allocated to the N threads, or limiting the dynamic usage range of the N threads for any hardware resource, where M and N are positive integers.

[0024] For example, in the resource allocation method provided in at least one embodiment of the present disclosure, any one of the hardware resources includes a cache, and the occupancy ratio and / or dynamic usage range of each hardware resource by each thread is adjusted according to the criticality of each hardware resource to each thread, including: reducing the allocation ratio of the cache allocated to the N threads, or restricting the N threads to select a cache line from the cache lines occupied by the N threads for cache replacement when cache replacement occurs.

[0025] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, any one of the hardware resources includes a branch target table, and each branch target table entry in the branch target table is used to store relevant information of branch jumps, and according to the criticality of each hardware resource to each thread, the occupation ratio and / or dynamic usage range of each hardware resource by each thread is adjusted, including: reducing the allocation ratio of the branch target table allocated to the N threads, or restricting the N threads to select a branch target table entry from the branch target table entries already occupied by the N threads for replacement when applying for a branch target table entry.

[0026] For example, in the resource allocation method provided in at least one embodiment of the present disclosure, any one of the hardware resources includes a first hardware resource, and the first hardware resource is a hardware resource exclusively used by each of the multiple threads. According to the criticality of each hardware resource to each thread, the occupancy ratio and / or dynamic usage range of each hardware resource by each thread is adjusted, including: in response to the criticality of the first hardware resource to at least one thread among the multiple threads being non-critical, for each thread among the at least one thread, the first hardware resource is allocated according to the total amount of occupancy of the first hardware resource by each thread, wherein the total amount of occupancy of the first hardware resource by each thread is determined during the process of collecting the performance data.

[0027] For example, in the resource allocation method provided in at least one embodiment of the present disclosure, the occupancy ratio and / or dynamic usage range of each thread for each hardware resource is adjusted according to the criticality of each hardware resource to each thread, including: for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, the allocation ratio of any hardware resource allocated to the M threads is increased.

[0028] For example, in the resource allocation method provided in at least one embodiment of the present disclosure, the hardware resources of the processor used when the processor executes a task are allocated according to compilation instruction information, including: according to the compilation instruction information, controlling the occupancy timing or resource occupancy priority of each thread for each hardware resource.

[0029] For example, in the resource allocation method provided by at least one embodiment of the present disclosure, in response to the existence of a dependency relationship between P hardware resources used by the thread to perform a first operation, the P hardware resources include a target hardware resource, and P is a positive integer greater than 1. According to the compilation instruction information, the occupancy timing or resource occupancy priority of each hardware resource by each thread is controlled, including: according to the compilation instruction information, after the remaining P-1 hardware resources other than the target hardware resource return the usage data required to perform the first operation, the occupancy right of the target hardware resource is allocated to the thread, or the occupancy priority of the thread for the target hardware resource is increased.

[0030] At least one embodiment of the present disclosure provides an information processing device, comprising: a collection module, configured to collect performance data generated by a processor during the execution of a task, wherein the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand of the multiple threads for different hardware resources in the processor; a generation module, configured to generate compilation instruction information corresponding to the task based on the performance data; and an insertion module, configured to insert the compilation instruction information into a compilation program of the task to obtain an optimized compilation program corresponding to the task, wherein the compilation instruction information is used for allocation of hardware resources to the processor when the processor runs the optimized compilation program.

[0031] At least one embodiment of the present disclosure provides a resource allocation device, comprising: an allocation module, configured to allocate hardware resources of a processor used when the processor executes a task according to compilation instruction information, wherein the compilation instruction information is generated according to performance data generated by the processor in the process of running a compilation program corresponding to the task, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand of different hardware resources in the processor by each of the multiple threads.

[0032] At least one embodiment of the present disclosure provides an electronic device, comprising: a memory, which non-transitorily stores computer-executable instructions; and a processor, which is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement the information processing method according to any embodiment of the present disclosure, or execute the resource allocation method according to any embodiment of the present disclosure.

[0033] At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the information processing method according to any embodiment of the present disclosure is implemented, or the resource allocation method according to any embodiment of the present disclosure is executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0035] Figure 1 Schematic diagram of optimizing guidance for one property;

[0036] Figure 2 A schematic flow chart of an information processing method provided for at least one embodiment of the present disclosure;

[0037] Figure 3 A schematic flow chart of a resource allocation method provided in at least one embodiment of the present disclosure;

[0038] Figure 4 A schematic block diagram of an information processing device provided for at least one embodiment of the present disclosure;

[0039] Figure 5 A schematic block diagram of a resource allocation device provided in at least one embodiment of the present disclosure

[0040] Figure 6 A schematic structural diagram of an electronic device provided for at least one embodiment of the present disclosure;

[0041] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0044] In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components.

[0045] There are generally multiple pipeline stages inside a modern processing core, such as branch prediction, instruction fetch, instruction decoding, instruction dispatch and rename, instruction execution, and Retire. In order to support high operating frequencies, each pipeline stage may contain multiple pipeline levels. An important feature of SMT is that in the same clock cycle, instructions in the same instruction execution pipeline level can come from multiple threads; while in other pipeline stages, often only one thread's instructions are selected and processed in one clock. Therefore, in these stages, it is necessary to select one from multiple threads to pass to the next pipeline stage, which is called thread scheduling. The choice of thread scheduling has an important impact on the overall performance, power consumption, and fairness between threads of SMT.

[0046] Depending on the maximum number of active threads supported, SMT can be called SMT2 (up to two active threads), SMT4 (up to four active threads), and so on.

[0047] There are different ways to allocate hardware resources within SMT. Commonly used methods are:

[0048] 1. All statically partitioned: All hardware resources are equally divided according to the maximum number of active threads supported by SMT.

[0049] 2. Full dynamic sharing: All hardware resources are dynamically shared by all threads.

[0050] 3. Hybrid mode: Some hardware resources are dynamically shared by all threads, while other resources are statically divided.

[0051] 4. Other methods: Multiple threads can be divided into multiple thread groups. All resources are statically divided between different thread groups, but resources within a thread group are dynamically shared.

[0052] During the process of compiling a program, by specifying the optimization level, the compiler can perform performance optimizations of varying degrees of aggressiveness, including but not limited to compilation techniques such as code reordering and code vectorization.

[0053] Figure 1 Schematic diagram of optimization guidance for one property.

[0054] For example, you can run the program once and analyze, through data collection, whether the program has a certain type of behavioral preference. If so, the compiler can perform further optimization based on the behavioral preference.

[0055] Take the following code as an example:

[0056] code A;

[0057] if (a == 0) / / code B;

[0058] a=a+1; / / code C;

[0059] code D;

[0060] If the above code exists, when the compiler statically compiles, there is no way to determine whether the variable a will be equal to 0 during actual execution. Therefore, the compiler chooses to follow the writing method of the high-level programming language, such as Figure 1 As shown in the flow on the left, the branch instruction (code B) is translated according to the original meaning and placed after code A. At this time, the program semantics is: if branch code B is established, skip code C and execute code D; if branch code B is not established, do not jump and execute code C in sequence. In other words, the compiler will follow the grammatical requirements of the high-level language itself and arrange code A, code B, code C, and code D continuously in the memory space.

[0061] Figure 1 In the figure, the dotted line represents the instruction control flow that rarely occurs, and the solid line represents the instruction control flow in most cases.

[0062] Assuming that the probability of a being equal to 0 being true is very low (low probability means <1%), then such code arrangement space will cause the program to frequently branch when code B is in progress, causing the CPU to interrupt the pipeline and re-fetch and decode the program flow where the branch occurred. Originally, the CPU thought that code C had been fetched when no branch occurred. After discovering the branch, the CPU needs to empty code C and all subsequent codes from the pipeline and re-fetch instructions from the address of code D. This behavior will have a serious impact on the performance of the CPU.

[0063] At this time, through the feature optimization guidance, after collecting the occurrence of branch code B during the dynamic execution of this program, such as Figure 1 As shown on the right, the compiler will choose to place the code of code C not after code B, but in a non-contiguous address space. At this time, the arrangement of code A, code B, and code D in the memory space is continuous, and code C is stored in another non-contiguous memory space with code A, code B, and code D. Therefore, the program is executed in the order of code A->code B->code D most of the time, and will not be interrupted by branch jumps (branch jumps include Figure 1Code B->code D on the left and Figure 1 The code B->code C->code D on the right side has a serious impact on CPU performance.

[0064] However, the above-mentioned compilation optimization technology only performs static analysis on the program code and does not care whether the program has certain preferences when it is actually executed. The optimization logic for executing programs of all characteristics is the same, and it is impossible to perform targeted optimization for the different characteristics of each program itself. Compilation optimization has limitations.

[0065] In addition, when the processing core uses SMT technology, since the thread has to share the hardware resources of the processing core with other threads, the performance of a thread running under SMT is often lower than its performance in single-threaded mode. Resource allocation is carried out according to the above four modes, and it is impossible to make targeted adjustments based on the characteristics of the program.

[0066] For example, taking SMT2 as an example, the processing core uses two threads (thread 0 and thread 1) to perform tasks at the same time. The cache is a dynamic shared resource, and thread 0 and thread 1 can share all storage space in the cache. Thread 0 is a streaming media application, for example. A large amount of streaming media data is often only used once and will not be used again in the future. Thread 0 is likely to occupy a large amount of cache, and then kick out thread 1's data from the cache, causing thread 1 to often pause due to cache misses, and performance plummets. At the same time, although thread 0 occupies a large amount of cache capacity, because these data are only one-time data, the cache capacity is used but the processor performance cannot be improved.

[0067] For example, branch instructions have the ability to interrupt the instruction flow. If the branch instructions are not handled well, the performance of the processor will be greatly affected. Branch prediction technology means that when the processor encounters a branch instruction, it no longer waits for the branch result to fetch the instruction, but directly predicts whether the branch will "jump" or "not jump" and the jump target address during the instruction fetch stage. The purpose is to achieve an uninterrupted instruction flow based on the prediction results, thereby reducing the processor's CPI (Cycle Per Instruction, the number of clock cycles required to execute an instruction). The processor can use the branch target table to store branch prediction information. Each branch target table entry in the branch target table is used to store relevant information about the branch jump, such as the jump direction and the jump target address.

[0068] The branch target table is a dynamically shared resource. Assuming that there are many branches in thread 0 that are difficult to predict accurately (for example, branches that are not direct jumps, such as jmp[mem], where the target address mem of the jump depends on the specific value written to mem by the previous program), thread 0 may use many branch target table entries, but this does not increase the branch prediction accuracy of thread 0. At the same time, thread 1 is kicked out by thread 0 because of the branch target table entries it occupies, resulting in the inability to make branch predictions when subsequent branches come, thereby reducing performance.

[0069] For example, statically partitioned resources are usually pre-divided equally among threads, and each thread uses them exclusively. However, it is very likely that some threads will not use so many resources in actual scenarios, or even if the pipeline of the processing core is occasionally stalled due to insufficient resources, it will not greatly affect performance, while another thread may urgently need the resource. In this case, if the resources are still divided equally, it will be detrimental to performance.

[0070] For example, in some cases, even if thread 0 has won some dynamically shared resource A, it may still need to wait for resource B to continue execution, which may cause another thread 1 to pause due to lack of resource A. For example, thread 0 has won resource A, but it needs the value returned by resource B to perform operations on resource A. Therefore, before resource B returns the value, thread 0 occupies a large amount of resource A, but there is no performance improvement.

[0071] At least one embodiment of the present disclosure provides an information processing method, a resource allocation method, an information processing device, a resource allocation device, an electronic device, and a non-transitory computer-readable storage medium.

[0072] The information processing method provided by at least one embodiment of the present disclosure includes: collecting performance data generated by a processor during the execution of a task, wherein the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads; generating compilation instruction information corresponding to the task based on the performance data; inserting the compilation instruction information into the compiler of the task to obtain the optimized compiler corresponding to the task, wherein the compilation instruction information is used for allocating hardware resources of the processor when the processor runs the optimized compiler.

[0073] The information processing method provided by at least one embodiment of the present disclosure can perform customized compilation optimization according to the characteristics of the program itself that runs different tasks, and obtains compilation instruction information for processor resource allocation when the program is running by collecting performance data generated by the running program, thereby providing a reference for resource allocation for the processor to run the program, so that the hardware resources used by the threads can be controlled or divided in a targeted manner according to the characteristics of the program itself, making resource allocation more reasonable and effectively improving the performance of the processor.

[0074] At least one embodiment of the present disclosure also provides a resource allocation method, including: allocating hardware resources of a processor used when the processor executes a task according to compilation instruction information, wherein the compilation instruction information is generated based on performance data generated by the processor in the process of executing a compilation program corresponding to the task, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads.

[0075] The information processing method provided by at least one embodiment of the present disclosure can allocate hardware resources with reference to the compilation instruction information obtained based on the collected performance data, so that the hardware resources used by the threads can be controlled or divided in a targeted manner according to the characteristics of the program itself, making the resource allocation more reasonable and effectively improving the performance of the processor.

[0076] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

[0077] Figure 2 A schematic flow chart of an information processing method provided by at least one embodiment of the present disclosure. Figure 2 As shown, the data processing method provided by the embodiment of the present disclosure includes at least steps S10-S30.

[0078] For example, the information processing method is applied to a processor, such as a processor using the SMT technology.

[0079] For example, the processor includes at least one processing core, which is a physical core. Multiple threads are used (or run) in parallel in one processing core to perform tasks. The multiple threads can be understood as multiple logical cores virtualized in one physical core.

[0080] For example, the number b of the multiple threads may be equal to or less than the maximum number of active threads supported by a physical core, where b is a positive integer greater than 1.

[0081] In step S10, performance data generated by the processor during task execution is collected.

[0082] For example, the processor uses multiple threads to execute tasks at the same time. For example, the processor uses concurrent multi-threading to execute tasks. Multiple threads are located in the same physical core, and multiple threads share the hardware resources in the physical core. This sharing includes static sharing and static sharing.

[0083] For example, hardware resources include computing resources and storage resources in a processor. For example, computing resources include hardware resources such as Arithmetic and Logic Unit (ALU) and Address Generation Unit (AGU) for computing. For example, storage resources include hardware resources such as cache, memory, queue, and register for caching data or pipeline-related instructions.

[0084] For example, in some examples, hardware resources may refer to all resources in a processor that can be used for computing or storage.

[0085] For example, hardware resources may also refer to some computing or storage resources in a processor. For example, by analyzing the performance data of multiple tasks collected, it is found that certain hardware resources are sufficient for most tasks, or their absence will not have a significant impact on the performance of the processor. These hardware resources do not need to be optimized for resource allocation, or resource allocation optimization cannot improve the performance of the processor. The hardware resources in this disclosure may include other hardware resources in the processor except these hardware resources.

[0086] For example, performance data can be collected by executing a compiler corresponding to a task. For example, the compiler is obtained by compiling the program corresponding to the task based on conventional optimization rules and general optimization logic. The compiler may be a compiler that has not undergone compilation optimization, or a compiler that has performed some optimizations such as code reordering after static analysis of the code itself.

[0087] For example, you can deploy a task on a processor that uses SMT technology, run a compiled program for a period of time, and collect performance data during the task execution.

[0088] For example, the performance data may indicate the degree of demand of multiple threads for different hardware resources in the processor. For example, by analyzing the performance data, the degree of demand of different threads for each hardware resource may be determined.

[0089] For example, for thread 0 included in multiple threads, if the absence of a certain hardware resource will cause thread 0 to be interrupted or stalled, such interruption or stalling will have a greater impact on the performance of the processor, and thread 0 has a higher demand for the hardware resource, and this hardware resource is more critical to thread 0. On the contrary, if the absence of a certain hardware resource will not cause thread 0 to be interrupted or stalled, or even if the interruption or stalling occurs, it will not have a significant impact on the performance of the processor, thread 0 has a lower demand for the hardware resource, and the criticality of this hardware resource to thread 0 is also lower.

[0090] For example, the performance data may indicate the timings at which multiple threads require different hardware resources in the processor. For example, by analyzing the performance data, the timings at which different threads require each hardware resource may be obtained.

[0091] In step S20, compilation instruction information corresponding to the task is generated according to the performance data.

[0092] In step S30, compilation instruction information is inserted into the compiler of the task to obtain an optimized compiler corresponding to the task.

[0093] For example, the compilation instruction information is used to allocate the hardware resources of the processor when the processor runs an optimizing compiler.

[0094] For example, the compilation instruction information corresponds to the task one by one, and different programs that execute different tasks have different compilation instruction information. The compilation instruction information provides a reference for hardware resource allocation for the processor according to the program characteristics of the corresponding task.

[0095] For example, the compilation instruction information may directly include performance data, that is, the performance data may be provided to the processor as the compilation instruction information, and the processor analyzes the performance data in the compilation instruction information when running the optimization compiler to determine the allocation of the processor's hardware resources. In this embodiment, the processor's analysis process of the performance data is similar to the process of generating the compilation instruction information as the analysis result described later, and will not be repeated here.

[0096] For example, the performance data can also be analyzed and processed to obtain compilation instruction information. The compilation instruction information provides analysis results of the degree of demand or criticality of some threads for different hardware resources. The processor can directly allocate resources based on the compilation instruction information, saving analysis time and reducing data transmission.

[0097] For example, compilation instructions can be inserted into the compiler header or other agreed locations to obtain an optimized compiler, which can perform targeted compilation optimization based on the characteristics of the task. Different from compilation optimization based on general scenarios or compilation optimization based on static code analysis, the optimized compiler can perform targeted compilation optimization based on the characteristics of the program itself during operation. This compilation optimization is mainly reflected in the allocation of hardware resources, so that hardware resources can be allocated more reasonably and the performance of the processor can be improved.

[0098] For example, when the processor runs the optimization compiler, it can refer to the compilation instruction information to allocate the hardware resources of the processor. For example, the allocation of hardware resources can include at least one of adjusting the resource allocation ratio and controlling the resource occupation timing. The specific process of generating the compilation instruction information is described below for the above two allocation methods.

[0099] For example, performance data includes how the processor uses different hardware resources while executing a task.

[0100] Step S20 may include: determining the criticality of each hardware resource to each thread based on the occupancy of different hardware resources by the processor in the process of executing the task; generating compilation instruction information based on the criticality of each hardware resource to each thread, wherein the compilation instruction information is used to adjust the occupancy ratio and / or dynamic usage range of each thread to each hardware resource according to the criticality of each hardware resource to each thread when running the optimization compiler.

[0101] For example, the criticality can indicate the degree of demand for the hardware resource for the thread, such as the importance level. For example, as mentioned above, if a certain hardware resource is missing, thread 0 will be interrupted or stalled, and such interruption or stalling will have a greater impact on the performance of the processor, and the criticality of this hardware resource for thread 0 is relatively high; if a certain hardware resource is missing, thread 0 will not be interrupted or stalled, or even if an interruption or stalling occurs, it will not have a significant impact on the performance of the processor, and the criticality of this hardware resource for thread 0 is relatively low.

[0102] For example, criticality can be defined using the two states "critical" and "non-critical".

[0103] For example, the criticality can be defined by multiple states, such as scoring the criticality, where a higher score represents a higher criticality, a more important thread, or a higher demand for the hardware resource by the thread. When the criticality is defined by multiple states, compared to defining it by two states, the importance level can be more refined, and the resource allocation ratio can be adjusted more reasonably.

[0104] For example, for a hardware resource, when some threads consider the hardware resource to be important or critical to themselves, and some threads consider the hardware resource to be unimportant or non-critical to themselves, adjusting the resource allocation ratio for these hardware resources can significantly improve the performance of the processor.

[0105] For example, in some embodiments, for any hardware resource, in response to the criticality of any hardware resource to M threads among multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to reduce the allocation ratio of any hardware resource to N threads, or to limit the dynamic usage range of any hardware resource by N threads.

[0106] For example, for a certain hardware resource, if the criticality of the hardware resource to M threads is greater than or equal to a first threshold, it means that M threads believe that the hardware resource is more critical to themselves, and the criticality of the hardware resource to N threads is less than or equal to a second threshold, it means that N threads believe that the hardware resource is less critical. At this time, when running the optimization compiler, you can refer to the compilation instruction information generated based on the criticality of each hardware resource to each thread, reduce the allocation ratio of the hardware resource to these N threads that believe that the hardware resource is not very important to them, or limit the dynamic usage range of the hardware resource by the N threads.

[0107] In this way, the waste of hardware resources can be reduced, and this also indirectly increases the allocation ratio of the hardware resources allocated to other threads. For example, the allocation ratio of M threads to the resources is increased, thereby improving the performance of the processor and reducing the number and duration of stagnation or interruption of the thread pipeline caused by the lack of the hardware resources.

[0108] For example, the first threshold and the second threshold can be set as needed. For example, when the criticality includes two states, namely, critical and non-critical, the first threshold can be set as critical and the second threshold can be set as non-critical. For example, when the criticality is measured by a score of 0-100, the first threshold can be set as 70 and the second threshold can be set as 30. The present disclosure does not make any specific restrictions on this.

[0109] By subdividing the criticality, for example, using multiple states to measure the criticality of threads, the criticality level can be refined, the criticality comparison between threads can be more accurate, and the rationality of resource allocation can be improved.

[0110] For example, in one example, the hardware resource is a cache. In this embodiment, the occupation of different hardware resources by the processor during the execution of the task includes the number of times each thread occupies the cache. For example, this number of occupancy can be the number of times cached data in the cache is reused, such as the number of cache hits.

[0111] For example, determining the criticality of each hardware resource to each thread based on the occupation of different hardware resources by the processor in the process of executing a task can include: for each thread: determining the criticality of the cache to the thread based on the number of times the thread occupies the cache, wherein the fewer the number of times the thread occupies the cache, the lower the criticality of the cache to the thread; wherein the compilation instruction information is used to instruct to reduce the allocation ratio of the cache to N threads when running the optimization compiler, or to restrict the N threads to select a cache line from the cache lines occupied by the N threads for cache replacement when a cache replacement occurs.

[0112] For example, the criticality can be divided into critical and non-critical. When the number of cache occupancy times by a thread is less than a cache occupancy times threshold, the criticality of the cache to the thread is determined to be non-critical. When the number of cache occupancy times by the thread is greater than or equal to the occupancy times threshold, the criticality of the cache to the thread is determined to be critical.

[0113] For example, the criticality may also be subdivided into more states. In response to a smaller number of times a thread occupies a cache, the criticality of the cache to the thread is lower, and the thread has a lower demand for the cache.

[0114] For example, the compilation instruction information may be generated in combination with the criticality of the cache to each thread. For example, the compilation instruction information may include the criticality of the cache to each thread.

[0115] For example, when it is determined that the criticality of the cache to a certain thread is low, such as lower than the second threshold or the criticality is not critical, when running the optimization compiler, the processor can refer to the compilation instruction information to know that the criticality of the cache to the thread is low, and the processor can stipulate that the thread can only use part of the capacity in the cache, such as only 20% of the cache, or it can be stipulated that when the cache replacement occurs in the thread, only one of the cache lines previously applied by the thread can be replaced with a new cache line, or the two methods can be combined. In this way, it can be ensured that other threads will not be affected by the thread when using the cache.

[0116] In this embodiment, the performance data collected during the program running process is used to guide the compilation optimization through feature analysis, and the allocation of multi-threaded resources is adjusted so that the statically allocated hardware resources can be divided according to the characteristics of different threads. The dynamically allocated and multi-threaded shared hardware resources are controlled according to the usage characteristics of different threads to prevent some threads from occupying too many resources without helping to improve performance. The hardware resource allocation is more reasonable, and the performance of the processor is improved.

[0117] For example, in one example, the hardware resource is a branch target table. Each branch target table entry in the branch target table is used to store branch jump related information.

[0118] For example, the processor's occupancy of different hardware resources during task execution includes the branch prediction accuracy of each branch in each thread.

[0119] For example, determining the criticality of each hardware resource to each thread based on the occupation of different hardware resources by the processor in the process of executing a task can include: for each thread: determining the criticality of the branch target table to the thread based on the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, wherein the more the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, the lower the criticality of the branch target table to the thread; wherein the compilation instruction information is used to instruct to reduce the allocation ratio of the branch target table to N threads when running the optimization compiler, or to restrict the N threads to select a branch target table entry from the branch target table entries already occupied by the N threads for replacement when applying for the branch target table entry.

[0120] For example, the criticality can be divided into critical and non-critical. When the number of branches in a thread whose branch prediction accuracy is lower than the accuracy threshold is greater than or equal to the branch occupancy count threshold, that is, there are many branches in the thread that are difficult to predict accurately, the criticality of the branch target table to the thread is determined to be non-critical. When the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold is less than the branch occupancy count threshold, the criticality of the branch target table to the thread is determined to be critical.

[0121] For example, the criticality can also be subdivided into more states. In response to the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, the branch target table is less critical to the thread and the thread has a lower need for the branch target table.

[0122] For example, the compilation instruction information may be generated in combination with the criticality of the branch target table to each thread. For example, the compilation instruction information may include the criticality of the branch target table to each thread.

[0123] For example, when it is determined that the branch target table has a low criticality for a certain thread, such as being lower than a second threshold or being non-critical, when the optimization compiler is run, the processor can refer to the compilation instruction information to learn that the branch target table has a low criticality for the thread, and the processor can refer to the compilation instruction information to stipulate that the thread can only use part of the capacity in the branch target table, such as only using 20% ​​of the branch target table entries in the branch target table, or it can be stipulated that when the thread applies for a branch target table entry, only one branch target table entry from the branch target table entries previously applied for by the thread can be selected for replacement, or the two methods can be used in combination. This ensures that other threads will not be affected by the thread when using the branch target table.

[0124] In this embodiment, the performance data collected during the program running process is used to guide the compilation optimization through feature analysis, and the allocation of multi-threaded resources is adjusted so that the statically allocated hardware resources can be divided according to the characteristics of different threads. The dynamically allocated and multi-threaded shared hardware resources are controlled according to the usage characteristics of different threads to prevent some threads from occupying too many resources without helping to improve performance. The hardware resource allocation is more reasonable, and the performance of the processor is improved.

[0125] For example, in some embodiments, the occupation of different hardware resources by the processor during the execution of the task may also include the total amount of occupation of each hardware resource by each thread during a preset period of time for executing the task. For example, the preset period of time for executing the task may refer to running a compiler corresponding to the task for a period of time, or a partial period of time within the entire period of time for running the compiler.

[0126] Determining the criticality of each hardware resource to each thread according to the occupation of different hardware resources by the processor during task execution may include: determining the criticality of each hardware resource to each thread according to the total occupation of each hardware resource by multiple threads.

[0127] For example, in some embodiments, determining the criticality of each hardware resource to each thread based on the total amount of hardware resources occupied by multiple threads may include: for a first hardware resource among different hardware resources: for each thread, in response to the total amount of the first hardware resource occupied by the thread being less than B / b, determining the criticality of the first hardware resource to the thread as non-critical, wherein the first hardware resource is a hardware resource exclusively used by multiple threads, B represents the total amount of resources of the first hardware resource, b is the total number of multiple threads, and B and b are integers greater than 1; wherein, in response to the first hardware resource being non-critical to at least one thread among the multiple threads, the compilation instruction information is used to instruct, when running the optimization compiler, to allocate the first hardware resource to each thread among the at least one thread according to the total amount of the first hardware resource occupied by each thread.

[0128] For example, the first hardware resource may be a hardware resource allocated in a static allocation mode. For example, it may be predetermined that each thread equally divides the first hardware resource, and each thread exclusively uses its allocated portion without occupying the first hardware resource of other threads.

[0129] For example, if after a thread has run for a period of time, the total amount b' of the first hardware resource used by it for most of the time (for example, 95% or more of the entire running period) is less than the equally divided first hardware resource (B / b), it means that the first hardware resource is not critical to the thread.

[0130] For example, the compilation instruction information may be generated in combination with the criticality of the first hardware resource to each thread. For example, the compilation instruction information may include the criticality of the first hardware resource to each thread.

[0131] For example, when it is determined that the first hardware resource is less critical to a thread, for example, the criticality is not critical, when running the optimization compiler, the processor can refer to the compilation instruction information to learn that the first hardware resource is less critical to the thread, and the processor can refer to the compilation instruction information to stipulate that only the total amount b' of the first hardware resource used by the thread is allocated to the thread.

[0132] For example, the total amount b' of the first hardware resource used by the thread may also be included in the compilation instruction information, and provided to the processor for allocation reference through the compilation instruction information.

[0133] In this embodiment, the performance data collected during the program running process is used to guide the compilation optimization through feature analysis, and the allocation of multi-threaded resources is adjusted so that the statically allocated hardware resources can be divided according to the characteristics of different threads. The dynamically allocated and multi-threaded shared hardware resources are controlled according to the usage characteristics of different threads to prevent some threads from occupying too many resources without helping to improve performance. The hardware resource allocation is more reasonable, and the performance of the processor is improved.

[0134] For example, in other embodiments, determining the criticality of each hardware resource to each thread based on the total amount of hardware resources occupied by multiple threads may include: for any hardware resource, determining the sum of the total amounts of any hardware resource occupied by multiple threads based on the total amount of hardware resource occupied by each thread; in response to the sum of the total amounts of occupation being greater than the total amount of resources of any hardware resource, determining the total duration of pipeline stagnation for each thread when any hardware resource is missing; determining the criticality of any hardware resource to each thread based on the total duration of pipeline stagnation of each thread, wherein the total duration of pipeline stagnation is positively correlated with the criticality; wherein the compilation instruction information is used to instruct, when running an optimization compilation program, to increase the allocation ratio of threads with higher criticality to any hardware resource and reduce the allocation ratio of threads with lower criticality to any hardware resource.

[0135] For example, for a certain hardware resource A, it is found that the total occupancy of a certain thread (for example, thread 0) during the running period is 90% of the hardware resource A, and the total occupancy of a certain thread (for example, thread 1) during the running period is 20% of the hardware resource A. That is, the sum of the total occupancy of the hardware resource A by the two threads is 110% of the hardware resource A, which is greater than the total resource amount of the hardware resource A. That is, the two threads will experience a pipeline stagnation due to the lack of hardware resource A.

[0136] At this time, the total duration t1 of the pipeline stagnation of thread 0 when lacking hardware resource A and the total duration t2 of the pipeline stagnation of thread 1 when lacking hardware resource A can be determined, and then the criticality of hardware resource A to each thread can be determined based on t1 and t2. For example, the longer the total duration t1 of the pipeline stagnation of thread 0 when lacking hardware resource A, the higher the criticality of hardware resource A to thread 0, and the shorter the total duration t1 of the pipeline stagnation of thread 0 when lacking hardware resource A, the lower the criticality of hardware resource A to thread 0.

[0137] For example, if t2 is greater than t1, it is considered that the criticality of hardware resource A to thread 1 is higher than the criticality of hardware resource A to thread 0.

[0138] For example, the compilation instruction information may be generated in combination with the criticality of the hardware resource A to each thread. For example, the compilation instruction information may include the criticality of the hardware resource A to each thread.

[0139] For example, when running an optimization compiler, the processor can refer to the compilation instruction information to learn the criticality of hardware resource A to two threads. The processor can refer to the compilation instruction information to stipulate that when running the optimization compiler, the allocation ratio of hardware resource A to the thread with a higher criticality (such as thread 1) is increased, and the allocation ratio of hardware resource A to the thread with a lower criticality (such as thread 0) is reduced. For example, 80% of hardware resource A can be allocated to thread 0 and 20% of hardware resource A can be allocated to thread 1. In this way, pipeline stagnation of thread 1 can be avoided and processor performance can be improved.

[0140] For example, the compilation instruction information may also include an allocation ratio of the hardware resource A to the two threads, which is provided to the processor as an allocation reference through the compilation instruction information.

[0141] In this embodiment, the performance data collected during the program running process is used to guide the compilation optimization through feature analysis, and the allocation of multi-threaded resources is adjusted so that the statically allocated hardware resources can be divided according to the characteristics of different threads. The dynamically allocated and multi-threaded shared hardware resources are controlled according to the usage characteristics of different threads to prevent some threads from occupying too many resources without helping to improve performance. The hardware resource allocation is more reasonable, and the performance of the processor is improved.

[0142] For example, in some embodiments, the allocation ratio of a certain hardware resource to threads with a higher criticality to the hardware resource may be increased.

[0143] For any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than a second threshold, that is, the hardware resource is critical to some threads but less critical to other threads, the compilation instruction information is used to instruct, when running the optimization compiler, to increase the allocation ratio of the hardware resource to the M threads that consider the hardware resource to be critical to themselves.

[0144] For example, the criticality of each hardware resource to each thread is determined based on the occupation of different hardware resources by the processor in the process of executing a task, including: determining the total duration of pipeline stagnation of the thread due to the lack of any hardware resource or the proportion of the stagnation time in the total running time based on the duration of pipeline interruption or stagnation of each thread when any hardware resource is missing and the number of times the thread lacks any hardware resource; determining the criticality of the thread to any hardware resource based on the proportion of the total time or the stagnation time in the total running time.

[0145] For example, for hardware resource B, the total duration of pipeline stagnation of each thread or the proportion of stagnation time in the total running time caused by the lack of hardware resource B is determined based on the duration of pipeline interruption or stagnation of each thread when the hardware resource B is lacking and the number of times each thread lacks hardware resource B. If the total stagnation time is long or the proportion of stagnation time in the total running time is large, it is determined that the criticality of the thread to hardware resource B is high; conversely, if the total stagnation time is short or the proportion of stagnation time in the total running time is small, it is determined that the criticality of the thread to hardware resource B is low.

[0146] For example, for thread 0, if the total duration of the stall is greater than a preset threshold or the proportion of the stall time in the total running time is greater than a preset threshold, the criticality of thread 0 to hardware resource B is determined to be critical, otherwise, the criticality of thread 0 to hardware resource B is determined to be non-critical. In this way, the criticality of hardware resource B to each thread can be determined.

[0147] For example, the compilation instruction information may be generated in combination with the criticality of the hardware resource B to each thread. For example, the compilation instruction information may include the criticality of the hardware resource B to each thread.

[0148] For example, the processor can refer to the compilation instruction information to learn that the criticality of hardware resource B to some threads is greater than a first threshold, and the criticality of hardware resource B to some threads is less than a second threshold, that is, hardware resource B is critical to some threads but not to other threads. When running the optimization compiler, the processor can refer to the compilation instruction information to increase the allocation ratio of hardware resource B to M threads whose criticality is greater than the first threshold.

[0149] In this embodiment, the performance data collected during the program running process is used to guide the compilation optimization through feature analysis, and the allocation of multi-threaded resources is adjusted so that the statically allocated hardware resources can be divided according to the characteristics of different threads. The dynamically allocated and multi-threaded shared hardware resources are controlled according to the usage characteristics of different threads to prevent some threads from occupying too many resources without helping to improve performance. The hardware resource allocation is more reasonable, and the performance of the processor is improved.

[0150] For example, in some embodiments, the allocation ratio of a certain hardware resource to N threads can be reduced, which in turn increases the allocation ratio of the hardware resource to other threads. For example, in other embodiments, the allocation ratio of the hardware resource to M threads can be increased, which in turn decreases the allocation ratio of the hardware resource to other threads. For example, in other embodiments, the allocation ratio of the hardware resource to N threads can be reduced, while the allocation ratio of the hardware resource to M threads can be increased, and the remaining hardware resources can be used for threads other than the M+N threads.

[0151] For example, the processor's occupation of the different hardware resources in the process of running the task includes any combination of the following parameters: the number of times each thread occupies each hardware resource, the number of times each thread stalls in the pipeline when each hardware resource is missing, the duration of the pipeline stall when each thread is missing each hardware resource, the total amount of each thread's occupation of each hardware resource, and the branch prediction accuracy of each branch in each thread.

[0152] Those skilled in the art can select parameters in combination with the hardware resources that need to be adjusted. For example, the criticality of each thread to the cache can be determined based on the number of times the thread occupies the cache, and the cache allocation ratio can be adjusted or the scope of use of each thread can be controlled, etc., and the present disclosure does not impose specific restrictions on this. In addition, the occupation of the different hardware resources by the processor during the execution of the task can also include more other parameters without being limited to the above parameters, and those skilled in the art can select and set them according to needs, and the present disclosure does not impose specific restrictions on this.

[0153] For example, when determining the criticality of each hardware resource to each thread based on the occupation of different hardware resources by the processor in the process of executing a task, for any hardware resource, one or more parameters can be used to judge the criticality. For example, the collected performance data for the hardware resource can be compared with a preset threshold, or the criticality of the hardware resource to each thread can be obtained by combining multiple parameters. The present disclosure does not impose specific restrictions on this.

[0154] As mentioned above, the allocation adjustment of the hardware resources of the processor can also control the timing of each thread occupying the hardware resources.

[0155] For example, performance data includes the time distribution of multiple threads occupying various hardware resources when the processor executes a task.

[0156] For example, step S20 may include: generating compilation instruction information in combination with the time distribution of multiple threads occupying each hardware resource when the processor executes a task, wherein the compilation instruction information is used to control the occupancy timing of each hardware resource by each thread according to the time distribution of multiple threads occupying each hardware resource when running the optimization compiler.

[0157] For example, the compilation instruction information may include the timings of multiple threads occupying various hardware resources, such as the time point at which a certain thread occupies a certain hardware resource and needs to control the occupancy timing. For example, when running an optimization compiler, the processor may refer to the compilation instruction information to obtain the timing of a thread occupying a certain hardware resource, and reserve the target hardware resource for the thread when the thread is close to using the target hardware resource.

[0158] For example, the compilation instruction information may include the time distribution of multiple threads occupying various hardware resources. For example, when running an optimization compiler, the processor may refer to the time distribution of threads occupying a certain hardware resource obtained from the compilation instruction information, analyze the timing of the thread occupying the hardware resource, and reserve the target hardware resource for the thread when the thread is close to using the target hardware resource.

[0159] For example, taking thread 0 as an example, performance data is collected to obtain the time distribution of hardware resource C occupied by thread 0. For example, the time distribution of hardware resource C occupied by thread 0 may include that thread 0 does not need hardware resource C from 0 to 100 seconds, but needs hardware C from 100 to 200 seconds. Then, the processor may reserve hardware resource C for thread 0 in advance at approximately 100 seconds, for example, starting from the 90th second. For example, the released hardware resource C is no longer allocated to other threads, but is reserved for thread 0. In this way, thread 0 can directly obtain the required hardware resource C when it needs to use the hardware resource C, and the pipeline of thread 0 will not be stalled due to the lack of hardware resource C, thereby improving the performance of the processor.

[0160] For example, in some embodiments, the performance data includes dependencies between hardware resources used by each thread of the processor in the process of executing a task.

[0161] For example, the dependency between the hardware resources used by each thread is obtained by the occupation of multiple hardware resources when the pipeline of each thread is stalled. For example, the multiple hardware resources include other hardware resources except the hardware resources that directly cause the pipeline stall of the thread.

[0162] For example, step S20 may include: generating compilation instruction information in combination with the dependency relationship between the hardware resources used by each thread, wherein the compilation instruction information is used to control the occupation timing or resource occupation priority of the hardware resources used by the thread according to the dependency relationship between the hardware resources used by each thread when running the optimization compiler.

[0163] For example, in response to a dependency relationship between P hardware resources used by the thread to perform the first operation, the P hardware resources include the target hardware resource, and P is a positive integer greater than 1. At this time, when running the optimization compiler, combined with the compilation instruction information generated according to the dependency relationship between the P hardware resources used by the thread, the processor can allocate the occupancy right of the target hardware resource to the thread, or increase the thread's occupancy priority for the target hardware resource, after the remaining P-1 hardware resources other than the target hardware resource return the usage data required to perform the first operation.

[0164] For example, the target hardware resource can only be used after waiting for the other P-1 hardware resources to return the usage data required to perform the first operation. In other words, the use of the target hardware resource requires the usage data returned by the other P-1 hardware resources.

[0165] For example, the compilation instruction information may include the dependency relationship between the hardware resources used by each thread, such as the dependency relationship between the hardware resources used by a certain thread that needs to control the occupancy timing. For example, when running an optimization compiler, the processor may refer to the dependency relationship between the P hardware resources used by the thread obtained from the compilation instruction information to analyze the timing of the thread occupying the hardware resource. After obtaining the usage data returned by the remaining P-1 hardware resources other than the target hardware resource, the processor may allocate the occupancy right of the target hardware resource to the thread, or increase the thread's occupancy priority for the target hardware resource.

[0166] For example, the compilation instruction information may include the timing of the thread occupying the target hardware resource, for example, the compilation instruction information includes suggestion information, which describes that the target hardware resource can be occupied when the remaining P-1 hardware resources other than the target hardware resource return usage data. For example, when running an optimization compiler, the processor can refer to the above-mentioned suggestion information of the thread occupying a certain hardware resource obtained from the compilation instruction information, and after obtaining the usage data returned by the remaining P-1 hardware resources other than the target hardware resource, the processor can allocate the occupation right of the target hardware resource to the thread, or increase the thread's occupation priority for the target hardware resource.

[0167] For example, taking thread 0 as an example, when running the compiler, the pipeline of thread 0 is stalled or interrupted due to the lack of hardware resource D. When thread 0 is stalled, the occupation of other hardware resources by thread 0 except hardware resource D is collected to determine that the lack of hardware resource D causes the pipeline to be unable to execute other hardware resources previously occupied by thread 0. For example, it is determined that after obtaining hardware resource D, thread 0 will also be unable to execute the pipeline due to the lack of hardware resource E. Therefore, for thread 0, it can be determined that there is a dependency relationship between the two hardware resources (i.e., hardware resource D and hardware resource E) used by it to execute the first operation. The compilation instruction information can be generated in combination with the dependency relationship, so that when running the optimized compiler, the processor can consider not occupying hardware resource E at the beginning, and wait until hardware resource D returns the usage data for executing the first operation before occupying hardware resource E. Specifically, the occupation right of hardware resource E can be allocated to thread 0 at this time, or the occupation priority of thread 0 for hardware resource E can be increased.

[0168] For example, in a specific example, even if thread 0 competes for the dynamically shared address calculation unit queue, it still needs to wait for the value returned from the memory before it can be executed. Before the memory returns the value, thread 0 occupies a large number of address calculation unit queues, which may cause another thread to pause due to the lack of address calculation unit queues, and there is no improvement in the performance of the processor. At this time, thread 0 can be allowed not to occupy the address calculation unit queue first, and wait for the memory to return the value before allocating the address calculation unit queue to thread 0, or the priority of thread 0 to occupy the address calculation unit can be increased, for example, thread 0 can use the address calculation unit queue first.

[0169] In this embodiment, the timing of each thread occupying hardware resources can be controlled, and the allocation of hardware resources can be reasonably adjusted to avoid some threads occupying too many hardware resources without helping to improve performance, but instead causing the pipeline of other threads to stagnate, thereby improving the performance of the processor.

[0170] In practice, performance data can be set as needed to adjust the resource allocation ratio between threads, or to control the occupation timing of each thread occupying hardware resources, or to adjust and control both the hardware allocation ratio and the occupation timing of hardware resources, and the present disclosure does not make specific restrictions on this. The specific method of adjusting the allocation ratio and controlling the occupation timing can refer to the description of the above embodiment.

[0171] In at least one embodiment of the present disclosure, performance data obtained by running a compiler of a task for a period of time can be collected. The compiler is a program compiled based on general rules. Based on the occupation of the different hardware resources by the processor in the process of running the task in the performance data, the criticality of each hardware to the thread can be determined. Compilation instruction information can be generated based on the criticality, and the compilation instruction information can be used to provide a reference when running the optimization compiler. For example, the processor can divide hardware resources based on the criticality, for example, more hardware resources can be allocated to threads with higher criticality, and fewer hardware resources can be allocated to threads with lower criticality, or the scope of use of hardware resources by threads with lower criticality can be limited, etc., so as to reasonably allocate hardware resources, and allocate hardware resources in a targeted manner according to the characteristics of the program to maximize the performance of the processor.

[0172] Furthermore, in at least one embodiment of the present disclosure, based on the distribution of the time when multiple threads occupy various hardware resources in the process of executing tasks or the dependency relationship between the hardware resources used by each thread in the performance data, compilation instruction information is generated, and the compilation instruction information can be used to provide a reference when running the optimization compiler. For example, the processor can control the occupation time of hardware resources according to the compilation instruction information, for example, the hardware resources can be reserved in advance when the thread needs the hardware resources, or for multiple hardware resources with dependencies, the hardware resources can be occupied after the usage data required for the execution operation is prepared, so that the dynamically allocated shared resources can be controlled according to the usage characteristics of different threads at the same time, preventing some threads from occupying too many resources but not helping to improve performance, reasonably allocating hardware resources, and making targeted hardware resource allocation according to program characteristics to maximize the performance of the processor.

[0173] At least one embodiment of the present disclosure provides a resource allocation method. Figure 3 A schematic flowchart of a resource allocation method provided in at least one embodiment of the present disclosure.

[0174] For example, Figure 3 As shown, the data processing method provided by the embodiment of the present disclosure includes at least step S40.

[0175] For example, the resource allocation method is applied to a processor, such as a processor using SMT technology. For example, the processor includes at least one processing core, which is a physical core, and a plurality of threads are used in parallel in one processing core to execute tasks, and the plurality of threads can be understood as a plurality of virtual logical cores in one physical core.

[0176] For example, the processor can be implemented as a GPU (graphics processing unit), a CPU (central processing unit), an NPU (neural network processor), a DSP (digital signal processor), etc. according to actual needs, and the present disclosure does not limit this.

[0177] In step S40, hardware resources of the processor used when the processor executes the task are allocated according to the compilation instruction information.

[0178] The compilation instruction information is generated based on the performance data generated by the processor during the execution of the compilation program corresponding to the task. The processor uses multiple threads to execute tasks simultaneously. The performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads.

[0179] For the process of collecting performance data and generating compilation instruction information based on the performance data, reference may be made to the relevant description in the above information processing method, and the repeated parts will not be repeated here.

[0180] For example, in some embodiments, step S40 may include: determining the criticality of each hardware resource to each thread based on the compilation instruction information; and adjusting the occupancy ratio and / or dynamic usage range of each thread for each hardware resource based on the criticality of each hardware resource to each thread.

[0181] For example, the compilation instructions can directly include the criticality of each hardware resource for each thread.

[0182] For example, the compilation instruction information may include performance data, and the criticality of each hardware resource to each thread is determined by analyzing the performance data. The criticality of each hardware resource to each thread can be obtained by analyzing the performance data. The relevant content in the above information processing method can be referred to, and the repeated parts will not be repeated.

[0183] For example, adjusting the occupancy ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread may include: for any hardware resource, in response to the criticality of any hardware resource to M threads among multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among multiple threads being less than or equal to a second threshold, reducing the allocation ratio of any hardware resource to N threads, or limiting the dynamic usage range of any hardware resource by N threads, where M and N are positive integers.

[0184] For example, for a certain hardware resource, if the criticality of the hardware resource to M threads is greater than or equal to the first threshold, it means that M threads believe that the hardware resource is highly critical to themselves, and if the criticality of the hardware resource to N threads is less than or equal to the second threshold, it means that N threads believe that the hardware resource is less critical. At this time, when running the optimization compiler, the processor can refer to the criticality of each hardware resource to each thread, reduce the allocation ratio of the hardware resource to the N threads that believe that the hardware resource is not very important to themselves, or limit the dynamic use range of the hardware resource by the N threads. In this way, the waste of hardware resources can be reduced, and this also indirectly increases the allocation ratio of the hardware resource allocated to other threads, for example, increasing the allocation ratio of the resource to M threads, thereby improving the performance of the processor and reducing the number and duration of stagnation or interruption of the thread pipeline caused by the lack of the hardware resource.

[0185] For example, in one example, the hardware resource is a cache. In this embodiment, adjusting the occupation ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread may include: reducing the allocation ratio of the cache to the N threads, or limiting the N threads to select a cache line from the cache lines occupied by the N threads for cache replacement when cache replacement occurs.

[0186] For example, the task executed by a thread may be a streaming media application, in which a large amount of streaming media data is often used only once and will not be used again in the future. For example, when running an optimized compiler, the processor can refer to the compilation instruction information to know that the cache is less critical to the thread. The processor can stipulate that the thread can only use part of the capacity in the cache, such as only 20% of the cache. Or, it can be stipulated that when the cache is replaced by the thread, only one of the cache lines previously applied by the thread can be replaced with a new cache line, or a combination of the two methods can be used. This ensures that other threads will not be affected by the thread when using the cache.

[0187] For example, in one example, the hardware resource is a branch target table. Each branch target table entry in the branch target table is used to store branch jump related information.

[0188] Adjusting the proportion of each hardware resource occupied and / or the dynamic usage range of each thread based on the criticality of each hardware resource to each thread may include: reducing the allocation ratio of the branch target table allocated to the N threads, or restricting the N threads to select a branch target table entry from the branch target table entries already occupied by the N threads for replacement when applying for a branch target table entry.

[0189] For example, there are many branches in a thread that are difficult to predict accurately. For example, when running an optimized compiler, the processor can refer to the compilation instruction information to learn that the branch target table is less critical to the thread. The processor can refer to the compilation instruction information to stipulate that the thread can only use part of the capacity in the branch target table, for example, only 20% of the branch target table entries in the branch target table can be used, or it can be stipulated that when the thread applies for a branch target table entry, only one branch target table entry from the branch target table entries previously applied by the thread can be selected for replacement, or a combination of the two methods can be used. This ensures that other threads will not be affected by the thread when using the branch target table.

[0190] For example, in one example, the hardware resource is a first hardware resource, which may be a hardware resource allocated in a static allocation mode among hardware resources, and the first hardware resource is a hardware resource exclusively used by multiple threads.

[0191] Adjusting the occupancy ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread may include: in response to the criticality of the first hardware resource to at least one thread among multiple threads being non-critical, allocating the first hardware resource to each thread among the at least one thread according to the total amount of occupancy of the first hardware resource by each thread, wherein the total amount of occupancy of the first hardware resource by each thread is determined during the process of collecting performance data.

[0192] For example, if after a thread has run for a period of time, the total amount b' of the first hardware resource used by it for most of the time (for example, 95% or more of the entire running period) is less than the equally divided first hardware resource (B / b), it means that the first hardware resource is not critical to the thread.

[0193] For the thread, the processor may only allocate the total amount b' of the first hardware resource used by the thread to the thread.

[0194] For example, in some embodiments, for any hardware resource, the total amount of occupancy of multiple threads using the hardware resource is greater than the total amount of resources of the hardware resource, that is, when these threads use the hardware resource, there will always be a thread that has a pipeline pause due to the lack of the hardware resource. At this time, according to the criticality of each hardware resource to each thread, the occupancy ratio and / or dynamic usage range of each thread to each hardware resource is adjusted, including: increasing the allocation ratio of threads with higher criticality to any hardware resource, and reducing the allocation ratio of threads with lower criticality to any hardware resource.

[0195] For example, the criticality can be determined based on the total duration of pipeline stagnation for each thread when the hardware resource is missing, or the criticality can be determined based on the proportion of the total duration of pipeline stagnation for each thread when the hardware resource is missing in the entire running time. For example, the longer the total duration of stagnation or the higher the proportion of the total duration of stagnation, the greater the impact of the pipeline stagnation of this thread on the performance, and the allocation ratio of hardware resources to this thread can be increased, while the allocation ratio of other threads to this hardware resource can be reduced. For example, if there are multiple threads occupying the hardware resource, they can be sorted from high to low based on the criticality, with threads with higher criticality being allocated a larger share of hardware resources, and threads with the lowest criticality being allocated a smallest share of hardware resources.

[0196] For example, in some embodiments, adjusting the occupancy ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread may include: for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, increasing the allocation ratio of any hardware resource to M threads.

[0197] For example, the criticality can be determined based on the total pipeline stagnation time of each thread when the hardware resource is missing, or the criticality can be determined based on the proportion of the total pipeline stagnation time of each thread when the hardware resource is missing in the entire running time. For example, at this time, the allocation ratio of hardware resources to the M threads that think the hardware resources are more critical to themselves can be increased.

[0198] For example, in some embodiments, allocating hardware resources of the processor used when the processor executes a task according to the compilation instruction information may include: controlling the occupation timing or resource occupation priority of each thread occupying each hardware resource according to the compilation instruction information.

[0199] For example, the compilation instruction information may include the timings of multiple threads occupying various hardware resources, such as the timing of a certain thread occupying a certain hardware resource that needs to be controlled. For example, when running an optimization compiler, the processor may refer to the compilation instruction information to obtain the timing of a thread occupying a certain hardware resource, reserve the target hardware resource for the thread when it is close to the thread's use of the target hardware resource, or occupy the hardware resource (such as computing resource) when all the data required for the thread to perform the operation is in place.

[0200] For example, the compilation instruction information may include the time distribution of multiple threads occupying various hardware resources. For example, when running an optimization compiler, the processor may refer to the time distribution of threads occupying a certain hardware resource obtained from the compilation instruction information, analyze the timing of the thread occupying the hardware resource, and reserve the target hardware resource for the thread when the thread is close to using the target hardware resource.

[0201] For example, the compilation instruction information may include the dependency relationship between multiple hardware resources used by the thread. For example, when running an optimization compiler, the processor may refer to the compilation instruction information to learn the dependency relationship between multiple hardware resources used by the thread, analyze the dependency relationship, and may stipulate that the hardware resources (such as computing resources) are occupied only when all data required for the thread to perform the operation are in place.

[0202] For example, in response to a dependency relationship between P hardware resources used by a thread to perform a first operation, the P hardware resources include a target hardware resource, and P is a positive integer greater than 1. For example, according to the compilation instruction information, controlling the occupation timing or resource occupation priority of each thread occupying each hardware resource may include: according to the compilation instruction information, when obtaining the usage data of the first operation returned by the remaining P-1 hardware resources except the target hardware resource, allocating the occupation right of the target hardware resource to the thread, or increasing the occupation priority of the thread for the target hardware resource.

[0203] For example, in other embodiments, there may be other resource allocation strategies for resource partitioning and occupancy timing control. The present disclosure includes but is not limited to the above resource allocation strategies, and the compilation instruction information can be used to provide references for a variety of different hardware resource allocation strategies.

[0204] In at least one embodiment of the present disclosure, the resource allocation method can provide a reference for resource allocation of a processor running an optimization compiler according to compilation instruction information. For example, the compilation instruction information can be generated by collecting performance data obtained by running the compiler of the task for a period of time.

[0205] For example, the processor can divide the hardware resources according to the compilation instruction information, allocate more hardware resources to threads with higher criticality and fewer hardware resources to threads with lower criticality, or limit the scope of use of hardware resources by threads with lower criticality, etc., so as to reasonably allocate hardware resources, allocate hardware resources in a targeted manner according to the characteristics of the program, and maximize the performance of the processor.

[0206] For example, the processor can control the timing of occupying hardware resources based on the compilation instruction information. For example, it can reserve hardware resources in advance when the thread needs the hardware resources, or for multiple hardware resources with dependencies, it can wait until the usage data required to execute the operation is prepared before occupying the hardware resources. In this way, the dynamically allocated shared resources can be controlled according to the usage characteristics of different threads at the same time, preventing some threads from occupying too many resources without helping to improve performance. Hardware resources can be allocated reasonably, and hardware resources can be allocated in a targeted manner according to the characteristics of the program to maximize the performance of the processor.

[0207] Corresponding to the above-mentioned information processing method, at least one embodiment of the present disclosure further provides an information processing device, Figure 4 A schematic block diagram of an information processing device provided for at least one embodiment of the present disclosure.

[0208] For example, Figure 4 As shown, the information processing device 100 at least includes: a collection module 101 , a generation module 102 and an insertion module 103 .

[0209] The collection module 101 is configured to collect performance data generated by the processor during the execution of a task.

[0210] For example, a processor runs multiple threads to perform tasks simultaneously, and the performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads.

[0211] The generating module 102 is configured to generate compilation instruction information corresponding to the task according to the performance data.

[0212] The inserting module 103 is configured to insert compilation instruction information into the compiler of the task to obtain the optimized compiler corresponding to the task, wherein the compilation instruction information is used to allocate hardware resources of the processor when the processor runs the optimized compiler.

[0213] For example, performance data includes how the processor uses different hardware resources while executing a task.

[0214] For example, Figure 4 As shown, the generating module 102 includes a first determining unit 1021 and a first generating unit 1022 .

[0215] The first determining unit 1021 is configured to determine the criticality of each hardware resource to each thread according to the occupation of different hardware resources by the processor in the process of executing the task.

[0216] The first generation unit 1022 is configured to generate compilation instruction information in combination with the criticality of each hardware resource to each thread, wherein the compilation instruction information is used to adjust the occupancy ratio and / or dynamic usage range of each thread for each hardware resource according to the criticality of each hardware resource to each thread when running the optimization compiler.

[0217] For example, for any hardware resource, in response to the criticality of any hardware resource to M threads among multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to reduce the allocation ratio of any hardware resource allocated to N threads, or to limit the dynamic usage range of any hardware resource by N threads, where M and N are positive integers.

[0218] For example, any hardware resource includes a cache, and the processor's occupation of different hardware resources during the execution of a task includes the number of times each thread occupies the cache. For example, the first determination unit 1021 determines the criticality of each hardware resource to each thread based on the processor's occupation of different hardware resources during the execution of a task, including performing the following operations: for each thread: determining the criticality of the cache to the thread based on the number of times the thread occupies the cache, wherein the less the number of times the thread occupies the cache, the lower the criticality of the cache to the thread; wherein the compilation instruction information is used to indicate a reduction in the allocation ratio of the cache to N threads when running an optimization compiler, or to restrict N threads from selecting a cache line from the cache lines occupied by N threads for cache replacement when a cache replacement occurs.

[0219] For example, any hardware resource includes a branch target table, each branch target table entry in the branch target table is used to store branch jump related information, and the occupation of different hardware resources by the processor in the process of executing the task includes the branch prediction accuracy of each branch in each thread. For example, the first determination unit 1021 determines the criticality of each hardware resource to each thread according to the occupation of different hardware resources by the processor in the process of executing the task, including the following operations: for each thread: according to the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, determine the criticality of the branch target table to the thread, wherein the more the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, the lower the criticality of the branch target table to the thread; wherein the compilation instruction information is used to indicate to reduce the allocation ratio of the branch target table to N threads when running the optimization compiler, or to restrict the N threads to select a branch target table entry from the branch target table entries occupied by the N threads for replacement when applying for the branch target table entry.

[0220] For example, the occupation of different hardware resources by the processor in the process of executing the task includes the total occupation of each hardware resource by each thread in the preset time period of executing the task. For example, the first determination unit 1021 determines the criticality of each hardware resource to each thread according to the occupation of different hardware resources by the processor in the process of executing the task, including performing the following operations: determining the criticality of each hardware resource to each thread according to the total occupation of each hardware resource by multiple threads.

[0221] For example, the first determination unit 1021 determines the criticality of each hardware resource to each thread based on the total amount of hardware resources occupied by multiple threads, including performing the following operations: for the first hardware resource among different hardware resources: for each thread, in response to the total amount of the first hardware resource occupied by the thread being less than B / b, determining that the criticality of the first hardware resource to the thread is not critical, wherein the first hardware resource is a hardware resource exclusively used by multiple threads, B represents the total amount of resources of the first hardware resource, b is the total number of multiple threads, and B and b are integers greater than 1; wherein, in response to the first hardware resource being not critical to at least one thread among the multiple threads, the compilation instruction information is used to instruct, when running the optimization compilation program, to allocate the first hardware resource to each thread among at least one thread according to the total amount of the first hardware resource occupied by each thread.

[0222] For example, the first determination unit 1021 determines the criticality of each hardware resource to each thread based on the total amount of hardware resources occupied by multiple threads, including the following operations: for any hardware resource, determine the sum of the total amount of occupation of any hardware resource by multiple threads based on the total amount of occupation of any hardware resource by each thread; in response to the sum of the total occupation being greater than the total amount of resources of any hardware resource, determine the total duration of pipeline stagnation for each thread when any hardware resource is missing; determine the criticality of any hardware resource to each thread based on the total duration of pipeline stagnation of each thread, wherein the total duration of pipeline stagnation is positively correlated with the criticality; wherein the compilation instruction information is used to instruct, when running an optimization compilation program, to increase the allocation ratio of threads with higher criticality to any hardware resource and reduce the allocation ratio of threads with lower criticality to any hardware resource.

[0223] For example, for any hardware resource, in response to the criticality of any hardware resource to M threads among multiple threads being greater than a first threshold, and the criticality of any hardware resource to N threads among multiple threads being less than a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to increase the allocation ratio of any hardware resource to M threads.

[0224] For example, the first determination unit 1021 determines the criticality of each hardware resource to each thread based on the occupancy of different hardware resources by the processor in the process of executing a task, including the following operations: determining the total duration of pipeline stagnation of the thread due to the lack of any hardware resource or the proportion of the stagnation time in the total running time based on the duration of pipeline interruption or stagnation of the thread when each thread lacks any hardware resource and the number of times the thread lacks any hardware resource; determining the criticality of the thread to any hardware resource based on the proportion of the total time or the stagnation time in the total running time.

[0225] For example, the processor's occupation of different hardware resources in the process of executing a task includes any combination of the following parameters: the number of times each thread occupies each hardware resource, the number of times each thread stalls in the pipeline when each hardware resource is missing, the duration of the pipeline stall when each thread is missing each hardware resource, the total amount of each hardware resource occupied by each thread, and the branch prediction accuracy of each branch in each thread.

[0226] For example, performance data includes the time distribution of multiple threads occupying various hardware resources when the processor executes a task.

[0227] For example, Figure 4 As shown, the generating module 102 may further include a second generating unit 1023 .

[0228] The second generation unit 1023 is configured to generate compilation instruction information in combination with the time distribution of multiple threads occupying each hardware resource when the processor executes a task, wherein the compilation instruction information is used to control the timing of each thread occupying each hardware resource according to the time distribution of multiple threads occupying each hardware resource when running the optimization compiler.

[0229] For example, the compilation instruction information is used to reserve target hardware resources for threads when the threads are close to using the target hardware resources according to the time distribution of the multiple threads occupying the various hardware resources when running the optimization compiler.

[0230] For example, performance data includes dependencies between hardware resources used by each thread in the process of executing tasks on the processor.

[0231] For example, Figure 4 As shown, the generating module 102 may further include a third generating unit 1024 .

[0232] For example, the third generation unit 1024 is configured to generate compilation instruction information in combination with the dependency relationship between the hardware resources used by each thread, wherein the compilation instruction information is used to control the occupation timing or resource occupation priority of the hardware resources used by the thread according to the dependency relationship between the hardware resources used by each thread when running the optimization compiler.

[0233] For example, in response to a dependency relationship between P hardware resources used by the thread to execute the first operation, the P hardware resources include the target hardware resource, and P is a positive integer greater than 1. The compilation instruction information is used to indicate, when running the optimization compiler, that after obtaining the usage data returned by the remaining P-1 hardware resources except the target hardware resource, the occupancy right of the target hardware resource is allocated to the thread, or the occupancy priority of the thread for the target hardware resource is increased.

[0234] For example, the dependency between the hardware resources used by each thread is obtained through the occupancy of multiple hardware resources when the pipeline of each thread is stalled, wherein the multiple hardware resources include other hardware resources among different hardware resources except the hardware resources that directly cause the pipeline stall of the thread.

[0235] For example, the hardware resources in the processor include computing resources and storage resources. The computing resources include computing logic units and address calculation units, and the storage resources include cache, memory, queues, and registers.

[0236] For example, a processor includes at least one physical core, and multiple threads run in the same physical core.

[0237] It should be noted that the collection module 101 is used to implement Figure 2 In step S10 shown in FIG. 1 , the generating module 102 is used to implement Figure 2 Step S20 shown, inserting a module to implement Figure 2 The step S30 shown. Therefore, the specific description of the collection module 101 can refer to the embodiment of the above information processing method. Figure 2 For the description of step S10 shown in FIG. 1 , the specific description of the generation module 102 can be referred to in the embodiment of the above information processing method. Figure 2 For the description of step S20 shown in FIG. 1 , the specific description of the insertion module 103 can be referred to in the embodiment of the above information processing method. Figure 2 In addition, the information processing device can achieve the technical effects similar to those of the aforementioned information processing method, which will not be described in detail here.

[0238] At least one embodiment of the present disclosure further provides a resource allocation device. Figure 5 A schematic block diagram of another resource allocation device provided by at least one embodiment of the present disclosure.

[0239] For example, Figure 5 As shown, the resource allocation device 200 at least includes: an allocation module 201.

[0240] For example, the allocation module 201 is configured to allocate the hardware resources of the processor used when the processor executes a task based on the compilation instruction information, wherein the compilation instruction information is generated based on the performance data generated by the processor in the process of executing the compilation program corresponding to the task, and the processor uses multiple threads to execute the task simultaneously, and the performance data indicates the degree and / or timing of the demand of different hardware resources in the processor by each of the multiple threads.

[0241] For example, the allocation module 201 includes a second determining unit 2011 and a resource adjusting unit 2012 .

[0242] The second determining unit 2011 is configured to determine the criticality of each hardware resource to each thread according to the compilation instruction information.

[0243] The resource adjustment unit 2012 is configured to adjust the occupation ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread.

[0244] For example, the resource adjustment unit 2012 adjusts the occupancy ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread, including performing the following operations: for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, reducing the allocation ratio of any hardware resource to N threads, or limiting the dynamic usage range of any hardware resource by N threads, where M and N are positive integers.

[0245] For example, if any hardware resource includes a cache, the resource adjustment unit 2012 adjusts the occupancy ratio and / or dynamic usage range of each hardware resource for each thread according to the criticality of each hardware resource to each thread, including performing the following operations: reducing the allocation ratio of the cache to N threads, or restricting the N threads to select a cache line from the cache lines occupied by the N threads for cache replacement when a cache replacement occurs.

[0246] For example, any hardware resource includes a branch target table, and each branch target table entry in the branch target table is used to store relevant information of branch jumps. The resource adjustment unit 2012 adjusts the occupancy ratio and / or dynamic usage range of each hardware resource for each thread according to the criticality of each hardware resource to each thread, including performing the following operations: reducing the allocation ratio of the branch target table allocated to N threads, or restricting N threads to select a branch target table entry from the branch target table entries already occupied by N threads for replacement when applying for a branch target table entry.

[0247] For example, any hardware resource includes a first hardware resource, which is a hardware resource exclusively used by multiple threads. The resource adjustment unit 2012 adjusts the occupancy ratio and / or dynamic usage range of each hardware resource by each thread according to the criticality of each hardware resource to each thread, including performing the following operations: in response to the criticality of the first hardware resource to at least one thread among the multiple threads being non-critical, allocating the first hardware resource to each thread among the at least one thread according to the total amount of occupancy of the first hardware resource by each thread, wherein the total amount of occupancy of the first hardware resource by each thread is determined during the process of collecting performance data.

[0248] For example, the resource adjustment unit 2012 adjusts the occupancy ratio and / or dynamic usage range of each hardware resource for each thread according to the criticality of each hardware resource to each thread, including performing the following operations: for any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, increasing the allocation ratio of any hardware resource to M threads.

[0249] For example, the resource adjustment unit 2012 allocates the hardware resources of the processor used when the processor executes the task according to the compilation instruction information, including the following operations: according to the compilation instruction information, controlling the occupation timing or resource occupation priority of each thread to occupy each hardware resource.

[0250] For example, in response to the existence of a dependency relationship between P hardware resources used by the thread to execute the first operation, the P hardware resources include a target hardware resource, and P is a positive integer greater than 1, the resource adjustment unit 2012 executes according to the compilation instruction information to control the occupancy timing or resource occupancy priority of each hardware resource by each thread, including the following operations: according to the compilation instruction information, after obtaining the usage data returned by the remaining P-1 hardware resources except the target hardware resource, the occupancy right of the target hardware resource is allocated to the thread, or the thread's occupancy priority of the target hardware resource is increased.

[0251] It should be noted that the allocation module 201 is used to implement Figure 3 Therefore, the detailed description of the allocation module 201 can refer to the embodiment of the above data communication method. Figure 3 In addition, the resource allocation device can achieve the technical effect similar to the above-mentioned resource allocation method, which will not be described in detail here.

[0252] Figure 6 A schematic diagram of the structure of an electronic device provided for at least one embodiment of the present disclosure. The terminal device in the embodiment of the present disclosure may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 6 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0253] For example, Figure 6As shown, in some examples, the electronic device 300 includes a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 301, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 302 or a program loaded from a storage device 308 into a random access memory (RAM) 303, such as executing an information processing method or a resource allocation method provided by at least one embodiment of the present disclosure. In RAM 303, various programs and data required for the operation of the computer system are also stored. The processing device 301, ROM 302, and RAM 303 are connected to each other via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0254] For example, the following components may be connected to the I / O interface 305: an input device 306 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 307 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 308 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 309 including a network interface card such as a LAN card, a modem, etc. The communication device 309 may allow the electronic device 300 to communicate with other devices wirelessly or by wire to exchange data, performing communication processing via a network such as the Internet. A drive 310 is also connected to the I / O interface 305 as needed. Removable media 311, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., are installed on the drive 310 as needed, so that a computer program read therefrom is installed into the storage device 309 as needed. Although Figure 6 The electronic device 300 including various devices is shown, but it should be understood that it is not required to implement or include all the devices shown. More or fewer devices may be implemented or included instead.

[0255] For example, the electronic device 300 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 309 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging and / or Short Message Service (SMS), or any other suitable communication protocol.

[0256] For example, the electronic device may be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, etc., or may be any combination of electronic devices and hardware, which is not limited in the embodiments of the present disclosure.

[0257] For example, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 309, or installed from the storage device 308, or installed from the ROM 302. When the computer program is executed by the processing device 301, the above-mentioned information processing method or resource allocation method defined in the method of the embodiment of the present disclosure is executed.

[0258] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In an embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0259] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0260] The computer-readable medium may be included in the electronic device, or may exist independently without being installed in the electronic device.

[0261] Figure 7 A schematic diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Figure 7As shown, one or more computer executable instructions 401 may be non-temporarily stored on the storage medium 400. For example, when the computer executable instructions 401 are executed by a processor, one or more steps in the information processing method described above may be executed, or one or more steps in the resource allocation method described above may be executed.

[0262] For example, the storage medium 400 may be applied to the above electronic device. For example, the storage medium 400 may include the memory 1003 in the electronic device.

[0263] For example, the description of the storage medium 400 may refer to the description of the memory in the embodiment of the electronic device, and the repeated parts will not be repeated.

[0264] Those skilled in the art will appreciate that the contents disclosed in this disclosure may be subject to various modifications and improvements. For example, the various devices or components described above may be implemented by hardware, or by software, firmware, or a combination of some or all of the three.

[0265] In addition, although the present disclosure makes various references to certain units in the system according to embodiments of the present disclosure, any number of different units can be used and run on the client and / or server. The units are only illustrative, and different aspects of the system and method can use different units.

[0266] Flowcharts are used in this disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the preceding or following steps are not necessarily performed precisely in order. On the contrary, various steps may be processed in reverse order or simultaneously. At the same time, other operations may also be added to these processes.

[0267] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present disclosure is not limited to any particular form of combination of hardware and software.

[0268] Unless otherwise defined, all terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or highly formal sense, unless explicitly defined as such herein.

Claims

1. An information processing method, comprising: collecting performance data generated by the processor in the process of executing a task, wherein the performance data is collected by pre-running a compiled program of the task for a preset time, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads; Generate compilation instruction information corresponding to the task according to the performance data, wherein the compilation instruction information provides at least one of the following information: the criticality of different hardware resources to each thread, the time distribution of each hardware resource occupied by the multiple threads, and the dependency relationship between the hardware resources used by each thread; The compilation instruction information is inserted into the compiler to obtain an optimized compiler corresponding to the task, wherein the compilation instruction information is used for allocating hardware resources of the processor when the processor runs the optimized compiler.

2. The information processing method according to claim 1, wherein: The performance data includes the occupation of the different hardware resources by the processor in the process of running the task, Generating compilation instruction information corresponding to the task according to the performance data includes: Determining the criticality of each hardware resource to each thread according to the occupation of the different hardware resources by the processor in the process of executing the task; The compilation instruction information is generated in combination with the criticality of each hardware resource to each thread, wherein the compilation instruction information is used to adjust the occupancy ratio and / or dynamic usage range of each thread to each hardware resource according to the criticality of each hardware resource to each thread when running the optimization compiler.

3. The information processing method according to claim 2, wherein: For any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to reduce the allocation ratio of any hardware resource allocated to the N threads, or to limit the dynamic usage range of any hardware resource by the N threads, Wherein, M and N are positive integers.

4. The information processing method according to claim 3, wherein: Any of the hardware resources includes a cache, The occupation of the different hardware resources by the processor in the process of executing the task includes the number of times each thread occupies the cache. Determining the criticality of each hardware resource to each thread according to the occupation of the different hardware resources by the processor in the process of running the task, including: For each thread: Determining the criticality of the cache to the thread according to the number of times the cache is occupied by the thread, wherein the less the number of times the cache is occupied by the thread, the lower the criticality of the cache to the thread; The compilation instruction information is used to instruct to reduce the allocation ratio of the cache allocated to the N threads when running the optimization compiler, or to restrict the N threads to select a cache line from the cache lines occupied by the N threads for cache replacement when cache replacement occurs.

5. The information processing method according to claim 3, wherein: Any of the hardware resources includes a branch target table, each branch target table entry in the branch target table is used to store relevant information of branch jumps, The occupation of the different hardware resources by the processor in the process of executing the task includes the branch prediction accuracy of each branch in each thread, Determining the criticality of each hardware resource to each thread according to the occupation of the different hardware resources by the processor in the process of running the task, including: For each thread: Determining the criticality of the branch target table to the thread according to the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, wherein the more the number of branches in the thread whose branch prediction accuracy is lower than the accuracy threshold, the lower the criticality of the branch target table to the thread; The compilation instruction information is used to instruct, when running the optimization compiler, to reduce the allocation ratio of the branch target table allocated to the N threads, or to restrict the N threads to select a branch target table entry from the branch target table entries already occupied by the N threads for replacement when applying for a branch target table entry.

6. The information processing method according to claim 2, wherein: The occupation of the different hardware resources by the processor in the process of running the task includes the total amount of occupation of each hardware resource by each thread within a preset period of time when running the task, Determining the criticality of each hardware resource to each thread according to the occupation of the different hardware resources by the processor in the process of running the task, including: The criticality of each hardware resource to each thread is determined according to the total amount of occupation of each hardware resource by the multiple threads.

7. The information processing method according to claim 6, wherein: Determining the criticality of each hardware resource to each thread according to the total amount of each hardware resource occupied by the multiple threads, including: For a first hardware resource among the different hardware resources: For each thread, in response to a total amount of the first hardware resource occupied by the thread being less than B / b, determining that the criticality of the first hardware resource to the thread is not critical, wherein the first hardware resource is a hardware resource exclusively used by each of the multiple threads, B represents the total amount of the first hardware resource, b is the total number of the multiple threads, and B and b are integers greater than 1; In which, in response to the criticality of the first hardware resource to at least one thread among the multiple threads being non-critical, the compilation instruction information is used to instruct, when running the optimization compiler, to allocate the first hardware resource for each thread among the at least one thread according to the total amount of the first hardware resource occupied by each thread.

8. The information processing method according to claim 6, wherein: Determining the criticality of each hardware resource to each thread according to the total amount of each hardware resource occupied by the multiple threads, including: For any hardware resource, according to the total amount of occupation of the any hardware resource by each thread, determine the sum of the total amount of occupation of the any hardware resource by the multiple threads; In response to the sum of the total occupied amounts being greater than the total resource amount of any one of the hardware resources: Determine the total pipeline stall time of each thread when any of the hardware resources is missing; Determining the criticality of any one of the hardware resources to each thread according to the total duration of pipeline stagnation of each thread, wherein the total duration of pipeline stagnation of each thread is positively correlated with the criticality; The compilation instruction information is used to instruct, when running the optimization compiler, to increase the allocation ratio of a thread with a higher criticality to any one of the hardware resources and to reduce the allocation ratio of a thread with a lower criticality to any one of the hardware resources.

9. The information processing method according to claim 2, wherein: For any one hardware resource, in response to the criticality of any one hardware resource to M threads among the multiple threads being greater than a first threshold, and the criticality of any one hardware resource to N threads among the multiple threads being less than a second threshold, the compilation instruction information is used to instruct, when running the optimization compiler, to increase the allocation ratio of any one hardware resource to the M threads.

10. The information processing method according to claim 9, wherein: Determining the criticality of each hardware resource to each thread according to the occupation of the different hardware resources by the processor in the process of running the task, including: Determine the total duration of pipeline stagnation of the thread due to lack of any hardware resource or the proportion of the stagnation time in the total running time according to the duration of pipeline interruption or stagnation of the thread when the thread lacks any hardware resource and the number of times the thread lacks any hardware resource; The criticality of the thread to any one of the hardware resources is determined according to the total duration or the proportion.

11. The information processing method according to any one of claims 2 to 10, wherein: The occupation of the different hardware resources by the processor in the process of executing the task includes any combination of the following parameters: The number of times each thread occupies each hardware resource, the number of times each thread stalls in the pipeline when each hardware resource is missing, the duration of the pipeline stall when each thread lacks each hardware resource, the total amount of each hardware resource occupied by each thread, and the branch prediction accuracy of each branch in each thread.

12. The information processing method according to claim 1, wherein: The performance data includes the time distribution of the multiple threads occupying each hardware resource when the processor runs the task, Generating compilation instruction information corresponding to the task according to the performance data includes: The compilation instruction information is generated in combination with the time distribution of the multiple threads occupying each hardware resource when the processor runs the task, wherein the compilation instruction information is used to control the occupation timing of each hardware resource by each thread according to the time distribution of the multiple threads occupying each hardware resource when running the optimization compiler.

13. The information processing method according to claim 12, wherein: The compilation instruction information is used to reserve the target hardware resource for the thread when approaching the timing of the thread using the target hardware resource according to the time distribution of the multiple threads occupying each hardware resource when running the optimization compiler.

14. The information processing method according to claim 1, wherein: The performance data includes dependencies between hardware resources used by each thread of the processor during execution of the task, wherein the dependencies between the hardware resources used by each thread are indicated by whether the thread will cause the pipeline of the thread to stall when the hardware resource is missing. Generating compilation instruction information corresponding to the task according to the performance data includes: The compilation instruction information is generated in combination with the dependency relationship between the hardware resources used by each thread, wherein the compilation instruction information is used to control the occupation timing or resource occupation priority of the hardware resources used by the thread according to the dependency relationship between the hardware resources used by each thread when running the optimization compiler.

15. The information processing method according to claim 14, wherein: In response to a dependency relationship between P hardware resources used by the thread to perform the first operation, the P hardware resources include a target hardware resource, and P is a positive integer greater than 1, The compilation instruction information is used to indicate, when running the optimization compiler, that after the remaining P-1 hardware resources other than the target hardware resource return the usage data required to perform the first operation, the occupancy right of the target hardware resource is allocated to the thread, or the occupancy priority of the thread for the target hardware resource is increased.

16. The information processing method according to claim 14, wherein: The dependency relationship between the hardware resources used by each thread is obtained through the occupancy of multiple hardware resources when the pipeline of each thread is stalled, wherein the multiple hardware resources include other hardware resources among the different hardware resources except the hardware resources that directly cause the pipeline of the thread to be stalled.

17. The information processing method according to any one of claims 1 to 10, 12 to 16, wherein: The hardware resources in the processor include computing resources and storage resources. The computing resources include a computing logic unit and an address computing unit. The storage resources include cache, memory, queue, and register.

18. The information processing method according to any one of claims 1 to 10, 12 to 16, wherein: The processor includes at least one physical core, and the multiple threads run in the same physical core.

19. A resource allocation method, comprising: Allocating hardware resources of the processor used by the processor when executing the task according to compilation instruction information, wherein the compilation instruction information is generated according to performance data generated by the processor in the process of running the compiler corresponding to the task, the performance data is collected by pre-running the compiler for a preset time, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree of demand and / or the timing of demand of different hardware resources in the processor by each of the multiple threads; The compilation instruction information provides at least one of the following information: the criticality of different hardware resources to each thread, the time distribution of each hardware resource occupied by the multiple threads, and the dependency relationship between the hardware resources used by each thread.

20. The resource allocation method according to claim 19, wherein: Allocating hardware resources of the processor used when the processor executes a task according to the compilation instruction information includes: Determining the criticality of each hardware resource to each thread according to the compilation instruction information; According to the criticality of each hardware resource to each thread, the occupation ratio and / or dynamic usage range of each hardware resource by each thread is adjusted.

21. The resource allocation method according to claim 20, wherein: According to the criticality of each hardware resource to each thread, adjust the occupation ratio and / or dynamic usage range of each hardware resource by each thread, including: For any hardware resource, in response to the criticality of any hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any hardware resource to N threads among the multiple threads being less than or equal to a second threshold, reduce the allocation ratio of any hardware resource to the N threads, or limit the dynamic usage range of any hardware resource by the N threads, where M and N are positive integers.

22. The resource allocation method according to claim 21, wherein: Any of the hardware resources includes a cache, According to the criticality of each hardware resource to each thread, adjust the occupation ratio and / or dynamic usage range of each hardware resource by each thread, including: The allocation ratio of the cache to the N threads is reduced, or the N threads are restricted to select one cache line from the cache lines occupied by the N threads for cache replacement when cache replacement occurs.

23. The resource allocation method according to claim 21, wherein: Any of the hardware resources includes a branch target table, each branch target table entry in the branch target table is used to store relevant information of branch jumps, According to the criticality of each hardware resource to each thread, adjust the occupation ratio and / or dynamic usage range of each hardware resource by each thread, including: The allocation ratio of the branch target table to the N threads is reduced, or the N threads are restricted to select a branch target table entry from the branch target table entries occupied by the N threads for replacement when applying for a branch target table entry.

24. The resource allocation method according to claim 20, wherein: Any of the hardware resources includes a first hardware resource, wherein the first hardware resource is a hardware resource exclusively used by each of the plurality of threads, According to the criticality of each hardware resource to each thread, adjust the occupation ratio and / or dynamic usage range of each hardware resource by each thread, including: In response to the first hardware resource being non-critical to at least one of the multiple threads, the first hardware resource is allocated for each of the at least one thread according to a total amount of the first hardware resource occupied by each thread, wherein the total amount of the first hardware resource occupied by each thread is determined during the process of collecting the performance data.

25. The resource allocation method according to claim 20, wherein: According to the criticality of each hardware resource to each thread, adjust the occupation ratio and / or dynamic usage range of each hardware resource by each thread, including: For any one hardware resource, in response to the criticality of any one hardware resource to M threads among the multiple threads being greater than or equal to a first threshold, and the criticality of any one hardware resource to N threads among the multiple threads being less than or equal to a second threshold, the allocation ratio of any one hardware resource to the M threads is increased.

26. The resource allocation method according to claim 19, wherein: Allocating hardware resources of the processor used when the processor executes a task according to the compilation instruction information includes: According to the compilation instruction information, the occupation timing or resource occupation priority of each thread for each hardware resource is controlled.

27. The resource allocation method according to claim 26, wherein: In response to a dependency relationship between P hardware resources used by the thread to perform a first operation, the P hardware resources include a target hardware resource, P is a positive integer greater than 1, and when the thread performs the first operation, the lack of the P hardware resources will cause the pipeline of the thread to stall, According to the compilation instruction information, the occupation timing or resource occupation priority of each thread for each hardware resource is controlled, including: According to the compilation instruction information, after the remaining P-1 hardware resources except the target hardware resource return the usage data required to perform the first operation, the occupancy right of the target hardware resource is allocated to the thread, or the occupancy priority of the thread for the target hardware resource is increased.

28. An information processing device, comprising: a collecting module configured to collect performance data generated by the processor in the process of executing a task, wherein the performance data is collected by pre-running a compiled program of the task for a preset time, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree and / or timing of the demand for different hardware resources in the processor by each of the multiple threads; A generation module configured to generate compilation instruction information corresponding to the task according to the performance data, wherein the compilation instruction information provides at least one of the following information: the criticality of different hardware resources to each thread, the time distribution of each hardware resource occupied by the multiple threads, and the dependency relationship between the hardware resources used by each thread; The inserting module is configured to insert the compilation instruction information into the compiler to obtain the optimized compiler corresponding to the task, wherein the compilation instruction information is used for allocating hardware resources of the processor when the processor runs the optimized compiler.

29. A resource allocation device, comprising: an allocation module, configured to allocate hardware resources of the processor used when the processor executes a task according to compilation instruction information, wherein the compilation instruction information is generated according to performance data generated by the processor in the process of running a compiler corresponding to the task, the performance data is collected by pre-running the compiler for a preset time, the processor simultaneously runs multiple threads to execute the task, and the performance data indicates the degree of demand and / or the timing of demand of different hardware resources in the processor by each of the multiple threads; The compilation instruction information provides at least one of the following information: the criticality of different hardware resources to each thread, the time distribution of each hardware resource occupied by the multiple threads, and the dependency relationship between the hardware resources used by each thread.

30. An electronic device comprising: A memory non-transitorily stores computer executable instructions; a processor configured to execute the computer executable instructions, When the computer executable instructions are executed by the processor, the information processing method according to any one of claims 1-18 is implemented, or the resource allocation method according to any one of claims 19-27 is executed.

31. A non-transitory computer-readable storage medium, wherein: The non-transitory computer-readable storage medium stores computer-executable instructions, which, when executed by a processor, implement the information processing method according to any one of claims 1-18, or execute the resource allocation method according to any one of claims 19-27.

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