Signal routing adjustment method based on critical path, electronic device and medium

Abstract

The present invention relates to the field of computer technology, and in particular to a signal routing adjustment method based on a critical path, an electronic device and a medium, comprising steps S1, obtaining an FPGA channel A containing a critical path in an FPGA system, m ; Step S2, set m = 1, execute step S3; Step S3, obtain A m The signal S to be processed corresponding to the critical path in k m ; Step S4, for each S k m Select a rewinding path; Step S5, the S that has the rewinding path in the current FPGA system k m The winding path is cleared and each S k m The corresponding rewinding path is for each S k m Rewinding the wire and generating winding information after rewinding; Step S6, judging whether the system performance corresponding to the winding information after rewinding is better than the system performance corresponding to the winding information before rewinding, if so, accepting the winding information after this rewinding. The present invention improves the system performance designed by the user.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a signal routing adjustment method based on a critical path, an electronic device and a medium. Background Art

[0002] In a prototype verification system or hardware simulation system composed of multiple Field-Programmable Gate Arrays (FPGAs), it is necessary to find the best path for the user design signal across the FPGA connection to minimize the signal transmission delay and meet the best timing performance of the user design.

[0003] In the prior art, the timing-driven routing process is usually based on the shortest path routing, and uses the average time division multiplexing ratio (TDR) allocation method to construct the signal routing result. However, due to the large number of signals, different signals may have different delay requirements. The existing signal routing method will cause some signals to fail to meet the system timing performance, thereby reducing the system performance designed by the user. Therefore, how to adjust the signal routing to improve the system performance designed by the user has become a technical problem that needs to be solved urgently. Summary of the invention

[0004] The purpose of the present invention is to provide a signal routing adjustment method based on a critical path, an electronic device and a medium, thereby improving the system performance designed by a user.

[0005] According to a first aspect of the present invention, a signal routing adjustment method based on a critical path is provided, comprising:

[0006] Step S1, obtain the FPGA channel {A1, A2, ..., A m ,...,A M}, where A m is the mth FPGA channel containing a critical path, where m ranges from 1 to M, and M is the total number of FPGA channels containing a critical path in the FPGA system. The critical path is the path for transmitting a signal with the worst delay margin, and the FPGA channel is a channel between two FPGAs connected by a cable in the FPGA system. A1, A2, ..., A m ,...,A M Sort by the number of critical paths included from large to small;

[0007] Step S2, set m=1, and execute step S3;

[0008] Step S3: Get Am The signal to be processed corresponding to the critical path in {S1 m ,S2 m ,...,S k m ,...,S h(m) m}, where S k m A m The signal to be processed corresponding to the kth critical path in, k from 1 to h(m), h(m) is A m The number of signals to be processed corresponding to the critical path in ;

[0009] Step S4: for each S k m Select a rewind path whose delay is less than S in the current FPGA system. k m Delay

[0010] Step S5: S k m The winding path is cleared and each S k m The corresponding rewinding path is for each S k m Rewinding the wire and generating the winding information after rewinding;

[0011] Step S6: determine whether the system performance corresponding to the winding information after rewinding is better than the system performance corresponding to the winding information before rewinding. If so, accept the winding information after this rewinding.

[0012] According to a second aspect of the present invention, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being configured to execute the method described in the first aspect of the present invention.

[0013] According to a third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the first aspect of the present invention.

[0014] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, the signal routing adjustment method based on the critical path, the electronic device and the medium provided by the present invention can achieve considerable technical advancement and practicality, and have wide industrial utilization value, and at least have the following beneficial effects:

[0015] The present invention first obtains FPGA channels containing critical paths in the FPGA system and sorts them in descending order according to the number of critical paths contained therein, then rewinds the critical paths in the FPGA channels containing the critical paths, and receives the rewound winding information when confirming that the system performance is better than the system performance corresponding to the winding information before the rewinding, thereby improving the system performance designed by the user through the local signal winding optimization based on the critical path in the FPGA system. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A flow chart of a signal routing adjustment method based on a critical path provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0019] The embodiment of the present invention provides a signal routing adjustment method based on a critical path, such as Figure 1 As shown, including:

[0020] Step S1, obtain the FPGA channel {A1, A2, ..., A m ,...,A M}, where A m is the mth FPGA channel containing a critical path, where m ranges from 1 to M, and M is the total number of FPGA channels containing a critical path in the FPGA system. The critical path is the path for transmitting a signal with the worst delay margin, and the FPGA channel is a channel between two FPGAs connected by a cable in the FPGA system. A1, A2, ..., A m ,...,A M Sort by the number of critical paths included from largest to smallest.

[0021] The delay margin of the signal is the difference between the preset delay of the signal and the actual delay of the signal.

[0022] Step S2, set m=1, and execute step S3.

[0023] Step S3: Get A m The signal to be processed corresponding to the critical path in {S1 m ,S2 m ,...,S k m ,...,S h(m) m}, where S k m A m The signal to be processed corresponding to the kth critical path in, k from 1 to h(m), h(m) is A m The number of signals to be processed corresponding to the critical path in .

[0024] It should be noted that A m The signal to be processed corresponding to the critical path in may be A m The signals corresponding to all critical paths in the m Signals corresponding to some critical paths in .

[0025] Step S4: for each S k m Select a rewind path whose delay is less than S in the current FPGA system. k m delay.

[0026] It should be noted that each S k m There may be other optional paths. In order to optimize S k m The delay needs to be S k m Select a value that is smaller than S in the current FPGA system. k m If a path with a delay of does not exist, the current routing path remains unchanged.

[0027] Step S5: S k m The winding path is cleared and each S k m The corresponding rewinding path is for each S k m Rewind the wire and generate the winding information after rewinding.

[0028] It should be noted that due to some S k m There may not be a better alternative path, so in the end only some S kThe rewinding path is selected. In step S5, only the S k m The routing paths are cleared from the current FPGA system and rerouted.

[0029] Step S6: determine whether the system performance corresponding to the winding information after rewinding is better than the system performance corresponding to the winding information before rewinding. If so, accept the winding information after this rewinding.

[0030] It should be noted that the system performance after rewinding is not necessarily better than the system performance before rewinding. Therefore, in step S6, it is further determined whether the system performance corresponding to the winding information after rewinding is better than the system performance corresponding to the winding information before rewinding. Only when it is determined that the system performance corresponding to the winding information after rewinding is better than the system performance corresponding to the winding information before rewinding, the winding information after this rewinding is finally accepted to achieve signal routing optimization of the FPGA system.

[0031] As an embodiment, in step S3, if A m There are multiple critical paths corresponding to the signal transmission back and forth, and multiple critical paths are on the same timing path, forming a Z-shaped signal, then in {S1 m ,S2 m ,...,S k m ,...,S h(m) m Only the first signal corresponding to the Z-shaped signal is stored in {S1}. The signals other than the first signal in the Z-shaped signal are not in {S1 m ,S2 m ,...,S k m ,...,S h(m) m It should be noted that when counting the number of critical paths contained in the FPGA channel, the number of signals corresponding to the critical paths corresponding to the Z-shaped signal needs to be counted. However, if all the signals corresponding to the critical paths corresponding to the Z-shaped signal are rewound during rewinding, the delay change from the perspective of the timing path will be multiple of the number of signals, which may cause excessive rewinding and fail to achieve the best effect. Therefore, for multiple signals of the Z-shaped signal on the same timing path, only in {S1 m ,S2 m ,...,S k m ,...,S h(m) m The first signal corresponding to the Z-shaped signal is stored in}, so that only one of the signals is rewound as the target signal in one iteration, and the optimization is performed step by step to avoid excessive one-time delay changes.

[0032] As an embodiment, in step S6, if the system performance corresponding to the winding information after rewinding is not better than the system performance corresponding to the winding information before rewinding, the FPGA system is restored to the state before rewinding, and it is determined whether m is less than M. If so, m=m+1 is set, and the process returns to step S3. If m=M, the process ends. It can be understood that if based on the current A m When the corresponding rewinding information cannot optimize the system performance, the FPGA system needs to be restored to the state before rewinding and the next A m Continue to rewind based on the critical path. It should be noted that if the worst delay margin corresponding to the rewinding information decreases and / or the number of critical paths decreases, it can be determined that the system performance corresponding to the rewinding information is better than the system performance corresponding to the rewinding information before rewinding. If the worst delay margin corresponding to the rewinding information does not decrease and the number of critical paths does not decrease, it is determined that the system performance corresponding to the rewinding information is not better than the system performance corresponding to the rewinding information before rewinding.

[0033] As an embodiment, in step S6, after accepting the winding information after this rewinding, it is determined whether the system performance corresponding to the winding information after the rewinding meets the preset target system performance. If so, the process is terminated; if not, the process returns to step S1 and iterates again until the preset target system performance is met or there is no other optimization space.

[0034] As an embodiment, step S4 includes:

[0035] Step S41: Obtain the current FPGA system S k m The corresponding current delay D1 k m .

[0036] Step S42: Get S k m The corresponding candidate rewind path {SL1 mk ,SL2 mk ,...,SL z mk ,...,SL J(mk) mk}, where SL z mk For S k m The corresponding z-th candidate rewinding path, z ranges from 1 to J(mz), J(mz) is S k m The total number of corresponding candidate rewind paths.

[0037] It should be noted that when the values ​​of m and z are different, the value of J(mz) may also be different.

[0038] Step S43: Get S k m Each corresponding SL z mk The corresponding predicted delay D2 z mk .

[0039] Step S44, determine S k m The corresponding minimum D2 z mk Is it less than S? k m The corresponding current delay D1 k m , if it is less than, then S k m The corresponding minimum D2 z mk Corresponding SL z mk Determined as S k m The corresponding rewinding path, otherwise, determine S k m There is no rewind path.

[0040] It should be noted that if the signal to be processed corresponding to the critical path is A m If the signal is directly connected, it means that there is a shortest path and there is no room for optimization, so there is no need to perform steps S41 to S44. In order to reduce the amount of calculation, as an embodiment, before step S41, the following is also included:

[0041] Step S40: Determine S k m Is it caused by A m Directly connected signal, if so, then directly determine S k m There is no rewinding path, otherwise, execute step S41.

[0042] As an example, SL z mk ={SL11 zmk ,SL12 zmk ,...,SL1 p zmk ,...,SL1 g(zmk) zmk ,SL21 zmk ,SL22 zmk ,...,SL2q zmk ,...,SL2 [g(zmk)-1] zmk}, where SL1 p zmk For S k m In SL z mk The pth FPGA channel passed through, the value range of p is 1 to g(zmk), g(zmk) is SL z mk The total number of FPGA channels in SL2 q zmk For SL z mk The qth FPGA passed through, the value range of q is 1 to [g(zmk)-1], [g(zmk)-1] is SL z mk The total number of FPGAs passed through, it should be noted that SL21 zmk Located at SL11 zmk and SL12 zmk Between, SL22 zmk Located at SL12 zmk and SL13 zmk Between, ..., SL2 [g(zmk)-1] zmk Located in SL1 [g(zmk)-1] zmk and SL1 g(zmk) zmk The step S43 comprises:

[0043] Step S431: Obtain SL1 in the current FPGA system p zmk The minimum time-to-multiplexing rate TDR of the cable in the FPGA channel p zmk .

[0044] It should be noted that, since the critical path is rewound, a cable with the smallest time division multiplexing rate should be selected for transmission in each FPGA channel to minimize the delay of the critical path.

[0045] Step S432: Based on the preset time division multiplexing mapping table and TDR p zmk Get every SL1 p zmk The corresponding delay value D3 p zmk The time division multiplexing mapping table stores a mapping relationship between time division multiplexing rate and delay value.

[0046] It should be noted that the time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. p zmk Find the corresponding delay value D3 p zmk .

[0047] Step S433: Based on D3 p zmk , SL z mk The total number of FPGAs in the SL z mk The corresponding predicted delay D2 z mk :

[0048]

[0049] Wherein, β is the preset routing cost through FPGA.

[0050] It should be noted that if there are multiple predicted delays D2 corresponding to candidate rewind paths z mk minimum, the path length factor will be further considered and multiple predicted delays D2 z mk Among the minimum rewinding paths, the candidate rewinding path with the shortest path is determined as S k m The rewind path.

[0051] As an embodiment, after receiving the winding information after the current rewinding, the step S6 executes:

[0052] Step D10: Perform TDM distribution on the rewound signals between every two interconnected FPGAs.

[0053] In the step D10, the existing TDM allocation method can be used to implement the step, or the following two methods can be used to implement the step.

[0054] Method 1:

[0055] The step D10 comprises:

[0056] Step D101, perform average TDM distribution on the signals between every two interconnected FPGAs. If all signals meet the preset timing requirements, the winding information in the current FPGA system is determined as the target winding information. Otherwise, adjust the TDM distribution of the signals between the interconnected FPGAs so that all signals meet the preset timing requirements.

[0057] Method 2:

[0058] Method 2 provides a signal TDM distribution method based on FPGA, including:

[0059] Step D1001: Obtain a signal set {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}, where E s is the sth signal between the first FPGA and the second FPGA, the value range of s is 1 to S, and S is the number of positive signals between the first FPGA and the second FPGA; E w is the wth signal between the first FPGA and the second FPGA, the value range of w is S+1 to W, and W is the sum of the number of forward signals and reverse signals between the first FPGA and the second FPGA; E s The upper limit of the delay between the first FPGA and the second FPGA is D s , D1>D2,...,>D s ,...,>D S ; E w The upper limit of the delay between the first FPGA and the second FPGA is D w , D S+1 >D S+2 >,...,>D w ,...,>D W .

[0060] Among them, the first FPGA and the second FPGA can be any two FPGAs in the FPGA system that are interconnected by cables and have signal transmission. The signal between the first FPGA and the second FPGA refers to the signal transmitted through the cable between the first FPGA and the second FPGA. It should be noted that the forward signal refers to the signal transmitted from the first FPGA to the second FPGA, and the reverse signal refers to the signal transmitted from the second FPGA to the first FPGA. There may be both forward signals and reverse signals between the first FPGA and the second FPGA, or there may be only forward signals, that is, there are bidirectional signals. The existence of only forward signals is equivalent to a special case of the existence of bidirectional signals, and is also applicable to the method described in the embodiment of the present invention. The delay upper limit refers to the maximum delay of the signal passing through the first FPGA and the second FPGA. Through D1>D2,...,>D s ,...,>D S and D S+1 >D S+2 >,...,>D w ,...,>D WIt can be seen that E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W The forward signal and the reverse signal are sorted in descending order according to the delay upper limit, and the forward signal is generally arranged before the reverse signal.

[0061] Step D1002, obtain E in sequence s The optimal TDR value corresponding to the case where there are f1 cables and s signals between the first FPGA and the second FPGA is TDR(s,f1), where the value range of f1 is 1 to F, and F is the total number of cables between the first FPGA and the second FPGA.

[0062] It should be noted that, by obtaining the optimal TDR value corresponding to each combination of f1 and s in step D1002, it can be understood that TDR (s, f1) may exist or may not exist.

[0063] Step D1003, obtain E in sequence w The optimal TDR value corresponding to the situation where there are f2 cables and w signals between the first FPGA and the second FPGA is TDR(w,f2), where the value range of f2 is 2 to F, and the same cable can only transmit signals in the same direction.

[0064] It should be noted that, by obtaining the optimal TDR value corresponding to each combination of f2 and w in step D1003, it can be understood that TDR (w, f2) may exist or may not exist.

[0065] Step D1004: If TDR (W, F) exists, determine the signal TDM allocation between the first FPGA and the second FPGA based on all TDR (s, f1) and TDR (w, f2).

[0066] It should be noted that if TDR(W,F) exists, it means that the W signals between the first FPGA and the second FPGA can be successfully TDM distributed on F cables. If it does not exist, it means that the W signals between the first FPGA and the second FPGA cannot be successfully TDM distributed on F cables. In this case, a corresponding prompt message can be generated, and the design can be adjusted and TDM distribution can be performed again by the method of embodiment 2 of the present invention.

[0067] As an embodiment, the step D1001 includes:

[0068] Step D10011, obtain the initial winding information in the FPGA system.

[0069] Step D10012: Generate a time margin (Slack) for each signal based on the initial winding information.

[0070] Step D10013, obtain the delay between the first FPGA and the second FPGA of each signal passing between the first FPGA and the second FPGA, and determine the sum of the delay between the first FPGA and the second FPGA of each signal passing between the first FPGA and the second FPGA and the time margin corresponding to the signal as the upper limit of the signal delay.

[0071] Step D10014: Sort the signals between the first FPGA and the second FPGA according to the direction of each signal passing between the first FPGA and the second FPGA and the upper limit of the delay of each signal, and generate {E1, E2, ..., E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}.

[0072] It is understandable that by D1>D2,...,>D s ,...,>D S and D S+1 >D S+2 >,...,>D w ,...,>D W sorting, generating {E1,E2,...,E s ,...,E S ,E S+1 ,E S+2 ,...,E w ,...,E W}.

[0073] As an embodiment, the step D1002 includes:

[0074] Step D10021, set s=1, f1=1, and execute step D10022.

[0075] Step D10022: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. s If so, set TDR(s,f1) to the value of the current TDR and execute step D10023. The time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. Otherwise, set TDR(s,f1) to empty and execute step D10024.

[0076] It should be noted that step D10022 determines the situation where there is only one cable for allocation. The delay corresponding to the TDR value allocated to the signal must be less than or equal to the upper limit of the signal delay in order to be successfully allocated. The smaller the TDR value, the smaller the delay. Therefore, when there is only one cable, the first available TDR value obtained in the order of TDR values ​​from small to large is the optimal TDR value.

[0077] Step D10023, determine whether s is less than S, if so, set s=s+1, return to execute step D10022, otherwise, execute step D10024.

[0078] Step D10024, determine whether f1 is less than F, if so, set s=1, f1=f1+1, and execute step D10025, otherwise, execute step D1003.

[0079] Step D10025: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. s If so, determine whether TDR(s-TDR0,f1-1) is empty, TDR0 is the value of the currently judged TDR, if it is not empty, set TDR(s,f1) to the value of the currently judged TDR, and execute step D10023, otherwise, set TDR(s,f1) to empty, and execute step D10024.

[0080] It should be noted that step D10025 obtains the TDR value of two or more cables. In this case, it is also necessary to satisfy that the number of allocated cables cannot exceed the current maximum number of cables. Therefore, it is necessary to simultaneously satisfy that TDR(s-TDR0,f1-1) is not empty, that is, s-TDR0 signals can be successfully allocated on f1-1 cables.

[0081] It should be noted that when there is only a forward signal between the first FPGA and the second FPGA, all possible TDR values ​​can be obtained through steps D10021-D10025. When there is a reverse signal between the first FPGA and the second FPGA, it is necessary to further perform step D1003 to obtain all possible TDR values ​​corresponding to the reverse signal. When TDR(s,f1) does not have a TDR value that meets the conditions, the corresponding setting is empty.

[0082] As an embodiment, step D1003 includes:

[0083] Step D10031, set w=S+1, f2=2, and execute step D10032.

[0084] It should be noted that the same cable can only transmit signals in one direction. Therefore, when there is a bidirectional signal between the first FPGA and the second FPGA, the forward signal needs to occupy at least one cable. Therefore, the value of f2 should start from 2.

[0085] Step D10032: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. w If so, set TDR(w,f2) to the value of the current TDR and execute step D10033. The time division multiplexing mapping table stores the mapping relationship between the time division multiplexing rate and the delay value. Otherwise, set TDR(w,f2) to empty and execute step D10034.

[0086] It should be noted that step D10032 determines the situation where there is only one cable for allocation. The delay corresponding to the TDR value allocated to the signal must be less than or equal to the upper limit of the signal delay in order to successfully allocate. The smaller the TDR value, the smaller the delay. Therefore, when there is only one cable, the first available TDR value obtained in the order of TDR values ​​from small to large is the optimal TDR value.

[0087] Step D10033, determine whether w is less than W, if so, set w=w+1, return to execute step D10032, otherwise, execute step D10034.

[0088] Step D10034, determine whether f2 is less than F, if so, set w=S+1, f2=f2+1, and execute step D10035, otherwise, execute step D1004.

[0089] Step D10035: Based on the preset time division multiplexing mapping table, determine in ascending order whether the corresponding delay is less than or equal to D according to the TDR value. w , if so, execute step D10036, otherwise, execute step D10034.

[0090] Step D10036: determine whether (w-TDR0)≥S+1 is satisfied. If so, execute step D10037; otherwise, execute step D10038.

[0091] Step D10037, determine whether TDR (w-TDR0, f2-1) is empty, TDR0 is the value of the currently judged TDR, if it is not empty, set TDR (w, f2) to the value of the currently judged TDR, and execute step D10033, otherwise, set TDR (w, f2) to empty, and execute step D10034.

[0092] Step D10038: Determine whether TDR(S, f2 - 1) is empty. If it is not empty, set TDR(w, f2) to the currently judged TDR value and execute Step D10033. Otherwise, set TDR(w, f2) to be empty and execute Step D10034.

[0093] It should be noted that if (w - TDR0) ≥ S + 1, it means that the (w - TDR0)th signal is also a reverse signal. Otherwise, it is a forward signal. Since only one signal can be transmitted on the same cable, the forward signal and the reverse signal cannot be allocated on the same cable. Therefore, when (w - TDR0) < S + 1, the boundary value adjacent to the reverse signal, that is, the (S + 1)th signal, should be taken for judgment instead of the (w - TDR0)th signal. When there is no TDR value that meets the conditions in TDR(w, f2), it is correspondingly set to be empty.

[0094] As an embodiment, the said Step D1004 includes:

[0095] Step D10041: If TDR(W, F) is not empty, set the cable number to be allocated XL = F and the signal termination number to be allocated ZL = W.

[0096] It should be noted that if TDR(W, F) is not empty, it means that the W signals between the first FPGA and the second FPGA can be allocated on F cables.

[0097] Step D10042: Set the TDR value of the XLth cable between the first FPGA and the second FPGA to TDR(ZL, XL).

[0098] Among them, the optimal TDR value of the XLth cable between the first FPGA and the second FPGA is TDR(ZL, XL). Therefore, directly set the TDR value of the XLth cable between the first FPGA and the second FPGA to TDR(ZL, XL). It shows that at this time, the XLth cable can accommodate at most TDR(ZL, XL) signals.

[0099] Step D10043: Determine whether ZL - TDR(ZL, XL) is greater than or equal to S. If so, execute Step D10045. Otherwise, execute Step D10044.

[0100] It should be noted that when ZL - TDR(ZL, XL) is greater than or equal to S, it means that all the signals to be allocated are reverse signals at this time. Therefore, directly execute Step D10045. When ZL - TDR(ZL, XL) is less than S, it may occur that the starting signal to be allocated is a forward signal and the terminating signal to be allocated is a reverse signal. However, since only one direction of signal can be allocated on the same cable, further judgment is needed and Step D10044 is executed.

[0101] Step D10044: If ZL > S, then execute Step D10046; otherwise, execute Step D10045.

[0102] It should be noted that when ZL > S and ZL - TDR(ZL, XL) < S, it indicates that the starting signal to be allocated is a positive signal and the terminating signal to be allocated is a negative signal. Therefore, through Step D10046, the starting signal to be allocated is set as the (S + 1)-th signal to ensure that only signals in the same direction are allocated to the same cable.

[0103] Step D10045: Set the starting signal number YL to be allocated as YL = ZL - TDR(ZL, XL) + 1, and allocate signals E YL to E ZL on the XL-th cable, and then execute Step D10047.

[0104] Step D10046: Set YL = S + 1, and allocate signals E YL to E ZL on the XL-th cable, and then execute Step D10047.

[0105] Step D10047: If YL - 1 = 1, then end the process; otherwise, set XL = XL - 1, ZL = YL - 1, and return to execute Step D10042.

[0106] It should be noted that through Steps D10041 - D10047, the TDR values corresponding to all signals and the cable numbers to which they are allocated can be determined. It can be understood that in the embodiments of the present invention, the cables are numbered in the order of 1, 2, 3..., F. In addition, after the TDM allocation is completed, all the cables in the first FPGA and the second FPGA may be occupied, or there may be remaining unoccupied cables.

[0107] Through the TDM allocation method provided in Method 2, an optimal TDM allocation can be achieved for signals between any two FPGAs, further improving the system performance.

[0108] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the description of the present invention herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention.

[0109] It should be noted that some exemplary embodiments are described as processes or methods depicted as flow charts. Although the flow charts describe the steps as sequential processes, many of the steps can be implemented in parallel, concurrently or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operation is completed, but it can also have additional steps not included in the accompanying drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, etc.

[0110] An embodiment of the present invention also provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0111] The embodiment of the present invention further provides a computer-readable storage medium storing computer-executable instructions, wherein the computer instructions are used to execute the method described in the embodiment of the present invention.

[0112] The embodiment of the present invention first obtains FPGA channels containing critical paths in the FPGA system and sorts them in descending order according to the number of critical paths contained therein, then rewinds the critical paths in the FPGA channels containing the critical paths, and receives the rewound routing information when it is confirmed that the system performance is better than the system performance corresponding to the routing information before the rewinding, thereby improving the system performance designed by the user through the local signal routing optimization based on the critical path in the FPGA system.

[0113] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modifications to equivalent embodiments of equivalent changes using the technical contents disclosed above without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of the technical solution of the present invention.

Claims

1. A signal routing adjustment method based on a critical path, characterized in that: include: Step S1, obtain the FPGA channel {A1, A2, ..., A m ,...,A M }, where A m is the mth FPGA channel containing a critical path, where m ranges from 1 to M, and M is the total number of FPGA channels containing a critical path in the FPGA system. The critical path is the path for transmitting a signal with the worst delay margin, and the FPGA channel is a channel between two FPGAs connected by a cable in the FPGA system. A1, A2, ..., A m ,...,A M Sort by the number of critical paths included from large to small; Step S2, set m=1, and execute step S3; Step S3: Get A m The signal to be processed corresponding to the critical path in {S1 m ,S2 m ,...,S k m ,...,S h(m) m }, where S k m A m The signal to be processed corresponding to the kth critical path in, k from 1 to h(m), h(m) is A m The number of signals to be processed corresponding to the critical path in ; Step S4: for each S k m Select a rewind path whose delay is less than S in the current FPGA system. k m Delay The step S4 comprises: Step S41: Obtain the current FPGA system S k m The corresponding current delay D1 k m ; Step S42: Get S k m The corresponding candidate rewind path {SL1 mk ,SL2 mk ,...,SL z mk ,...,SL J(mk) mk }, where SL z mk For S k m The corresponding z-th candidate rewinding path, z ranges from 1 to J(mz), J(mz) is S k m The total number of corresponding candidate rewind paths; Step S43: Get S k m Each corresponding SL z mk The corresponding predicted delay D2 z mk ; Step S44, determine S k m The corresponding minimum D2 z mk Is it less than S? k m The corresponding current delay D1 k m , if it is less than, then S k m The corresponding minimum D2 z mk Corresponding SL z mk Determined as S k m The corresponding rewinding path, otherwise, determine S k m There is no rewind path; Step S5: S k m The winding path is cleared and each S k m The corresponding rewinding path is for each S k m Rewinding the wire and generating the winding information after rewinding; Step S6: determine whether the system performance corresponding to the winding information after rewinding is better than the system performance corresponding to the winding information before rewinding. If so, accept the winding information after this rewinding.

2. The method according to claim 1, characterized in that: In step S6, if the system performance corresponding to the winding information after rewinding is not better than the system performance corresponding to the winding information before rewinding, the FPGA system is restored to the state before rewinding, and it is determined whether m is less than M. If so, m=m+1 is set, and the process returns to step S3. If m=M, the process ends.

3. The method according to claim 1, characterized in that In step S6, after receiving the winding information after this rewinding, it is determined whether the system performance corresponding to the winding information after the rewinding meets the preset target system performance. If so, the process ends; if not, the process returns to step S1.

4. The method according to claim 1, characterized in that: Before step S41, the following steps are also included: Step S40: Determine S k m Is it caused by A m Directly connected signal, if so, then directly determine S k m There is no rewinding path, otherwise, execute step S41.

5. The method according to claim 1, characterized in that SL z mk ={SL11 zmk ,SL12 zmk ,...,SL1 p zmk ,...,SL1 g(zmk) zmk ,SL21 zmk ,SL22 zmk ,...,SL2 q zmk ,...,SL2 [g(zmk)-1] zmk }, Among them, SL1 p zmk For S k m In SL z mk The pth FPGA channel passed through, the value range of p is 1 to g(zmk), g(zmk) is SL z mk The total number of FPGA channels in SL2 q zmk For SL z mk The qth FPGA passed through, the value range of q is 1 to [g(zmk)-1], [g(zmk)-1] is SL z mk The total number of FPGAs passed through, the step S43 comprises: Step S431: Obtain SL1 in the current FPGA system p zmk The minimum time-to-multiplexing rate TDR of the cable in the FPGA channel p zmk ; Step S432: Based on the preset time division multiplexing mapping table and TDR p zmk Get every SL1 p zmk The corresponding delay value D3 p zmk The time division multiplexing mapping table stores a mapping relationship between time division multiplexing rate and delay value; Step S433: Based on D3 p zmk , SL z mk The total number of FPGAs in the SL z mk The corresponding predicted delay D2 z mk : Wherein, β is the preset routing cost through FPGA.

6. The method according to claim 1, characterized in that After receiving the winding information after the current rewinding, the step S6 executes: Step D10: Perform TDM distribution on the signals between every two interconnected FPGAs after rewinding.

7. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions executable by the at least one processor, wherein the instructions are configured to execute the method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: Computer executable instructions are stored, and the computer executable instructions are used to execute the method according to any one of the preceding claims 1-6.

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