Precharge drive circuit, array substrate, display panel

Abstract

The present application relates to a pre-charging drive circuit, an array substrate and a display panel. The pre-charging drive circuit includes: the pre-charging drive circuit includes a plurality of cascaded drive components, each of the drive components includes two gate drive units, and the gate drive unit includes: a control circuit for providing a first drive signal or a second drive signal, wherein the first drive signal and the second drive signal are different drive signals; a gate drive circuit connected to the output end of the control circuit, for performing pre-charging at a preset point according to the first drive signal or the second drive signal; and electrical connections between different gate drive circuits in the same drive component. Different drive signals are provided to the gate drive circuit for pre-charging at preset points, thereby being compatible with the driving modes of two different drive power supplies.

Description

Technical Field

[0001] The present application relates to the technical field of display panels, and in particular to a pre-charge driving circuit, an array substrate, and a display panel. Background Art

[0002] Most liquid crystal displays (LCDs) are backlight type LCDs, which include a housing, a liquid crystal display panel disposed in the housing, and a backlight module in the housing. The LCD requires a light source provided by the backlight module to display light normally.

[0003] Usually, a liquid crystal display panel is made of two glass substrates (array glass and color filter glass) bonded together, and liquid crystal is poured between the two glass substrates. Pixel electrodes and common electrodes are set on the opposite inner sides of the two glass substrates, and the voltage field strength is used to control the rotation direction of the liquid crystal molecules, and the picture is produced by refracting the light of the backlight module.

[0004] The TV display market is currently developing towards ultra-large size (above 85 inches) and ultra-high refresh rate (above 240HZ). In order to improve GOA drive (progressive scan drive), there are currently two ways to pre-charge the Q point, namely using VPC DC high voltage for Q point pre-charging, or using Gout (n) signal for Q point pre-charging. However, using VPC DC high voltage for Q point pre-charging will cause serious Vth shif (voltage threshold shift) for TFT electrical properties for a long time, and using Gout (n) signal for Q point pre-charging has poor low-temperature driving capability. Currently, there is no technology that can be compatible with both driving methods. Summary of the invention

[0005] The present application provides a pre-charging driving circuit, an array substrate, and a display panel to solve the problem of how to be compatible with two different pre-charging driving modes at the same time.

[0006] In a first aspect, the present application provides a pre-charge driving circuit, the pre-charge driving circuit comprising a plurality of cascaded driving components, each of the driving components comprising two gate driving units, and the gate driving unit comprising:

[0007] A control circuit, used for providing a first drive signal or a second drive signal, wherein the first drive signal and the second drive signal are different drive signals;

[0008] A gate drive circuit, connected to the output end of the control circuit, and configured to perform pre-charging at a preset point according to the first drive signal or the second drive signal;

[0009] Different gate driving circuits in the same driving component are electrically connected.

[0010] In a second aspect, the present application provides an array substrate, which includes the above-mentioned pre-charging driving circuit and a carrier substrate for carrying the pre-charging driving circuit.

[0011] In a third aspect, the present application provides a display panel, which includes the above-mentioned array substrate and an opposing substrate arranged opposite to the array substrate.

[0012] The above-mentioned technical solution provided by the embodiment of the present application has the following advantages compared with the prior art: the pre-charging drive circuit provided by the embodiment of the present application includes a plurality of cascaded drive components, each of the drive components includes two gate drive units, and the gate drive unit includes: a control circuit, used to provide a first drive signal or a second drive signal, wherein the first drive signal and the second drive signal are different drive signals; a gate drive circuit, connected to the output end of the control circuit, and used to perform pre-charging of a preset point according to the first drive signal or the second drive signal; and electrical connection between different gate drive circuits in the same drive component.

[0013] Each gate drive unit switches the first drive signal or the second drive signal through the control circuit therein, thereby providing different drive signals to the gate drive circuit for pre-charging at preset points, thereby being compatible with two different drive power supply driving modes and expanding the scope of application of the pre-charging drive circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0015] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0016] One or more embodiments are exemplarily described by pictures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0017] Figure 1 A schematic diagram of the structure of a single driving component in a pre-charging driving circuit provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a single driving component in a pre-charging driving circuit provided in an embodiment of the present application;

[0019] Figure 3 A schematic diagram of the structure of a control circuit provided in an embodiment of the present application;

[0020] Figure 4 A schematic diagram of a driving signal waveform for point pre-charging provided in an embodiment of the present application;

[0021] Figure 5 A schematic diagram of a driving signal waveform for point pre-charging provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the structure of a single driving component in a pre-charging driving circuit provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the structure of a single driving component in a pre-charging driving circuit provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of the structure of a single driving component in a pre-charging driving circuit provided in an embodiment of the present application;

[0025] Fig. 9 A schematic diagram of the structure of a display panel provided in an embodiment of the present application.

[0026] 100, driving component; 110, gate driving unit; 111, control circuit; 1111, first control branch; 1112, second control branch; 112, gate driving circuit; 1121, pull-up module; 1122, point pull-down module; 1123, pull-down maintaining module; 1124, level transfer pull-down module; 1101, first gate driving unit 1101; 1102, second gate driving unit; 210, array substrate; 220, opposing substrate. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0028] The disclosure below provides many different embodiments or examples to implement different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or letters in different examples. This repetition is for the purpose of simplification and clarity, and does not itself indicate the relationship between the various embodiments and / or settings discussed.

[0029] Figure 1 FIG. 1 is a schematic diagram of a pre-charge drive circuit in an embodiment. The pre-charge drive circuit includes a plurality of cascaded drive components 100. Figure 1 Each of the driving components 100 includes two gate driving units 110, and the gate driving unit 110 includes:

[0030] The control circuit 111 is used to provide a first driving signal or a second driving signal, wherein the first driving signal and the second driving signal are different driving signals;

[0031] A gate drive circuit 112, connected to the output end of the control circuit 111, for performing pre-charging at a preset point according to the first drive signal or the second drive signal;

[0032] Different gate driving circuits 112 in the same driving component 100 are electrically connected.

[0033] Specifically, the gate drive unit 110 is recorded as a GOA unit, the first drive signal is a VPC DC high voltage signal or a Gout(n) signal, and the second drive signal is a Gout(n) signal or a VPC DC high voltage signal, that is, the first drive signal and the second drive signal are two different drive signals. The control circuit 111 can only provide one drive signal to the gate drive circuit 112 at the same time, and the control circuit 111 switches different drive signals to provide them to the gate drive circuit 112, so that the gate drive circuit 112 performs pre-charging at a preset point according to different drive signals, and the preset point is the Q point in the gate drive circuit 112.

[0034] Specifically, it can switch to using the VPC DC high voltage signal for Q point pre-charging when the low-temperature driving capability requirement is high, or switch back to using the Gout(n) signal for Q point pre-charging before using the VPC DC high voltage signal for pre-charging to generate Vth shif. This makes it compatible with two different driving power supply driving methods, expands the scope of application of the pre-charging driving circuit, and can quickly switch the driving signal in different scenarios to meet the scene requirements.

[0035] In the prior art, if you want to switch different driving signals, you need to switch the panel layer (Mask) corresponding to the different driving signals, but changing the panel layer will increase the production cost and reduce the risk resistance of GOA. However, in the present application, there is no need to change the panel layer to achieve compatibility of two different driving methods, which not only saves production costs, but also improves the risk resistance of GOA.

[0036] In one embodiment, Figure 2 As shown, the control circuit 111 includes:

[0037] The first control branch 1111 is used to provide a first driving signal;

[0038] A second control branch 1112, wherein the output end of the second control branch 1112 is connected to the output end of the first control branch 1111 and serves as the output end of the control circuit 111, and the second control branch 1112 is used to provide a second drive signal, and the drive state of the first control branch 1111 and the drive state of the second control branch 1112 are mutually exclusive.

[0039] Specifically, taking the first drive signal as a VPC DC high voltage signal and the second drive signal as a Gout(n) signal as an example, the output end of the first control branch 1111 is connected to the output end of the second control branch 1112, but the drive state of the first control branch 1111 and the drive state of the second control branch 1112 are mutually exclusive, and the drive states are driven and undriven. If the drive state of the first control branch 1111 is driven, it means that the first control branch 1111 is providing the first drive signal to the gate drive circuit 112. At this time, the drive state of the second control branch 1112 is undriven, indicating that the second control branch 1112 is in an off state and cannot provide the second drive signal to the gate drive circuit 112; conversely, if the drive state of the first drive branch is undriven, it means that the first control branch 1111 is in an off state and cannot provide the first drive signal to the gate drive circuit 112. At this time, the drive state of the second drive branch is driven, indicating that the second drive branch is providing the second drive signal to the gate drive circuit 112.

[0040] In one embodiment, the first control branch 1111 includes a first external signal source, a first drive signal source and a first transistor, the first external signal source is connected to the gate of the first transistor, the first drive signal source is connected to the source of the first transistor, and the drain of the first transistor serves as the output end of the first control branch 1111.

[0041] Specifically, Figure 3As shown, the first external signal source is denoted as Vcon1, the first drive signal source is used to provide a VPC DC high voltage signal, the first transistor is denoted as T8-1, and the first transistor is used to control the shutdown state according to the signal provided by the first external signal source, and the shutdown state determines whether the VPC DC high voltage signal provided by the first drive signal source is passed to the gate drive circuit 112.

[0042] In one embodiment, the second control branch 1112 includes a second external signal source, a second drive signal source and a second transistor, the second external signal source is connected to the gate of the second transistor, the second drive signal source is connected to the source of the second transistor, and the drain of the second transistor serves as the output end of the second control branch 1112.

[0043] Specifically, Figure 3 As shown, the second external signal source is denoted as Vcon2, the second drive signal source is used to provide a Gout(n) signal, the second transistor is denoted as T8-2, and the second transistor is used to control the off state according to the signal provided by the second external signal source, and the off state determines whether the Gout(n) signal provided by the second drive signal source is passed to the gate drive circuit 112.

[0044] In one embodiment, when the first external signal source provides a high level signal to the first transistor, the first transistor outputs the first drive signal provided by the first drive signal source to the gate drive circuit 112, and the second external signal source provides a low level signal to the second transistor, and the second transistor is in an off state;

[0045] When the second external signal source provides a high level signal to the second transistor, the second transistor outputs the second drive signal provided by the second drive signal source to the gate drive circuit 112, and the first external signal source provides a low level signal to the first transistor, and the first transistor is in an off state.

[0046] Specifically, Figure 4 As shown, when the VPC DC high voltage signal is connected to the gate drive circuit 112, the VPC DC high voltage signal passes through the first transistor T8-1, the Vcon1 signal sets the VGH high voltage, the second transistor T8-2 is in a normally closed state, the Gout (n-8) signal cannot be written, the first transistor T8-1 is in a normally open state, the VPC DC high voltage signal is always written, and the Q point in the gate drive circuit 112 is pre-charged.

[0047] like Figure 5As shown, when the Gout(n-8) signal is switched to access the gate drive circuit 112, the Gout(n-8) signal passes through the second transistor T8-2, then the Vcon2 signal sets the VGH high voltage, the second transistor T8-2 is in a normally open state, the Vcon1 signal sets the VGL low voltage, the first transistor T8-1 is in a normally closed state, and the VPC DC high voltage signal cannot be written. In this way, only the voltages of Vcon1 and Vcon2 need to be changed at the IC end, and the compatible design of the two driving schemes can be realized without changing the mask.

[0048] In one embodiment, the gate drive circuit 112 includes a preset point, a pull-up module 1121, a point pull-down module 1122, a level transmission pull-down module 1124 and a pull-down maintaining module 1123. The pull-up module 1121 is respectively connected to the control circuit 111, the point pull-down module 1122, the level transmission pull-down module 1124 and the pull-down maintaining module 1123 at the preset point, and the point pull-down module 1122 is also connected to the level transmission pull-down module 1124.

[0049] Specifically, Figure 6 As shown, the preset point is the Q point, the pull-up module 1121 is composed of a T1 transistor, the point pull-down module 1122 is composed of two T3 transistors, the pull-down maintenance module 1123 is composed of a T4Q transistor, a T4A transistor, a T4 transistor, a T5Qi transistor, a T5Q transistor, and a T5 transistor, and the level transfer pull-down module 1124 is composed of a T6N transistor, a T6 transistor, two T7N transistors and two T7 transistors. The connection relationship between each device is as shown in FIG. Figure 6 The pull-up module 1121 is used to pull up the Q point potential, the point pull-down module 1122 is used to pull down the Q point potential, the level transmission pull-down module 1124 is used to pull down the level transmission signal, and the pull-down maintenance module 1123 is used to maintain the pull-down voltage of the gate drive circuit 112. The Q point is pre-charged according to the drive signal provided by the control circuit 111 through each functional module in the gate drive circuit 112.

[0050] In one embodiment, the two gate driving units 110 include a first gate driving unit 1101 and a second gate driving unit 1102, the preset point in the first gate driving unit 1101 is connected to the pull-down maintaining module 1123 in the second gate driving unit 1102, the pull-down maintaining module 1123 in the first gate driving unit 1101 is connected to the preset point in the second gate driving unit 1102, and the level-transmitting pull-down module 1124 in the first gate driving unit 1101 is connected to the level-transmitting pull-down module 1124 in the second gate driving unit 1102.

[0051] Specifically, Figure 6 As shown, the Q(n) point in the first gate driving unit 1101 is connected to the gate of the T5Qi transistor in the pull-down maintaining module 1123 in the second gate driving unit 1102, and the gate of the T5Qi transistor in the pull-down maintaining module 1123 in the first gate driving unit 1101 is connected to the Q(n+1) point in the second gate driving unit 1102, and the gate of the T7N transistor in the intermediate pull-down module 1124 of the first gate driving unit 1101 is also connected to the gate of the T7N transistor in the intermediate pull-down module 1124 of the second gate driving unit 1102. This circuit connection method is used to switch the Gout(n-8) signal or the VPC DC high voltage signal to pre-charge the Q point.

[0052] In one embodiment, the connections between the various devices in the gate driving unit are distributed on two different panel layers, the two different panel layers are stacked in a vertical direction, a plurality of perforations are opened on the two different panel layers, and the functional modules distributed on different panel layers are connected through the perforations.

[0053] Specifically, the devices in the gate driving unit are the above-mentioned external signal source, driving signal source, capacitor and multiple transistors. Assuming that the connection lines between the devices in the first gate driving unit 1101 are distributed on the first panel layer and the second panel layer, the connection lines between the devices in the second gate driving unit 1102 are distributed on the third panel layer and the fourth panel layer. Figure 7 As shown, the connection between the first external signal source and the first transistor in the first gate driving unit 1101 is distributed on the first panel layer (Metal1 mask), and the connection between the first drive signal source and the first transistor in the first gate driving unit 1101 is distributed on the second panel layer (Metal2 mask). The first transistor is connected to the first external signal source and the first drive signal source through the perforations on the first panel layer and the second panel layer. The connection between the second external signal source and the second transistor in the first gate driving unit 1101, and the connection between the second drive signal source and the second transistor are both distributed on the second panel layer. Similarly, the second transistor is connected to the second external signal source and the second drive signal source through the perforations on the first panel layer and the second panel layer. The dotted lines between the various devices in the first gate driving unit 1101 indicate the connection lines distributed on the first panel layer, and the solid lines between the various devices indicate the connection lines distributed on the second panel layer.

[0054] Reference Figure 7, the first gate driving unit 1101 also includes: connections between the first transistor, the second transistor and the T1 transistor in the pull-up module 1121, respectively; connections between the T1 transistor and the point pull-down module 1122, the reset transistor, the T3N pull-down transistor, the Q(n) point, the T5Q transistor, the T5 transistor, the T7N transistor, and two T7 transistors, connections between the T1 transistor and , connections between the transistors in the pull-down maintenance module 1123, and connections between the transistors in the stage transfer pull-down module 1124. Also distributed on the first panel layer in the first gate driving unit 1101 are: the gate connection of the T1 transistor, the gate connection of the reset transistor, the gate connection of the T3N pull-down transistor, the gate connection of the T4A transistor and the T4 transistor, the connection between the T4Q transistor and the Q(n) point, the connection between the T5Qi transistor and other devices, the connection between the Q(n) point and the T6N transistor and the T6 transistor, the connection between the T3 transistor and the T7N transistor and the T7 transistor, and the connection between the first gate driving unit 1101 and the second gate driving unit 1102.

[0055] The connections distributed on the third panel layer in the second gate drive unit 1102 include: the gate connection of the first transistor T8-1, the T1 transistor, the reset transistor, the T3N pull-down transistor, the T4A transistor, the T4 transistor, the T4Q transistor, the T5Qi transistor, the T3 transistor, the T6N transistor, the T6 transistor, the T7N transistor, the T7 transistor, the T5Q transistor, and the T5 transistor. The other connections are distributed on the fourth panel layer, and each transistor is connected to the connections on different panel layers through the through holes on the third panel layer and the fourth panel layer. The dotted lines between the various devices in the second gate drive unit 1102 indicate the connections distributed on the third panel layer, and the solid lines between the various devices indicate the connections distributed on the fourth panel layer. The connections between the first gate drive unit 1101 and the second gate drive unit 1102 can be distributed on the first panel layer corresponding to the first gate drive unit 1101, or on the third panel layer corresponding to the second gate drive unit 1102.

[0056] like Figure 8 As shown, the circuit connections corresponding to each gate drive unit are distributed on two overlapping panel layers. When switching different drive signals, the Q point can be pre-charged without changing the panel layer, thereby reducing the production cost of changing the panel layer and improving the risk resistance of the gate drive circuit 112.

[0057] In one embodiment, an array substrate 210 is provided. The array substrate 210 includes the pre-charging driving circuit in each of the above embodiments and a carrier substrate for carrying the pre-charging driving circuit.

[0058] In one embodiment, a display panel is provided. Fig. 9 As shown, the display panel includes the array substrate 210 as described in the above embodiment and an opposing substrate 220 disposed opposite to the array substrate 210 .

[0059] Those skilled in the art will understand that Figure 1 or Figure 2 The structure shown in the figure is merely a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the display device to which the scheme of the present application is applied. The specific display device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0060] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, i.e., they may be located in one place or distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0061] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a display device (which can be a personal computer, a server, or a network device, etc.) to execute the pre-charge drive circuit described in each embodiment or some parts of the embodiment.

[0062] It should be understood that the terms used herein are for the purpose of describing specific example embodiments only and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "one", "an", and "said" as used herein may also be meant to include plural forms. The terms "include", "comprise", "contain", and "have" are inclusive and therefore specify the presence of the stated features, steps, operations, elements, and / or parts, but do not exclude the presence or addition of one or more other features, steps, operations, elements, parts, and / or combinations thereof. The pre-charge drive circuit steps, processes, and operations described herein are not to be construed as necessarily requiring them to be performed in the specific order described or illustrated, unless the order of execution is explicitly stated. It should also be understood that additional or alternative may be used.

[0063] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A precharge driving circuit, characterized in that: The pre-charge driving circuit includes a plurality of cascaded driving components, each of which includes two gate driving units, and the gate driving unit includes: A control circuit, used for providing a first drive signal or a second drive signal, wherein the first drive signal and the second drive signal are different drive signals; A gate drive circuit, connected to the output end of the control circuit, and configured to perform pre-charging at a preset point according to the first drive signal or the second drive signal; Different gate drive circuits in the same drive component are electrically connected; The control circuit comprises: A first control branch, used for providing a first driving signal; A second control branch, wherein the output end of the second control branch is connected to the output end of the first control branch and serves as the output end of the control circuit, the second control branch is used to provide a second drive signal, and the drive state of the first control branch is mutually exclusive with the drive state of the second control branch.

2. The precharge driving circuit according to claim 1, characterized in that: The first control branch includes a first external signal source, a first drive signal source and a first transistor, the first external signal source is connected to the gate of the first transistor, the first drive signal source is connected to the source of the first transistor, and the drain of the first transistor serves as the output end of the first control branch.

3. The precharge driving circuit according to claim 2, characterized in that: The second control branch includes a second external signal source, a second drive signal source and a second transistor, the second external signal source is connected to the gate of the second transistor, the second drive signal source is connected to the source of the second transistor, and the drain of the second transistor serves as the output end of the second control branch.

4. The precharge driving circuit according to claim 3, characterized in that: When the first external signal source provides a high level signal to the first transistor, the first transistor outputs the first drive signal provided by the first drive signal source to the gate drive circuit, and the second external signal source provides a low level signal to the second transistor, and the second transistor is in an off state; When the second external signal source provides a high level signal to the second transistor, the second transistor outputs the second drive signal provided by the second drive signal source to the gate drive circuit, and the first external signal source provides a low level signal to the first transistor, and the first transistor is in an off state.

5. The precharge driving circuit according to claim 1, characterized in that: The gate drive circuit includes a preset point, a pull-up module, a point pull-down module, a level transmission pull-down module and a pull-down maintaining module. The pull-up module is respectively connected to the control circuit, the point pull-down module, the level transmission pull-down module and the pull-down maintaining module at the preset point, and the point pull-down module is also connected to the level transmission pull-down module.

6. The precharge driving circuit according to claim 5, characterized in that: The two gate driving units include a first gate driving unit and a second gate driving unit, the preset point in the first gate driving unit is connected to the pull-down maintaining module in the second gate driving unit, the pull-down maintaining module in the first gate driving unit is connected to the preset point in the second gate driving unit, and the stage-transmitting pull-down module in the first gate driving unit is connected to the stage-transmitting pull-down module in the second gate driving unit.

7. The precharge driving circuit according to claim 6, characterized in that: The connections between the various devices in the gate driving unit are distributed on two different panel layers, the two different panel layers are stacked in a vertical direction, a plurality of through-holes are opened on the two different panel layers, and the functional modules distributed on different panel layers are connected through the through-holes.

8. An array substrate, characterized in that: The array substrate comprises a pre-charge driving circuit as claimed in any one of claims 1 to 7 and a carrier substrate for carrying the pre-charge driving circuit.

9. A display panel, characterized in that: The display panel comprises the array substrate as claimed in claim 8 and an opposing substrate disposed opposite to the array substrate.

Images