A device

Abstract

The present invention discloses a device, the device includes a variable potential multi-field plate structure, including a drain electrode, a source electrode, a gate electrode, a plurality of resistors and a plurality of field plates, the number of the resistors is equal to the number of the field plates, the plurality of field plates include a first field plate and a remaining field plate, the first field plate is connected to the gate electrode, and the remaining are the remaining field plates; the remaining field plates are connected between the source electrode and the drain electrode or between the gate electrode and the drain electrode through the resistor. The device of the present invention has a variable multi-potential that the field plate can self-gradiently match with the drain electrode potential; it solves the problem of dielectric layer breakdown reliability failure caused by high electric field and the problem of dielectric layer charge capture caused by high electric field strength.

Description

[0001] This application is a divisional application of the invention patent application with application date of January 9, 2024, application number 2024100287467, and invention name “A device containing a variable potential multi-field plate structure and its preparation method”. Technical Field

[0002] The present invention particularly relates to a device of a high electron mobility transistor (HEMT) comprising a variable multi-potential field plate. Background Art

[0003] As a third-generation semiconductor material, GaN has significant advantages over first-generation Si and second-generation GaAs. AlGaN / GaNHEMT has a large energy band gap, high peak saturated electron velocity, high-concentration two-dimensional electron gas and high electron mobility, making AlGaN / GaN HEMT widely used in RF (radio frequency), microwave, power switching power supply and other fields.

[0004] AlGaN / GaN HEMT is a planar channel field effect transistor. When a high voltage is applied to the drain electrode, a large electric field spike will be generated on the side of the gate electrode edge close to the drain electrode, which will lead to local dielectric layer degradation, causing time breakdown, and seriously affecting device reliability. In order to solve the serious electric field spike problem, the existing technology generally adopts one or more field plates placed at the gate electrode position to suppress the spike height and improve device reliability.

[0005] The electrical connections of the field plate in the industry mainly include the gate field plate connected to the gate electrode and the source field plate connected to the source electrode, and the implementation methods mainly include multi-step structures or inclined structures. Many current solutions are essentially to gradually increase the distance between the field plate and the two-dimensional electron gas, gradually reduce the capacitance, and thus gradually increase the turn-off voltage while keeping the total charge unchanged, and finally form an electric field gradient.

[0006] For example, the Chinese invention patent with announcement number CN1938859B and name "Wide Bandgap Transistor Device with Field Plate" discloses a technical solution that is the field plate structure currently commonly used in the industry. It forms field plates of multiple heights through multiple dielectric layers. The main problems are: 1. In order to form a gradient field plate, 2 to 5 steps need to be added, and the process is complicated; 2. The dielectric layer is subjected to high electric field strength, which can easily cause device reliability failure; 3. The high electric field strength can easily cause the dielectric layer to capture charges and increase the dynamic resistance; 4. Since the potential of the field plate is fixed and the drain voltage is above a certain value, the electric field strength under the field plate no longer changes. Only the electric field strength between the end of the field plate and the drain electrode increases with the increase of the drain voltage, which limits the high voltage resistance range.

[0007] Another example is the Chinese invention patent with announcement number CN104332498B, titled A Slanted Field Plate Power Device and a Method for Preparing a Slanted Field Plate Power Device. The field plate formation method is changed by tilting the field plate. The electric field distribution is optimized to solve the complex problem of the multi-field plate preparation process. The main problems are: 1. The dielectric layer is subjected to high electric field strength, which easily causes device reliability failure; 2. The electric field strength causes the dielectric layer to capture charge and thus increase the dynamic resistance; 3. The formation of a slow tilt angle is difficult to achieve and has poor repeatability; 4. Since the potential of the field plate is fixed and the drain voltage is above a certain value, the electric field strength under the field plate no longer changes. Only the electric field strength between the end of the field plate and the drain electrode increases with the increase of the drain voltage, which limits the high voltage resistance range.

[0008] It can be seen that the planar channel structure of the existing AlGaN / GaN HEMT and the introduction of multiple field plates have caused many problems: in order for the device to withstand high voltage, multiple field plates are required to suppress voltage spikes. The field plates currently used in the industry include gate field plates and source field plates, but because the field plate potential is equal to the gate potential or equal to the source potential, it will form a large potential difference with the two-dimensional electron gas below the field plate, and most of the reasons for device failure are here, mainly because the dielectric layer is subjected to high electric field strength, which can easily cause device reliability failure; at the same time, high electric field strength causes the dielectric layer to capture charge and thus increase dynamic resistance; in addition, the fixed field plate potential makes the electric field strength under the field plate no longer change when the drain voltage is above a certain value, and only the electric field strength between the end of the field plate and the drain electrode increases with the increase of the drain voltage, which limits the high voltage resistance range. Therefore, a better implementation of the field plate is a key issue that AlGaN / GaN HEMT urgently needs to solve. Summary of the invention

[0009] In view of this, in order to overcome the defects of the prior art, an object of the present invention is to provide an improved device structure, which forms a field plate structure with variable multi-potential by setting a resistor.

[0010] In order to achieve the above object, the present invention adopts the following technical solutions:

[0011] A device with a variable potential multi-field plate structure, comprising a drain electrode, a source electrode, a gate electrode, a plurality of resistors, a plurality of field plates, and a substrate, a stacked structure, and a dielectric layer arranged in sequence from bottom to top, wherein the drain electrode and the source electrode are located in the stacked structure and the dielectric layer, and the gate electrode is located in the dielectric layer. The number of the resistors is equal to the number of the field plates, and the adjacent resistors are connected in series through the resistor electrodes; the plurality of field plates comprises a first field plate and a remaining field plate, and the first field plate is connected to the gate electrode; each of the remaining field plates and the drain electrode is respectively connected to a resistor electrode, and the remaining resistor electrode is connected to the source electrode or the gate electrode. That is, the important structural feature of the present invention is that a plurality of remaining field plates are connected between the gate electrode and the drain electrode or between the source electrode and the drain electrode through a series resistor and a resistor electrode, so that the plurality of field plates automatically match the gradually changing voltage according to the resistance value.

[0012] According to some preferred implementation aspects of the present invention, the plurality of field plates are located at the same layer height. Preferably, the plurality of field plates are all located above the dielectric layer.

[0013] According to some preferred embodiments of the present invention, the stacked structure includes a nucleation layer, a buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top, and the resistor electrode, the drain electrode and the source electrode are located in the barrier layer and the dielectric layer.

[0014] The resistor is prepared by the following method: the barrier layer is patterned and ion material is injected to form an electrically isolated region, a conductive region for forming the resistor is reserved outside the electrically isolated region, and the electrically isolated region is located between adjacent resistors and between the resistor and an unconnected electrode.

[0015] According to some preferred implementation aspects of the present invention, each conductive region corresponding to the resistor has a width of 50 to 2000 nm and a length of 1 to 1e6 um; and a resistance value of each resistor is 1e2 to 5e8 Ω.

[0016] According to some preferred implementation aspects of the present invention, the number of the field plates is 3-11, the number of the resistors is 3-11, and the number of the resistor electrodes is 4-12. In some embodiments, the number of the field plates is 3-4, the number of the resistors is 3-4, and the number of the resistor electrodes is 4-5.

[0017] According to some preferred implementation aspects of the present invention, there are two remaining field plates, including a second field plate and a third field plate, there are four resistance electrodes, the gate electrode or the first field plate, the second field plate, the third field plate, and the drain electrode are respectively connected to a resistance electrode, and resistors are arranged between adjacent resistance electrodes.

[0018] According to some preferred implementation aspects of the present invention, there are two remaining field plates, including a second field plate and a third field plate, there are four resistance electrodes, the source electrode, the second field plate, the third field plate, and the drain electrode are respectively connected to a resistance electrode, and resistors are arranged between adjacent resistance electrodes.

[0019] According to some preferred implementation aspects of the present invention, there are three remaining field plates, including a second field plate, a third field plate and a fourth field plate, there are five resistance electrodes, the gate electrode, the second field plate, the third field plate, the fourth field plate and the drain electrode are respectively connected to a resistance electrode, and resistors are arranged between adjacent resistance electrodes.

[0020] According to some preferred implementation aspects of the present invention, the resistor is an external resistor arranged outside the device, and the gate electrode or source electrode, the remaining field plate, and the drain electrode are respectively connected to resistor electrodes of different potentials of the external resistor connected in series.

[0021] That is, the resistor in the present invention can be formed by injecting ion materials and retaining the corresponding conductive area, or it can be formed in the form of an external resistor. It is only necessary to ensure that each remaining field plate and drain electrode are respectively connected to a resistor, and the source electrode or gate electrode is connected to a resistor, so as to realize variable multi-potential with self-gradient matching.

[0022] The present invention also provides a method for preparing the above-mentioned device, characterized in that it comprises the following steps:

[0023] Performing epitaxial growth of nitride on the substrate to sequentially form a nucleation layer, a buffer layer, a channel layer and a barrier layer, wherein the nucleation layer, the buffer layer, the channel layer and the barrier layer constitute the stacked structure;

[0024] Performing a patterning process on the barrier layer and injecting ion materials to form an electrically isolated region, and retaining a conductive region for forming the resistor outside the electrically isolated region;

[0025] On the barrier layer, etching to form a source electrode hole, a drain electrode hole and a plurality of resistor electrode holes;

[0026] Filling metal in the source electrode hole and the drain electrode hole to form the source electrode and the drain electrode respectively, and performing annealing to form ohmic contacts; and filling the resistor electrode hole to form a plurality of resistor electrodes;

[0027] Depositing a dielectric layer on the barrier layer and etching a gate electrode hole;

[0028] Filling the dielectric layer with metal and etching away excess metal to form a gate electrode and a plurality of field plates; and obtaining the device.

[0029] The principle of the present invention is as follows: the present invention adopts multiple discrete metal field plates, including a first field plate connected to a gate electrode and multiple remaining field plates, and simultaneously introduces resistors having the same number as the field plates, adjacent resistors are connected in series through resistor electrodes, and each remaining field plate and the drain electrode are respectively connected to a resistor electrode, and the remaining resistor electrode is connected to a source electrode or a gate electrode.

[0030] Assume that the D-MODE GaN HEMT device is turned off when the gate is at a negative voltage V0, and assume that multiple field plates are all on the same dielectric layer. When the gate terminal is turned off by supplying a negative voltage Vg1 (less than V0), the source terminal is 0V, and the drain terminal is applied with a high voltage Vd. Since multiple remaining field plates are connected between the gate electrode and the drain electrode (or between the source electrode and the drain electrode) through a series resistor, the multiple field plates will automatically match the gradient voltage according to the resistance value. This voltage is between Vg1 (or 0V) and Vd. At this time, the gate electrode (the first field plate and the gate electrode have the same potential), the second field plate, the third field plate, and more field plates and drain electrodes that may be included form a relatively uniformly increasing potential gradient. Since the gate is turned off at this time, that is, the potential under the gate is 0V, the two-dimensional electron gas under the gate is depleted. At this time, the potential under the first field plate needs to increase. Since the distance between the first field plate and the two-dimensional electron gas is larger than the distance between the gate electrode and the two-dimensional electron gas, that is, the capacitance formed by the first field plate and the two-dimensional electron gas below is smaller, the same amount of charge as the gate capacitance requires a higher voltage to be depleted. This voltage increase is positively correlated with the thickness of the dielectric layer. Finally, the potential under the first field plate stabilizes at a voltage value V1 higher than 0V.

[0031] Furthermore, the potential under the second field plate increases, and the capacitor formed by the second field plate and the two-dimensional electron gas below is the same as the first field plate in height. The potential difference between the upper and lower electrodes when the charge is exhausted is consistent and equal to V1, but the second field plate itself is divided into voltages due to resistance, and the two-dimensional electron gas below it is exhausted and the voltage is equal to the second field plate potential + V1. Similarly, the potential under the third field plate is stabilized at the third field plate potential + V1. If more field plates are designed, there will be more gradient potentials under the field plates, thus achieving uniform distribution of the electric field.

[0032] In addition, when the drain voltage Vd increases or decreases, the potentials of the second field plate, the third field plate and possibly more field plates will also increase or decrease accordingly, further causing the electric field distribution under the field plate to be evenly adjusted, thereby better matching the high voltage and improving the voltage resistance of the device.

[0033] When the gate terminal is actively supplied with voltage Vg2 (greater than V0, often 0V in practical applications), the gate is turned on, and the two-dimensional electron gas under the gate resumes conduction. At this time, the potential under the first field plate is pulled down, and the two-dimensional electron gas under the first field plate resumes conduction. Similarly, the two-dimensional electron gas under the second field plate and the third field plate resumes conduction, and the entire device is turned on. At this time, the drain electrode voltage Vd is pulled down to Vd1=Ids*Rds_on, which is usually a very low value. While Vd1 is pulled down, due to the second field plate, the third field plate and possibly more field plates, the voltage division will also change, and its voltage is between Vg1 (or 0V) and Vd1, and all become extremely low voltages. At this time, the entire device has no high-voltage part and is safely turned on at low voltage. Through the above design and principle, the present invention enables the device to achieve switch conversion and realize variable multi-potential with self-gradient matching.

[0034] Due to the adoption of the above technical scheme, compared with the prior art, the advantages of the present invention are as follows: the device of the present invention containing a variable potential multi-field plate structure has a variable multi-potential that the field plate can self-gradiently match the drain electrode potential; the multi-potential field plate can greatly simplify the process while also achieving a far greater number of field plates than the traditional structure, further improving the electric field distribution and enhancing the device's voltage resistance; effectively controlling the potential difference between the field plate and the two-dimensional electron gas below, solving the problem of dielectric layer breakdown reliability failure caused by high electric fields and the problem of dielectric layer charge capture caused by high electric field strength, thereby reducing dynamic resistance; in addition, the electric field distribution is automatically matched with the leakage voltage, so that the device can withstand higher voltages. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 It is a cross-sectional schematic diagram after a stacked structure is formed in a method for preparing a device in a preferred embodiment of the present invention;

[0037] Figure 2 It is a cross-sectional schematic diagram of the device during the injection process in the method for preparing the device in the preferred embodiment of the present invention;

[0038] Figure 3 It is a cross-sectional schematic diagram after forming electrode holes in the method for preparing a device in a preferred embodiment of the present invention;

[0039] Figure 4 It is a cross-sectional schematic diagram after forming electrodes in the method for preparing a device in a preferred embodiment of the present invention;

[0040] Figure 5It is a cross-sectional schematic diagram after forming a dielectric layer in the method for preparing a device in a preferred embodiment of the present invention;

[0041] Figure 6 It is a cross-sectional schematic diagram after a gate electrode hole is formed in a method for preparing a device in a preferred embodiment of the present invention;

[0042] Figure 7 It is a cross-sectional schematic diagram after forming a gate electrode and a field plate in a method for preparing a device in a preferred embodiment of the present invention;

[0043] Figure 8 It is a schematic diagram of the top view of the device in the preferred embodiment 1 of the present invention;

[0044] Fig. 9 It is a schematic diagram of the top view of the device in the second preferred embodiment of the present invention;

[0045] Fig.10 Schematic diagram of the top view of the device in the third preferred embodiment of the present invention;

[0046] Fig.11 Schematic diagram of the top view of the device in the fourth preferred embodiment of the present invention;

[0047] In the accompanying drawings, 1, substrate; 2, stacked structure; 20, nucleation layer; 21, buffer layer; 22, channel layer; 23, barrier layer; 231, photoresist; 232, drain electrode hole; 233, source electrode hole; 234, resistor electrode hole; 3, drain electrode; 4, source electrode; 5, resistor; 51, resistor electrode; 6, dielectric layer; 61, gate electrode hole; 7, gate electrode; 71, first field plate; 72, second field plate; 73, third field plate; 74, fourth field plate; 8, external resistor; 9, package bonding. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the technical solution of the present invention, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] The device of the present invention containing a variable potential multi-field plate structure comprises a drain electrode 3, a source electrode 4, a gate electrode 7, a plurality of resistors 5, a plurality of field plates, and a substrate 1, a stacked structure 2, and a dielectric layer 6 arranged in sequence from bottom to top, wherein the stacked structure 2 comprises a nucleation layer 20, a buffer layer 21, a channel layer 22, and a barrier layer 23 arranged in sequence from bottom to top, a resistor electrode 51, a drain electrode 3, and a source electrode 4 are located in the barrier layer 23 and the dielectric layer 6, and a gate electrode 7 is located in the dielectric layer 6. The plurality of field plates are all located above the dielectric layer 6, and preferably, the plurality of field plates are located at the same layer height. The plurality of field plates comprises a first field plate 71 and a remaining field plate, wherein the first field plate 71 is connected to the gate electrode 7, and the remaining field plate is not connected to the gate electrode 7, and the remaining field plate is connected between the source electrode 4 and the drain electrode 3 or between the gate electrode 7 and the drain electrode 3 through the resistor 5 and the resistor electrode 51.

[0050] Each resistor 5 has a width of 50 to 2000 nm, a length of 1 to 1e6 um, and a resistance of 1e2 to 5e8 Ω. The number of resistors 5 is equal to the number of field plates, the number of field plates is 3 to 11, the number of resistors 5 is 3 to 11, and the number of resistor electrodes 51 is 4 to 12. Preferably, the number of field plates is 3 to 4, the number of resistors 5 is 3 to 4, and the number of resistor electrodes 51 is 4 to 5.

[0051] Adjacent resistors 5 are connected in series through resistor electrodes 51, and each remaining field plate (i.e., field plates other than the first field plate 71) and drain electrode 3 are respectively connected to a resistor electrode 51, and the remaining resistor electrode 51 is connected to the source electrode 4 or the gate electrode 7. That is, the device of the present invention uses a plurality of remaining field plates between the gate electrode 7 and the drain electrode 3 or between the source electrode 4 and the drain electrode 3 to connect through the series resistors 5 and the resistor electrodes 51, so that the plurality of field plates automatically match the gradually changing voltage according to the resistance value.

[0052] Embodiment 1 Device structure

[0053] like Figure 7 and Figure 8 As shown, the device with variable potential multi-field plate structure in this embodiment includes a drain electrode 3, a source electrode 4, a gate electrode 7, a plurality of resistors 5, a plurality of field plates, and a substrate 1, a stacked structure 2 and a dielectric layer 6 arranged in sequence from bottom to top. The stacked structure 2 includes a nucleation layer 20, a buffer layer 21, a channel layer 22 and a barrier layer 23 arranged in sequence from bottom to top. The resistor electrode 51, the drain electrode 3, and the source electrode 4 are located in the barrier layer 23 and the dielectric layer 6, and the gate electrode 7 is located in the dielectric layer 6. The plurality of field plates are located at the same layer height and are all located above the dielectric layer 6. The number of resistors 5 is equal to the number of field plates, and adjacent resistors 5 are connected in series through resistor electrodes 51.

[0054] In this embodiment, there are three field plates, three resistors 5 and four resistor electrodes 51, and the three resistors 5 are connected in series through the four resistor electrodes 51. The three field plates include a first field plate 71, a second field plate 72 and a third field plate 73, and the first field plate 71 is connected to the gate electrode 7. In this embodiment, the gate electrode 7 or the first field plate 71, the second field plate 72, the third field plate 73 and the drain are respectively connected with a resistor electrode 51, that is, a resistor 5 is connected between the gate electrode 7 and the second field plate 72, between the second field plate 72 and the third field plate 73, and between the third field plate 73 and the drain electrode 3, so as to realize automatic adjustment of the field plate bias through the preset resistor 5 and the voltage actually applied to the gate electrode and the drain electrode.

[0055] Embodiment 2 Device structure

[0056] like Figure 7 and Fig. 9 As shown, the device with variable potential multi-field plate structure in this embodiment is different from that in embodiment 1 in that: the source electrode 4 in this embodiment is connected with a resistor electrode 51, while the first field plate 71 or the gate electrode 7 is not connected with the resistor electrode 51. That is, a resistor 5 is connected between the source electrode 4 and the second field plate 72, between the second field plate 72 and the third field plate 73, and between the third field plate 73 and the drain electrode 3 in this embodiment, so as to realize automatic adjustment of the field plate bias through the preset resistor 5 and the voltage actually applied to the source electrode and the drain electrode.

[0057] Embodiment 3 Device structure

[0058] like Figure 7 and Fig.10 As shown, the device with variable potential multi-field plate structure in this embodiment is different from that in embodiment 1 in that: one field plate is added in this embodiment, that is, four field plates, four resistors 5 and five resistor electrodes 51 are contained in this embodiment, and the four resistors 5 are connected in series through five resistor electrodes 51. The four field plates include a first field plate 71, a second field plate 72, a third field plate 73 and a fourth field plate 74, and the first field plate 71 is connected to the gate electrode 7. In this embodiment, the gate electrode 7 or the first field plate 71, the second field plate 72, the third field plate 73, the fourth field plate 74 and the drain electrode 3 are respectively connected with a resistor electrode 51, that is, a resistor 5 is connected between the gate electrode 7 and the second field plate 72, between the second field plate 72 and the third field plate 73, between the third field plate 73 and the fourth field plate 74, and between the fourth field plate 74 and the drain electrode 3, so as to realize automatic allocation of the field plate bias through the preset resistor 5 and the voltage actually applied at the drain electrode end. And the gate electrode 7 and the four field plates make the distribution of the electric field more uniform, and the device reliability is higher.

[0059] Embodiment 4 Device structure

[0060] like Figure 7 and11 As shown, the device with variable potential multi-field plate structure in this embodiment is different from that in Embodiment 1 in that: in this embodiment, the resistor 5 is not formed on the chip by two-dimensional electron gas, but three external resistors 8 are connected by package bonding wires 9. The gate electrode 7 or the first field plate 71, the second field plate 72, the third field plate 73, and the drain electrode 3 are respectively connected to four different potential ends of the three series-connected external resistors 8, so as to realize automatic adjustment of the field plate bias through the preset external resistor 8 and the voltage actually applied by the gate electrode and the drain electrode.

[0061] Example 5 Preparation method

[0062] This embodiment provides a method for preparing the device structure in the above embodiment 1, which specifically includes the following steps:

[0063] Step 1: Forming a laminated structure 2

[0064] like Figure 1 As shown, nitride epitaxial growth is performed on a substrate 1 to sequentially form a nucleation layer 20, a buffer layer 21, a channel layer 22 and a barrier layer 23, and the materials include group III nitride materials such as GaN, AlGaN, AlN, AlGaNInN, etc. The nucleation layer 20, the buffer layer 21, the channel layer 22 and the barrier layer 23 constitute a stacked structure 2, thereby forming a complete semiconductor epitaxial layer structure, and can form a high-concentration two-dimensional electron gas at the heterojunction interface between the channel layer 22 and the barrier layer 23 to generate a conductive channel.

[0065] The substrate 1 is one or more combinations selected from silicon, gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, gallium arsenide, silicon carbide, diamond, sapphire, germanium or any other material capable of growing group III nitride materials.

[0066] Step 2: Forming the resistor 5 structure

[0067] like Figure 2 As shown, on the epitaxial barrier layer 23, glue coating, graphic exposure, development treatment, and injection are performed, and the injected materials include N, O, He plasma. The location where the photoresist 231 is present will not damage the epitaxial layer structure because the ions cannot penetrate the photoresist 231. In the area where the photoresist 231 is developed, high-energy ions will penetrate and embed into the epitaxial layer structure, disrupting the arrangement of atoms on the lattice of the material to form a high-resistance area, and finally forming a graphic electrically isolated area on the chip surface. In other embodiments, there is also a table isolation method to achieve isolation, that is, the conductive path is blocked by a method of forming an isolation groove by table etching. The electrically isolated area is located between adjacent resistors and between resistors and unconnected electrodes.

[0068] Isolation is formed by injecting and destroying the structure of the two-dimensional electron gas, forming the active area (conductive area) and the passive area (isolation area) patterns. The main structure of the device is processed in the active area, and the passive area is surrounded by the edge of the device to form electrical isolation.

[0069] In this embodiment, 3 to 11 mutually independent elongated active regions (conductive regions) are retained at the same time, with a width of 50 to 2000 nm and a length of 1 to 1e6 um, and the size of the active region of the corresponding resistor is designed according to the required resistance value, thereby forming the resistor 5 structure at 3 to 11 positions, and the resistance value of each resistor 5 is 1e2 to 5e8 Ω. Then, the photoresist 231 is removed.

[0070] Step 3: Forming electrodes

[0071] On the epitaxial barrier layer 23, pattern etching is performed to form a source electrode hole 233, a drain electrode hole 232 and a plurality of resistor electrode holes 234, such as Figure 3 As shown. The source electrode hole 233, the drain electrode hole 232, and the resistor electrode hole 234 are filled with metal, the metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu, and the filling method includes injection, sputtering, etc., and annealing is performed to form ohmic contacts, respectively forming the source electrode 4, the drain electrode 3, and the resistor electrode 51, as shown. Figure 4 shown.

[0072] Step 4: Forming dielectric layer 6 and field plate

[0073] Deposition is performed on the barrier layer 23 to form a dielectric layer 6 including one or more combinations of SiN, SiO2, SiON, and Al2O3. Figure 5 As shown, a gate electrode hole 61 is etched, as shown Figure 6 As shown. Metal is filled on the dielectric layer 6, and the metal includes one or more combinations of Ti, Al, TiN, Au, AlCu, and AlSiCu, and the filling method includes injection, sputtering, etc. And the excess metal is etched away by patterning to form a gate electrode 7 and multiple field plates to obtain a device structure, such as Figure 7 shown.

[0074] Among them, the gate electrode 7 or the first field plate 71, the second field plate 72, the third field plate 73, and the drain electrode 3 are respectively connected to the four resistor electrodes 51, so as to realize automatic adjustment of the field plate bias through the preset resistor 5 and the voltage actually applied to the gate and drain terminals.

[0075] The device containing a multi-potential field plate structure of the present invention adopts multiple remaining field plates between the gate electrode and the drain electrode or between the source electrode and the drain electrode through a series resistor and a resistor electrode to realize that multiple field plates automatically match the gradually changing voltage according to the resistance value. The field plate is an adaptive multi-potential structure, thereby solving the problem of high electric field strength between the field plate and the two-dimensional electron gas below, and the process of forming the field plate is simpler. The device structure of the present invention forms an electric field gradient field plate on the same layer, which reduces 2 to 5 steps compared with the traditional field plate process, simplifies the process, and can also achieve a far greater number of field plates than the traditional structure, further improve the electric field distribution and enhance the device's withstand voltage; make the field plates at each location and the two-dimensional electron gas below bear a lower electric field strength, improve the device reliability; make the field plates at each location and the two-dimensional electron gas below bear a lower electric field strength, improve the phenomenon of charge capture in the dielectric layer, and reduce the dynamic resistance; in addition, the electric field distribution is automatically matched with the leakage voltage, so that the device can withstand a higher voltage.

[0076] The above embodiments prepared by the method of the present invention are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit and essence of the present invention should be included in the protection scope of the present invention.

Claims

1. A device of a high electron mobility transistor, characterized in that: The device contains a variable potential multi-field plate structure, including a drain electrode, a source electrode, a gate electrode, multiple resistors and multiple field plates, the number of the resistors is equal to the number of the field plates, the multiple field plates include a first field plate and remaining field plates, the first field plate is connected to the gate electrode, and the rest are the remaining field plates; the remaining field plates are connected between the source electrode and the drain electrode or between the gate electrode and the drain electrode through the resistor; the resistor is formed by retaining the corresponding conductive area after injecting ion materials.

2. The device according to claim 1, characterized in that Each of the remaining field plates and the drain electrode is connected to a resistor respectively, and the source electrode or the gate electrode is connected to a resistor.

3. The device according to claim 1, characterized in that The implanted ion materials include N, O, and He ions.

4. The device according to claim 1, characterized in that The conductive region of each resistor has a width of 50 to 2000 nm and a length of 1 to 1e6 um; the resistance of each resistor is 1e2 to 5e8 Ω.

5. The device according to claim 1, characterized in that The device comprises a stacked structure, which comprises a nucleation layer, a buffer layer, a channel layer and a barrier layer arranged in sequence from bottom to top.

6. The device according to claim 5, characterized in that The resistor is prepared by the following method: a patterning process is performed on the barrier layer, and ion materials are injected to form an electrically isolated region, a conductive region for forming the resistor is reserved outside the electrically isolated region, and the electrically isolated region is located between adjacent resistors and between a resistor and an unconnected electrode.

7. The device according to claim 1 or 2, characterized in that The adjacent resistors are connected in series through resistor electrodes; each of the remaining field plates and the drain electrode is connected to a resistor electrode respectively, and the remaining resistor electrode is connected to the source electrode or the gate electrode.

8. The device according to claim 1, characterized in that The plurality of field plates are located at the same level.

9. The device according to claim 5, characterized in that The device comprises a substrate and a dielectric layer. The substrate, the stacked structure and the dielectric layer are arranged in sequence from bottom to top, and a plurality of field plates are all located above the dielectric layer.

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