Demultiplexing circuit, demultiplexing circuit structure and manufacturing method, and display panel

Abstract

The present application relates to a demultiplexing circuit, a demultiplexing circuit structure, a manufacturing method, and a display panel. The demultiplexing circuit includes: a data bus; N groups of data lines; a switch unit; N groups of signal lines, each group of signal lines includes 3 pairs of signal lines, and each pair of signal lines includes a main signal line and an auxiliary signal line; each switch unit includes two thin film transistors, which are a P-type thin film transistor and an N-type thin film transistor; the gate of one thin film transistor is connected to the main signal line of one group of signal lines, and the gate of the other thin film transistor is connected to the auxiliary signal line of the group of signal lines; the source electrodes of the two thin film transistors are electrically connected to the data bus; the drain electrodes of the two thin film transistors are connected to the corresponding one of the data lines; an inverter is provided between the main signal line and the auxiliary signal line of each group of signal lines. The demultiplexing circuit of the present application adopts a stacked CMOS structure, which has relatively lower power efficiency and can have a narrower border.

Description

Technical Field

[0001] The present application belongs to the technical field of display panels, and more specifically, relates to a demultiplexing circuit, a demultiplexing circuit structure and a manufacturing method, and a display panel. Background Art

[0002] As mobile games become more and more popular, users have higher and higher requirements for mobile phone screens; 1. The effective display ratio of mobile phone screens is required to be higher and higher; 2. The refresh rate of mobile phone screens is high. Currently, high-end mobile phones basically use 120HZ as the refresh rate. Due to the high frequency, the screen power consumption is always high; in order to reduce power consumption, the display screens of electronic products on the market generally use low-temperature polycrystalline oxide (LTPO) display panels.

[0003] Secondly, the LTPO display panel includes an effective display area (AA area) and a border, such as Figure 1 As shown; the frame includes the IC, fanout wiring (fanout) and demultiplexing circuit (demux circuit). Currently, the demux circuit is used to decompose a signal channel into multiple signal channels; as shown Figure 2 As shown, a data signal is transformed into three data signal lines through the demux circuit and input into the panel, which directly reduces the number of data lines in the fanout to 1 / 3. However, since the data signal lines in the AA area need to be charged and discharged, the TFTs in the demux circuit will be larger, which will increase power consumption and the area of ​​the demux circuit, which is not conducive to the design of narrow bezels. Summary of the invention

[0004] An object of an embodiment of the present application is to provide a demultiplexing circuit structure, which can effectively reduce power consumption.

[0005] To achieve the above purpose, the technical solution adopted by the present application is: to provide a demultiplexing circuit structure, including:

[0006] A demultiplexing circuit, comprising:

[0007] Data bus;

[0008] N groups of data lines, each group of data lines includes 3 data lines;

[0009] A switch unit is provided corresponding to each data line of each group of data lines;

[0010] N groups of signal lines, each group of signal lines includes 3 pairs of signal lines, and each pair of signal lines includes a main signal line and a sub-signal line;

[0011] Each switch unit includes two thin film transistors, namely a P-type thin film transistor and an N-type thin film transistor;

[0012] The gate of one of the thin film transistors is connected to a main signal line of one group of signal lines, and the gate of the other thin film transistor is connected to a secondary signal line of the group of signal lines; the source electrodes of the two thin film transistors are electrically connected to the data bus; the drain electrodes of the two thin film transistors are connected to a corresponding one of the data lines;

[0013] An inverter is provided between the main signal line and the auxiliary signal line of each pair of signal lines. Wherein, N is a natural number.

[0014] Preferably, the inverter includes two thin film transistors, namely a P-type thin film transistor and an N-type thin film transistor; the gates of the two thin film transistors are electrically connected to the main signal line; the source of the N-type thin film transistor is electrically connected to the gate-on power supply, the source of the P-type thin film transistor is electrically connected to the gate-off power supply, and the drains of the two thin film transistors are connected to the auxiliary signal line.

[0015] It includes: a dual thin film transistor (TFT) structure, the dual thin film transistor structure includes:

[0016] A P-type substrate, a first insulating layer, a first gate, a second insulating layer, a semiconductor layer, a source-drain layer, a third insulating layer, and a second gate are stacked in sequence; the P-type substrate is low-temperature polycrystalline silicon (LTPS), and the semiconductor layer is indium gallium zinc oxide (IGZO);

[0017] The source-drain layer includes a first source, a second source, a first drain and a second drain; the first source and the second source are located on one side of the semiconductor layer, and the first drain and the second drain are located on the other side of the semiconductor layer; the first drain is electrically connected to the second drain, and the second drain is connected to one end of the P-type substrate;

[0018] When the first source is electrically connected to one end of the semiconductor layer, the first source and the second source are both arranged on the second insulating layer, the second source is spaced apart from the first source and the IGZO semiconductor layer, and is connected to the other end of the P-type substrate; the first drain is electrically connected to the other end of the semiconductor layer; the dual TFT structure constitutes an inverter;

[0019] When the first source electrode is electrically connected to the second source electrode, the first source electrode is electrically connected to one end of the semiconductor layer; the second source electrode is connected to the P-type substrate; and the dual TFT structure constitutes a switch unit.

[0020] Preferably, the first drain and the second drain are integrated into a total drain.

[0021] The first source and the second source are connected to the gate-on power supply and the gate-off power supply respectively through wires; the total drain is connected to the auxiliary signal line for outputting the current signal externally; the first gate and the second gate are connected to the main signal line of the input signal through wires.

[0022] Furthermore, the second insulating layer and the first insulating layer are provided with a first via hole and a second via hole at both ends respectively, the main drain is electrically connected to the P-type substrate through the first via hole, and the second gate is electrically connected to the P-type substrate through the second via hole.

[0023] As a variation of the above structure, the total drain, the first source, and the second source are all arranged above the first insulating layer and covered by the second insulating layer. The first insulating layer is provided with a third via and a fourth via at both ends, and the total drain is electrically connected to the P-type substrate through the third via, and the second gate is electrically connected to the P-type substrate through the fourth via. The second insulating layer is also provided with a fifth via and a sixth via at both ends, and the two ends of the IGZO semiconductor layer are electrically connected to the total drain through the fifth via, and the sixth via is electrically connected to the first source and the second source.

[0024] A method for manufacturing a demultiplexing circuit structure comprises the following steps:

[0025] Providing a P-type substrate; the P-type substrate is low temperature polycrystalline silicon (ITPS);

[0026] forming a first insulating layer on a P-type substrate;

[0027] forming a first gate on the first insulating layer;

[0028] forming a second insulating layer on the first gate and the first insulating layer;

[0029] forming a source-drain layer on both sides of the first insulating layer or the second insulating layer;

[0030] forming a semiconductor layer on the middle portion of the second insulating layer; the semiconductor layer is indium gallium zinc oxide (IGZO);

[0031] forming a third insulating layer on the source / drain electrode layer and the semiconductor layer;

[0032] A second gate is formed on the third insulating layer.

[0033] Among them, when the source-drain layer is formed on both sides of the second insulating layer, the source-drain layer includes: a first source, a second source, a first drain, and a second drain; the first source and the second source are spaced apart and electrically connected to one end of the semiconductor layer respectively; the first drain and the second drain are electrically connected or integrated into one, and the first drain is electrically connected to the other end of the semiconductor layer; the second source is electrically connected to one end of the P-type substrate, and the second drain is electrically connected to the other end of the P-type substrate.

[0034] Secondly, before forming the source and drain layers on both sides of the second insulating layer, the demultiplexing circuit structure manufacturing method further includes:

[0035] Forming a first via hole and a second via hole on both sides of the first insulating layer and the second insulating layer respectively;

[0036] The second drain is electrically connected to the other end of the P-type substrate through the first via hole; the second source is electrically connected to one end of the P-type substrate through the second via hole.

[0037] When the source-drain layer is formed on both sides of the first insulating layer, the source-drain layer includes: a first source, a second source, a first drain, and a second drain; the first source and the second source are spaced apart and electrically connected to one end of the semiconductor layer respectively; the first drain and the second drain are electrically connected or integrated into one, and the first drain is electrically connected to the other end of the semiconductor layer; the second source is electrically connected to one end of the P-type substrate, and the second drain is electrically connected to the other end of the P-type substrate.

[0038] Before forming the source and drain layers on both sides of the first insulating layer, the method for manufacturing the demultiplexing circuit structure further includes:

[0039] Forming a third via hole and a fourth via hole on both sides of the first insulating layer respectively;

[0040] The second drain is electrically connected to the other end of the P-type substrate through the first via hole; the second source is electrically connected to one end of the P-type substrate through the second via hole.

[0041] Forming a fifth via hole and a sixth via hole on both sides of the second insulating layer respectively;

[0042] Two ends of the semiconductor layer are electrically connected to the first drain and the first source through a fifth via hole and a sixth via hole, respectively.

[0043] A display panel comprises the above-mentioned demultiplexing circuit structure.

[0044] The beneficial effect of the present application is that the demultiplexing circuit of the present application adopts a stacked CMOS structure, which has relatively lower power efficiency and a narrower frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0046] Figure 1 A schematic diagram of a display screen in the prior art Figure 1 ;

[0047] Figure 2 A schematic diagram of a demultiplexing circuit in the prior art Figure 2 ;

[0048] Figure 3 A schematic diagram of a demultiplexing circuit for the present application;

[0049] Figure 4 A circuit diagram of the inverter of the present application;

[0050] Figure 5 A circuit diagram of the switch unit of this application Figure 2 ;

[0051] Figure 6 A cross-sectional schematic diagram of an inverter structure in a demultiplexing circuit structure of the present application;

[0052] Figure 7 A cross-sectional schematic diagram of a switch unit structure in a demultiplexing circuit structure of the present application;

[0053] Figure 8 Another cross-sectional schematic diagram of the inverter structure in the demultiplexing circuit structure of the present application;

[0054] Fig. 9 Another cross-sectional schematic diagram of the switch unit structure in the demultiplexing circuit structure of the present application;

[0055] Fig.10 A schematic diagram of a display driving circuit in a display panel of the present application.

[0056] Among them, the reference numerals in the figure are:

[0057] 1. P-type substrate; 2. first insulating layer; 3. first gate; 4. second insulating layer; 5. second drain; 6. first drain; 7. second gate; 8. first via; 9. first source; 10. second source; 11. IGZO semiconductor layer; 12. third insulating layer; 13. second via; 14. third via; 15. fifth via; 16. sixth via; 17. fourth via; 18. total source. DETAILED DESCRIPTION

[0058] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0059] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0060] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0062] Please also read Figure 3 and Figure 5 , the demultiplexing circuit provided by the embodiment of the present application is now described. Embodiment 1: A demultiplexing circuit, comprising:

[0063] Data bus Data;

[0064] N groups of data lines, each group of data lines includes 3 data lines; each group of data lines is a Data_1 data line, a Data_2 data line and a Data_3 data line;

[0065] A switch unit is provided corresponding to each data line of each group of data lines. In this embodiment, there are three switch units connected between the data bus and the three data lines, namely, the first, second and third switch units;

[0066] N groups of signal lines, each group of signal lines includes 3 pairs of signal lines, and each pair of signal lines includes a main signal line and a sub-signal line;

[0067] The main signal lines in each group of signal lines are: demux_R; demux_G; demux_B; the secondary signal lines are: demux_(R); demux_(G); demux_(B).

[0068] Each switch unit includes two thin film transistors, namely a P-type thin film transistor and an N-type thin film transistor; see Figure 4 , Figure 5 .

[0069] The gate of one of the thin film transistors is connected to a main signal line of one group of signal lines, and the gate of the other thin film transistor is connected to a secondary signal line of the group of signal lines; the source electrodes of the two thin film transistors are electrically connected to the data bus; the drain electrodes of the two thin film transistors are connected to a corresponding one of the data lines;

[0070] An inverter is provided between the main signal line and the auxiliary signal line of each pair of signal lines. When there is a signal, the current signal phases of the main signal line and the auxiliary signal line are opposite.

[0071] like Figure 2 As shown, in the prior art, each switch unit is only a thin film transistor; the thin film transistor is turned on when there is a signal as a switch tube, and the technical solution of the present application adopts a combination of an N-type thin film transistor and a P-type thin film transistor, see Figure 5 When working, the gate potential of the N-type thin film transistor is opposite to the gate potential of the P-type thin film transistor, so that the N-type thin film transistor and the P-type thin film transistor are turned on at the same time and charge the AA area; the N-type and P-type TFTs form a CMOS structure, and the power consumption is much smaller than that of a single thin film transistor; it is effectively conducive to narrow borders.

[0072] See also Figure 4 The inverter includes two thin film transistors, namely a P-type thin film transistor and an N-type thin film transistor; the gates of the two thin film transistors are electrically connected to the main signal line; the source of the N-type thin film transistor is electrically connected to the gate-on power supply VGH, the source of the P-type thin film transistor is electrically connected to the gate-off power supply VGL, and the drains of the two thin film transistors are connected to the auxiliary signal line.

[0073] See also Figure 4 , the inverter also uses a combination of two thin film transistors. When there is a signal on the main signal line and the input signal is at a high level, the gates of the two thin film transistors are at a high potential, and the P-type thin film transistor is cut off; the N-type thin film transistor is turned on, the auxiliary signal line and the gate shutdown power supply VGL are turned on, and the output of the auxiliary signal line is low level; when the input signal is at a low level, the P-type thin film transistor is turned on, the N-type thin film transistor is turned off, the auxiliary signal line and the gate opening power supply VGH are turned on, and the auxiliary signal line outputs a high level. Secondly, the inverter and the switch unit both use a combination of two thin film transistors, which is conducive to the unified processing of the inverter and the switch unit, as well as the narrowing of the frame.

[0074] Example 2: See Figures 6 to 9 A demultiplexing circuit structure, comprising: a dual TFT structure, the dual TFT structure comprising:

[0075] A P-type substrate 1, a first insulating layer 2, a first gate 3, a second insulating layer 4, an IGZO semiconductor layer 11, a source-drain layer, a third insulating layer 12, and a second gate 7 are stacked in sequence; the P-type substrate is low temperature polycrystalline silicon (ITPS);

[0076] The source-drain layer includes a first source electrode 9, a second source electrode 10, a first drain electrode 6 and a second drain electrode 5; the first source electrode 9 and the second source electrode 10 are located on one side of the IGZO semiconductor layer 11, and the first drain electrode 6 and the second drain electrode 5 are located on the other side of the IGZO semiconductor layer 11; the first drain electrode 6 is electrically connected to the second drain electrode 5, and the second drain electrode 5 is connected to one end of the P-type substrate 1;

[0077] When the first source electrode 9 is electrically connected to one end of the IGZO semiconductor layer, the first source electrode 9 and the second source electrode 10 are both arranged on the second insulating layer 4, the second source electrode 10 is spaced apart from the first source electrode 9 and the IGZO semiconductor layer 11, and is connected to the other end of the P-type substrate 1; the first drain electrode 6 is electrically connected to the other end of the IGZO semiconductor layer; the double TFT structure constitutes an inverter;

[0078] When the first source electrode 9 is electrically connected to the second source electrode 10 , the first source electrode 9 is electrically connected to one end of the IGZO semiconductor layer; the second source electrode 10 is connected to the P-type substrate 1 ; and the dual TFT structure constitutes a switch unit.

[0079] In the demultiplexing circuit structure of the present technical solution, a CMOS TFT structure is adopted, and different connection methods of the second source 10 can respectively constitute an inverter and a switch unit; therefore, the inverter and the switch unit can be constituted by the same or similar stacked structure, which is beneficial to reducing the thickness of the demultiplexing circuit.

[0080] See also Figure 6 , Figure 7 The demultiplexing circuit includes two thin film transistors, which are named as a first thin film transistor and a second thin film transistor for convenience of explanation; the first thin film transistor includes a first gate electrode 3, a first active layer (IGZO semiconductor layer 11), a first source electrode 9 and a first drain electrode 6; the second thin film transistor includes a second gate electrode 7, a second active layer (IGZO semiconductor layer 11), a second source electrode 10 and a second drain electrode 5; wherein the two thin film transistors share the IGZO semiconductor layer 11; the IGZO semiconductor layer 11 is respectively used as the first active layer and the second active layer; the first source electrode 9 and the second source electrode 10 are both located on the second insulating layer 4, and are arranged at intervals, and are respectively connected to the IGZO semiconductor layer 11.

[0081] Preferably, the first drain 6 and the second drain 5 are integrated into a total drain.

[0082] Whether used as an inverter or a switch unit, the drains of the first thin film transistor and the second thin film transistor are electrically connected together; therefore, during design, the first drain 6 and the second drain 5 are integrated into a total drain, making the overall structure simple and easy to process.

[0083] Please combine Figure 4 The first source 9 and the second source 10 are connected to the gate-on power supply VGH and the gate-off power supply VGL respectively through wires; the total drain is connected to a secondary signal line for outputting a current signal to the outside; the first gate 3 and the second gate 7 are connected to the main signal line of the input signal through wires.

[0084] When working, the main signal line sends a level signal to the first gate 3 and the second gate 7. When a high level signal is sent, current flows through the IGZO semiconductor layer 11, and the current flows from the first source 9 to the total drain. The total drain outputs a low level through the auxiliary signal line. (The first thin film transistor is N-type and the second thin film transistor is P-type)

[0085] When a low level signal is sent, current flows through the IGZO semiconductor layer 11 , and the current flows from the second source 10 to the total drain, and the total drain outputs a high level through the auxiliary signal line.

[0086] Recombination Figure 5 , Figure 7 , Fig. 9 ; Switch unit: The first source 9 and the second source 10 are electrically connected, and the electrical connection can be: 1. When used as a switch unit, the first source 9 and the second source 10 are integrated into one to form a total source 18; 2. Connected by wires to form an electrical connection. The first gate 3 in the switch unit is electrically connected to the main signal line, and the second gate 7 in the switch unit is electrically connected to the auxiliary signal line; the first source 9 is electrically connected to the data bus, and the total drain is connected to the data line.

[0087] When working, the main signal line and the auxiliary signal line simultaneously send high-level and low-level signals to the first gate 3 and the second gate 7, current flows through the IGZO semiconductor layer 11, and the data line sends data signals (data) to the outside;

[0088] Furthermore, a first via 8 and a second via 13 are respectively provided at both ends of the second insulating layer 4 and the first insulating layer 2 , the total drain is electrically connected to the P-type substrate 1 through the first via 8 , and the second gate 7 is electrically connected to the P-type substrate 1 through the second via 13 .

[0089] See also Figure 8 , Fig. 9; As a variation of the above structure, the total drain, the first source 9, and the second source 10 are all arranged above the first insulating layer 2 and covered by the second insulating layer 4, and the third via 14 and the fourth via 17 are respectively provided at the two ends of the first insulating layer 2. The total drain is electrically connected to the P-type substrate 1 through the third via 14, and the second gate 7 is electrically connected to the P-type substrate 1 through the fourth via 17; the fifth via 15 and the sixth via 16 are also respectively provided at the two ends of the second insulating layer 4, and the two ends of the IGZO semiconductor layer 11 are electrically connected to the total drain through the fifth via 15, and the sixth via 16 is electrically connected to the first source 9 and the second source 10.

[0090] Please combine Figure 3 , the orthographic projection of the first gate 3 on the substrate and the orthographic projection of the second gate 7 on the substrate at least partially overlap. It can be understood that when the orthographic projection of the first gate 3 on the substrate and the orthographic projection of the second gate 741 on the substrate partially overlap, compared with the technical solution in which the orthographic projection of the first gate 3 on the substrate and the orthographic projection of the second gate 7 on the substrate 10 do not overlap at all, the occupied area of ​​the Demux circuit in the horizontal direction (parallel to the display surface) can be reduced, which is conducive to realizing narrow-frame display. In some embodiments, the orthographic projection of the first gate 3 on the substrate and the orthographic projection of the second gate 7 on the substrate completely (100%) overlap, at which time, the occupied area of ​​the Demux circuit in the horizontal direction (parallel to the display surface) can be minimized to achieve an extremely narrow-frame display.

[0091] Secondly, it can be seen that the first gate 3 is arranged below the IGZO semiconductor layer 11 to form a bottom gate, and the second gate 7 is arranged above the IGZO semiconductor layer 11 to form a top gate. That is to say, the embodiment of the present application adopts a combination of a top gate structure and a bottom gate structure to realize the design of the Demux circuit as a three-dimensional structure extending in the vertical direction (perpendicular to the display surface), thereby reducing the occupied area of ​​the Demux circuit on the horizontal plane (parallel to the display surface), thereby realizing a narrow frame design of the display device.

[0092] The present application adopts a stacked structure, which does not increase the design area, effectively reduces the space of the demux circuit, and is conducive to achieving a narrow frame.

[0093] Embodiment 3: A method for manufacturing a demultiplexing circuit structure, comprising the following steps:

[0094] Providing a P-type substrate 1;

[0095] forming a first insulating layer 2 on a P-type substrate 1;

[0096] forming a first gate 3 on the first insulating layer 2;

[0097] forming a second insulating layer 4 on the first gate 3 and the first insulating layer 2;

[0098] forming source and drain layers on both sides of the first insulating layer 2 or the second insulating layer 4;

[0099] An IGZO semiconductor layer 11 is formed on the middle portion of the second insulating layer 4;

[0100] forming a third insulating layer 12 on the source and drain electrode layers and the IGZO semiconductor layer 11;

[0101] The second gate 7 is formed on the third insulating layer 12 .

[0102] Among them, when the source-drain layer is formed on both sides of the second insulating layer 4, the source-drain layer includes: a first source electrode 9, a second source electrode 10, a first drain electrode 6 and a second drain electrode 5; the first source electrode 9 and the second source electrode 10 are arranged at intervals and are electrically connected to one end of the IGZO semiconductor layer 11 respectively; the first drain electrode 6 and the second drain electrode 5 are electrically connected or integrated into one, and the first drain electrode 6 is electrically connected to the other end of the IGZO semiconductor layer 11; the second source electrode 10 is electrically connected to one end of the P-type substrate 1, and the second drain electrode 5 is electrically connected to the other end of the P-type substrate 1.

[0103] Secondly, before forming the source and drain layers on both sides of the second insulating layer 4, the demultiplexing circuit structure manufacturing method further includes:

[0104] A first via hole 8 and a second via hole 13 are formed on both sides of the first insulating layer 2 and the second insulating layer 4 respectively;

[0105] The second drain electrode 5 is electrically connected to the other end of the P-type substrate 1 through the first via hole 8 ; the second source electrode 10 is electrically connected to one end of the P-type substrate 1 through the second via hole 13 .

[0106] When the source-drain layer is formed on both sides of the first insulating layer 2, the source-drain layer includes: a first source electrode 9, a second source electrode 10, a first drain electrode 6 and a second drain electrode 5; the first source electrode 9 and the second source electrode 10 are arranged at intervals and are electrically connected to one end of the IGZO semiconductor layer 11 respectively; the first drain electrode 6 and the second drain electrode 5 are electrically connected or integrated into one, and the first drain electrode 6 is electrically connected to the other end of the IGZO semiconductor layer 11; the second source electrode 10 is electrically connected to one end of the P-type substrate 1, and the second drain electrode 5 is electrically connected to the other end of the P-type substrate 1.

[0107] Before forming the source and drain layers on both sides of the first insulating layer 2, the method for manufacturing the demultiplexing circuit structure further includes:

[0108] A third via hole 14 and a fourth via hole 17 are formed on both sides of the first insulating layer 2 respectively;

[0109] The second drain electrode 5 is electrically connected to the other end of the P-type substrate 1 through the first via hole 8 ; the second source electrode 10 is electrically connected to one end of the P-type substrate 1 through the second via hole 13 .

[0110] A fifth via hole 15 and a sixth via hole 16 are formed on both sides of the second insulating layer 4 respectively;

[0111] Two ends of the IGZO semiconductor layer 11 are electrically connected to the first drain electrode 6 and the first source electrode 9 through a fifth via hole 15 and a sixth via hole 16 respectively.

[0112] Exemplarily, the first via hole 8 and the second via hole 13 can be completed in the same process; the third via hole 14 and the fourth via hole 17 can be completed in the same process; and the fifth via hole 15 and the sixth via hole 16 can be completed in the same process.

[0113] Example 4: See Fig.10 A display panel includes a display driving circuit, the display driving circuit includes the above-mentioned demultiplexing circuit, and the data line of the demultiplexing circuit is connected to the organic light-emitting diode; or, the display driving circuit includes the above-mentioned demultiplexing circuit structure and multiple organic light-emitting diodes, the demultiplexing circuit structure is electrically connected to the corresponding organic light-emitting diodes through the data lines, and controls the light emission of the organic light-emitting diodes.

[0114] Organic light-emitting diodes are arranged in rows on the display panel to form pixels. Fig.10 The pixels are controlled by data lines, which apply different data voltage signals to sub-pixels to make the sub-pixels display different grayscales, thereby realizing the display of full-color pictures.

[0115] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A demultiplexing circuit, comprising: Data bus; N groups of data lines, each group of data lines includes 3 data lines; A switch unit is provided corresponding to each data line of each group of data lines; N groups of signal lines, each group of signal lines includes 3 pairs of signal lines, and each pair of signal lines includes a main signal line and a sub-signal line; Features: Each switch unit includes two thin film transistors, namely a P-type thin film transistor and an N-type thin film transistor; The gate of one of the thin film transistors is connected to a main signal line of one group of signal lines, and the gate of the other thin film transistor is connected to a secondary signal line of the group of signal lines; the source electrodes of the two thin film transistors are electrically connected to the data bus; the drain electrodes of the two thin film transistors are connected to a corresponding one of the data lines; An inverter is provided between the main signal line and the auxiliary signal line of each pair of signal lines; The inverter includes two thin film transistors, namely a P-type thin film transistor and an N-type thin film transistor; the gates of the two thin film transistors are electrically connected to the main signal line; the source of the N-type thin film transistor is electrically connected to the gate-on power supply, the source of the P-type thin film transistor is electrically connected to the gate-off power supply, and the drains of the two thin film transistors are connected to the auxiliary signal line; The dual thin film transistor structure of the switch unit and the inverter includes: A P-type substrate, a first insulating layer, a first gate, a second insulating layer, a semiconductor layer, a source-drain layer, and a third insulating layer and a second gate are stacked in sequence; the P-type substrate is low-temperature polysilicon, and the semiconductor layer is indium gallium zinc oxide; The source-drain layer includes a first source, a second source, a first drain and a second drain; the first source and the second source are located on one side of the semiconductor layer, and the first drain and the second drain are located on the other side of the semiconductor layer; the first drain is electrically connected to the second drain, and the second drain is connected to one end of the P-type substrate; The orthographic projection of the first gate on the P-type substrate and the orthographic projection of the second gate on the P-type substrate at least partially overlap; The first source of the dual thin film transistor structure of the inverter is electrically connected to one end of the semiconductor layer, the first source and the second source are both arranged on the second insulating layer, the second source is spaced apart from the first source and the semiconductor layer, and is connected to the other end of the P-type substrate; the first drain is electrically connected to the other end of the semiconductor layer; The first source electrode and the second source electrode of the dual thin film transistor structure of the switch unit are electrically connected, the first source electrode is electrically connected to one end of the semiconductor layer; the second source electrode is connected to the P-type substrate; When working, the gate potential of the N-type thin film transistor of the switch unit is opposite to the gate potential of the P-type thin film transistor, so that the N-type thin film transistor and the P-type thin film transistor are turned on at the same time.

2. The demultiplexing circuit according to claim 1, characterized in that: The first drain and the second drain are integrated into a total drain; the first source and the second source are respectively connected to the gate-on power supply and the gate-off power supply through wires; the total drain is connected to a secondary signal line for outputting a current signal to the outside; the first gate and the second gate are connected to the main signal line of the input signal through wires.

3. The demultiplexing circuit according to claim 2, characterized in that: The second insulating layer and the first insulating layer are provided with a first via hole and a second via hole at both ends respectively, the main drain is electrically connected to the P-type substrate through the first via hole, and the second gate is electrically connected to the P-type substrate through the second via hole.

4. The demultiplexing circuit according to claim 2, characterized in that: The total drain, the first source and the second source are all arranged above the first insulating layer and covered by the second insulating layer. The third via and the fourth via are respectively provided at both ends of the first insulating layer. The total drain is electrically connected to the P-type substrate through the third via, and the second gate is electrically connected to the P-type substrate through the fourth via. The fifth via and the sixth via are also respectively provided at both ends of the second insulating layer. The two ends of the semiconductor layer are electrically connected to the total drain through the fifth via, and the sixth via is electrically connected to the first source and the second source.

5. A method for manufacturing a demultiplexing circuit according to any one of claims 1 to 4, characterized in that: The following steps are involved: Providing a P-type substrate; the P-type substrate is low-temperature polycrystalline silicon; forming a first insulating layer on a P-type substrate; forming a first gate on the first insulating layer; forming a second insulating layer on the first gate and the first insulating layer; forming a source-drain layer on both sides of the first insulating layer or the second insulating layer; forming a semiconductor layer on the middle portion of the second insulating layer; the semiconductor layer is indium gallium zinc oxide; forming a third insulating layer on the source / drain electrode layer and the semiconductor layer; A second gate is formed on the third insulating layer.

6. The method according to claim 5, characterized in that: When the source-drain layer is formed on both sides of the second insulating layer, the source-drain layer includes: a first source, a second source, a first drain, and a second drain; the first source and the second source are spaced apart and electrically connected to one end of the semiconductor layer respectively; the first drain and the second drain are electrically connected or integrated into one, and the first drain is electrically connected to the other end of the semiconductor layer; the second source is electrically connected to one end of the P-type substrate, and the second drain is electrically connected to the other end of the P-type substrate.

7. The method according to claim 6, characterized in that: Before forming the source and drain layers on both sides of the second insulating layer, the manufacturing method further includes: Forming a first via hole and a second via hole on both sides of the first insulating layer and the second insulating layer respectively; The second drain is electrically connected to the other end of the P-type substrate through the first via hole; the second source is electrically connected to one end of the P-type substrate through the second via hole.

8. The method according to claim 6, characterized in that: When the source-drain layer is formed on both sides of the first insulating layer, the source-drain layer includes: a first source, a second source, a first drain, and a second drain; the first source and the second source are spaced apart and electrically connected to one end of the semiconductor layer respectively; the first drain and the second drain are electrically connected or integrated into one, and the first drain is electrically connected to the other end of the semiconductor layer; the second source is electrically connected to one end of the P-type substrate, and the second drain is electrically connected to the other end of the P-type substrate.

9. The method according to claim 7, characterized in that: Before forming the source and drain layers on both sides of the first insulating layer, the manufacturing method further includes: Forming a third via hole and a fourth via hole on both sides of the first insulating layer respectively; The second drain is electrically connected to the other end of the P-type substrate through the first via hole; the second source is electrically connected to one end of the P-type substrate through the second via hole; Forming a fifth via hole and a sixth via hole on both sides of the second insulating layer respectively; Two ends of the semiconductor layer are electrically connected to the first drain and the first source through a fifth via hole and a sixth via hole, respectively.

10. A display panel, comprising a display driving circuit, characterized in that: The display driving circuit comprises the demultiplexing circuit as claimed in any one of claims 1 to 4 and a plurality of organic light emitting diodes, wherein the demultiplexing circuit is electrically connected to the corresponding organic light emitting diodes through data lines to control the light emission of the organic light emitting diodes.

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