Array substrate and display panel

Abstract

The embodiment of the present application provides an array substrate and a display panel, and relates to the technical field of display, the array substrate comprises a display area and a non-display area surrounding at least part of the display area, the array substrate comprises a substrate, a signal trace and a plurality of electrostatic protection units, the signal trace is located on one side of the substrate, the signal trace is located in the non-display area, the signal trace comprises a straight line segment extending along a first direction and an oblique line segment connected with the straight line segment, and the oblique line segment and the straight line segment have a first included angle. The plurality of electrostatic protection units are located on one side of the substrate, the plurality of electrostatic protection units comprise a first electrostatic protection unit, the first electrostatic protection unit is located on a side of the oblique line segment away from the display area, and the included angle β1 between the extension direction of the first electrostatic protection unit and the extension direction of the oblique line segment is less than or equal to 30 DEG. The present application can reduce the space occupied by the first electrostatic protection unit in the frame, so that the frame of the array substrate can be narrower.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to an array substrate and a display panel. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display panels.

[0003] However, there are still some problems with the display panel that need to be addressed. Summary of the Invention

[0004] To overcome the technical problems mentioned in the background, embodiments of this application provide an array substrate, the array substrate including a display area and a non-display area surrounding at least a portion of the display area, the array substrate comprising:

[0005] Substrate; A signal trace is located on one side of the substrate. The signal trace is located in a non-display area. The signal trace includes a straight line segment extending along a first direction and an oblique line segment connected to the straight line segment. The oblique line segment and the straight line segment have a first included angle. Multiple electrostatic discharge (ESD) protection units are located on one side of the substrate. The multiple ESD protection units include a first ESD protection unit located on the side of the oblique line segment away from the display area. The angle between the extension direction of the first ESD protection unit and the extension direction of the oblique line segment is less than or equal to 30°.

[0006] In some possible implementations, the extension direction of the first electrostatic protection unit is the same as the extension direction of the oblique line segment; Preferably, the orthographic projection of the first electrostatic discharge protection unit on the substrate and the orthographic projection of the signal trace on the substrate are spaced apart; Preferably, at least a portion of the signal trace has a longer extension length than the straight segment. Preferably, the array substrate further includes scan lines, and the first direction includes the extension direction of the scan lines in the display area.

[0007] In some possible implementations, the array substrate further includes: Multiple time-division multiplexing units are located on one side of the substrate. The signal traces are connected to the time-division multiplexing units. The time-division multiplexing units are located on the side of the straight line segment of the signal trace closest to the display area, which is close to the display area. The multiple time-division multiplexing units include multiple groups of time-division multiplexing units. The straight line segment includes a first type of straight line segment, which corresponds to a group of time-division multiplexing units. The first electrostatic discharge protection unit is located on the side of the oblique line segment of the signal trace farthest from the display area, which corresponds to the first type of straight line segment. Preferably, the extension length of the first electrostatic protection unit is less than the extension length of the oblique segment of the signal trace furthest from the display area; Preferably, the distance between the orthographic projection of the first electrostatic protection unit on the substrate and the orthographic projection of the signal trace furthest from the display area on the substrate is greater than or equal to 3 μm and less than or equal to 8 μm. Preferably, the array substrate further includes: The power supply voltage trace is located on one side of the substrate, and the power supply voltage trace is located on the side of the time-division multiplexing unit closest to the display area.

[0008] In some possible implementations, the straight line segment further includes a second type of straight line segment, which corresponds to two or more groups of time-division multiplexing unit groups. The plurality of electrostatic discharge protection units further include a second electrostatic discharge protection unit, which is located on the side of the second type of straight line segment of the signal trace farthest from the display area that is away from the display area, or the second electrostatic discharge protection unit is located on the side of the oblique line segment of the signal trace farthest from the display area that is away from the display area. Preferably, the angle between the extension direction of the second electrostatic protection unit and the extension direction of the straight line segment is less than or equal to 30°, or the angle between the extension direction of the second electrostatic protection unit and the extension direction of the oblique line segment is less than or equal to 30°. Preferably, the extension direction of the second electrostatic protection unit is the same as the extension direction of the straight line segment, or the extension direction of the second electrostatic protection unit is the same as the extension direction of the oblique line segment. Preferably, the extension length of the second electrostatic discharge protection unit is less than the extension length of the second type of straight segment of the signal trace farthest from the display area, or the extension length of the second electrostatic discharge protection unit is less than the extension length of the oblique segment of the signal trace farthest from the display area. Preferably, the extension length of the second type of straight line segment is greater than the extension length of the first type of straight line segment; Preferably, the orthographic projection of the second electrostatic discharge protection unit on the substrate and the orthographic projection of the signal trace on the substrate are spaced apart; Preferably, the distance between the orthographic projection of the second electrostatic protection unit on the substrate and the orthographic projection of the signal trace furthest from the display area on the substrate is greater than or equal to 3 μm and less than or equal to 8 μm.

[0009] In some possible implementations, three adjacent first-type straight segments correspond to one first electrostatic protection unit; Preferably, the array substrate further includes: A virtual in-plane gate driving unit is located on one side of the substrate. The virtual in-plane gate driving unit is located on the side of the first electrostatic protection unit away from the display area. The orthographic projection of the first electrostatic protection unit on the substrate is located between the orthographic projection of the virtual in-plane gate driving unit on the substrate and the orthographic projection of the oblique segment of the signal trace farthest from the display area on the substrate. Preferably, the array substrate further includes: An in-plane gate driving unit is located on one side of the substrate. The in-plane gate driving unit is located on the side of the first electrostatic protection unit away from the display area. The orthographic projection of the in-plane gate driving unit on the substrate and the orthographic projection of the virtual in-plane gate driving unit on the substrate are spaced apart.

[0010] In some possible implementations, the array substrate further includes: Multiple pixel circuits are located on one side of the substrate and in the display area. The multiple pixel circuits include a first type of pixel circuit, a second type of pixel circuit, and a third type of pixel circuit. The first type of pixel circuit is connected to a first sub-pixel, the second type of pixel circuit is connected to a second sub-pixel, and the third type of pixel circuit is connected to a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors. Data voltage traces are located on one side of the substrate. A group of time-division multiplexing units includes a first time-division multiplexing sub-unit, a second time-division multiplexing sub-unit, and a third time-division multiplexing sub-unit. One first time-division multiplexing sub-unit is connected to the first type of pixel circuit through the corresponding data voltage trace. One second time-division multiplexing sub-unit is connected to the second type of pixel circuit through the corresponding data voltage trace. One third time-division multiplexing sub-unit is connected to the third type of pixel circuit through the corresponding data voltage trace.

[0011] In some possible implementations, the array substrate further includes: The source connection trace is located between the substrate and the film layer where the signal trace is located. The source connection trace is connected to the electrostatic discharge protection unit. The orthographic projection of the source connection trace on the substrate intersects with the orthographic projection of the signal trace on the substrate. Preferably, the orthographic projection of the source connection trace on the substrate is perpendicular to the orthographic projection of the signal trace on the substrate.

[0012] In some possible implementations, the angle between the extension direction of the oblique line segment and the first direction is greater than or equal to 30° and less than or equal to 60°.

[0013] In some possible implementations, the non-display area includes an arc-shaped area, and the electrostatic protection unit is located in the arc-shaped area.

[0014] In some possible implementations, this application also provides a display panel, which includes the array substrate described in this application.

[0015] Compared with the prior art, this application has the following beneficial effects: The array substrate and display panel provided in this application can reduce the space occupied by the first electrostatic protection unit in the frame by setting the first electrostatic protection unit to be located on the side of the oblique line segment away from the display area, and setting the angle β1 between the extension direction of the first electrostatic protection unit and the extension direction of the oblique line segment to be less than or equal to 30°, thereby making the frame of the array substrate narrower. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is one of the top views of the array substrate provided in the embodiments of this application; Figure 2 A top view of the first electrostatic discharge protection unit and signal traces provided in the embodiments of this application; Figure 3 A schematic cross-sectional view of the signal traces disposed on the substrate according to an embodiment of this application; Figure 4 A top view schematic diagram showing that the first electrostatic discharge protection unit and the signal trace are parallel to each other, as provided in the embodiments of this application; Figure 5A top view schematic diagram showing the second electrostatic protection unit provided in this application embodiment located on the side of the second type of straight line segment away from the display area; Figure 6 A top view of the second electrostatic protection unit provided in this application embodiment, located on the side of the oblique line segment connected to the second type of straight line segment away from the display area; Figure 7 A schematic diagram of the interconnected structure of signal traces, time-division multiplexing unit groups, data lines, pixel circuits, and sub-pixels provided in the embodiments of this application; Figure 8 This is a schematic diagram of the pixel circuit provided in an embodiment of this application; Figure 9 The array substrate provided in the embodiments of this application also includes a top view of the source interconnect wiring; Figure 10 A schematic cross-sectional view of the source connection traces and signal traces located on one side of the substrate, as provided in the embodiments of this application; Figure 11 The array substrate provided in the embodiments of this application also includes one of the top view schematic diagrams of a virtual in-plane gate driving unit; Figure 12 The array substrate provided in the embodiments of this application also includes a second top view of a virtual in-plane gate driving unit; Figure 13 The array substrate provided in the embodiments of this application also includes a top view of the power supply traces; Figure 14 This is a second top view of the array substrate provided in the embodiments of this application; Figure 15 A cross-sectional schematic diagram of the display panel provided in an embodiment of this application; Figure 16 This is a three-dimensional structural diagram of the electronic device provided in an embodiment of this application.

[0018] Reference numerals: 01, Display panel; 100, Electronic device; 1, Substrate; 2, Signal trace; 21, Straight line segment; 211, First type of straight line segment; 212, Second type of straight line segment; 22, Diagonal line segment; 3, Electrostatic discharge protection unit; 31, First electrostatic discharge protection unit; 32, Second electrostatic discharge protection unit; 4, Scan line; 5, Time-division multiplexing unit group; 51, First time-division multiplexing subunit; 52, Second time-division multiplexing subunit; 53, Third time-division multiplexing subunit; 6, Data voltage trace; 7 71. Pixel circuit; 72. First type pixel circuit; 73. Second type pixel circuit; 74. Third type pixel circuit; 8. First sub-pixel; 9. Second sub-pixel; 10. Third sub-pixel; 11. Source connection trace; 12. In-plane gate driving unit; 13. Virtual in-plane gate driving unit; 14. Power supply voltage trace; 15. Array substrate; 16. Pixel defining layer; 161. Pixel aperture; 17. First electrode; 18. Light-emitting functional part; 19. Second electrode layer; 20. Sub-pixel. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. It should be noted that, unless otherwise specified, different features in the embodiments of this application can be combined with each other.

[0022] Furthermore, when using terms such as "above," "above," "below," "below," and "relative" to define the positional relationship between two elements, this includes not only the state where the two elements are directly connected, but also the state where the two elements are separated by gaps or other elements. In addition, the terms "first," "second," and "third," etc., are only used for distinguishing descriptions and should not be interpreted as indicating or implying relative importance.

[0023] It should be noted that, where there is no conflict, different features in the embodiments of this application can be combined with each other.

[0024] The array substrate in the related technology includes a display area and a non-display area surrounding at least part of the display area. The array substrate includes a substrate and an electrostatic discharge (ESD) protection unit located on one side of the substrate. The ESD protection unit is located in the non-display area. In order to make the ESD protection unit have a better waterproof effect, the ESD protection unit needs to be placed inside the encapsulation layer.

[0025] However, placing the electrostatic discharge protection unit inside the encapsulation layer will affect the bezel width of the array substrate, making it difficult for the array substrate to meet the requirements for narrow bezels.

[0026] To address the aforementioned technical problems, the following innovative technical solutions are designed. The specific implementation schemes of this application will be described in detail below with reference to the accompanying drawings. It should be noted that the deficiencies in the existing solutions are the result of practical experience and careful research. Therefore, the discovery process of the aforementioned technical problems and the solutions proposed in this embodiment below should be considered contributions made to this application during the invention process, and should not be construed as technical content known to those skilled in the art.

[0027] Please see Figures 1-3 This embodiment provides an array substrate 15, which includes a display area AA and a non-display area AB surrounding at least a portion of the display area AA. The array substrate 15 includes a substrate 1, signal traces 2, and a plurality of electrostatic discharge protection units 3.

[0028] The signal trace 2 is located on one side of the substrate 1 and in the non-display area AB. The signal trace 2 includes a straight line segment 21 extending along a first direction and an oblique line segment 22 connected to the straight line segment 21. The oblique line segment 22 and the straight line segment 21 have a first angle between them.

[0029] Multiple electrostatic discharge protection units 3 are located on one side of the substrate 1. The multiple electrostatic discharge protection units 3 include a first electrostatic discharge protection unit 31. The first electrostatic discharge protection unit 31 is located on the side of the oblique line segment 22 away from the display area AA. The angle β1 between the extension direction of the first electrostatic discharge protection unit 31 and the extension direction of the oblique line segment 22 is less than or equal to 30°.

[0030] The non-display area AB includes the bezel of the array substrate 15. The narrower the bezel, the higher the screen-to-body ratio of the array substrate 15, and the stronger its market competitiveness. The electrostatic discharge protection unit 3 is located in the bezel position, and the space occupied by the electrostatic discharge protection unit 3 in the bezel affects the bezel width of the array substrate 15. Specifically, the larger the space occupied by the electrostatic discharge protection unit 3 in the bezel, the more difficult it is for the array substrate 15 to achieve a narrow bezel.

[0031] In related technologies, the orientation of the electrostatic protection unit 3 is relatively arbitrary. For example, the electrostatic protection unit 3 may be placed horizontally. This will cause the electrostatic protection unit 3 to occupy more horizontal space of the frame, making it difficult to further reduce the size of the frame of the array substrate 15.

[0032] In this embodiment, the signal trace 2 includes a slanted segment 22, that is, part of the signal trace 2 is set to be slanted, which can reduce the horizontal space of the signal trace 2 at the border position, thereby reducing the space occupied by the signal trace 2 on the border.

[0033] Simultaneously, the first electrostatic discharge (ESD) protection unit 31 is positioned on the side of the oblique line segment 22 away from the display area AA, that is, the first ESD protection unit 31 is positioned opposite to the oblique line segment 22, and the angle β1 between the extension direction of the first ESD protection unit 31 and the extension direction of the oblique line segment 22 is set to be less than or equal to 30°. For example, the angle β1 can be 30°, 25°, 20°, 15°, 10°, 5°, or 0°, etc. In this way, the space occupied by the first ESD protection unit 31 in the bezel can be reduced, thereby making the bezel of the array substrate 15 narrower.

[0034] Based on the above design, this embodiment sets the first electrostatic protection unit 31 to be located on the side of the oblique line segment 22 away from the display area AA, and sets the angle β1 between the extension direction of the first electrostatic protection unit 31 and the extension direction of the oblique line segment 22 to be less than or equal to 30°, which can reduce the space occupied by the first electrostatic protection unit 31 in the frame, thereby making the frame of the array substrate 15 narrower.

[0035] For some possible implementations, please refer to Figure 4 The extension direction of the first electrostatic protection unit 31 is the same as the extension direction of the oblique line segment 22.

[0036] Optionally, please see again Figure 1 The array substrate 15 also includes a scan line 4, and the first direction includes the extension direction of the scan line 4 in the display area AA.

[0037] In this embodiment, the orthographic projection of the first electrostatic protection unit 31 on the substrate 1 is parallel to the orthographic projection of the oblique line segment 22 on the substrate 1. That is, the angle β1 between the extension direction of the first electrostatic protection unit 31 and the extension direction of the oblique line segment 22 is 0°. In this way, the first electrostatic protection unit 31 is arranged along the oblique line segment 22, which can make the lateral space occupied by the first electrostatic protection unit 31 smaller, thereby further reducing the bezel of the array substrate 15 and making it easier for the array substrate 15 to achieve the purpose of narrow bezel.

[0038] Optionally, the orthographic projection of the first electrostatic discharge (ESD) protection unit 31 on the substrate 1 and the orthographic projection of the signal trace 2 on the substrate 1 are spaced apart. That is, the orthographic projection of the first ESD protection unit 31 on the substrate 1 and the orthographic projection of the signal trace 2 on the substrate 1 do not overlap, so that the first ESD protection unit 31 and the signal trace 2 are less likely to interfere with each other.

[0039] Optionally, please see again Figure 4 At least part of the signal trace 2 has a diagonal segment 22 with a length W1 that is greater than the straight segment 21 with a length W2.

[0040] Generally, the longer the signal trace 2 is tilted, the smaller the horizontal space occupied by the signal trace 2 in the frame, which is more conducive to the array substrate 15 achieving a narrow frame.

[0041] In this embodiment, the length W1 of the oblique segment 22 of at least part of the signal trace 2 is set to be greater than the length W2 of the straight segment 21, which can further reduce the space occupied by the signal trace 2 in the frame, thereby making the frame of the array substrate 15 narrower.

[0042] For some possible implementations, please refer to Figure 5 The array substrate 15 also includes multiple time-division multiplexing units.

[0043] Multiple time-division multiplexing units are located on one side of substrate 1. Signal traces 2 are connected to the time-division multiplexing units. The time-division multiplexing units are located on the side of the straight line segment 21 of the signal trace 2 closest to the display area AA, which is close to the display area AA. The multiple time-division multiplexing units include multiple groups of time-division multiplexing units 5. The straight line segment 21 includes a first type of straight line segment 211, which corresponds to a group of time-division multiplexing units 5. The first electrostatic discharge protection unit 31 is located on the side of the oblique line segment 22 of the signal trace 2 farthest from the display area AA, which corresponds to the first type of straight line segment 211.

[0044] Signal trace 2 is electrically connected to the time-division multiplexing unit; therefore, signal trace 2 is a time-division multiplexed signal trace 2.

[0045] The space corresponding to the first type of straight line segment 211 is limited. Therefore, only one set of time-multiplexing unit group 5 can be placed in the space corresponding to the first type of straight line segment 211. The space on the side of the first type of straight line segment 211 farthest from the display area AA is limited, so the first electrostatic discharge protection unit 31 cannot be placed there. Therefore, the first electrostatic discharge protection unit 31 is set on the side of the oblique line segment 22 of the signal trace 2 farthest from the display area AA corresponding to the first type of straight line segment 211. In this way, not only can the first electrostatic discharge protection unit 31 be set more reasonably, but the space occupied by the first electrostatic discharge protection unit 31 in the frame can also be reduced.

[0046] Optionally, the extension length D1 of the first electrostatic discharge protection unit 31 is less than the extension length D2 of the oblique segment 22 of the signal trace 2 furthest from the display area AA. In this way, by making the oblique segment 22 longer, the first electrostatic discharge protection unit 31 can be better positioned at the oblique segment 22.

[0047] Optionally, the distance L1 between the orthographic projection of the first electrostatic discharge (ESD) protection unit 31 on the substrate 1 and the orthographic projection of the signal trace 2 furthest from the display area AA on the substrate 1 is greater than or equal to 3 μm and less than or equal to 8 μm. For example, the distance L1 can be 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, or 8 μm, etc. By reasonably setting the distance L1, the lateral space occupied by the first ESD protection unit 31 on the bezel can be reduced, and the mutual interference between the first ESD protection unit 31 and the signal trace 2 can be minimized.

[0048] For some possible implementations, please refer to Figure 5 and Figure 6 The straight segment 21 also includes a second type of straight segment 212, which corresponds to two or more time-division multiplexing unit groups 5. The multiple electrostatic discharge protection units 3 also include a second electrostatic discharge protection unit 32. The second electrostatic discharge protection unit 32 is located on the side of the second type of straight segment 212 of the signal line 2 farthest from the display area AA that is away from the display area AA, or the second electrostatic discharge protection unit 32 is located on the side of the oblique segment 22 of the signal line 2 farthest from the display area AA that is away from the display area AA.

[0049] Optionally, the extension length L3 of the second type of straight segment 212 is greater than the extension length L4 of the first type of straight segment 211.

[0050] The second electrostatic discharge protection unit 32 has the same function as the first electrostatic discharge protection unit 31, except that the second electrostatic discharge protection unit 32 and the first electrostatic discharge protection unit 31 are located in different positions.

[0051] The extension length of the second type of straight segment 212 is longer than that of the first type of straight segment 211. There is more space to set up time-division multiplexing units at the position of the second type of straight segment 212. Usually, two or more groups of time-division multiplexing units 5 can be set up at the position of the second type of straight segment 212.

[0052] Because the extended length of the second type of straight segment 212 is relatively longer, there is more space in the position of the second type of straight segment 212 away from the display area AA.

[0053] Therefore, in some embodiments, please refer again Figure 5The second electrostatic discharge protection unit 32 can be set on the side of the second type of straight segment 212 of the signal line 2 furthest from the display area AA, that is, the second electrostatic discharge protection unit 32 is set at the position corresponding to the second type of straight segment 212.

[0054] In other embodiments, please refer again. Figure 6 There is also a large space at the position of the oblique segment 22 connected to the second type of straight segment 212, so the second electrostatic protection unit 32 can also be set to the side of the oblique segment 22 connected to the second type of straight segment 212 that is furthest from the display area AA, away from the display area AA.

[0055] By placing the second electrostatic discharge protection unit 32 in a more suitable position, the lateral space occupied by the second electrostatic discharge protection unit 32 can be further reduced, thereby further reducing the border width of the array substrate 15.

[0056] Optionally, the angle between the extension direction of the second electrostatic protection unit 32 and the extension direction of the straight line segment 21 is less than or equal to 30°, or the angle between the extension direction of the second electrostatic protection unit 32 and the extension direction of the oblique line segment 22 is less than or equal to 30°.

[0057] In some embodiments, please refer again Figure 5 When the second electrostatic discharge protection unit 32 is located on the side of the second type of straight segment 212 of the signal trace 2 furthest from the display area AA, the angle between the extension direction of the second electrostatic discharge protection unit 32 and the extension direction of the straight segment 212 is less than or equal to 30°. For example, this angle can be 30°, 25°, 20°, 15°, 10°, 5°, or 0°. In this way, the space occupied by the second electrostatic discharge protection unit 32 in the bezel can be reduced, thereby making the bezel of the array substrate 15 narrower.

[0058] Optionally, the extension direction of the second electrostatic protection unit 32 is the same as the extension direction of the straight line segment 21.

[0059] The orthographic projection of the second electrostatic protection unit 32 on the substrate 1 is parallel to the orthographic projection of the straight line segment 21 on the substrate 1. That is, the angle between the extension direction of the second electrostatic protection unit 32 and the extension direction of the straight line segment 21 is 0°. In this way, the second electrostatic protection unit 32 is arranged along the straight line segment 21, which can make the space occupied by the second electrostatic protection unit 32 smaller, thereby further reducing the bezel width of the array substrate 15 and making it easier for the array substrate 15 to achieve the purpose of narrow bezel.

[0060] Optionally, the extension length D3 of the second electrostatic discharge protection unit 32 is less than the extension length D4 of the second type of straight segment 212 of the signal trace 2 furthest from the display area AA. In this way, there is more space on the side of the second type of straight segment 212 furthest from the display area AA to accommodate the second electrostatic discharge protection unit 32.

[0061] In other embodiments, please refer again. Figure 6 When the second electrostatic discharge protection unit 32 is located on the side of the oblique line segment 22 connected to the second type of straight line segment 212 furthest from the display area AA, the angle between the extension direction of the second electrostatic discharge protection unit 32 and the extension direction of the oblique line segment 22 is less than or equal to 30°. For example, this angle can be 30°, 25°, 20°, 15°, 10°, 5°, or 0°. In this way, the space occupied by the second electrostatic discharge protection unit 32 in the bezel can be reduced, thereby making the bezel of the array substrate 15 narrower.

[0062] Optionally, the extension direction of the second electrostatic protection unit 32 is the same as the extension direction of the oblique line segment 22.

[0063] The orthographic projection of the second electrostatic protection unit 32 on the substrate 1 is parallel to the orthographic projection of the oblique line segment 22 on the substrate 1. That is, the angle between the extension direction of the second electrostatic protection unit 32 and the extension direction of the oblique line segment 22 connected by the second type of straight line segment 212 is 0°. In this way, the second electrostatic protection unit 32 is arranged along the oblique line segment 22, which can make the space occupied by the second electrostatic protection unit 32 smaller, thereby further reducing the bezel width of the array substrate 15 and making it easier for the array substrate 15 to achieve the purpose of narrow bezel.

[0064] Optionally, the extension length D3 of the second electrostatic discharge protection unit 32 is less than the extension length D5 of the oblique segment 22 of the signal trace 2 furthest from the display area AA. Thus, there is more space to accommodate the second electrostatic discharge protection unit 32 on the side of the oblique segment 22 connected to the second type of straight segment 212 that is furthest from the display area AA.

[0065] Optionally, the orthographic projection of the second electrostatic discharge (ESD) protection unit 32 on the substrate 1 is spaced apart from the orthographic projection of the signal trace 2 on the substrate 1. In this way, the second ESD protection unit 32 and the signal trace 2 do not interfere with each other.

[0066] Optionally, please see again Figure 5 The distance L2 between the orthographic projection of the second electrostatic protection unit 32 on the substrate 1 and the orthographic projection of the signal trace 2 farthest from the display area AA on the substrate 1 is greater than or equal to 3μm and less than or equal to 8μm.

[0067] For example, the distance L2 can be 3μm, 4μm, 5μm, 6μm, 7μm, or 8μm. Properly setting the distance L2 can reduce the lateral space occupied by the second electrostatic discharge (ESD) protection unit 32 on the frame, and also minimize mutual interference between the second ESD protection unit 32 and the signal trace 2.

[0068] For some possible implementations, please refer to Figure 7 The array substrate 15 also includes multiple pixel circuits 7 and data voltage traces 6.

[0069] Multiple pixel circuits 7 are located on one side of the substrate 1 and in the display area AA. The multiple pixel circuits 7 include a first type of pixel circuit 71, a second type of pixel circuit 72 and a third type of pixel circuit 73. The first type of pixel circuit 71 is connected to the first sub-pixel 8, the second type of pixel circuit 72 is connected to the second sub-pixel 9, and the third type of pixel circuit 73 is connected to the third sub-pixel 10. The first sub-pixel 8, the second sub-pixel 9 and the third sub-pixel 10 emit different colors.

[0070] Data voltage traces 6 are located on one side of substrate 1. A group of time-division multiplexing units 5 includes a first time-division multiplexing sub-unit 51, a second time-division multiplexing sub-unit 52, and a third time-division multiplexing sub-unit 53. A first time-division multiplexing sub-unit 51 is connected to a first type of pixel circuit 71 through a corresponding data voltage trace 6, a second time-division multiplexing sub-unit 52 is connected to a second type of pixel circuit 72 through a corresponding data voltage trace 6, and a third time-division multiplexing sub-unit 53 is connected to a third type of pixel circuit 73 through a corresponding data voltage trace 6.

[0071] Please see Figure 8 The pixel circuit 7 includes a driving transistor T1 and a data transistor T2. The first terminal of the data transistor T2 is connected to the data voltage trace 6 that provides the data signal Data. The gate of the data transistor T2 is connected to the scan line 4 that provides the scan signal Scan. The second terminal of the data transistor T2 is connected to the gate of the driving transistor T1. The two ends of the storage capacitor C1 are respectively connected to the gate and the first terminal of the driving transistor T1. The second terminal of the driving transistor T1 is connected to the sub-pixel 20. Figure 8 This is one embodiment of pixel circuit 7, but pixel circuit 7 in this application is not limited to... Figure 8 The pixel circuit 7 shown in the 2T1C diagram can also be other pixel circuits 7, such as 7T1C, 8T1C pixel circuits, etc.

[0072] For example, the first sub-pixel 8 emits red light, the second sub-pixel 9 emits green light, and the third sub-pixel 10 emits blue light.

[0073] Signal line 2 is connected to the time-division multiplexing unit, the time-division multiplexing unit is connected to the data voltage line 6, the data voltage line 6 is connected to the corresponding pixel circuit 7, and the pixel circuit 7 is then connected to the corresponding sub-pixel to provide data voltage to the corresponding sub-pixel.

[0074] Specifically, a first time-division multiplexing subunit 51 is connected to a first type of pixel circuit 71 via a corresponding data voltage line 6, and the first type of pixel circuit 71 is connected to a first sub-pixel 8; a second time-division multiplexing subunit 52 is connected to a second type of pixel circuit 72 via a corresponding data voltage line 6, and the second type of pixel circuit 72 is connected to a second sub-pixel 9; a third time-division multiplexing subunit 53 is connected to a third type of pixel circuit 73 via a corresponding data voltage line 6, and the third type of pixel circuit 73 is connected to a third sub-pixel 10.

[0075] Specifically, a group of time-division multiplexing units 5 corresponding to a group of pixels (including a first sub-pixel 8, a second sub-pixel 9, and a third sub-pixel 10) is set at the position of the first type of straight line segment 211, and two or more groups of time-division multiplexing units 5 corresponding to two or more groups of pixels (including a first sub-pixel 8, a second sub-pixel 9, and a third sub-pixel 10) are set at the position of the second type of straight line segment 212.

[0076] For some possible implementations, please refer to Figure 9 and Figure 10 The array substrate 15 also includes a source connection trace 11, which is located between the substrate 1 and the film layer where the signal trace 2 is located. The source connection trace 11 is connected to the electrostatic discharge protection unit 3, and the orthographic projection of the source connection trace 11 on the substrate 1 intersects with the orthographic projection of the signal trace 2 on the substrate 1.

[0077] The electrostatic discharge protection unit 3 is formed by multiple layers of film in the array substrate 15. The source connection trace 11 is electrically connected to the electrostatic discharge protection unit 3. Therefore, the electrostatic discharge protection unit 3 can be used to prevent the source connection trace 11 from generating static electricity. The source connection trace 11 can be connected to the source of the transistor in the pixel circuit 7.

[0078] Optionally, the orthographic projection of the source connection trace 11 on the substrate 1 is perpendicular to the orthographic projection of the signal trace 2 on the substrate 1. In this way, the overlapping area of ​​the source connection trace 11 and the signal trace 2 can be reduced, thereby making it less likely for the signals of the source connection trace 11 and the signal trace 2 to couple, thus improving the effectiveness of the source connection trace 11 and the signal trace 2 in transmitting the corresponding signals.

[0079] For some possible implementations, please refer to Figure 11 Three adjacent first-class straight segments 211 correspond to one first electrostatic protection unit 31.

[0080] In this embodiment, a first electrostatic discharge protection unit 31 needs to be set at the position of the oblique line segment 22 corresponding to every three adjacent first type straight line segments 211. In this way, the space of the non-display area AB can be better utilized, thereby further reducing the bezel of the array substrate 15.

[0081] Optionally, please see Figure 12 The array substrate 15 also includes a virtual in-plane gate driving unit 13 and an in-plane gate driving unit 12. The virtual in-plane gate driving unit 13 is located on one side of the substrate 1. The virtual in-plane gate driving unit 13 is located on the side of the first electrostatic protection unit 31 away from the display area AA. The orthographic projection of the first electrostatic protection unit 31 on the substrate 1 is located between the orthographic projection of the virtual in-plane gate driving unit 13 on the substrate 1 and the orthographic projection of the oblique segment 22 of the signal trace 2 farthest from the display area AA on the substrate 1.

[0082] The in-plane gate driving unit 12 is located on one side of the substrate 1. The in-plane gate driving unit 12 is located on the side of the first electrostatic protection unit 31 away from the display area AA. The orthographic projection of the in-plane gate driving unit 12 on the substrate 1 and the orthographic projection of the virtual in-plane gate driving unit 13 on the substrate 1 are spaced apart.

[0083] The in-plane gate drive unit 12 (GIP) can provide drive signals for the corresponding pixels. The virtual in-plane gate drive unit 13 does not transmit signals. The virtual in-plane gate drive unit 13 exists independently and mainly plays the role of making the array substrate 15 more uniform.

[0084] In this embodiment, when a first electrostatic discharge (ESD) protection unit 31 needs to be set at the position of the oblique line segment 22 corresponding to three adjacent first-type straight line segments 211, the first ESD protection unit 31 is preferentially set at the position corresponding to the gate driving unit 13 in the virtual plane. In this way, the space occupied by the first ESD protection unit 31 can be further reduced, thereby further reducing the bezel width of the array substrate 15.

[0085] Optionally, please see Figure 13 The array substrate 15 also includes a power supply voltage trace 14, which is located on one side of the substrate 1 and on the side of the time-division multiplexing unit closest to the display area AA. The power supply voltage trace 14 provides a power signal to the corresponding pixel so that the corresponding pixel emits light.

[0086] In some possible implementations, please refer again. Figure 2 The angle β2 between the extension direction of the oblique line segment 22 and the first direction is greater than or equal to 30° and less than or equal to 60°.

[0087] For example, the included angle β2 can be 30°, 35°, 40°, 45°, 50°, 55° or 60°, etc. By reasonably setting the included angle β2, the space occupied by the oblique line segment 22 and the first electrostatic protection unit 31 in the frame can be reduced, thereby further reducing the frame width of the array substrate 15.

[0088] In some possible implementations, please refer again. Figure 1 The non-display area AB includes an arc area, and the electrostatic protection unit 3 is located in the arc area.

[0089] In some embodiments, please refer again Figure 1 If the top view of the array substrate 15 is rectangular, then the electrostatic protection unit 3 is located in the arc area of ​​the lower frame, that is, the electrostatic protection unit 3 is located at the two chamfered corners of the lower frame.

[0090] In other embodiments, please refer to Figure 14 If the top view of the array substrate 15 is circular, then the electrostatic protection unit 3 is located in the arc area of ​​the lower frame, that is, the electrostatic protection unit 3 is located in the lower half of the non-display area AB of the array substrate 15.

[0091] Thus, by setting the electrostatic protection unit 3 to be located in the arc area, the width of the arc area can be reduced, thereby reducing the border width of the array substrate 15.

[0092] For example, the above solution can reduce the border width by about 60μm.

[0093] For some possible implementations, please refer to Figure 15 This application also provides a display panel, which includes the array substrate 15, pixel defining layer 16 and sub-pixels 20 of this application.

[0094] The pixel defining layer 16 is located on one side of the array substrate 15. The pixel defining layer 16 encloses and forms a plurality of pixel openings 161. At least a portion of the sub-pixel 20 is located within the pixel openings 161. The sub-pixel includes a first electrode 17, a light-emitting functional part 18, and a second electrode layer 19, which are sequentially stacked along a direction away from the array substrate 15.

[0095] Since the display panel includes the array substrate 15 of this application, the bezel of the display panel can be made narrower, thereby obtaining a display panel with a narrower bezel.

[0096] For some possible implementations, please refer to Figure 16This application also provides an electronic device 100, which includes the display panel 01 described in this application. The electronic device 100 may include devices with image processing capabilities, such as mobile phones, desktop computers, laptops, tablets, in-vehicle displays, wearable devices, etc. Because the electronic device 100 includes the display panel 01 described in this application, the bezel of the electronic device 100 can be made narrower.

[0097] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0098] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An array substrate, characterized in that, The array substrate includes a display area and a non-display area surrounding at least a portion of the display area, the array substrate comprising: Substrate; A signal trace is located on one side of the substrate. The signal trace is located in a non-display area. The signal trace includes a straight line segment extending along a first direction and an oblique line segment connected to the straight line segment. The oblique line segment and the straight line segment have a first included angle. Multiple electrostatic discharge (ESD) protection units are located on one side of the substrate. The multiple ESD protection units include a first ESD protection unit located on the side of the oblique line segment away from the display area. The angle between the extension direction of the first ESD protection unit and the extension direction of the oblique line segment is less than or equal to 30°.

2. The array substrate according to claim 1, characterized in that, The extension direction of the first electrostatic protection unit is the same as the extension direction of the oblique line segment; Preferably, the orthographic projection of the first electrostatic discharge protection unit on the substrate and the orthographic projection of the signal trace on the substrate are spaced apart; Preferably, at least a portion of the signal trace has a longer extension length than the straight segment. Preferably, the array substrate further includes scan lines, and the first direction includes the extension direction of the scan lines in the display area.

3. The array substrate according to claim 1, characterized in that, The array substrate further includes: Multiple time-division multiplexing units are located on one side of the substrate. The signal traces are connected to the time-division multiplexing units. The time-division multiplexing units are located on the side of the straight line segment of the signal trace closest to the display area, which is close to the display area. The multiple time-division multiplexing units include multiple groups of time-division multiplexing units. The straight line segment includes a first type of straight line segment, which corresponds to a group of time-division multiplexing units. The first electrostatic discharge protection unit is located on the side of the oblique line segment of the signal trace farthest from the display area, which corresponds to the first type of straight line segment. Preferably, the extension length of the first electrostatic protection unit is less than the extension length of the oblique segment of the signal trace furthest from the display area; Preferably, the distance between the orthographic projection of the first electrostatic protection unit on the substrate and the orthographic projection of the signal trace furthest from the display area on the substrate is greater than or equal to 3 μm and less than or equal to 8 μm. Preferably, the array substrate further includes: The power supply voltage trace is located on one side of the substrate, and the power supply voltage trace is located on the side of the time-division multiplexing unit closest to the display area.

4. The array substrate according to claim 3, characterized in that, The straight line segment also includes a second type of straight line segment, which corresponds to two or more groups of time-division multiplexing units. The plurality of electrostatic discharge protection units also include a second electrostatic discharge protection unit, which is located on the side of the second type of straight line segment of the signal trace farthest from the display area that is away from the display area, or the second electrostatic discharge protection unit is located on the side of the oblique line segment of the signal trace farthest from the display area that is away from the display area. Preferably, the angle between the extension direction of the second electrostatic protection unit and the extension direction of the straight line segment is less than or equal to 30°, or the angle between the extension direction of the second electrostatic protection unit and the extension direction of the oblique line segment is less than or equal to 30°. Preferably, the extension direction of the second electrostatic protection unit is the same as the extension direction of the straight line segment, or the extension direction of the second electrostatic protection unit is the same as the extension direction of the oblique line segment. Preferably, the extension length of the second electrostatic discharge protection unit is less than the extension length of the second type of straight segment of the signal trace farthest from the display area, or the extension length of the second electrostatic discharge protection unit is less than the extension length of the oblique segment of the signal trace farthest from the display area. Preferably, the extension length of the second type of straight line segment is greater than the extension length of the first type of straight line segment; Preferably, the orthographic projection of the second electrostatic discharge protection unit on the substrate and the orthographic projection of the signal trace on the substrate are spaced apart; Preferably, the distance between the orthographic projection of the second electrostatic protection unit on the substrate and the orthographic projection of the signal trace furthest from the display area on the substrate is greater than or equal to 3 μm and less than or equal to 8 μm.

5. The array substrate according to claim 3, characterized in that, Three adjacent straight segments of the first type correspond to one first electrostatic protection unit; Preferably, the array substrate further includes: A virtual in-plane gate driving unit is located on one side of the substrate. The virtual in-plane gate driving unit is located on the side of the first electrostatic protection unit away from the display area. The orthographic projection of the first electrostatic protection unit on the substrate is located between the orthographic projection of the virtual in-plane gate driving unit on the substrate and the orthographic projection of the oblique segment of the signal trace farthest from the display area on the substrate. Preferably, the array substrate further includes: An in-plane gate driving unit is located on one side of the substrate. The in-plane gate driving unit is located on the side of the first electrostatic protection unit away from the display area. The orthographic projection of the in-plane gate driving unit on the substrate and the orthographic projection of the virtual in-plane gate driving unit on the substrate are spaced apart.

6. The array substrate according to claim 3, characterized in that, The array substrate further includes: Multiple pixel circuits are located on one side of the substrate and in the display area. The multiple pixel circuits include a first type of pixel circuit, a second type of pixel circuit, and a third type of pixel circuit. The first type of pixel circuit is connected to a first sub-pixel, the second type of pixel circuit is connected to a second sub-pixel, and the third type of pixel circuit is connected to a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel emit different colors. Data voltage traces are located on one side of the substrate. A group of time-division multiplexing units includes a first time-division multiplexing sub-unit, a second time-division multiplexing sub-unit, and a third time-division multiplexing sub-unit. One first time-division multiplexing sub-unit is connected to the first type of pixel circuit through the corresponding data voltage trace. One second time-division multiplexing sub-unit is connected to the second type of pixel circuit through the corresponding data voltage trace. One third time-division multiplexing sub-unit is connected to the third type of pixel circuit through the corresponding data voltage trace.

7. The array substrate according to claim 1, characterized in that, The array substrate further includes: The source connection trace is located between the substrate and the film layer where the signal trace is located. The source connection trace is connected to the electrostatic discharge protection unit. The orthographic projection of the source connection trace on the substrate intersects with the orthographic projection of the signal trace on the substrate. Preferably, the orthographic projection of the source connection trace on the substrate is perpendicular to the orthographic projection of the signal trace on the substrate.

8. The array substrate according to claim 1, characterized in that, The angle between the extension direction of the oblique line segment and the first direction is greater than or equal to 30° and less than or equal to 60°.

9. The array substrate according to any one of claims 1-8, characterized in that, The non-display area includes an arc-shaped area, and the electrostatic protection unit is located in the arc-shaped area.

10. A display panel, characterized in that, The display panel includes the array substrate as described in any one of claims 1-9.

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