OLED micro-display device and manufacturing method thereof

Abstract

The invention provides an OLED (Organic Light Emitting Diode) micro display device and a manufacturing method thereof, a driving circuit and a pixel circuit are respectively and independently manufactured on two wafers to obtain a driving wafer with the driving circuit and a pixel wafer with a plurality of pixel cathodes, and then the two wafers are bonded together by introducing a hybrid bonding process, so that the OLED micro display device is manufactured. The driving circuit is electrically connected with the pixel cathode, and then the pixel cathode is led out to the back surface of the pixel wafer through a through silicon via (TSV) technology so as to be electrically connected with the OLED pixel structure formed on the back surface of the pixel wafer, so that wiring from the driving circuit to the OLED pixel structure when the driving circuit and the OLED pixel structure are integrated on the same wafer plane is omitted; according to the OLED micro-display device, the wiring length is reduced, so that the driving circuit directly controls the OLED pixel structure in a point-to-point manner, the RC delay is greatly reduced, the refresh rate is improved, the working frequency of the manufactured OLED micro-display device can be remarkably increased, and the OLED micro-display device is small in area and narrow in frame.

Description

Technical Field

[0001] The present invention relates to the technical field of display manufacturing, and in particular to an OLED micro-display device and a manufacturing method thereof. Background Art

[0002] Silicon-based organic light-emitting diode (OLED) display is an innovative micro display that combines semiconductor CMOS technology and OLED technology. Figure 1 It uses single crystal silicon as a substrate or base plate (also known as a driving backplane), and divides the base plate into a pixel area 102 and a driving circuit area 101. Usually, the pixel area 102 is located in the central area of ​​the base plate, and the driving circuit area 101 is located around the periphery of the pixel area 101. The integrated CMOS driving circuit (including the pixel circuit, row and column driving circuit, etc. required for silicon-based micro-display) 101 is manufactured in the driving circuit area 101 by applying a standard CMOS process, and pixels arranged in rows and columns are manufactured in the pixel area 102 by applying OLED technology. Silicon-based OLED display devices have outstanding features such as small area, high resolution, high refresh rate, and light weight. They are recognized as the best choice for display devices such as the next generation of augmented reality (AR) / virtual reality (VR) and head-mounted display devices.

[0003] For display devices such as AR / VR, high refresh rate and smaller area have always been their constant pursuit. High refresh rate means short response time. Although the current silicon-based OLED display devices are more competitive than micro light emitting diode displays (Micro Light Emitting Diode Display, micro LED) and silicon-based liquid crystal (Liquid Crystal On Silicon, LCOS) displays, their driving backplane area is much larger than the pixel area, and controlling the entire row and column of pixels in the pixel area through row and column driving circuits will cause a large delay and reduce the refresh rate. Therefore, it cannot meet the needs of higher performance AR / VR and other display devices. Summary of the invention

[0004] The object of the present invention is to provide an OLED micro-display device and a manufacturing method thereof, which has a small area, a narrow frame, and can reduce delay and increase refresh rate.

[0005] To achieve the above object, the present invention provides a method for manufacturing an OLED micro display device, which comprises the following steps:

[0006] Providing a driving wafer and a pixel wafer, wherein the driving wafer has a driving circuit inside, and the pixel wafer has a plurality of pixel cathodes inside, and the pixel cathodes are located in a pixel area of ​​the pixel wafer;

[0007] Forming a first bonding dielectric layer and a first metal contact on the driving wafer, and forming a second bonding dielectric layer and a second metal contact on the front side of the pixel wafer, wherein the bottom of the first metal contact is electrically connected to the driving circuit and the top is exposed by the first bonding dielectric layer, and the bottom of the second metal contact is electrically connected to the corresponding pixel cathode and the top is exposed by the second bonding dielectric layer;

[0008] Inverting the pixel wafer onto the driving wafer for hybrid bonding, so that the first bonding medium layer and the second bonding medium layer are bonded together, and the corresponding first metal contact and the second metal contact are bonded together to form a bonded wafer;

[0009] An interlayer dielectric layer is covered on the back side of the pixel wafer, and a corresponding cathode conductive column is formed on the back side of the pixel wafer by a through silicon via process, wherein the cathode conductive column penetrates the interlayer dielectric layer of the pixel region and is electrically connected to the corresponding pixel cathode at the bottom;

[0010] Forming a plurality of OLED pixel structures on the back side of the pixel wafer, wherein the OLED pixel structures are located in the pixel area and are electrically connected to the top of the corresponding cathode conductive pillar;

[0011] The bonded wafer is cut and packaged to form an OLED micro display device.

[0012] Optionally, the first metal contact and the second metal contact are both copper contacts, with a critical dimension of 0.3 μm to 0.8 μm, and a critical dimension of the pixel cathode is 1 μm to 3 μm.

[0013] Optionally, before hybrid bonding is performed, the bonding surfaces of the driving wafer and the pixel wafer are both thinned; or, after hybrid bonding is performed, thinning is performed from the back side of the pixel wafer to thin the pixel wafer to 1 μm to 3 μm.

[0014] Optionally, the step of forming a corresponding cathode conductive column on the back side of the pixel wafer by a through silicon via process includes:

[0015] Coating a photoresist on the interlayer dielectric layer on the back side of the pixel wafer, and performing photolithography on the photoresist using a corresponding through silicon hole mask to form a patterned photoresist;

[0016] Using the patterned photoresist as a mask, etching the interlayer dielectric layer and the back side of the pixel wafer until the corresponding pixel cathode is exposed to form a corresponding plurality of through silicon vias;

[0017] The first metal is filled into the silicon through hole and chemical mechanical polishing is performed using the interlayer dielectric layer as a stop layer to form the cathode conductive column.

[0018] Optionally, after forming the cathode conductive column and before forming the OLED pixel structure, a diffusion barrier layer is further formed to bury the interlayer dielectric layer and the cathode conductive column.

[0019] Optionally, the step of forming the OLED pixel structure on the back side of the pixel wafer includes:

[0020] Opening the diffusion barrier layer in the pixel region by photolithography and etching processes to expose the top surface of the cathode conductive column;

[0021] A high reflectivity cathode metal material layer, an organic semiconductor layer, a semi-transparent anode layer and a thin film encapsulation layer are sequentially formed on the diffusion barrier layer in the pixel area and the exposed cathode conductive column thereof to form an OLED pixel functional layer.

[0022] Optionally, the pixel wafer provided further has a peripheral electrode formed therein, and the peripheral electrode is formed in a peripheral region outside the pixel region;

[0023] After forming the cathode conductive column and before or after forming the OLED pixel structure, the manufacturing method further includes: forming a peripheral pad on the back side of the pixel wafer, wherein the peripheral pad penetrates the interlayer dielectric layer and is electrically connected to the peripheral electrode.

[0024] Optionally, the step of forming the peripheral pad includes:

[0025] Opening the interlayer dielectric layer in the peripheral area and a portion of the thickness of the pixel wafer by photolithography and etching processes to form a contact hole exposing at least a portion of the surface of the peripheral electrode;

[0026] Filling a second metal in the contact hole;

[0027] A passivation layer is deposited on the second metal and the interlayer dielectric layer, and the passivation layer is etched to expose at least a portion of the top of the second metal and remove the passivation layer in the pixel area to form the peripheral pad.

[0028] Based on the same inventive concept, the present invention also provides an OLED micro display device, which includes:

[0029] A driver chip, wherein a driver circuit is provided inside the driver chip, and a first bonding dielectric layer and a first metal contact are formed on the driver chip, wherein the bottom of the first metal contact is electrically connected to the driver circuit and the top is exposed by the first bonding dielectric layer;

[0030] A pixel chip, wherein the pixel chip is invertedly stacked on the driver chip and has a plurality of pixel cathodes inside, wherein the pixel cathodes are located in the pixel area of ​​the pixel chip, a second bonding medium layer and a second metal contact are formed on the front side of the pixel chip, the bottom of the second metal contact is electrically connected to the corresponding pixel cathode and the top is exposed by the second bonding medium layer, the second bonding medium layer and the first bonding medium layer are bonded together, and the corresponding second metal contact and the first metal contact are bonded together, so that the front side of the pixel chip is hybrid-bonded with the driver chip;

[0031] An interlayer dielectric layer covering the back side of the pixel wafer;

[0032] A cathode conductive column, extending from the back of the pixel wafer through the interlayer dielectric layer of the pixel region and electrically connected to the corresponding pixel cathode at the bottom;

[0033] A plurality of OLED pixel structures are formed on the back side of the pixel wafer. The OLED pixel structures are located in the pixel region and are electrically connected to the top of the corresponding cathode conductive column.

[0034] Optionally, the OLED micro display device further includes at least one of the following structures:

[0035] a passivation layer formed on the interlayer dielectric layer in the peripheral region and exposing at least a portion of a top surface of the peripheral pad;

[0036] a diffusion barrier layer covering the interlayer dielectric layer and exposing the top of the cathode conductive column so that the OLED pixel structure is electrically connected to the cathode conductive column;

[0037] The black matrix fills the gaps between adjacent OLED pixel structures.

[0038] A peripheral electrode formed in the pixel wafer and located in a peripheral region outside the pixel region;

[0039] The peripheral pad penetrates the interlayer dielectric layer of the peripheral area from the back side of the pixel chip and is electrically connected to the peripheral electrode.

[0040] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0041] 1. First, the driving circuit and the pixel circuit are made separately. Specifically, the driving circuit is manufactured on the driving wafer, and the pixel cathode and related peripheral electrodes are manufactured on the pixel wafer. Then, the two wafers are bonded together by introducing a hybrid bonding process to electrically connect the driving circuit to the pixel cathode. Then, the pixel cathode is led out to the back of the pixel wafer through a through silicon via (TSV) process to electrically connect to the OLED pixel structure formed on the back of the pixel wafer. This eliminates the need for routing the driving circuit to the OLED pixel structure when the driving circuit and the OLED pixel structure are integrated on the same wafer plane, reduces the routing length, enables the driving circuit to directly control the OLED pixel structure point-to-point, greatly reduces the RC delay, improves the refresh rate, and significantly increases the operating frequency of the OLED micro display device.

[0042] 2. The driver wafer and the pixel wafer are stacked and packaged together. Compared with integrating the driver circuit and the OLED pixel structure on the same wafer plane, the area of ​​the OLED micro display device of the present invention is greatly reduced, and an ultra-narrow frame can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0044] Figure 1 It is a schematic diagram of the top view structure of an existing silicon-based OLED microdisplay device.

[0045] Figure 2 It is a schematic flow chart of a method for manufacturing an OLED micro-display device according to a specific embodiment of the present invention.

[0046] Figures 3 to 8 It is a schematic diagram of the cross-sectional structure of a device in a method for manufacturing an OLED micro-display device according to a specific embodiment of the present invention. DETAILED DESCRIPTION

[0047] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0049] Please refer to Figure 2 An embodiment of the present invention provides a method for manufacturing an OLED micro display device, which comprises the following steps:

[0050] S1, providing a driving wafer and a pixel wafer, wherein the driving wafer has a driving circuit inside, and the pixel wafer has a plurality of pixel cathodes inside, and the pixel cathodes are located in a pixel area of ​​the pixel wafer;

[0051] S2, forming a first bonding dielectric layer and a first metal contact on the driving wafer, and forming a second bonding dielectric layer and a second metal contact on the front side of the pixel wafer, wherein the bottom of the first metal contact is electrically connected to the driving circuit and the top is exposed by the first bonding dielectric layer, and the bottom of the second metal contact is electrically connected to the corresponding pixel cathode and the top is exposed by the second bonding dielectric layer;

[0052] S3, placing the pixel wafer upside down on the driving wafer for hybrid bonding, so that the first bonding medium layer and the second bonding medium layer are bonded together, and the corresponding first metal contact and the second metal contact are bonded together to form a bonded wafer;

[0053] S4, covering the back side of the pixel wafer with an interlayer dielectric layer, and forming a corresponding cathode conductive column on the back side of the pixel wafer by a through silicon via process, wherein the cathode conductive column penetrates the interlayer dielectric layer of the pixel region and is electrically connected to the corresponding pixel cathode at the bottom;

[0054] S5, forming a plurality of OLED pixel structures on the back side of the pixel wafer, wherein the OLED pixel structures are located in the pixel area and are electrically connected to the top of the corresponding cathode conductive pillar;

[0055] S6, cutting and packaging the bonded wafer to form an OLED micro display device.

[0056] Please refer to Figure 3 In step S1, two wafers of any suitable semiconductor material in the art, such as silicon, silicon carbide, silicon germanium, gallium arsenide, indium gallium arsenide, gallium nitride, mercury telluride or indium phosphide, are provided. The materials of the two wafers can be the same or different; a driving circuit (not shown) is manufactured in one wafer according to the CMOS process to form a driving wafer 100, and a plurality of pixel cathodes 202R, 202G, 202B and peripheral electrodes 202P are manufactured in the other wafer to form a pixel wafer 200.

[0057] Among them, the driving circuit in the driving wafer 100 is used to control and drive the OLED pixel structure formed on the pixel wafer 200, which may include a row driving circuit for providing a row scanning signal, a column driving circuit for providing a column scanning signal, a data driving circuit for providing a data signal, an emission driving circuit for providing an emission control signal, a timing control circuit for controlling the working timing of the row driving circuit, the column driving circuit, the data driving circuit and the emission driving circuit, etc. The driving circuit can also be further formed by a multi-layer metal interconnection process. The metal wirings may include a row scanning line electrically connected to the row driving circuit, a column scanning line electrically connected to the column driving circuit, a data line electrically connected to the data driving circuit, an emission control line electrically connected to the emission driving circuit, a power line for connecting to an external power supply, and other signal lines.

[0058] Several pixel cathodes 202R, 202G, and 202B are located in the pixel region of the pixel wafer 200, and the number of various pixel cathodes depends on the display requirements such as the resolution of the OLED micro display device to be formed. These pixel cathodes are arranged according to the pixel array required in the pixel region of the OLED micro display device. The peripheral electrode 202P is formed in the peripheral region (located at the periphery of the pixel region) of the pixel wafer 200, and the peripheral electrode 202P is used for the peripheral pad required for the subsequent external OLED micro display device.

[0059] In one example, the peripheral electrode 202P in the peripheral area and the pixel cathode 202R, 202G, 202B in the pixel area are arranged on the same layer, and both can be arranged by the same process. The peripheral electrode 202P and the pixel cathode can be a single-layer film structure or a structure formed by stacking multiple films. For example, the pixel cathode includes at least one material selected from zirconium, chromium, titanium, molybdenum, titanium nitride, zirconium nitride, chromium nitride, titanium aluminum nitride (TiAlN), aluminum, magnesium, gold, and silver.

[0060] It is also worth noting that the structure of the peripheral electrode 202P may include at least one of a dot-shaped or island-shaped structure, a small amount of peripheral metal wiring, and a small amount of peripheral circuits. The peripheral electrode 202P may be connected to the corresponding pixel electrode in a partial area of ​​the pixel wafer 200 .

[0061] As an example, any one or more metal wirings of the row scan lines, column scan lines, data lines, emission control lines, power lines, timing control lines, etc. required by the OLED microdisplay device are not arranged on the driving wafer 100, but are arranged on the pixel wafer 200 and serve as part or all of the peripheral electrode 202P.

[0062] As an example, the line width of the metal wiring in the driving circuit is 0.3 μm to 0.8 μm, and the pixel size (pitch) corresponding to the pixel cathode is 1 μm to 3 μm.

[0063] Please continue to refer to Figure 3In step S2, the driving wafer 100 and the pixel wafer 200 are subjected to hybrid bonding pre-processing by any appropriate process, so as to form a first bonding medium layer 101 and first metal contacts 101a-101c on the driving wafer 100 (thereby forming the bonding surface of the driving wafer 100), and to form a second bonding medium layer 201 and second metal contacts 201a-201c on the front side of the pixel wafer 200 (thereby forming the bonding surface of the pixel wafer 200). In this step, the driving wafer 100 may be subjected to hybrid bonding pre-processing first, and then the pixel wafer 200 may be subjected to hybrid bonding pre-processing; the pixel wafer 200 may be subjected to hybrid bonding pre-processing first, and then the driving wafer 100 may be subjected to hybrid bonding pre-processing; and the driving wafer 100 and the pixel wafer 200 may be subjected to hybrid bonding pre-processing at the same time.

[0064] Optionally, in step S2, that is, before hybrid bonding, the bonding surface of the driving wafer 100 is thinned during or after forming the first metal contacts 101a~101c, or the bonding surface of the pixel wafer 200 is thinned during or after forming the second metal contacts 201a~201c.

[0065] As an example, the process of performing hybrid bonding pre-processing on the driver wafer 100 includes: firstly, forming a first bonding dielectric layer 101 of any suitable material such as silicon oxide on the driver wafer 100 through any suitable film forming process such as chemical vapor deposition process, and etching the first bonding dielectric layer 101 to form a plurality of first openings (not shown), then filling the first openings with a metal such as copper through a process such as electroplating, and further performing chemical mechanical polishing (CMP) on the electroplated metal to form a plurality of first metal contacts 101a to 101b corresponding to the pixel cathodes 202R, 202G, and 202B. 101c, and the surface jointly formed by the first bonding dielectric layer 101 and the first metal contacts 101a~101c is the bonding surface of the driving wafer 100, the process of chemical mechanical polishing the first bonding dielectric layer 101 is also the process of thinning the bonding surface of the driving wafer 100, the thickness of the remaining first bonding dielectric layer 101 after CMP meets the bonding requirements, the bottoms of each first metal contact 101a~101c are respectively electrically connected to the corresponding parts of the driving circuit, and the tops of each first metal contact 101a~101c are exposed by the first bonding dielectric layer 101.

[0066] As another example, the process of performing hybrid bonding pre-processing on the driver wafer 100 includes: firstly forming a plurality of first metal contacts 101a-101c corresponding to the pixel cathodes 202R, 202G, and 202B on the driver wafer 100 through any suitable process such as a metal lift-off process or a process of first electroplating metal and then etching, wherein the bottom of each first metal contact 101a-101c is electrically connected to the corresponding part of the driver circuit respectively; then forming a first bonding dielectric layer 101 covering the driver wafer 100 and the first metal contacts 101a-101c through any suitable process such as chemical vapor deposition; and then performing a bonding process on the covered first metal contacts 101a-101c. A bonding dielectric layer 101 is subjected to chemical mechanical polishing (CMP) so that the tops of the first metal contacts 101a to 101c are exposed by the first bonding dielectric layer 101, and the surface formed by the first bonding dielectric layer 101 and the first metal contacts 101a to 101c is the bonding surface of the driver wafer 100. The process of chemical mechanical polishing the first bonding dielectric layer 101 is also the process of thinning the bonding surface of the driver wafer 100. The thickness of the remaining first bonding dielectric layer 101 after CMP meets the bonding requirements.

[0067] The above method can be used to form a second bonding dielectric layer 201 and a plurality of second metal contacts 201a-201c on the pixel wafer 200. For example, a second bonding dielectric layer 201 of any suitable material such as silicon oxide is formed on the pixel wafer 200 by any suitable film forming process such as chemical vapor deposition process, and the second bonding dielectric layer 201 is etched to form a plurality of openings (not shown) corresponding to the corresponding pixel cathodes 202R, 202G, and 202B. Then, a metal such as copper is filled in these openings by a process such as electroplating, and The electroplated metal is further subjected to chemical mechanical polishing (CMP) to form a plurality of second metal contacts 201a-201c corresponding to the pixel cathodes 202R, 202G, and 202B, and the surface jointly formed by the second bonding medium layer 201 and the second metal contacts 201a-201c is the bonding surface of the pixel wafer 200. The process of chemical mechanical polishing the second bonding medium layer 201 is also the process of thinning the bonding surface of the pixel wafer 200. The thickness of the remaining second bonding medium layer 201 after CMP meets the bonding requirements.

[0068] Among them, each second metal contact 201a~201c corresponds to the corresponding pixel cathode 202R, 202G, 202B respectively, and the bottom of each second metal contact 201a~201c is electrically connected to the corresponding pixel cathode 202R, 202G, 202B, and the top of each second metal contact 201a~201c is exposed by the second bonding medium layer 201.

[0069] Please continue to refer to Figure 3 In step S3, the pixel wafer 200 is first placed upside down on the driving wafer 100, and the first bonding medium layer 101 and the second bonding medium layer 201 are in contact, and the corresponding first metal contacts and the second metal contacts are aligned and in contact; then high-temperature annealing is performed to perform a hybrid bonding operation, so that the first bonding medium layer 101 and the second bonding medium layer 201 are bonded together by melting or condensation reaction, etc., and the corresponding first metal contacts and the second metal contacts are bonded together by metal diffusion. Thus, the two wafers are stacked and bonded together to form a bonded wafer.

[0070] In this embodiment, the first metal contact 101a and the second metal contact 201a are bonded together, the first metal contact 101b and the second metal contact 201b are bonded together, and the first metal contact 101c and the second metal contact 201c are bonded together, thereby electrically connecting the driving circuit in the driving wafer 100 and the corresponding pixel cathode in the pixel wafer 200.

[0071] In step S4, any suitable process may be used to form the interlayer dielectric layer 300 and the cathode conductive pillar 301. As an example, the specific process of step S4 includes:

[0072] First, please refer to Figure 4 The back side of the pixel wafer 200 is thinned by any suitable process or a combination of processes such as wet etching or chemical mechanical polishing (CMP) to a suitable thickness so as to ensure that the pixel cathode and other structures are not damaged while ensuring the implementation of the subsequent back through silicon via (TSV) process. As an example, the pixel wafer 200 is thinned to 1 μm to 3 μm.

[0073] Next, please refer to Figure 5 , an interlayer dielectric layer 300 is deposited on the back side of the pixel wafer 200. The interlayer dielectric layer 300 may be any suitable dielectric material, such as plasma enhanced oxide or tetraethyl orthosilicate TEOS, etc., which may be used as a stop layer for subsequent through silicon via processes and as an isolation layer between the photoresist and the pixel wafer 200 in subsequent photolithography processes. The thickness of the interlayer dielectric layer 300 is, for example, 1000 Å.

[0074] Then, please continue to refer to Figure 5, a photoresist is coated on the interlayer dielectric layer 300, and a through silicon hole mask is used to perform photolithography (including exposure, development, etc.) on the photoresist to form a patterned photoresist, and then the positions of each through silicon hole distributed and aligned with the corresponding pixel cathode are defined in the pixel area of ​​the pixel wafer 200; further, the interlayer dielectric layer 300 and a portion of the thickness of the pixel wafer 300 are sequentially etched with the patterned photoresist as a mask to expose the top of the corresponding pixel cathode, thereby forming a corresponding through silicon hole (i.e., cathode connection hole) 301a. Among them, the through silicon hole 301a can be set one-to-one with the pixel cathode, or multiple pixel cathodes can share one through silicon hole 301a for connection, and the driving circuit has a multiplexer (MUX) circuit corresponding to the shared through silicon hole 301a, thereby realizing the control of the pixel cathode (or OLED pixel structure) corresponding to the shared through silicon hole 301a. The critical size of the through silicon hole 301a is, for example, 0.5μm to 3μm.

[0075] Afterwards, please refer to Figure 6 , electroplating and deposition of metals such as copper are performed through processes such as seed layer deposition and electroplating (ECP), thereby filling each TSV 301a with the corresponding metal, and further using the interlayer dielectric layer 300 as a stop layer, CMP is performed on the deposited metal, thereby forming cathode conductive pillars 301 filled in each TSV 301a. Each cathode conductive pillar 301 is formed in the pixel region and penetrates the interlayer dielectric layer 300, and the bottom is electrically connected to the corresponding pixel cathode, thereby leading the corresponding pixel cathode outward from the back side of the pixel wafer 200.

[0076] As an example, after executing step S4 and before executing the subsequent step S5, a diffusion barrier layer 302 may be formed on the interlayer dielectric layer 300 and the cathode conductive pillar 301 by any suitable process such as chemical vapor deposition. The diffusion barrier layer 302 may bury the interlayer dielectric layer 300 and the cathode conductive pillar 301 and prevent the cathode conductive pillar 301 from diffusing into a film layer formed subsequently.

[0077] Optionally, refer to Figure 7 After forming the diffusion barrier layer 302 and before executing the subsequent step S5, a peripheral pad 303 is further formed on the back side of the pixel wafer 200. The peripheral pad 303 sequentially penetrates the diffusion barrier layer 302, the interlayer dielectric layer 300 and a partial thickness of the pixel wafer 200 from the back side of the pixel wafer 200, and is electrically connected to the peripheral electrode 202P in the peripheral area of ​​the pixel wafer 200.

[0078] As an example, the steps of forming the peripheral pad 303 include:

[0079] First, please refer to Figure 6The diffusion barrier layer 302, the interlayer dielectric layer 300 and a portion of the thickness of the pixel wafer 200 on the peripheral area of ​​the pixel wafer 200 are opened by photolithography and etching processes to form contact holes 303a that expose at least a portion of the surface of the peripheral electrode 202P. The number and position of the contact holes 303a depend on the requirements of the OLED micro display device that is finally formed.

[0080] Then, please refer to Figure 7 The contact hole 303a is filled by depositing a second metal such as AL, and the deposited second metal is etched or chemically mechanically polished to remove the second metal in the pixel area and excess second metal around the contact hole 303a.

[0081] Next, a passivation layer 304 is formed on the diffusion barrier layer 302 and the remaining second metal by any suitable process such as chemical vapor deposition, and the passivation layer is photolithographically and etched to remove the passivation layer 304 in the pixel area and open the passivation layer 304 on the top of the contact hole 303a to expose at least a portion of the top surface of the second metal filled in the contact hole 303a, thereby forming a peripheral pad 303 filled in the contact hole 303a and exposed by the passivation layer 304. The material of the passivation layer 304 can be any suitable material, such as a silicon nitride film, a silicon oxide film, or a combination of a silicon nitride film and a silicon oxide film.

[0082] It should be understood that the peripheral pad 303 leads the peripheral electrode 202P to the back of the pixel wafer 200, and the peripheral pad 303 can be a pin or other structure of the OLED micro display device that is finally formed, such as a pin connecting a row scan line, a pin connecting a data line, a pin connecting a power line, a pin connecting an emission control line, etc.

[0083] In step S5 , a plurality of OLED pixel structures 306R, 306G, 306B are formed on the diffusion barrier layer 302 in the pixel region by any appropriate process, and each OLED pixel structure 306R, 306G, 306B is electrically connected to the top of the corresponding cathode conductive column 301 .

[0084] As an example, the process of step S5 includes:

[0085] First, please refer to Figure 7 , through photolithography and etching processes, the diffusion barrier layer 302 on the top of each cathode conductive column 301 in the pixel area is opened to expose the top of each cathode conductive column 301.

[0086] Then, please refer to Figure 8, a highly reflective cathode metal material layer 305 such as aluminum, magnesium, gold or silver is deposited through processes such as physical vapor deposition, and the cathode metal material layer 305 is etched to achieve separation of the cathode metal material layer 305 between different pixel structures.

[0087] Next, any suitable one or more processes such as mask evaporation or inkjet printing are used to sequentially form organic semiconductor layers such as a hole injection layer (not shown), a hole transport layer (not shown), an organic light-emitting layer (not shown), an electron transport layer (not shown), and an electron injection layer (not shown) on the high-reflective cathode metal material layer 305 in the pixel area, as well as an anode material layer (not shown) and a thin film encapsulation layer (not shown), thereby forming an OLED pixel function layer stacked by the high-reflective cathode metal material layer 305, the organic semiconductor layer, the anode material layer and the thin film encapsulation layer. Among them, the anode material layer is a semi-transparent film, which can include at least one of Ag, Au, Mg, Al, Ca, Yb, indium tin oxide ITO, indium zinc oxide IZO or zinc aluminum oxide AZO and the like. As an example, the organic light-emitting layer is a single-color light-emitting layer to achieve a monochrome display function. As another example, within the plane of the bonded wafer, the organic light-emitting layer may also be composed of light-emitting layers of multiple different colors (e.g., red R, green G, blue B, etc.) to provide a color display. For example, the organic light-emitting layer includes a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, etc., and may even further include a white light-emitting layer, a yellow light-emitting layer, and other light-emitting layers. These light-emitting layers of different colors may be arranged in parallel and spaced apart, or may be arranged in series.

[0088] Afterwards, a color filter layer (not shown, also referred to as a color filter) is formed on the thin film encapsulation layer. The color filter layer is an optical filter that expresses color. It can accurately select a small range of light waves to be passed through, and reflect other undesirable bands. As an example, a black matrix 307 and a color filter layer (not shown) are coated on the OLED pixel function layer. The black matrix 307 is located between two adjacent color filter layers, thereby forming a number of OLED pixel structures 306R, 306G, and 306B, and the black matrix is ​​filled in the gaps between adjacent OLED pixel structures. The color filter layer may include a red filter unit, a green filter unit, and a blue filter unit to respectively form a red sub-pixel (R pixel), a green sub-pixel (G pixel), and a blue sub-pixel (B pixel) with the OLED pixel function layer below. When the organic light-emitting layer in the OLED pixel function layer includes a red light-emitting layer, a green light-emitting layer, and a blue light-emitting layer, the color of each filter unit in the color filter layer is the same as the light-emitting color of the corresponding organic light-emitting layer.

[0089] Then, a protective layer (not shown) or a protective cover (not shown) may be further formed on the surface of the color filter layer.

[0090] It should be understood that in some examples, it is not necessary to form a color filter layer or other structures.

[0091] In step S6, the bonded wafer processed in step S5 can be taped out to an IC packaging factory for cutting and packaging to form an ultra-narrow frame OLED micro display device.

[0092] The manufacturing method of the OLED micro display device of this embodiment realizes the stacking of the driving wafer and the pixel wafer through the hybrid bonding process and the silicon through hole process, and enables the driving circuit in the driving wafer to point-to-point control the OLED pixel structure on the pixel wafer. Therefore, the prepared OLED micro display device has the advantages of short wiring, small delay (RC delay), fast refresh frequency, small area, narrow frame, etc.

[0093] Based on the same inventive concept, an embodiment of the present invention further provides an OLED micro display device, which is preferably manufactured using the manufacturing method of the OLED micro display device of the present invention. Figure 8 , the OLED micro display device comprises:

[0094] A driver chip (i.e., a portion obtained by cutting the driver wafer 100), wherein a driver circuit (not shown) is provided inside the driver chip, and a first bonding dielectric layer 101 and a plurality of first metal contacts 101a-101c are formed on the driver chip, wherein the bottom of the first metal contacts 101a-101c is electrically connected to the driver circuit and the top is exposed by the first bonding dielectric layer 101;

[0095] A pixel chip (i.e., a portion obtained by cutting the driver wafer 200), wherein the pixel chip is invertedly stacked on the driver chip and has a plurality of pixel cathodes 202R, 202G, and 202B inside, wherein the pixel cathodes 202R, 202G, and 202B are located in a pixel region of the pixel chip, and a second bonding medium layer 201 and second metal contacts 201a-201c are formed on the front side of the pixel wafer, wherein the bottom of the second metal contacts 201a-201c are electrically connected to the corresponding pixel cathodes and the top is exposed by the second bonding medium layer 201, wherein the second bonding medium layer 201 and the first bonding medium layer 101 are bonded together, and the corresponding second metal contacts 201a-201c and the first metal contacts 101a-101c are bonded together, so that the front side of the pixel chip and the driver chip are hybrid-bonded together;

[0096] An interlayer dielectric layer 300, covering the back side of the pixel chip;

[0097] A cathode conductive column 301 extends from the back side of the pixel chip through the interlayer dielectric layer 300 of the pixel region and is electrically connected to the corresponding pixel cathodes 202R, 202G, 202B at the bottom;

[0098] A plurality of OLED pixel structures 306R, 306G, and 306B are formed on the back side of the pixel wafer. The OLED pixel structures 306R, 306G, and 306B are located in the pixel region and are electrically connected to the top of the corresponding cathode conductive pillar 301 .

[0099] Optionally, the OLED micro display device further includes at least one of the following structures:

[0100] A passivation layer 304 is formed on the interlayer dielectric layer 300 in the peripheral region and exposes at least a portion of the top surface of the corresponding peripheral pad 303;

[0101] a diffusion barrier layer 302 covering the interlayer dielectric layer 300 and exposing the top of the cathode conductive column 301 so that the bottom of the OLED pixel structure 306R, 306G, 306B is electrically connected to the top of the corresponding cathode conductive column 301;

[0102] The black matrix 307 fills the gaps between the adjacent OLED pixel structures 306R, 306G, and 306B.

[0103] A peripheral electrode 202P, formed in the pixel wafer and located in a peripheral region outside the pixel region;

[0104] The peripheral pad 303 penetrates through the interlayer dielectric layer 300 in the peripheral region from the back side of the pixel chip and is electrically connected to the peripheral electrode 202P.

[0105] The material selection, shape, size and other features of the various structures in the OLED micro display device of this embodiment all depend on the performance and design requirements of the OLED micro display device. For details, please refer to the manufacturing method of the OLED micro display device above and will not be repeated here.

[0106] In the OLED micro display device of this embodiment, the pixel chip and the driver chip are hybrid-bonded together, so that the driving circuit in the driver chip can point-to-point control the OLED pixel structure on the pixel chip. Compared with the existing OLED micro display device in which the driving circuit and the OLED pixel structure are integrated on the same wafer plane, it has the advantages of short wiring, small delay (RC delay), and fast refresh frequency. In addition, the area of ​​the OLED micro display device is greatly reduced, and an ultra-narrow frame can be obtained.

[0107] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A method for manufacturing an OLED micro display device, characterized in that: include: Providing a driving wafer and a pixel wafer, wherein the driving wafer has a driving circuit inside, and the pixel wafer has a plurality of pixel cathodes inside, and the pixel cathodes are located in a pixel area of ​​the pixel wafer; Forming a first bonding dielectric layer and a first metal contact on the driving wafer, and forming a second bonding dielectric layer and a second metal contact on the front side of the pixel wafer, wherein the bottom of the first metal contact is electrically connected to the driving circuit and the top is exposed by the first bonding dielectric layer, and the bottom of the second metal contact is electrically connected to the corresponding pixel cathode and the top is exposed by the second bonding dielectric layer; Inverting the pixel wafer onto the driving wafer for hybrid bonding, so that the first bonding medium layer and the second bonding medium layer are bonded together, and the corresponding first metal contact and the second metal contact are bonded together to form a bonded wafer; An interlayer dielectric layer is covered on the back side of the pixel wafer, and a corresponding cathode conductive column is formed on the back side of the pixel wafer by a through silicon via process, wherein the cathode conductive column penetrates the interlayer dielectric layer of the pixel region and is electrically connected to the corresponding pixel cathode at the bottom; Forming a plurality of OLED pixel structures on the back side of the pixel wafer, wherein the OLED pixel structures are located in the pixel area and are electrically connected to the top of the corresponding cathode conductive column; The bonded wafer is cut and packaged to form an OLED micro display device.

2. The manufacturing method according to claim 1, characterized in that The first metal contact and the second metal contact are both copper contacts, with a critical dimension of 0.3 μm to 0.8 μm, and the critical dimension of the pixel cathode is 1 μm to 3 μm.

3. The manufacturing method according to claim 1, characterized in that: Before hybrid bonding, the bonding surfaces of the driving wafer and the pixel wafer are both thinned; or, after hybrid bonding, thinning is performed from the back side of the pixel wafer to thin the pixel wafer to 1 μm to 3 μm.

4. The manufacturing method according to claim 1, characterized in that: The step of forming a corresponding cathode conductive column on the back side of the pixel wafer by a through silicon via process comprises: Coating a photoresist on the interlayer dielectric layer on the back side of the pixel wafer, and photolithography the photoresist using a corresponding through silicon hole mask to form a patterned photoresist; Using the patterned photoresist as a mask, etching the interlayer dielectric layer and the back side of the pixel wafer until the corresponding pixel cathode is exposed to form a corresponding plurality of through silicon vias; The first metal is filled into the silicon through hole and chemical mechanical polishing is performed using the interlayer dielectric layer as a stop layer to form the cathode conductive column.

5. The manufacturing method according to claim 1, characterized in that: After forming the cathode conductive column and before forming the OLED pixel structure, a diffusion barrier layer is further formed to bury the interlayer dielectric layer and the cathode conductive column.

6. The manufacturing method according to claim 5, characterized in that: The step of forming the OLED pixel structure on the back side of the pixel wafer comprises: Opening the diffusion barrier layer of the pixel region by photolithography and etching processes to expose the top surface of the cathode conductive column; A high reflectivity cathode material layer, an organic semiconductor layer, a semi-transparent anode layer and a thin film encapsulation layer are sequentially formed on the diffusion barrier layer in the pixel area and the exposed cathode conductive column thereof to form an OLED pixel functional layer.

7. The manufacturing method according to claim 1, characterized in that: The pixel wafer provided further has a peripheral electrode formed therein, the peripheral electrode being formed in a peripheral region outside the pixel region; After forming the cathode conductive column and before or after forming the OLED pixel structure, the manufacturing method further includes: forming a peripheral pad on the back side of the pixel wafer, wherein the peripheral pad penetrates the interlayer dielectric layer and is electrically connected to the peripheral electrode.

8. The manufacturing method according to claim 7, characterized in that: The steps of forming the peripheral pad include: Opening the interlayer dielectric layer in the peripheral area and a portion of the thickness of the pixel wafer by photolithography and etching processes to form a contact hole exposing at least a portion of the surface of the peripheral electrode; Filling a second metal in the contact hole; A passivation layer is deposited on the second metal and the interlayer dielectric layer, and the passivation layer is etched to expose at least a portion of the top of the second metal to form the peripheral pad.

9. An OLED micro display device, characterized in that: include: A driver chip, wherein a driver circuit is provided inside the driver chip, and a first bonding dielectric layer and a first metal contact are formed on the driver chip, wherein the bottom of the first metal contact is electrically connected to the driver circuit and the top is exposed by the first bonding dielectric layer; A pixel chip, wherein the pixel chip is invertedly stacked on the driver chip and has a plurality of pixel cathodes inside, wherein the pixel cathodes are located in the pixel area of ​​the pixel chip, a second bonding medium layer and a second metal contact are formed on the front side of the pixel chip, the bottom of the second metal contact is electrically connected to the corresponding pixel cathode and the top is exposed by the second bonding medium layer, the second bonding medium layer and the first bonding medium layer are bonded together, and the corresponding second metal contact and the first metal contact are bonded together, so that the front side of the pixel chip is hybrid-bonded with the driver chip; An interlayer dielectric layer covering the back side of the pixel wafer; A cathode conductive column, extending from the back side of the pixel wafer through the interlayer dielectric layer of the pixel region and electrically connected to the corresponding cathode conductive column; A plurality of OLED pixel structures are formed on the back side of the pixel wafer. The OLED pixel structures are located in the pixel region and are electrically connected to the top of the corresponding cathode conductive column.

10. The OLED micro display device according to claim 9, characterized in that: Also includes at least one of the following structures: a passivation layer formed on the interlayer dielectric layer in the peripheral region and exposing at least a portion of a top surface of a corresponding peripheral pad; a diffusion barrier layer covering the interlayer dielectric layer and exposing the top of the cathode conductive column so that the OLED pixel structure is electrically connected to the cathode conductive column; The black matrix fills the gaps between adjacent OLED pixel structures. A peripheral electrode formed in the pixel wafer and located in a peripheral region outside the pixel region; The peripheral pad penetrates the interlayer dielectric layer of the peripheral area from the back side of the pixel chip and is electrically connected to the peripheral electrode.

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