Phase frequency detector, phase-locked loop and chip

Abstract

The invention discloses a phase frequency detector, a phase-locked loop and a chip. The phase frequency detector comprises N sub-modules. Each sub-module comprises a first trigger, a second trigger, a third trigger, an AND gate, a first switch unit and a first phase inverter. In the N sub-modules, a control end of a first switch unit of a first sub-module is connected with a first reset signal, a first end is connected with a first power supply signal, and a second end is connected with an output end of an AND gate in the first sub-module; the control end of the first switch unit in the ith sub-module is connected with a second reset signal, the first end is connected with the output end of the AND gate in the ith sub-module, and the second end is connected with a second power supply signal; the input end of the first phase inverter in the ith sub-module is connected with the output end of the AND gate in the ith sub-module, and the output end of the first phase inverter in the ith sub-module is connected with the setting end of the third trigger in the (i + 1) th sub-module. According to the invention, the phase discrimination range of the phase frequency detector can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a frequency detector, a phase-locked loop and a chip. Background Art

[0002] Phase Locked Loop (PLL) is widely used in clock generation, signal recovery, frequency synthesis and other occasions. PLL is an indispensable part in high-speed integrated circuits.

[0003] PLL is mainly composed of a phase frequency detector (PFD), a charge pump (CP), a loop filter (LPF), a voltage controlled oscillator (VCO) and a divider (DIV).

[0004] Among them, PFD is used to detect the frequency and phase of the input reference signal and the feedback signal, and generate a switch control signal for the charge and discharge current of the subsequent CP. Under the action of this control signal, CP charges and discharges the LPF, causing the tuning voltage of the VCO to change accordingly, thereby changing the resonant frequency of the VCO. The VCO oscillation output signal is divided by DIV and participates in frequency and phase discrimination, thereby forming a closed-loop feedback system to achieve the phase-locked frequency multiplication function.

[0005] However, the PFD in the prior art has the problem of small phase detection range. Summary of the invention

[0006] The invention provides a phase frequency detector, a phase locked loop and a chip, which can improve the phase detection range of a PFD.

[0007] In a first aspect, the present invention provides a frequency detector and phase detector, comprising: N submodules, N is an integer greater than or equal to 2; the submodules include a first trigger, a second trigger, a third trigger, an AND gate, a first switch unit and a first inverter; the first trigger is used to receive a reference clock signal and output a first trigger signal; the second trigger is used to receive a feedback clock signal and output a second trigger signal; the AND gate is used to receive the first trigger signal and the second trigger signal, and generate a first control signal according to the first trigger signal and the second trigger signal, which is input to the trigger input terminal of the third trigger; the third trigger is used to receive the first control signal, and output the second control signal to the reset terminal of the first trigger and the reset terminal of the second trigger; in the N submodules, the control terminal of the first switch unit of the first submodule is connected to the first reset signal, the first terminal is connected to the first power supply signal, and the second terminal is connected to the first The output end of the AND gate in the submodule is connected, and is used to be turned on when the first reset signal is a valid level signal; the control end of the first switch unit in the ith submodule is connected to the second reset signal, the first end is connected to the output end of the AND gate in the ith submodule, and the second end is connected to the second power supply signal, and is used to be turned on when the second reset signal is a valid level signal; the set end of the third trigger in the 1st submodule is connected to the output end of the first inverter in the Nth submodule, and the input end of the first inverter in the Nth submodule is connected to the output end of the AND gate in the Nth submodule; the input end of the first inverter in the ith submodule is connected to the output end of the AND gate in the ith submodule, and the output end of the first inverter in the ith submodule is connected to the set end of the third trigger in the (i+1)th submodule; wherein i is an integer greater than or equal to 1 and less than or equal to N-1.

[0008] Optionally, the submodule also includes a first delay control module, the input end of the first delay control module is connected to the output end of the AND gate, and the output end of the first delay control module is connected to the trigger input end of the third trigger, for delaying the first control signal and controlling the delay duration of the first control signal.

[0009] Optionally, the first delay control module includes M delay units and M second switch units; M is an integer greater than or equal to 1; the delay unit and the Mth second switch unit are connected in series between the input end of the first delay control module and the output end of the first delay control module in sequence; the jth second switch unit is connected between the input end of the jth delay unit and the output end of the first delay control module; wherein j is an integer greater than or equal to 1 and less than or equal to M-1; the ath second switch unit is used to control whether the ath delay unit is working, so as to control the delay duration of the first control signal; wherein a is an integer greater than or equal to 1 and less than or equal to M.

[0010] Optionally, the submodule further includes a second inverter and a second delay control module; the second inverter is used to invert the first trigger signal and output a charging current control signal; the second delay control module is used to delay the second trigger signal and output a discharging current control signal.

[0011] Optionally, the submodule also includes a charging current control signal output terminal and a discharging current control signal output terminal, the charging current control signal output terminal is used to output the charging current control signal, and the discharging current control signal output terminal is used to output the discharging current control signal; the frequency detector and phase detector also include a charge pump, the charge pump includes N first branches, and N second branches connected to the output nodes with the N first branches, and the first branches are connected to the charging current control signal output terminal in a one-to-one correspondence, and the second branches are connected to the discharging current control signal output terminal in a one-to-one correspondence; the first branch is used to provide a charging current to the output node, and the second branch is used to provide a discharging current to the output node.

[0012] Optionally, the first branch includes a first switch tube and a first current source, the gate of the first switch tube is connected to the corresponding charging current control signal, the first pole of the first switch tube is connected to the second power supply signal, the second pole of the first switch tube is connected to the first end of the first current source, the second end of the first current source is connected to the output node, the first switch tube is used to selectively turn on according to the charging current control signal, when the first switch is turned on, the first branch is used to provide charging current to the output node; and / or, the second branch includes a second switch tube and a second current source, the gate of the second switch tube is connected to the corresponding discharge current control signal, the first pole of the second switch tube is connected to the second power supply signal, the second pole of the second switch tube is connected to the first end of the second current source, the second end of the second current source is connected to the output node, the second switch tube is used to selectively turn on according to the discharge current control signal, when the second switch tube is turned on, the second branch is used to provide discharge current to the output node.

[0013] Optionally, the charge pump further includes a first capacitor, a first end of the first capacitor is connected to the output node, and a second end of the first capacitor is connected to the first power signal.

[0014] Optionally, the feedback clock signal leads or lags behind the reference clock signal.

[0015] In a second aspect, the present invention provides a phase-locked loop, comprising a phase frequency detector provided by any embodiment of the present invention, the phase-locked loop also comprising a loop filter, a voltage-controlled oscillator and a frequency divider; the input end of the loop filter is connected to the output end of the phase frequency detector, and the output end of the loop filter is connected to the input end of the voltage-controlled oscillator; the voltage-controlled oscillator is used to output a first signal; the loop filter is used to generate a second signal according to a current signal generated by the phase frequency detector, and adjust the frequency of the first signal output by the voltage-controlled oscillator through the second signal; the input end of the frequency divider is connected to the output end of the voltage-controlled oscillator, and the frequency divider is used to divide the first signal output by the voltage-controlled oscillator to generate a feedback clock signal.

[0016] In a third aspect, an embodiment of the present invention provides a chip, comprising a phase-locked loop provided by an embodiment of the present invention, and also comprising a control module, the control module being communicatively connected to the phase-locked loop and being used to output a coded signal, and the coded signal being used to control the delay duration of an internal loop of a phase frequency detector in the phase-locked loop.

[0017] The frequency detector and phase detector provided by the embodiment of the present invention include N submodules, wherein the submodules include a first trigger, a second trigger, a third trigger, an AND gate, a first switch unit and a first inverter. By setting the control end of the first switch unit of the first submodule to be connected to the first reset signal, the first end to be connected to the first power supply signal, and the second end to be connected to the output end of the AND gate in the first submodule; the control end of the first switch unit in the i-th submodule to be connected to the second reset signal, the first end to be connected to the output end of the AND gate in the i-th submodule, and the second end to be connected to the second power supply signal; the set end of the third trigger in the 1st submodule to be connected to the output end of the first inverter in the N-th submodule, the input end of the first inverter in the N-th submodule to be connected to the output end of the AND gate in the N-th submodule; the input end of the first inverter in the i-th submodule to be connected to the output end of the AND gate in the i-th submodule, and the output end of the first inverter in the i-th submodule to be connected to the set end of the third trigger in the i+1-th submodule, the phase detection range can be improved, and the clock frequency of the input reference clock signal can be improved. That is to say, the PFD of the embodiment of the present invention has a high operating frequency and a large phase detection range.

[0018] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 It is a structural schematic diagram of a phase-locked loop provided by the relevant technology;

[0021] Figure 2 1 is a schematic diagram of the structure of a frequency and phase detector provided by an embodiment of the present invention;

[0022] Figure 3 is a structural schematic diagram of another frequency and phase detector provided by an embodiment of the present invention;

[0023] Figure 4 is a working timing diagram of a PFD provided by an embodiment of the present invention;

[0024] Figure 5 is another working timing diagram of a PFD provided by an embodiment of the present invention;

[0025] Figure 6 is a structural schematic diagram of another frequency and phase detector provided by an embodiment of the present invention;

[0026] Figure 7 is a structural schematic diagram of a first delay control module provided by an embodiment of the present invention;

[0027] Figure 8 is a structural schematic diagram of another frequency and phase detector provided by an embodiment of the present invention;

[0028] Fig. 9 is a schematic diagram of the structure of a phase-locked loop provided by an embodiment of the present invention;

[0029] Fig.10 It is a schematic diagram of the structure of a chip provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0032] As mentioned in the background technology, the existing PFD has the problem of small phase discrimination range. After careful research, the inventors found that the reasons for this technical problem are:

[0033] Figure 1 This is a schematic diagram of the structure of a phase-locked loop provided by the relevant technology. Figure 1 As shown, the PLL includes a frequency detector 110, a charge pump 120, a filter 130, a voltage controlled oscillator 140 and a frequency divider 150. The PLL is a negative feedback system. The PFD compares the feedback clock signal output by the frequency divider 150 with the reference clock signal REF1 to obtain a phase difference signal. The phase difference signal is processed by the charge pump 120 and the filter 130 and is used to control the first signal OUT1 output by the voltage controlled oscillator 140. When the phase and frequency of the feedback clock signal are the same as those of the reference clock signal REF1, the PLL loop is locked. At this time, the clock frequency of the first signal OUT1 output by the voltage controlled oscillator 140 is locked at N times the clock frequency of the reference clock signal REF1.

[0034] When the division ratio n of the divider 150 is higher, the clock frequency of the first signal output by the PLL is higher, but the noise introduced by the reference clock signal REF1, the frequency detector 110, the charge pump 120 and the divider 150 is proportional to the division ratio n. Therefore, in order to achieve a broadband low-jitter first signal output, the clock frequency of the reference clock signal should be increased and the division ratio n of the divider 150 should be reduced.

[0035] Assume that the time difference corresponding to the phase difference between the reference clock signal REF1 and the feedback clock signal FB1 is ΔT, and the fixed delay of the PFD internal loop is T D , the clock period of the reference clock signal is T CLK , if there is

[0036] ΔT+T D <T CLK (1)

[0037] Therefore, when the clock frequency Fclk of the reference clock signal of the PFD is too high, the clock period T CLKThe phase detection range ΔT of the PFD is compressed, and the PLL may not be able to lock. And from formula (1), it can be seen that when the clock period T of the reference clock signal CLK When the phase detection range of the phase frequency detector 11 is unchanged, it is limited by the internal loop delay of the PFD. In order to realize a wideband low-jitter PLL, a PFD with a high operating frequency and a large phase detection range is required.

[0038] In order to improve the phase detection range of PFD, the present invention proposes a novel PFD structure. Figure 2 It is a structural schematic diagram of a frequency and phase detector provided by an embodiment of the present invention. Figure 3 FIG. 1 is a schematic diagram of the structure of another frequency and phase detector provided by an embodiment of the present invention. Figure 2 and Figure 3 The frequency phase detector includes: N submodules 1, where N is an integer greater than or equal to 2; the submodule 1 includes a first trigger T1, a second trigger T2, a third trigger T3, an AND gate U1, a first switch unit 10 and a first inverter U2. Figure 3 The case where N is equal to 2 is schematically shown.

[0039] The first trigger T1 is used for receiving the reference clock signal CLK_REF and outputting a first trigger signal.

[0040] The second trigger T2 is used for receiving the feedback clock signal CLK_IN and outputting a second trigger signal.

[0041] The AND gate U1 is used for receiving the first trigger signal and the second trigger signal, and generating a first control signal Ctr1 according to the first trigger signal and the second trigger signal, and inputting the first control signal Ctr1 to the trigger input terminal CK of the third trigger T3 .

[0042] The third flip-flop T3 is used for receiving the first control signal Ctr1 and outputting the second control signal Ctr2 to the reset terminal RB of the first flip-flop T1 and the reset terminal RB of the second flip-flop T2.

[0043] In the N sub-modules 1, the control end of the first switch unit 10 of the first sub-module is connected to the first reset signal RST, the first end is connected to the first power supply signal VSS, and the second end is connected to the output end of the AND gate U1 in the first sub-module, and is used to be turned on when the first reset signal RST is a valid level signal.

[0044] The control end of the first switch unit 10 in the i-th submodule is connected to the second reset signal RSTN, the first end is connected to the output end of the AND gate U1 in the i-th submodule 12, and the second end is connected to the second power supply signal VDD, for being turned on when the second reset signal RSTN is a valid level signal.

[0045] The set end SB of the third trigger T3 in the 1st submodule is connected to the output end of the first inverter U2 in the Nth submodule, and the input end of the first inverter U2 in the Nth submodule is connected to the output end of the AND gate U1 in the Nth submodule.

[0046] The input end of the first inverter U2 in the i-th submodule is connected to the output end of the AND gate U1 in the i-th submodule, and the output end of the first inverter U2 in the i-th submodule is connected to the set end SB of the third trigger T3 in the i+1-th submodule; wherein i is an integer greater than or equal to 1 and less than or equal to N-1.

[0047] Specifically, the first power signal VSS may be a low level signal, and the second power signal VDD may be a high level signal. The feedback clock signal CLK_IN may be ahead of or behind the reference clock signal CLK_REF.

[0048] The first trigger T1, the second trigger T2 and the third trigger T3 can all be rising edge triggered D triggers. When the set terminals SB of the first trigger T1 and the second trigger are connected to a low level signal, the first output terminal Q of the first trigger T1 and the second trigger is set to 1, that is, the set terminals SB of the first trigger T1 and the second trigger T2 are low level valid. In the embodiment of the present invention, the set terminals SB of the first trigger T1 and the second trigger are both connected to the second power supply signal VDD, so the set terminals SB of the first trigger T1 and the second trigger T2 are always invalid.

[0049] Optionally, the data input terminals D of the first trigger T1 and the second trigger T2 are both connected to the second power signal VDD. The data input terminal D of the third trigger T3 is connected to the first power signal VSS. The second output terminals QB of the first trigger T1, the second trigger T2 and the third trigger T3 are suspended.

[0050] Optionally, the first switch unit 10 may include a switch device. By controlling the on and off of the switch device, the first power signal VSS or the second power signal VDD is output. The switch device may be a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), or a gallium nitride (GaN) transistor.

[0051] Figure 4 This is a working timing diagram of a PFD provided by an embodiment of the present invention. This working timing diagram can be applied to Figure 3 PFD shown. Combined Figure 3 and Figure 4 , the working process of the PFD is:

[0052] At the first moment t1, the first reset signal RST flips to 1, and the second reset signal RSTN flips to 0. At this time, the trigger input terminal CK and the set terminal SB of the second flip-flop T2 in the first submodule 11 are set to 0, and its first output terminal Q is set to 1, and it is ensured that the second flip-flop T2 in the first submodule 11 can generate a rising edge instead of a permanent high level when receiving the high level signal output by the AND gate U1 in the first submodule. The trigger input terminal CK and the set terminal SB of the second flip-flop T2 in the second submodule 12 are set to 1, the reset terminal RB is set to 0, and its first output terminal Q is set to 0. When the second reset signal RSTN is restored to 1, the entire PFD ends the reset state and enters the normal working mode. At this time, the first output terminal Q of the second flip-flop T2 in the second submodule 12 is always 0, that is, the first node EN <1> It is always 0, so that the first trigger T1 and the third trigger T3 in the second submodule 12 are in a reset state, and continuously output 0, and the second submodule 12 does not work. Among them, 1 represents a high level, and 0 represents a low level.

[0053] At the second time t2, the rising edge of the reference clock signal CLK_REF arrives, and the first trigger T1 in the first submodule 11 outputs a high level to the second node DN <0> .

[0054] At the third time t3, the rising edge of the feedback clock signal CLK_IN arrives, and the third trigger T3 in the first submodule 11 outputs a high level to the third node UP. <0> At the same time, the AND gate U1 before the second trigger T2 in the first submodule 11 triggers the input terminal CK to output a high level, so that the second trigger T2 in the first submodule 11 receives a rising edge, and its first output terminal Q outputs a low level 0 to the fourth node EN <0> , the first submodule 11 stops working, so that the first output terminal Q output of the first trigger T1 and the third trigger T3 in the first submodule 11 is reset to 0,

[0055] The first delay time from "the rising edge of the feedback clock signal CLK_IN arrives" to "resets the first output terminal Q of the first flip-flop T1 and the third flip-flop T3 in the first submodule 11 to 0" is Delay_0. At the same time, the high-level signal generated by the AND gate U1 in the first submodule 11 passes through the first inverter U2 in the first submodule 11 and reaches the set terminal SB of the second flip-flop T2 in the second submodule 12, resetting its first output terminal Q to a high level, that is, the first node EN <1> is high level, the second submodule 12 starts to work, and the second delay time from "arrival of the rising edge of the feedback clock signal CLK_IN" to "the first output terminal Q of the second flip-flop T2 in the second submodule 12 is reset to a high level" is Delay_1.

[0056] At the fourth time t4, the second node DN <0> And the third node UP <0> By the fourth node EN <0> Reset to 0.

[0057] At the fifth time t5, the second rising edge of the reference clock signal CLK_REF causes the third flip-flop T3 in the second submodule 12 to output a high level to the fifth node DN <1> .

[0058] At the sixth moment t6, the second rising edge of the feedback clock signal CLK_IN causes the first trigger T1 in the second submodule 12 to output a high level to the sixth node UP. <1> At the same time, the AND gate U1 connected to the second trigger T2 in the second submodule 12 generates a high level signal, and the second trigger T2 in the second submodule 12 receives the rising edge and outputs a low level 0 to the first node EN <1> , reset the first trigger T1 and the third trigger T3 in the second submodule 12 to a low level, and then start to repeat the reset process of the first submodule 11, and the high level generated by the AND gate U1 in the second submodule 12 is flipped by the first inverter U2 and outputs a low level to the set end SB of the second trigger T2 in the first submodule 12, so that the output of the second trigger T2 in the first submodule 12 is set to a high level 1, and the first submodule 11 is restarted.

[0059] Due to the use of an alternating phase-detection structure, the PFD can detect the phase of a reference clock signal CLK_REF with a higher frequency. It can be considered that as long as:

[0060] ΔT+T D <2T CLK (2)

[0061] Wherein, ΔT is the time difference between the reference clock signal CLK_REF and the feedback clock signal phase difference CLK_IN, T D is the phase detection range, T CLKis the clock period of the reference clock signal CLK_REF, then the PFD can perform phase detection normally. From formula (2), we can see that as the right side of the inequality increases, the phase detection range T D It can be larger, that is, the phase detection range of the PFD of the embodiment of the present invention is larger than the phase detection range of the PFD in the related art. If it is necessary to further increase the clock frequency of the reference clock signal CLK_REF of the PFD, more submodules 1 can be used for alternate phase detection, such as N submodules, whose working principle is similar to the alternate phase detection of two submodules 1, and the clock frequency of the reference clock signal CLK_REF of the PFD can be increased to N times to reduce the division ratio of DIV, thereby reducing the noise of the entire PLL.

[0062] Figure 5 This is another working timing diagram of a PFD provided by an embodiment of the present invention. This working timing diagram can also be applied to Figure 3 PFD shown. Combined Figure 3 and Figure 5 , the working process of the PFD is:

[0063] At the first moment t1, the first reset signal RST flips to 1, and the second reset signal RSTN flips to 0. At this time, the trigger input terminal CK and the set terminal SB of the second flip-flop T2 in the first submodule 11 are set to 0, and its first output terminal Q is set to 1, and it is ensured that the second flip-flop T2 in the first submodule 11 can generate a rising edge instead of a permanent high level when receiving the high level signal output by the AND gate U1 in the first submodule. The trigger input terminal CK and the set terminal SB of the second flip-flop T2 in the second submodule 12 are set to 1, the reset terminal RB is set to 0, and its first output terminal Q is set to 0. When the second reset signal RSTN is restored to 1, the entire PFD ends the reset state and enters the normal working mode. At this time, the first output terminal Q of the second flip-flop T2 in the second submodule 12 is always 0, that is, the first node EN <1> It is always 0, so that the first trigger T1 and the third trigger T3 in the second submodule 12 are in a reset state, and continuously output 0, and the second submodule 12 does not work. Among them, 1 represents a high level, and 0 represents a low level.

[0064] At the second moment t2, the rising edge of the feedback clock signal CLK_IN arrives, and the third trigger T3 in the first submodule 11 outputs a high level to the third node UP. <0> .

[0065] At the third time t3, the rising edge of the reference clock signal CLK_REF arrives, and the first flip-flop T1 in the first submodule 11 outputs a high level to the second node DN <0> At the same time, the AND gate U1 before the second trigger T2 in the first submodule 11 triggers the input terminal CK to output a high level, so that the second trigger T2 in the first submodule 11 receives a rising edge, and its first output terminal Q outputs a low level 0 to the fourth node EN <0> , the first submodule 11 stops working, so that the first output terminal Q output of the first trigger T1 and the third trigger T3 in the first submodule 11 is reset to 0,

[0066] The first delay time from "the rising edge of the reference clock signal CLK_REF arrives" to "the first output terminal Q of the first flip-flop T1 and the third flip-flop T3 in the first submodule 11 is reset to 0" is Delay_0. At the same time, the high-level signal generated by the AND gate U1 in the first submodule 11 passes through the first inverter U2 in the first submodule 11 and reaches the set terminal SB of the second flip-flop T2 in the second submodule 12, so that its first output terminal Q is reset to a high level, that is, the first node EN <1> is high level, the second submodule 12 starts to work, and the second delay time from "the rising edge of the reference clock signal CLK_REF arrives" to "the first output terminal Q of the second flip-flop T2 in the second submodule 12 is reset to a high level" is Delay_1.

[0067] At the fourth time t4, the second node DN <0> And the third node UP <0> By the fourth node EN <0> Reset to 0.

[0068] At the fifth time t5, the second rising edge of the feedback clock signal CLK_IN causes the first trigger T1 in the second submodule 12 to output a high level to the sixth node UP. <1> .

[0069] At the sixth time t6, the second rising edge of the reference clock signal CLK_REF causes the third flip-flop T3 in the second submodule 12 to output a high level to the fifth node DN <1> At the same time, the AND gate U1 connected to the second trigger T2 in the second submodule 12 generates a high level signal, and the second trigger T2 in the second submodule 12 receives the rising edge and outputs a low level 0 to the first node EN <1> , reset the first trigger T1 and the third trigger T3 in the second submodule 12 to a low level, and then start to repeat the reset process of the first submodule 11, and the high level generated by the AND gate U1 in the second submodule 12 is flipped by the first inverter U2 and outputs a low level to the set end SB of the second trigger T2 in the first submodule 12, so that the output of the second trigger T2 in the first submodule 12 is set to a high level 1, and the first submodule 11 is restarted.

[0070] The frequency detector and phase detector provided by the embodiment of the present invention include N submodules, wherein the submodules include a first trigger, a second trigger, a third trigger, an AND gate, a first switch unit and a first inverter. By setting the control end of the first switch unit of the first submodule to be connected to the first reset signal, the first end to be connected to the first power supply signal, and the second end to be connected to the output end of the AND gate in the first submodule; the control end of the first switch unit in the i-th submodule to be connected to the second reset signal, the first end to be connected to the output end of the AND gate in the i-th submodule, and the second end to be connected to the second power supply signal; the set end of the third trigger in the 1st submodule to be connected to the output end of the first inverter in the N-th submodule, the input end of the first inverter in the N-th submodule to be connected to the output end of the AND gate in the N-th submodule; the input end of the first inverter in the i-th submodule to be connected to the output end of the AND gate in the i-th submodule, and the output end of the first inverter in the i-th submodule to be connected to the set end of the third trigger in the i+1-th submodule, the phase detection range can be improved, and the clock frequency of the input reference clock signal can be improved. That is to say, the PFD of the embodiment of the present invention has a high operating frequency and a large phase detection range.

[0071] Optionally, continue to refer to Figure 2 and Figure 3 The first switch unit 10 includes a third switch tube K3, the gate of the first switch tube K3 serves as the control end of the first switch unit 10, the first electrode of the third switch tube K3 serves as the first end of the first switch unit 10, and the second electrode of the third switch tube K3 serves as the second end of the first switch unit 10. Optionally, the third switch tube K3 is an N-channel semiconductor device.

[0072] Figure 6 FIG. 1 is a schematic diagram of the structure of another frequency and phase detector provided by an embodiment of the present invention. Figure 6 As shown, the submodule 1 also includes a first delay control module 20, the input terminal IN of the first delay control module 20 is connected to the output terminal of the AND gate U1, and the output terminal OUT of the first delay control module 20 is connected to the trigger input terminal CK of the third trigger T3, which is used to delay the first control signal Ctr1 and control the delay duration of the first control signal Ctr1.

[0073] As a preferred implementation provided by the embodiment of the present invention, Figure 7 Schematic diagram of the structure of a first delay control module provided by an embodiment of the present invention. Figure 7 As shown, optionally, the first delay control module 20 includes M delay units 201 and M second switch units 202; M is an integer greater than or equal to 1.

[0074] The delay unit 201 and the Mth second switch unit 202 are connected in series between the input terminal IN of the first delay control module 20 and the output terminal OUT of the first delay control module 10. The jth second switch unit 202 is connected between the input terminal of the jth delay unit 201 and the output terminal OUT of the first delay control module 20; wherein j is an integer greater than or equal to 1 and less than or equal to M-1. The ath second switch unit 202 is used to control whether the ath delay unit 201 works, so as to control the delay time of the first control signal; wherein a is an integer greater than or equal to 1 and less than or equal to M.

[0075] When the ath second switch unit 202 is closed, the ath delay unit 201 will delay the first control signal passing through; when the ath second switch unit 202 is open, the ath delay unit 201 will not delay the signal. By controlling the closed or open state of different second switch units 202, different numbers of delay units 201 can be combined to participate in the first control signal delay processing. For example, if there are 3 delay units (M=3), when only the first second switch unit 202 is closed, only the first delay unit 201 delays the first control signal Ctr1; when the first and second second switch units 202 are closed, the first and second delay units 201 delay the first control signal Ctr1, thereby realizing flexible control of the delay time of the first control signal Ctr1. This design enables the entire PFD to accurately adjust the delay time of the first control signal according to actual needs.

[0076] In some embodiments, the conduction state of each second switch unit 202 can be controlled by coding, thereby controlling the delay size of the first delay module 20. If the width of the first delay time length Delay_0 is too small, it will cause the current switching time of the subsequent CP to be not proportional to the phase difference of the two input clock signals (i.e., the reference clock signal CLK_REF and the feedback clock signal CLK_IN), resulting in an error. At this time, the delay size of the first delay module 20 can be adjusted by coding to make the CP work normally. By adjusting the delay size by coding, the critical delay for the CP to work normally can be found. Under this delay condition, the internal loop delay of the PFD is the smallest and the CP can work normally. This method can further improve the clock frequency of the reference clock signal CLK_REF input to the PFD.

[0077] Optionally, continue to refer to Figure 7 , a different coding signal can be connected to the control end of each second switch unit 202. Each coding signal controls the conduction state of the corresponding second switch unit 202.

[0078] Figure 8 FIG. 1 is a schematic diagram of the structure of another frequency and phase detector provided by an embodiment of the present invention. Figure 8 As shown, optionally, the submodule 1 further includes a second inverter U3 and a second delay control module 30 .

[0079] The second inverter U3 is used to invert the first trigger signal and output a charging current control signal. The second delay control module 30 is used to delay the second trigger signal and output a discharging current control signal.

[0080] Optionally, the submodule 1 further includes a charging current control signal output terminal IN1 and a discharging current control signal output terminal IN2, wherein the charging current control signal output terminal IN1 is used to output a charging current control signal, and the discharging current control signal output terminal IN2 is used to output a discharging current control signal.

[0081] The frequency detector and phase detector also include a charge pump 2, which includes N first branches 210 and N second branches 220 connected to the output node out1 with the N first branches 210, and the first branches 210 are connected to the charging current control signal output terminal IN1 in a one-to-one correspondence, and the second branches 220 are connected to the discharge current control signal output terminal IN2 in a one-to-one correspondence. The charging current control signal and the discharge current control signal are generated by the second inverter U3 and the second delay control module 30 respectively, so that the on and off of the charging and discharging currents in the charge pump 2 can be accurately controlled to achieve accurate current regulation of the output node out1. By setting a plurality of first branches 210 and second branches 220, the size and quantity of the charging and discharging currents can be flexibly adjusted according to actual needs to meet the requirements of different application scenarios.

[0082] The first branch 210 is used to provide a charging current to the output node out1 , and the second branch 220 is used to provide a discharging current to the output node out1 .

[0083] Optionally, the first branch 210 includes a first switch tube K1 and a first current source IS1.

[0084] The gate of the first switch tube K1 is connected to the corresponding charging current control signal, the first electrode of the first switch tube K1 is connected to the second power supply signal VDD, the second electrode of the first switch tube K1 is connected to the first end of the first current source IS1, and the second end of the first current source IS1 is connected to the output node out1. The first switch tube K1 is used to selectively turn on according to the charging current control signal. When the first switch tube K1 is turned on, the first branch 210 is used to provide a charging current to the output node out1.

[0085] And / or, the second branch 220 includes a second switch tube K2 and a second current source IS2.

[0086] The gate of the second switch tube K2 is connected to the corresponding discharge current control signal, the first electrode of the second switch tube K2 is connected to the second power supply signal VDD, the second electrode of the second switch tube K2 is connected to the first end of the second current source IS2, the second end of the second current source IS2 is connected to the output node out1, and the second switch tube K2 is used to selectively conduct according to the discharge current control signal. When the second switch tube K2 is turned on, the second branch 220 is used to provide a discharge current to the output node out1. The first branch 210 and the second branch 220 use a combination of a switch tube and a current source, which can quickly respond to the charging current control signal and the discharging current control signal, realize an efficient charging and discharging process, and improve the performance and response speed of the PFD.

[0087] Optionally, the charge pump 2 further includes a first capacitor C1, a first end of the first capacitor C1 is connected to the output node out1, and a second end of the first capacitor C1 is connected to the first power signal VSS. The first capacitor can smooth the voltage of the output node out1, reduce voltage fluctuations, and improve the stability of the PFD.

[0088] Based on the same inventive concept, an embodiment of the present invention further provides a phase-locked loop, Fig. 9 Schematic diagram of a phase-locked loop provided by an embodiment of the present invention. Fig. 9 As shown, the phase-locked loop includes a phase frequency detector 101 provided by any embodiment of the present invention, and the phase-locked loop also includes a loop filter 102 , a voltage-controlled oscillator 103 and a frequency divider 104 .

[0089] The input end of the loop filter 102 is connected to the output end of the frequency detector 101, and the output end of the loop filter 102 is connected to the input end of the voltage-controlled oscillator 103; the voltage-controlled oscillator 103 is used to output a first signal CLK_OUT; the loop filter 102 is used to generate a second signal according to the current signal generated by the frequency detector 101, and adjust the frequency of the first signal output by the voltage-controlled oscillator 103 through the second signal; the input end of the frequency divider 104 is connected to the output end of the voltage-controlled oscillator 103, and the frequency divider 104 is used to divide the first signal CLK_OUT output by the voltage-controlled oscillator 103 to generate a feedback clock signal.

[0090] Optionally, continue to refer to Fig. 9 The phase-locked loop also includes a serial peripheral interface 105 (Serial Peripheral Interface, SPI), which includes four connection ports, namely a serial data input terminal SDI, a serial data output terminal SDO, a serial clock terminal SCLK, and a chip selection signal terminal CSN.

[0091] Fig.10 is a schematic diagram of the structure of a chip provided by an embodiment of the present invention, such as Fig.10 As shown, the chip includes the phase-locked loop 110 provided in an embodiment of the present invention, and also includes a control module 120. The control module 120 is communicated with the phase-locked loop 110 and is used to output a coding signal ENCODE. The coding signal ENCODE is used to control the delay duration of the internal loop of the frequency detector 101 in the phase-locked loop 110.

[0092] Optionally, the control module 120 may exchange data with the phase-locked loop 110 via the serial peripheral interface 105. Optionally, the control module 120 may include a single-chip microcomputer, a digital signal processor (DSP) or a field programmable gate array (FPGA).

[0093] The chip may be a radio frequency chip, an analog-to-digital converter (ADC) chip of various sampling rates, an automotive radar chip or a satellite chip.

[0094] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A phase frequency detector, characterized in that: include: N submodules, where N is an integer greater than or equal to 2; the submodules include a first trigger, a second trigger, a third trigger, an AND gate, a first switch unit, and a first inverter; The first trigger is used to receive a reference clock signal and output a first trigger signal; The second trigger is used to receive the feedback clock signal and output a second trigger signal; The AND gate is used to receive the first trigger signal and the second trigger signal, and generate a first control signal according to the first trigger signal and the second trigger signal and input it to the trigger input terminal of the third trigger; The third trigger is used to receive the first control signal and output a second control signal to a reset terminal of the first trigger and a reset terminal of the second trigger; In the N submodules, a control end of a first switch unit of a first submodule is connected to a first reset signal, a first end is connected to a first power signal, and a second end is connected to an output end of an AND gate in the first submodule, so as to be turned on when the first reset signal is a valid level signal; The control end of the first switch unit in the i-th submodule is connected to the second reset signal, the first end is connected to the output end of the AND gate in the i-th submodule, and the second end is connected to the second power supply signal, so as to be turned on when the second reset signal is a valid level signal; The set end of the third trigger in the first submodule is connected to the output end of the first inverter in the Nth submodule, and the input end of the first inverter in the Nth submodule is connected to the output end of the AND gate in the Nth submodule; The input end of the first inverter in the i-th submodule is connected to the output end of the AND gate in the i-th submodule, and the output end of the first inverter in the i-th submodule is connected to the set end of the third trigger in the i+1-th submodule; wherein i is an integer greater than or equal to 1 and less than or equal to N-1.

2. The phase frequency detector according to claim 1, characterized in that: The submodule also includes a first delay control module, the input end of the first delay control module is connected to the output end of the AND gate, and the output end of the first delay control module is connected to the trigger input end of the third trigger, for delaying the first control signal and controlling the delay duration of the first control signal.

3. The phase frequency detector according to claim 2, characterized in that: The first delay control module includes M delay units and M second switch units; M is an integer greater than or equal to 1; The delay unit and the Mth second switch unit are sequentially connected in series between the input end of the first delay control module and the output end of the first delay control module; The jth second switch unit is connected between the input end of the jth delay unit and the output end of the first delay control module; wherein j is an integer greater than or equal to 1 and less than or equal to M-1; The ath second switch unit is used to control whether the ath delay unit works, so as to control the delay time of the first control signal; Wherein a is an integer greater than or equal to 1 and less than or equal to M.

4. The phase frequency detector according to claim 1, characterized in that: The submodule further includes a second inverter and a second delay control module; The second inverter is used to invert the first trigger signal and output a charging current control signal; The second delay control module is used to delay the second trigger signal and output a discharge current control signal.

5. The phase frequency detector according to claim 4, characterized in that: The submodule further includes a charging current control signal output terminal and a discharging current control signal output terminal, wherein the charging current control signal output terminal is used to output the charging current control signal, and the discharging current control signal output terminal is used to output the discharging current control signal; The phase frequency detector further includes a charge pump, the charge pump includes N first branches and N second branches connected to output nodes with the N first branches, and the first branches are connected to the charging current control signal output terminals in a one-to-one correspondence, and the second branches are connected to the discharging current control signal output terminals in a one-to-one correspondence; The first branch is used to provide a charging current to the output node, and the second branch is used to provide a discharging current to the output node.

6. The phase frequency detector according to claim 5, characterized in that: The first branch includes a first switch tube and a first current source; The gate of the first switch tube is connected to the corresponding charging current control signal, the first electrode of the first switch tube is connected to the second power supply signal, the second electrode of the first switch tube is connected to the first end of the first current source, the second end of the first current source is connected to the output node, the first switch tube is used to selectively turn on according to the charging current control signal, and when the first switch tube is turned on, the first branch is used to provide a charging current to the output node; And / or, the second branch includes a second switch tube and a second current source; The gate of the second switch tube is connected to the corresponding discharge current control signal, the first electrode of the second switch tube is connected to the second power supply signal, the second electrode of the second switch tube is connected to the first end of the second current source, the second end of the second current source is connected to the output node, and the second switch tube is used to selectively turn on according to the discharge current control signal. When the second switch tube is turned on, the second branch is used to provide a discharge current to the output node.

7. The phase frequency detector according to claim 5, characterized in that: The charge pump further includes a first capacitor, a first end of the first capacitor is connected to the output node, and a second end of the first capacitor is connected to the first power signal.

8. The phase frequency detector according to claim 1, characterized in that: The feedback clock signal leads or lags behind the reference clock signal.

9. A phase-locked loop, characterized in that: The phase frequency detector comprises the phase frequency detector as claimed in any one of claims 1 to 8, wherein the phase locked loop further comprises a loop filter, a voltage controlled oscillator and a frequency divider; The input end of the loop filter is connected to the output end of the frequency and phase detector, and the output end of the loop filter is connected to the input end of the voltage-controlled oscillator; The voltage controlled oscillator is used to output a first signal; The loop filter is used to generate a second signal according to the current signal generated by the frequency and phase detector, and adjust the frequency of the first signal output by the voltage-controlled oscillator through the second signal; The input end of the frequency divider is connected to the output end of the voltage-controlled oscillator, and the frequency divider is used to divide the frequency of the first signal output by the voltage-controlled oscillator to generate a feedback clock signal.

10. A chip, characterized in that: The phase-locked loop of claim 9 further comprises a control module, wherein the control module is communicatively connected to the phase-locked loop and is used to output a coded signal, wherein the coded signal is used to control the delay duration of an internal loop of a phase frequency detector in the phase-locked loop.

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