An AXI-based data storage method, device, storage medium and equipment

Abstract

The application provides an AXI-based data storage method, device, storage medium and equipment, the method comprising: judging whether there is a spare command cache space in a read-write command receiving FIFO; in response to the spare command cache space, sending a command transmission request to an arbitrator, and storing corresponding command information in the read-write command receiving FIFO based on the command transmission request by the arbitrator; checking whether there is a read command and a write command in the read-write command receiving FIFO through an AXI read channel converter and an AXI write channel converter respectively; in response to the read command, converting first AXI read timing information into second SPRAM read timing information through the AXI read channel converter, and outputting the second read timing information to the SPRAM; in response to the write command, converting first AXI write timing information into second SPRAM write timing information through the AXI write channel converter, and outputting the second write timing information to the SPRAM. The application has the advantage of small area in the design of a chip with more storage.

Description

Technical Field

[0001] This invention relates to the field of AXI technology, and in particular to an AXI-based data storage method, apparatus, storage medium and device. Background Technology

[0002] With the development of modern chip technology, chip integration density is increasing exponentially. For chip development, the best way to optimize PPA (performance, power consumption, and area) is to carefully design the various basic unit libraries used in chip development. RAM (Random Access Memory) controllers, as fundamental units in chip design, are used extensively. Therefore, designing around RAM is of great significance for improving chip PPA.

[0003] SRAM (Static Random Access Memory) is a storage device that can store data as long as it is powered on, and it is a key component of most high-performance systems. It has been widely used in various applications for many years. It is common knowledge that SRAM is considered for any application requiring fast data access, especially where initial access latency is very short.

[0004] AXI (Advanced eXtensible Interface) is a bus protocol designed for high-performance, high-bandwidth, and low-latency on-chip buses. It features decoupled address / control and data phases, supports unaligned data transfers, separate read / write data channels in burst transfers, and supports outstanding (outgoing address) transfers and out-of-order access, while also facilitating timing closure. AXI is a new high-performance protocol within AMBA (Advanced Microcontroller Bus Architecture). AXI technology enriches the existing AMBA standard, meeting the needs of ultra-high-performance and complex System-on-Chip (SoC) designs.

[0005] In light of the above, efficient data storage and retrieval have become crucial aspects of chip performance design. Currently, combining the AXI bus with RAM perfectly meets the storage requirements of high-speed chip designs.

[0006] Currently, there are designs that convert the AXI protocol to TPRAM (Two-Port RAM) protocol. This design can meet the storage requirements of current chip designs. However, because TPRAM has a dual-port structure, it has a relatively large area and high cost. Therefore, it is not very suitable in situations where chip resources are scarce.

[0007] Besides the TPRAM solution, SPRAM (Single-Port RAM) is also used in practical engineering to implement related functions. However, SPRAM is a single-port RAM with only one set of control interfaces, so read and write operations cannot be performed simultaneously. Therefore, a solution for converting AXI protocol to SPRAM storage is needed. Summary of the Invention

[0008] In view of this, the purpose of this invention is to propose a data storage method, apparatus, storage medium and device based on AXI, so as to solve the problem that the storage scheme of AXI protocol to TPRAM in high-speed chip design in the prior art occupies a large chip area, resulting in a lot of resources and high cost.

[0009] To achieve the above objectives, the present invention provides a data storage method based on AXI, comprising the following steps:

[0010] Determine if there is free command buffer space in the read / write command receive FIFO;

[0011] In response to available command cache space, a command transmission request is sent to the arbitrator, and the arbitrator stores the corresponding command information into the read / write command receive FIFO based on the command transmission request.

[0012] The AXI read channel converter and AXI write channel converter are used to check whether there are read and write commands in the read and write command receive FIFO, respectively.

[0013] In response to a read command, the first read timing information of AXI is converted into the second read timing information of SPRAM through the AXI read channel converter, and the second read timing information is output to SPRAM;

[0014] In response to a write command, the first write timing information of AXI is converted into the second write timing information of SPRAM through the AXI write channel converter, and the second write timing information is output to SPRAM.

[0015] In some embodiments, the method further includes:

[0016] The SPRAM outputs the read data corresponding to the read command to the read data buffer FIFO according to the second read timing information, and the read data buffer FIFO sends the read data to the AXI bus.

[0017] In some embodiments, the method further includes:

[0018] Write the write data corresponding to the write command into SPRAM according to the second write timing information.

[0019] In some embodiments, determining whether there is free command buffer space in the read / write command receive FIFO includes:

[0020] The first number of read commands cached in the FIFO is counted by the read command counter, and it is determined whether the first number exceeds the first preset threshold.

[0021] In response to the first quantity not exceeding the first preset threshold, it is determined that there is free read command buffer space in the read / write command receiving FIFO;

[0022] The write command counter counts the second number of write commands buffered in the read / write command receiving FIFO, and determines whether the second number exceeds the second preset threshold.

[0023] In response to the second quantity not exceeding the second preset threshold, it is determined that there is free write command buffer space in the read / write command receiving FIFO.

[0024] In some embodiments, the method further includes:

[0025] In response to the first quantity exceeding the first preset threshold, a read command space full signal is generated by the read command counter, so that the arbitrator refuses to receive the read command transmission request;

[0026] In response to the second quantity exceeding the second preset threshold, the write command counter generates a write command space full signal to cause the arbitrator to refuse to receive the write command transmission request.

[0027] In some embodiments, outputting the second read timing information to the SPRAM includes:

[0028] The second read timing information is stored in the D flip-flop for one clock cycle and then output to the SPRAM.

[0029] In some embodiments, outputting the second write timing information to SPRAM includes:

[0030] The second writing timing information is registered for one clock cycle by a D flip-flop and then output to the SPRAM.

[0031] In some embodiments, the AXI read channel converter and the AXI write channel converter each contain a state machine.

[0032] In another aspect, the present invention also provides an AXI-based data storage device, comprising:

[0033] AXI to SPRAM interface controller, including:

[0034] The command counter is configured to determine whether there is free command buffer space in the read / write command receiving FIFO, and to issue a command transmission request in response to the availability of free command buffer space.

[0035] Arbitrator, configured to receive command transmission requests and obtain corresponding command information;

[0036] The read / write command receive FIFO is configured to store command information.

[0037] The AXI read channel converter is configured to check if a read command is present in the read / write command receive FIFO, and in response to a read command, convert the first read timing information of the AXI into the second read timing information of the SPRAM, and output the second read timing information; and

[0038] The AXI write channel converter is configured to check whether there is a write command in the read / write command receive FIFO, and in response to the presence of a write command, convert the first write timing information of AXI into the second write timing information of SPRAM, and output the second write timing information.

[0039] SPRAM is configured to receive second read timing information and second write timing information.

[0040] In another aspect, the present invention provides a computer-readable storage medium storing computer program instructions that, when executed by a processor, implement the above-described method.

[0041] In another aspect, the present invention provides a computer device including a memory and a processor, wherein the memory stores a computer program that, when executed by the processor, performs the above-described method.

[0042] The present invention has at least the following beneficial technical effects:

[0043] The AXI-based data storage method of the present invention realizes SPRAM-based AXI interface storage, which is similar to traditional TPRAM-based AXI interface memory in terms of timing and performance. It can effectively replace the function of traditional TPRAM-based AXI interface memory, and users can switch seamlessly. Since SPRAM is much smaller than TPRAM, the present invention has the advantage of small area in chip designs that use a lot of storage, reducing chip power consumption and cost, and has higher performance and operating frequency, and has stronger versatility. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0045] Figure 1This is a schematic diagram of an AXI-based data storage method provided according to an embodiment of the present invention;

[0046] Figure 2 This is a schematic diagram of the AXI interface protocol to SPRAM protocol conversion provided by an embodiment of the present invention;

[0047] Figure 3 This is a schematic diagram of the structure of an AXI-based data storage device provided according to an embodiment of the present invention;

[0048] Figure 4 This is a flowchart of the write data channel protocol conversion process according to an embodiment of the present invention;

[0049] Figure 5 This is a flowchart of the read data channel protocol conversion process according to an embodiment of the present invention;

[0050] Figure 6 A schematic diagram of the timing structure of two consecutive OUTSTANDING write commands provided according to an embodiment of the present invention;

[0051] Figure 7 A schematic diagram of the timing structure of two consecutive OUTSTANDING read commands provided in an embodiment of the present invention;

[0052] Figure 8 This is a schematic diagram of an AXI-based data storage device according to an embodiment of the present invention;

[0053] Figure 9 This is a schematic diagram of a computer-readable storage medium for implementing an AXI-based data storage method according to an embodiment of the present invention.

[0054] Figure 10 This is a schematic diagram of the hardware structure of a computer device for executing an AXI-based data storage method according to an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0056] It should be noted that all uses of the terms "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two different entities or different parameters with the same name. Therefore, "first" and "second" are merely for convenience of expression and should not be construed as limiting the embodiments of the present invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, such as other steps or units inherent in a process, method, apparatus, product, or device that includes a series of steps or units.

[0057] To achieve the above objectives, a first aspect of the present invention provides an embodiment of an AXI-based data storage method. Figure 1 The diagram shown is a schematic representation of an embodiment of the AXI-based data storage method provided by the present invention. Figure 1 As shown, the embodiments of the present invention include the following steps:

[0058] Step S10: Determine if there is any free command buffer space in the read / write command receiving FIFO;

[0059] Step S20: In response to the availability of command cache space, a command transmission request is sent to the arbitrator, and the arbitrator stores the corresponding command information into the read / write command receiving FIFO based on the command transmission request.

[0060] Step S30: Check whether there are read commands and write commands in the read and write command receiving FIFO using the AXI read channel converter and the AXI write channel converter respectively;

[0061] Step S40: In response to a read command, the first read timing information of AXI is converted into the second read timing information of SPRAM through the AXI read channel converter, and the second read timing information is output to SPRAM;

[0062] Step S50: In response to a write command, the first write timing information of AXI is converted into the second write timing information of SPRAM through the AXI write channel converter, and the second write timing information is output to SPRAM.

[0063] The AXI-based data storage method of this invention realizes SPRAM-based AXI interface storage, which is similar to traditional TPRAM-based AXI interface memory in terms of timing and performance. It can effectively replace the function of traditional TPRAM-based AXI interface memory, and users can switch seamlessly. Since SPRAM is much smaller than TPRAM, this invention has the advantage of small area in chip designs that use a lot of storage, reducing chip power consumption and cost, and has higher performance and operating frequency, and stronger versatility.

[0064] In some embodiments, the method further includes: the SPRAM outputs the read data corresponding to the read command to the read data buffer FIFO according to the second read timing information, and the read data buffer FIFO sends the read data to the AXI bus.

[0065] In some embodiments, the method further includes: writing the write data corresponding to the write command into SPRAM according to the second write timing information.

[0066] In some embodiments, determining whether there is free command buffer space in the read / write command receiving FIFO includes: counting a first number of read commands buffered in the read / write command receiving FIFO using a read command counter, and determining whether the first number exceeds a first preset threshold; in response to the first number not exceeding the first preset threshold, determining that there is free read command buffer space in the read / write command receiving FIFO; counting a second number of write commands buffered in the read / write command receiving FIFO using a write command counter, and determining whether the second number exceeds a second preset threshold; in response to the second number not exceeding the second preset threshold, determining that there is free write command buffer space in the read / write command receiving FIFO.

[0067] In some embodiments, the method further includes: in response to a first quantity exceeding a first preset threshold, generating a read command space full signal by a read command counter to cause the arbitrator to refuse to receive a read command transmission request; and in response to a second quantity exceeding a second preset threshold, generating a write command space full signal by a write command counter to cause the arbitrator to refuse to receive a write command transmission request.

[0068] In some embodiments, outputting the second read timing information to the SPRAM includes: storing the second read timing information for one clock cycle through a D flip-flop and then outputting it to the SPRAM;

[0069] In some embodiments, outputting the second write timing information to the SPRAM includes: registering the second write timing information for one clock cycle through a D flip-flop and then outputting it to the SPRAM.

[0070] In some embodiments, the AXI read channel converter and the AXI write channel converter each contain a state machine.

[0071] The data storage method based on AXI (Advanced eXtensible Interface, an on-chip bus protocol for high performance, high bandwidth, and low latency) in this invention is suitable for chip designs where area is a concern. Since the area of ​​SPRAM (Single-Port RAM) is much smaller than that of TPRAM (Two-Port RAM), replacing TPRAM with SPRAM using the AXI protocol for RAM protocol conversion can reduce chip area and lower chip cost while maintaining performance.

[0072] Because TPRAM's read and write ports are independent, while SPRAM only has one set of control terminals, the design process needs to consider merging the independent read and write channels of AXI into a single channel to drive the SPRAM. While this will slightly reduce bus performance, it will significantly reduce chip area. This approach has a large market potential in applications where performance is less critical but area and price are more important.

[0073] Figure 2 This is a schematic diagram of the AXI interface protocol to SPRAM protocol conversion provided by an embodiment of the present invention. Figure 3 This is a schematic diagram of the structure of an AXI-based data storage device according to an embodiment of the present invention. Figure 2 In light of the above, embodiments of the present invention are designed with Figure 3 The storage device shown.

[0074] like Figure 3 As shown, the AXI-based data storage device comprises a read command counter module, a write command counter module, a round-robin arbiter module, a read / write command receiving FIFO (First In First Out, a buffer mechanism where the first data written to the FIFO is the first data read out) module, an AXI read channel conversion module, an AXI write channel conversion module, a read data buffer FIFO module, and an SPRAM storage module. The functions of each module are described below:

[0075] Read command counter module: counts the number of AXI read commands received in the FIFO. This embodiment assumes that it can support 16 AXI OUTSTANDING (representing the number of addresses sent out; unprocessed addresses can be stored in the AXI bus buffer first, and after a transmission transaction is completed, there is no need to handshake to transmit addresses again, and the next data transmission can be performed immediately). When the number of AXI read commands received in the FIFO exceeds 16, the counter will generate a command space full signal, thereby blocking the arbitrator from receiving AXI read commands (this does not affect the parsing of write commands).

[0076] Write command counter module: counts the number of AXI write commands received in the FIFO. This embodiment assumes that it can support OUTSTANDING transmission of 16 AXI write commands. When the number of AXI write commands received in the FIFO exceeds 16, the counter will generate a command space full signal, thereby blocking the arbitrator from receiving AXI write commands (this does not affect the parsing of read commands).

[0077] The round-robin arbitrator module arbitrates the independent read and write channels of AXI using a round-robin method, storing the arbitrated commands in the read / write command receive FIFO. When the read command space is full, it blocks valid command requests from the read arbitration port and applies back pressure to the AXI read command channel. When the write command space is full, it blocks valid command requests from the write arbitration port and applies back pressure to the AXI write command channel.

[0078] Read / Write Command Receiver FIFO Module: The main function of this module is to cache AXI read commands and their accompanying information, as well as write commands and their accompanying information. Assuming a maximum of 16 read commands and 16 write commands can be cached, a total of 32 commands can be cached.

[0079] AXI Read Channel Converter: This module's main function is to check if the read / write command receiving FIFO module has read command information. If so, it starts the AXI read channel converter, using an internal state machine to convert the behavior of the AXI read channel side to the behavior of the SPRAM side. It's important to note that to adapt to higher frequency scenarios, the converted signal needs to be registered with a D flip-flop for one clock cycle before being input to the SPRAM module. Data read from the SPRAM needs to pass through the FIFO module before being output externally.

[0080] AXI Write Channel Converter: This module's main function is to check if the read / write command receiving FIFO module has write command information. If so, it starts the AXI write channel converter, using an internal state machine to convert the behavior of the AXI write channel side to the behavior of the SPRAM side. It's important to note that to adapt to higher frequency scenarios, the converted signals need to be registered with a D flip-flop for one clock cycle before being input to the SPRAM module, including the write enable signal and the write data signal.

[0081] Read Data Buffer FIFO: This module primarily buffers the data read from the SPRAM read channel before outputting it externally. It has three main functions: Function 1: Enables uninterrupted continuous transmission within an AXI transmission burst, without data bubbles; Function 2: Enables uninterrupted continuous transmission between AXI bursts and bursts, without data bubbles; Function 3: Adds a FIFO buffer function, essentially buffering the signal by one clock cycle using a register, which improves the timing convergence of the entire hardware device within the SOC (System-on-a-Chip).

[0082] SPRAM: This RAM (Random Access Memory) has only one set of read and write lines, and read and write operations are multiplexed. You cannot write while reading, and you cannot read while writing. It is a data storage module.

[0083] Figure 4 This is a flowchart illustrating the working data conversion process of the write data channel protocol according to an embodiment of the present invention. Figure 5 This is a flowchart illustrating the working data conversion process of the read data channel protocol according to an embodiment of the present invention. Figure 4 and Figure 5 It describes the entire operation process of the hardware storage device (an AXI-based data storage device). Figure 4 It describes how the AXI read channel converts the interface signals into SPRAM step by step. Figure 5It describes how the AXI write channel converts the interface signals of SPRAM step by step.

[0084] Having understood the entire workflow of the device, we will now further explore its mechanism from the perspective of data timing.

[0085] Figure 6 This is a schematic diagram illustrating the timing structure of two consecutive OUTSTANDING write commands according to an embodiment of the present invention. Figure 6 As shown, each write command writes three data entries consecutively (A0, A1, A2; B0, B1, B2). AXI MASTER is a high-speed interface whose main function is to receive and send data. CMD FIFO (Read / Write Command Receive FIFO) is a module that buffers AXI read / write commands and their accompanying information. SPRAM is a data storage module. The above process will be explained in detail below:

[0086] 1. AXI MASTER initiates a write data A request and sends the write address A to the CMD FIFO module.

[0087] 2. Address A and its associated information are cached in the CMD FIFO through the arbitrator module.

[0088] 3. Read the starting address A of the write data from the CMD FIFO, calculate the subsequent address values, and send these addresses to the SPRAM module in sequence. At the same time, AXI MASTER initiates a write data request B.

[0089] 4. Notify the AXI MASTER SPRAM side that it is ready to receive data, and at the same time, address B and its associated information are cached into the CMD FIFO through the arbitrator module.

[0090] 5. AXI MASTER writes data B0-B2 sequentially into SPRAM.

[0091] 6. Once the last A2 data has been written to SPRAM, return a write completion response to AXI MASTER.

[0092] 7. If an instruction to write data B is found in the CMD FIFO, read the starting address B of the write data from the CMD FIFO, calculate the subsequent address values, and send these addresses to the SPRAM module in sequence.

[0093] 8. Notify the AXI MASTER SPRAM side that it is ready to receive data, and at the same time, address B and its associated information are cached into the CMD FIFO through the arbitrator module.

[0094] 9. AXI MASTER writes data B0-B2 sequentially into SPRAM.

[0095] 10. Once the last B2 data has been written to SPRAM, return a write completion response to AXI MASTER.

[0096] Figure 7 This is a schematic diagram illustrating the timing structure of two consecutive OUTSTANDING read commands according to an embodiment of the present invention. AXI MASTER is a high-speed interface whose main function is to receive and transmit data. CMD FIFO is a module that buffers AXI read / write commands and their accompanying information. SPRAM is a data storage module. RDATA_FIFO (read data buffer FIFO) is a module that buffers read data. The above process will be described in detail below:

[0097] 1. AXI MASTER initiates a read data A request and sends the read address A to the CMD FIFO module.

[0098] 2. Address A and its associated information are cached in the CMD FIFO through the arbitrator module.

[0099] 3. Read the starting address A of the read data from the CMD FIFO, calculate the subsequent address values, and send these addresses to the SPRAM module in sequence. At the same time, AXI MASTER initiates a read data request B.

[0100] 4. Based on the address information, the data is sequentially read from the SPRAM and sent to the RDATA_FIFO buffer. Simultaneously, address B and its associated information are cached into the CMD FIFO via the arbitrator module.

[0101] 5. When it is detected that AXI MASTER can receive data, send the data to AXI MASTER.

[0102] 6. Read the starting address B of the read data from the CMD FIFO, calculate the subsequent address values, and send these addresses to the SPRAM module in sequence. At the same time, AXI MASTER initiates a read data B request.

[0103] 7. Based on the address information, the data is read from the SPRAM sequentially and sent to the RDATA_FIFO buffer.

[0104] 8. When it is detected that AXI MASTER can receive data, send the data to AXI MASTER.

[0105] The embodiments of the AXI-based data storage method of the present invention support continuous read / write enable, burst read / write, and loopback read / write. For continuous burst commands and error reporting, its throughput is close to 99%, demonstrating high performance. Addressing the issue of timing convergence difficulties caused by the long internal traces, wide application, and numerous drivers of the memory, FIFOs and D flip-flops are used to trim signals and eliminate metastability at the interfaces throughout the embodiments of the invention, resulting in excellent system timing convergence. Therefore, it can operate at higher frequencies and improves system stability and application breadth. The AXI-based data storage device can achieve uninterrupted continuous transmission within a single AXI transmission burst without bubble generation; it can also achieve uninterrupted continuous transmission between AXI bursts without bubble generation, exhibiting good performance.

[0106] A second aspect of the present invention also provides an AXI-based data storage device. Figure 8 The diagram shown is a schematic representation of an embodiment of the AXI-based data storage device provided by the present invention. Figure 8 As shown, an AXI-based data storage device includes an AXI-to-SPRAM interface controller 10 and an SPRAM 20. The AXI-to-SPRAM interface controller 10 includes: a command counter 101, configured to determine whether there is free command buffer space in the read / write command receiving FIFO, and to issue a command transmission request in response to the availability of free command buffer space; an arbitrator 102, configured to receive the command transmission request and obtain the corresponding command information; a read / write command receiving FIFO 103, configured to store command information; an AXI read channel converter 104, configured to check whether there is a read command in the read / write command receiving FIFO, and to convert the first read timing information of AXI into the second read timing information of SPRAM in response to the availability of a read command, and output the second read timing information; and an AXI write channel converter 105, configured to check whether there is a write command in the read / write command receiving FIFO, and to convert the first write timing information of AXI into the second write timing information of SPRAM in response to the availability of a write command, and output the second write timing information; the SPRAM 20 is configured to receive the second read timing information and the second write timing information.

[0107] A third aspect of the present invention also provides a computer-readable storage medium. Figure 9 A schematic diagram of a computer-readable storage medium implementing an AXI-based data storage method according to an embodiment of the present invention is shown. Figure 9 As shown, the computer-readable storage medium 3 stores computer program instructions 31. When executed by a processor, the computer program instructions 31 implement the method of any of the above embodiments.

[0108] It should be understood that, where there is no conflict, all the embodiments, features and advantages described above for the AXI-based data storage method according to the present invention are equally applicable to the AXI-based data storage device and storage medium according to the present invention.

[0109] A fourth aspect of the present invention also provides a computer device, including as follows: Figure 10 The memory 402 and processor 401 shown are provided. The memory 402 stores a computer program that, when executed by the processor 401, implements the method of any of the above embodiments.

[0110] like Figure 10 The diagram shown is a hardware structure schematic of an embodiment of a computer device for executing an AXI-based data storage method provided by the present invention. Figure 10 Taking the computer device shown as an example, this computer device includes a processor 401 and a memory 402, and may also include an input device 403 and an output device 404. The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 10 Taking a bus connection as an example, input device 403 can receive input digital or character information, and generate key signal inputs related to user settings and function control of the AXI-based data storage device. Output device 404 may include display devices such as a display screen.

[0111] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions / modules corresponding to the AXI-based data storage method in this embodiment. Memory 402 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and application programs required for at least one function; the data storage area may store data created by using the AXI-based data storage method, etc. In addition, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories can be connected to the local module via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0112] The processor 401 executes various server functions and data processing by running non-volatile software programs, instructions, and modules stored in the memory 402, thereby implementing the AXI-based data storage method of the above method embodiment.

[0113] Finally, it should be noted that the computer-readable storage medium (e.g., memory) in this article may be volatile memory or non-volatile memory, or may include both volatile memory and non-volatile memory.

[0114] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0115] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0116] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0117] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A data storage method based on AXI, characterized in that, Includes the following steps: Determine if there is free command buffer space in the read / write command receive FIFO; In response to available command cache space, a command transmission request is sent to the arbitrator, and the arbitrator stores the corresponding command information into the read / write command receiving FIFO based on the command transmission request. The AXI read channel converter and AXI write channel converter are used to check whether there are read commands and write commands in the read and write command receiving FIFO, respectively. In response to the read command, the first read timing information of AXI is converted into the second read timing information of SPRAM through the AXI read channel converter, and the second read timing information is output to the SPRAM; In response to the write command, the first write timing information of AXI is converted into the second write timing information of SPRAM through the AXI write channel converter, and the second write timing information is output to the SPRAM.

2. The method according to claim 1, characterized in that, Also includes: The SPRAM outputs the read data corresponding to the read command to the read data buffer FIFO according to the second read timing information, and the read data buffer FIFO sends the read data to the AXI bus.

3. The method according to claim 1, characterized in that, Also includes: Write the write data corresponding to the write command into the SPRAM according to the second write timing information.

4. The method according to claim 1, characterized in that, Determining whether there is free command buffer space in the read / write command receive FIFO includes: The first number of read commands cached in the read / write command receiving FIFO is counted by the read command counter, and it is determined whether the first number exceeds a first preset threshold. In response to the first quantity not exceeding the first preset threshold, it is determined that there is free read command buffer space in the read / write command receiving FIFO; The number of write commands cached in the read / write command receiving FIFO is counted by the write command counter, and it is determined whether the second number exceeds a second preset threshold. In response to the second quantity not exceeding the second preset threshold, it is determined that there is free write command buffer space in the read / write command receiving FIFO.

5. The method according to claim 4, characterized in that, Also includes: In response to the first quantity exceeding the first preset threshold, the read command counter generates a read command space full signal to cause the arbitrator to refuse to receive the read command transmission request; In response to the second quantity exceeding the second preset threshold, the write command counter generates a write command space full signal to cause the arbitrator to refuse to receive the write command transmission request.

6. The method according to claim 1, characterized in that, Outputting the second read timing information to the SPRAM includes: The second read timing information is stored for one clock cycle by a D flip-flop and then output to the SPRAM. Outputting the second write timing information to the SPRAM includes: The second write timing information is stored for one clock cycle by the D flip-flop and then output to the SPRAM.

7. The method according to claim 1, characterized in that, The AXI read channel converter and the AXI write channel converter each contain a state machine.

8. A data storage device based on AXI, characterized in that, include: AXI to SPRAM interface controller, including: The command counter is configured to determine whether there is free command buffer space in the read / write command receiving FIFO, and to issue a command transmission request in response to the availability of free command buffer space. An arbitrator, configured to receive the command transmission request and obtain the corresponding command information; The read / write command receiving FIFO is configured to store the command information. An AXI read channel converter is configured to check whether a read command is present in the read / write command receive FIFO, and in response to the presence of the read command, to convert the first read timing information of the AXI into the second read timing information of the SPRAM, and to output the second read timing information; and The AXI write channel converter is configured to check whether there is a write command in the read / write command receiving FIFO, and in response to the presence of the write command, convert the first write timing information of AXI into the second write timing information of SPRAM, and output the second write timing information. SPRAM is configured to receive the second read timing information and the second write timing information.

9. A computer-readable storage medium, characterized in that, The system stores computer program instructions that, when executed by a processor, implement the method as described in any one of claims 1-7.

10. A computer device, comprising a memory and a processor, characterized in that, The memory stores a computer program, which, when executed by the processor, performs the method as described in any one of claims 1-7.

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