Self-induced crystallization phase change memory cell and preparation method thereof

Abstract

The invention relates to a self-induced crystallization phase change storage unit and a preparation method thereof, the self-induced crystallization phase change storage unit comprises a phase change storage medium layer, the phase change storage medium layer is a multi-layer structure formed by phase change material layers and self-induced crystallization InyTe100-y material layers which are vertically stacked, periodically and alternately grown, and y is more than or equal to 20 and less than or equal to 80. The self-induced crystallization phase change memory cell has the characteristics of rapid data writing capability and long service life, can realize high-low resistance difference of more than three orders of magnitude, effectively improves the multi-resistance state memory stability, and can solve the problems of high power consumption, short service life, slow phase change speed and the like of a phase change memory in the prior art.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a self-induced crystallization phase change memory cell and its preparation method. Background Technology

[0002] With the continuous growth of global data volume and the rapid development of artificial intelligence technology, the demand for data storage is increasing daily, and new computer architectures are placing higher demands on memory performance. Phase-change memory (Phase-change memory), as one of the most mature new memory technologies, achieves data storage through the rapid non-volatile phase transition of chalcogenides between crystalline and amorphous states. It boasts speed and lifespan thousands of times faster than Flash memory and 16 times the capacity of DRAM. Therefore, Phase-change memory holds the promise of bridging the performance gap between Flash and DRAM, reducing system costs, and is the most promising new memory technology.

[0003] In phase-change memory (PCM), the selection of the phase change material (PCT) is crucial, and the crystallization temperature, as a key parameter of PCT, directly or indirectly affects critical indicators such as PCM lifetime, power consumption, and storage speed. Taking the currently popular PCT material Sb₂Te₃ as an example, it can spontaneously crystallize at room temperature. Therefore, its amorphous state is highly unstable at room temperature, which is detrimental to the high lifetime requirements of PCM. Currently, for PCT materials with low crystallization temperatures, the mainstream solution generally focuses on doping the PCT to increase its crystallization temperature and thus improve its data retention. However, doped PCT materials generally have higher melting temperatures and are prone to phase separation, which leads to increased power consumption and reduced lifetime of PCM. Therefore, it is necessary to develop a new type of PCM device to achieve a balance between phase change speed, power consumption, and data retention from a new perspective. Summary of the Invention

[0004] The present invention aims to provide a self-induced crystallization phase change memory unit and its preparation method, in order to solve the problems of high power consumption, poor thermal stability, short lifespan and slow phase change speed of existing phase change memory.

[0005] This invention provides a self-induced crystallization phase change memory cell, comprising a phase change memory dielectric layer, wherein the phase change memory dielectric layer is composed of a phase change material layer and a self-induced crystallization In layer. y Te 100-y A multi-layered structure formed by vertically stacking and periodically alternating growth of material layers, wherein 20≤y≤80.

[0006] Preferably, the phase change material layer is a chalcogenide compound material with reversible structural phase change, including one or more of Sb2Te3, Sb2Te, GeTe, Ge2Sb2Te5, and Ge1Sb2Te4.

[0007] Preferably, the thickness of the phase change material layer is in the range of 3–6 nm; the self-induced crystallization In y Te 100-y The thickness of the material layer ranges from 3 to 6 nm.

[0008] Preferably, the initial state of the phase change material layer is amorphous or crystalline after heat treatment; the self-induced crystallization In y Te 100-y The initial state of the material layer is either amorphous or crystalline after heat treatment.

[0009] Preferably, the vertical stacking cycle is 2 to 10 cycles.

[0010] Preferably, the total thickness of the phase change region in the phase change storage medium layer is in the range of 12–120 nm.

[0011] Preferably, the self-induced crystallization phase change storage unit is a confined structure or a T-type structure.

[0012] Preferably, the self-induced crystallization phase change storage unit can be repeated at a number of times not less than 10. 4 Second-rate.

[0013] Preferably, the data write speed of the self-induced crystallization phase change storage unit is on the nanosecond level.

[0014] This invention also provides a method for preparing a self-induced crystallization phase change memory cell, comprising the following steps:

[0015] S1. A substrate having heating electrodes fabricated thereon is provided, wherein the heating electrodes are covered by an insulating medium;

[0016] S2. Deposit a phase change storage medium layer on the heating electrode. The phase change storage medium layer is composed of a phase change material layer and self-induced crystallized In. y Te 100-y A multi-layered structure formed by vertically stacked and periodically alternating material layers, wherein 20≤y≤80;

[0017] S3. Deposit an electrode on the phase change storage medium layer to obtain a self-induced crystallization phase change storage cell.

[0018] Preferably, the material of the heating electrode in step S1 is one of Al, W or TiN; and the insulating medium is one of SiO2 or Si3N4.

[0019] Preferably, the deposition of the phase change storage medium layer in step S2 is performed using physical vapor deposition, chemical vapor deposition, or metal-organic deposition processes.

[0020] Preferably, the material of the upper electrode in step S3 is one of Al, W or TiN.

[0021] Beneficial effects

[0022] (1) In this invention, self-induced crystallization In y Te 100-y The melting point of the material layer is close to that of the phase change material layer, and the large electronegativity difference between In and Te can form stable In-Te bonds in amorphous materials. Therefore, it can be used as a structural stabilizing layer for the phase change material layer to improve the thermal stability and retention of the phase change material layer. At the same time, it can also be used as an inducing layer for the crystallization of the phase change material layer to accelerate the crystallization process and enable the phase change memory to have high-speed erase and write operation time.

[0023] (2) The In-Te system crystal in the selected region of this invention has a good geometric match between its own octahedral units and the octahedral units of the phase change material layer, thus extending the lifetime of the device unit and reducing power consumption; In induced self-induced crystallization In y Te 100-y The insertion of material layers can also help increase the resistance difference, increase the storage window, reduce resistance drift, and improve the reliability of the device during erasure and writing.

[0024] (3) The self-induced crystallization phase change memory unit of the present invention has the characteristics of fast data writing capability and long life, and can achieve a high and low resistance difference of more than three orders of magnitude, effectively improving the stability of multi-resistance state storage, and can solve the problems of high power consumption, short life and slow phase change speed of the existing phase change memory. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of the self-induced crystallization phase change memory unit of Example 1.

[0026] Figure 2 Example 1 is based on In 40 Te 60 A schematic diagram of the lattice structure of a self-induced crystallization phase change memory cell of -Sb2Te3.

[0027] Figure 3 Example 1 is based on In 40 Te 60 Resistance-voltage test curves of self-induced crystallization phase change memory cells of Sb2Te3.

[0028] Figure 4 Example 1 is based on In 40 Te 60 Fatigue characteristic test curve of self-induced crystallization phase change memory cell of Sb2Te3.

[0029] Figure 5 Example 2 is based on In 50 Te 50 Resistance-voltage test curves of self-induced crystallization phase change memory cells of GeTe.

[0030] Figure 6 Example 2 is based on In 50 Te 50 Fatigue characteristic test curves of self-induced crystallization phase change memory cells of GeTe.

[0031] Figure 7 Example 2 is based on In 50 Te 50 Resistance drift characteristics of self-induced crystallization phase change memory cells of GeTe.

[0032] Component designation explanation

[0033] 11. First phase change material layer;

[0034] 12 First layer of self-induced crystallization In y Te 100-y layer;

[0035] 21. Second phase change material layer;

[0036] 22 Second layer self-induced crystallization In y Te 100-y layer;

[0037] 101 substrate;

[0038] 102 Heating electrode;

[0039] 103 Phase-change storage medium layer;

[0040] 104 Upper electrode. Detailed Implementation

[0041] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0042] Example 1

[0043] like Figure 1 As shown, this embodiment provides a method for fabricating a self-induced crystallization phase change memory device unit, including the following steps:

[0044] Step 1: Provide a substrate 101, on which a cylindrical heating electrode 102 is fabricated. The heating electrode 102 is covered by an insulating medium. The insulating medium is Si3N4 with a thickness of 200 nm, and the heating electrode material is TiN. Clean the substrate 101 to remove impurities such as organic matter, metal ions, and oxides from its surface. After cleaning, dry the substrate.

[0045] Step 2: A phase change storage medium layer 103 is deposited on substrate 101 by measurement and control sputtering. The phase change material layer can be made of Sb2Te3, Sb2Te, GeTe, Ge2Sb2Te5, or Ge1Sb2Te4. For this example, Sb2Te3 is selected as the phase change material layer. In this example, the phase change storage medium layer 103 consists of five Sb2Te3 phase change material layers and four self-induced In crystal layers. 40 Te 60 The material layers are stacked sequentially; in this example, each layer contains Sb2Te3 and In. 40 Te 60 The thickness of all materials is 5 nm.

[0046] Step 3: Deposit an upper electrode 104 on top of the phase change material layer by magnetron sputtering. In this example, the upper electrode material is TiN with a thickness of 40 nm.

[0047] Step 4: Use an exposure-etching process to etch the upper electrode 104 and the phase change storage medium layer 103 until the substrate 101 is exposed, so as to physically isolate the phase change storage medium layer 103 on top of different heating electrodes. The exposure method used in the exposure-etching process described in this example is electron beam exposure, and the etching method is reactive ion etching.

[0048] After the above-mentioned device units were fabricated, electrical measurements were performed on them. Please refer to [link / reference needed]. Figure 3 and Figure 4 . Figure 3 The resistance-voltage test curves of the device unit are shown. As can be seen from the figure, the device unit has a SET voltage of 2.1V and a RESET voltage of 3.5V with a pulse width of 500ns, and the resistance of the device is very stable after SET. The device unit has a SET voltage of 2.0V and a RESET voltage of 3.9V with a pulse width of 100ns, and the resistance of the device is very stable when no phase transition occurs. Figure 4 The fatigue characteristic curves of the device unit are shown, indicating that the device unit can successfully perform more than 200,000 repeated operations and can stably maintain the difference between the high resistance and low resistance of the device unit within about three orders of magnitude.

[0049] Example 2

[0050] This embodiment provides a method for preparing a self-induced crystallization phase change memory device cell using a stripping process, including the following steps:

[0051] Step 1: Provide a substrate 101 identical to that in Example 1. Clean the substrate 101 to remove impurities such as organic matter, metal ions, and oxides from its surface, and then dry it.

[0052] Step 2: By using a spin-coating-exposure-development process, a dried photoresist with holes is left on the substrate 101. The holes should expose the heating electrode 102 of the substrate so that the grown film will be deposited on the heating electrode 102 in the following steps.

[0053] Step 3: A phase change storage medium layer 103 is deposited on the substrate 101 after step 2 via measurement and control sputtering. Due to the presence of photoresist, some phase change material is deposited on the photoresist, and some is deposited in the holes from step 2. The phase change material layer in the phase change storage medium layer 103 can be Sb₂Te₃, Sb₂Te, GeTe, Ge₂Sb₂Te₅, or Ge₁Sb₂Te₄. For this example, GeTe is selected as the phase change material layer. In this example, the phase change storage medium layer 103 consists of five standard GeTe phase change material layers and four self-induced crystallized In layers. 50 Te 50 The material layers are stacked sequentially. In this example, each layer contains GeTe and In. 50 Te 50 The thickness of all materials is 5 nm.

[0054] Step 4: Deposit an upper electrode 104 on the phase change storage medium layer 103 by magnetron sputtering. In this example, the material for depositing the upper electrode is TiN, and its thickness is 40 nm.

[0055] Step 5: Remove the photoresist described in Step 2 using acetone solution. At this time, the phase change storage medium film and TiN electrode deposited on top of the photoresist are also removed, leaving only the film deposited in the holes in Step 3 and the electrode deposited on top thereafter. After the photoresist removal is completed, clean with alcohol and dry.

[0056] The device unit is subjected to electrical measurements after its fabrication is completed. Figure 5 The resistance-voltage test curves of the device unit are shown. It can be seen that when a 100ns pulse width is applied, the SET voltage of the device unit is 1.6V and the RESET voltage is 3.4V. Furthermore, the figure shows five different resistance states (a, b, c, d, and e), with the resistance between adjacent points differing by an order of magnitude. This indicates that the device unit has good potential for multi-value storage. Figure 6The fatigue characteristic test curve of the device unit is shown, which shows that the fabricated device unit can successfully perform more than 60,000 repeated operations and can stably maintain the difference between the high resistance and low resistance of the device within about three orders of magnitude. Figure 7 The resistance drift characteristic curve of the device unit is shown. During the resistance-voltage test, the device unit was operated to different resistance states, and the resistance value changed over time at room temperature. The device unit fabricated in this example has a low drift coefficient, indicating that the device unit has good stability.

[0057] In summary, based on the phase change material layer and self-induced crystallization of In... y Te 100-y Phase-change memory (PCM) devices formed by periodically alternating phase-change dielectric layers at nanometer-thickness exhibit nanosecond-level phase-change rates, low SET voltages, and long fatigue lifetimes. These results further validate the theory that the In-Te crystal system, due to the similarity between its octahedral units and the octahedral units of Sb-Te and Ge-Te, can effectively match and participate in inducing the crystallization process of amorphous Sb-Te and Ge-Te, while simultaneously improving device fatigue and lifetime. This invention proposes a multilayer structure for PCM and provides a method for fabricating PCM cells based on this structure, which is expected to become an important reference for novel memory technologies and provide more diverse and reliable solutions for future memory designs.

[0058] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the following embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A self-induced crystallization phase change memory cell, comprising a phase change memory dielectric layer, characterized in that, The phase change storage medium layer is composed of a phase change material layer and self-induced crystallized In. y Te 100-y A multi-layered structure formed by vertically stacking and periodically alternating growth of material layers, wherein 20≤y≤80.

2. The self-induced crystallization phase change memory unit according to claim 1, characterized in that, The phase change material layer is a chalcogenide compound material with reversible structural phase change, including one or more of Sb2Te3, Sb2Te, GeTe, Ge2Sb2Te5, and Ge1Sb2Te4.

3. The self-induced crystallization phase change memory unit according to claim 1, characterized in that, The thickness of the phase change material layer ranges from 3 to 6 nm; the self-induced crystallization In y Te 100-y The thickness of the material layer ranges from 3 to 6 nm.

4. The self-induced crystallization phase change memory unit according to claim 1, characterized in that, The initial state of the phase change material layer is amorphous or crystalline after heat treatment; the self-induced crystallization In y Te 100-y The initial state of the material layer is either amorphous or crystalline after heat treatment.

5. A self-induced crystallization phase change memory unit according to claim 1, characterized in that, The vertical stacking cycle is 2 to 10 cycles.

6. The self-induced crystallization phase change memory unit according to claim 1, characterized in that, The total thickness of the phase change region in the phase change storage medium layer ranges from 12 to 120 nm.

7. A method for preparing a self-induced crystallization phase change memory unit, characterized in that, Includes the following steps: S1. A substrate having heating electrodes fabricated thereon is provided, wherein the heating electrodes are covered by an insulating medium; S2. Deposit a phase change storage medium layer on the heating electrode. The phase change storage medium layer is composed of a phase change material layer and self-induced crystallized In. y Te 100-y A multi-layered structure formed by vertically stacked and periodically alternating material layers, wherein 20≤y≤80; S3. Deposit an electrode on the phase change storage medium layer to obtain a self-induced crystallization phase change storage cell.

8. The preparation method according to claim 7, characterized in that: The material of the heating electrode in step S1 is one of Al, W or TiN; the insulating medium is one of SiO2 or Si3N4.

9. The preparation method according to claim 7, characterized in that: In step S2, the deposition of the phase change storage medium layer adopts physical vapor deposition, chemical vapor deposition, or metal-organic deposition processes.

10. The preparation method according to claim 7, characterized in that: In step S3, the material of the upper electrode is one of Al, W or TiN.

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