Method and device for reducing processor load

Abstract

A navigation receiver receives global navigation satellite system signals and processes the signals in a manner that reduces the load on a processor used in the navigation receiver. The navigation receiver includes a plurality of components that are assembled and configured to detect and respond to events, such as the generation of a signal, using a slack tick signal that reduces the load on the processor of the navigation receiver.

Description

Technical Field

[0001] The present disclosure generally relates to methods for processing signals from different Global Navigation Satellite Systems (GNSS) such as GPS or GLONASS, and more particularly to methods for reducing processor load. Background Art

[0002] The speed of the processor in a Global Navigation Satellite System receiver must be fast enough so that the processor can detect events such as signal generation and respond accordingly. When the processor is too slow or overloaded, it cannot process events in a timely manner.

[0003] U.S. Patent No. 8,401,546 B2 relates to a general acquisition and tracking device for a Global Navigation Satellite System (GNSS). The acquisition and tracking device is described as having channels that process input signals at 1 ms intervals and generate time frames (code epochs) that are input to a local interrupt manager. A global time signal (Global1ms) with a rate of 1 ms is also generated and used as an interrupt signal. The global interrupt manager assigns the global time signal to each of a plurality of channel processors, collects cumulative data including at least one of a plurality of correlation signals and sampled carrier and code phase signals from each channel processor, and forwards the cumulative data to a computer host for further processing. Correlations are always accumulated and "dumped" to the local interrupt module of the interrupt handler for processing at a rate of 1 ms, while feedback signals are updated at the end of a specified total coherent and non-coherent integration period.

[0004] U.S. Patent No. 8,331,422 B2 relates to a method and device for acquisition, tracking, and transmission using sub-microsecond time transfer with weak GPS / GNSS signals. The method and device provide high-sensitivity GPS / GNSS signal acquisition in a fixed GPS / GNSS receiver. There is also a control algorithm and device in which 1 ms correlations of an input signal, a pseudo-random noise (PRN) code signal, and an output signal of a numerically controlled oscillator (NCO) are generated and 20 ms symbols are output. The frequency uncertainty due to the apparent Doppler shift is divided into a plurality of consecutive frequency bins, and the uncertainty of the navigation data bit boundary position is divided into equally spaced trial bit boundary positions. For example, compensation for the Doppler shift is produced by correcting at a rate not greater than 1 Hertz / second.

[0005] Although these patents describe configurations that enable a processor to operate based on specific intervals, these configurations do not reduce the processor load. There is a need for a method and device that reduces the processor load so that it can process signals in a timely manner. Summary of the Invention

[0006] In one embodiment, a GNSS receiver (also referred to as a navigation receiver) includes an RF path configured to receive Global Navigation Satellite System (GNSS) signals from an antenna and to transmit the GNSS signals via an intermediate frequency. An analog-to-digital converter (ADC) is used to receive the GNSS signals from the RF path at the intermediate frequency and to sample the GNSS signals at a frequency CLKnav. A time scale generator is configured to generate a tick signal and a relax tick signal. A channel configured to receive the GNSS signals from the ADC includes an intermediate frequency numerically controlled oscillator (NCO) configured to generate a pulse having an intermediate frequency and an intermediate frequency phase. The channel also includes a code rate NCO configured to generate a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency. The channel also includes a code generator configured to generate a code signal based on the code rate NCO frequency. The channel also includes: a gating generator configured to generate a gating signal based on the shape of the code signal and the code rate NCO phase; an integration period counter configured to generate an integration period signal based on the code rate NCO frequency; and a commutator configured to receive the GNSS signals from the ADC. The channel also includes a correlator configured to: multiply the signal output from the commutator, the signal output from the code generator, and the intermediate frequency phase from the intermediate frequency NCO to generate a first product, and the correlator is configured to: store the first product during the integration period. The correlator is also configured to: multiply the signal output from the commutator, the signal from the gating signal, and the intermediate frequency phase from the intermediate frequency NCO to generate a second product, and the correlator is configured to: store the second product during the integration period. The navigation receiver also includes a CPU that controls the navigation receiver and reads data from the correlator. A method for operating the navigation receiver is also described. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 Shows a Global Navigation Satellite System (GNSS) receiver according to an embodiment;

[0008] Figure 2 Shows Figure 1 details of the time scale generator shown in;

[0009] Figure 3 Shows Figure 1 and Figure 2 details of one of the channels shown in;

[0010] Figure 4 Shows Figure 3 details of the correlator shown in;

[0011] Figure 5 A timing diagram showing the relationship between a display tick (i.e., a clock pulse signal), an integration period signal, and the data in the first-stage buffer and the data in the second-stage buffer according to an embodiment;

[0012] Figure 6 A timing diagram showing the relationship between a display tick and read operations, process operations, and write operations according to an embodiment;

[0013] Figure 7 A timing diagram showing the relationship between a display tick, a slack tick (i.e., a tick generated based on a clock pulse and occurring later in time than the clock pulse), and read operations, process operations, and write operations according to an embodiment;

[0014] Figure 8 A GNSS receiver according to an embodiment, in which a slack tick is generated and utilized;

[0015] Figure 9 Shows Figure 8 Details of the time scale generator shown in;

[0016] Figure 10 Shows Figure 8 And Figure 9 Details of the channels shown in; and

[0017] Figure 11 A method for operating a navigation receiver according to an embodiment. Detailed Description

[0018] The speed of the processor in a global navigation satellite system receiver must be fast enough so that the processor can detect events that occur, such as the generation of signals, and respond accordingly. This detection and response are required to generate raw measurements. To correctly generate raw measurements, it is necessary to update the control values for the intermediate frequency and the code frequency according to a tick signal (i.e., a clock pulse). Specifically, it is necessary to update the control values based on events that occur at exactly known times. The integration of the code frequency and the intermediate frequency over time is used to generate code and phase measurement results. Any error in the usage time of the new intermediate frequency and code frequency will cause the accumulation of errors in the raw measurement structure.

[0019] The control signal is programmable and is generated by a tracking algorithm executed by the CPU. The control signal is written to one or more channels at a specific time. The control signal causes an operation (e.g., update / copy) to start based on a known tick signal (e.g., an occurring clock pulse). This limitation of starting an operation based on a known tick signal applies to the strict real-time requirements of the program components of the GNSS receiver. Additionally, the generation of the control signal lasts longer than one tick duration (e.g., the time between two temporally adjacent ticks) and can be interrupted by different tasks, such as reading components from the channel correlator and data exchange tasks in the communication subsystem. The time period of the operation executed during a tick cannot be longer than the time period of one code duration (1 / 1023000 = 977 ms) minus the time required to read data from the channel to the CPU memory.

[0020] Slack ticks can be added to allow certain operations more time. A slack tick is a tick that is generated to occur after a tick that normally occurs based on a clock pulse. For example, a tick output by a clock at a rate of two per second will provide a tick frequency of 2 Hz. Slack ticks can be generated such that a tick generated by the clock occurs and the slack tick occurs later (e.g., later than the next clock tick after the original tick generated by the clock), in order to provide a tick frequency of 1 Hz. Adding slack ticks that delay by a time period longer than the time when a tick generated from a clock pulse occurs and that are a multiple of the clock pulse allows a significant reduction in the execution time requirements of the signal tracking algorithm, thereby reducing the additional overhead required to provide a guaranteed new value. Slack ticks are generated at a frequency lower than the tick.

[0021] Figure 1A global navigation satellite system receiver is shown. The global navigation satellite system receiver has an antenna 100 that receives signals, and the signals are input into RF paths 101(1, ……, N). Each of the RF paths 101(1, ……, N) transmits the signal to a corresponding analog-to-digital converter (ADC) 102(1, ……, N). The outputs of the ADCs 102(1, ……, N) are input into channels 103(1, 2, ……, N). It should be noted that the ADCs 102(1, ……, N) and the channels 103(1, 2, ……, N) may be collectively referred to as the ADCs 102 and the channels 103 herein. Other similarly numbered components may be collectively referred to in a similar manner. The channels 103(1, 2, ……, N) are also connected to a time scale generator 104. The channels 103(1, 2, ……, N) receive a tick signal S107 from the time scale generator 104. The tick signal is also transmitted from the time scale generator 104 to a central processing unit (CPU) 105 (also referred to as a processor). The CPU 105 can transmit information to a user 109 via a communication module 106 and receive information from the user 109 via the communication module 106.

[0022] In one embodiment, the CPU 105 controls the channels 103 and the time scale generator 104. In one embodiment, Figure 1 The shown receiver operates as follows. Before the receiver operates, the CPU 105 adjusts the time scale generator 104. The time scale generator 104 generates a tick signal S107 (tick) with equal time instants.

[0023] Satellite signals are received by the antenna 100 and pass through the RF paths 101 and the ADCs 102, and then are input into the channels 103. The channels 103 process the signals from the ADCs 102. The time scale generator 104 generates clock cycles (ticks). The CPU 105 controls the channels 103 and the time scale generator 104. When the tick signal S107 is available, the CPU 105 also processes the information received from the channels 103 and transmits the generated data to the user 109 via the communication module 106 through the communication module 106. In one embodiment, the ADCs 102, the channels 103, and the time scale generator 104 operate with a clock CLKnav.

[0024] Figure 2 is shown Figure 1 Details of the time scale generator 104 shown in are shown. In one embodiment, the time scale generator 104 includes a threshold unit 301 and a clock counter 300 that communicates with the CPU 105. In one embodiment, the time scale generator 104 operates as follows.

[0025] Before the operation of the time stamp generator 104 starts, the CPU 105 allocates a threshold to the threshold unit 301. Before the operation starts, the value in the clock counter 300 is 0. For each pulse of the clock CLKnav, the value of the clock counter 300 is incremented by 1. The value of the clock counter 300 is transmitted to the input of the threshold unit 301. If the value is equal to the threshold allocated by the CPU 105 to the threshold unit 301, the output of the threshold unit 301 is 1. If the value of the clock counter 300 is not equal to the threshold, the output of the threshold unit 301 is 0. The output signal from the threshold unit 301 is input to the channel 103, the clock counter 300, and is input to the CPU 105 as an interrupt. If the output signal of the threshold unit 301 is equal to 1, the clock counter 300 is reset (e.g., set to be equal to 0) at the next clock. The tick signal S107 is the output signal of the threshold unit of the clock counter.

[0026] Figure 3 shows Figure 1 and Figure 2 the details of the channel 103 shown in. In one embodiment, the channel 103 includes a code rate numerically controlled oscillator (NCO) 200 called CRNCO, a code generator 201, an intermediate frequency NCO (IFNCO) 202, an integration period counter 203, a converter 204, a correlator 205, an integration period signal S206, an update frequency CRNCO 207, an update shift phase CRNCO 208, an update lock phase CRNCO 209, an update frequency IFNCO 210, an update shift phase IFNCO 211, an update lock phase IFNCO 212, an update frequency CRNCO signal S207, an update shift phase CRNCO signal S208, an update lock phase CRNCO signal S209, an update frequency IFNCO signal S210, an update shift phase IFNCO signal S211, an update lock phase IFNCO signal S212, a gating generator 213, a code frequency signal S215, a code phase signal S216, a COS cosine signal S217, a SIN sine signal S218, a code (PRN code signal) S219, a gating signal S220. The update CRNCO 207, 208, and 209 and the update IFNCO 210, 211, and 212 are also referred to as units.

[0027] In one embodiment, the CPU 105 controls and / or receives data from the CRNCO 200, code generator 201, IFNCO 202, integration period counter 203, transducer 204, correlator 205, update frequency CRNCO 207, update shift phase CRNCO 208, update lock phase CRNCO 209, update frequency IFNCO 210, update shift phase IFNCO 211, update lock phase IFNCO 212, and strobe generator 213.

[0028] In one embodiment, signals are transmitted between components as follows. The update frequency CRNCO signal S207 is output from the update frequency CRNCO 207 and transmitted to the input of the CRNCO 200. The update shift phase CRNCO signal S208 is output from the update shift phase CRNCO 208 and transmitted to the input of the CRNCO 200. The update lock phase CRNCO signal S209 is output from the update lock phase CRNCO 209 and transmitted to the input of the CRNCO 200.

[0029] The update frequency IFNCO signal S210 is output from the update frequency IFNCO 210 and transmitted to the input of the IFNCO 202. The update shift phase signal IFNCO S211 is output from the update shift phase IFNCO 211 and transmitted to the input of the IFNCO 202. The update lock phase IFNCO signal S212 is output from the update lock phase IFNCO 212 and transmitted to the input of the IFNCO 202. The signals S207, S208, S209, S210, S211, and S212 are also referred to as update signals.

[0030] In one embodiment, the CPU 105 controls the CRNCO 200. The CPU 105 allocates the code frequency and interface register, assigns a value to the CRNCO 200, and updates / copies the data from the interface register to a buffer (which operates at the clock frequency CLKnav) based on the signal S207. The CPU 105 shifts the code phase into the interface register, and based on the signal S208, the code phase shift from the interface register is added to the current code phase, and the code phase shift in the interface register is set to equal 0. The CPU 104 copies the current state of the code phase to the code lock phase register in the CRNCO 200, and this value is updated based on the signal S209.

[0031] In one embodiment, the CPU 105 controls the IFNCO 202 as follows. The CPU 105 inputs an intermediate frequency into an interface register, assigns a value to the IFNCO 202, and updates / copies the data from the interface register to a buffer register (which operates at the clock frequency CLKnav) based on the signal S210. The CPU 105 inputs an intermediate frequency phase shift into the interface register, and based on the signal S211, the intermediate frequency phase shift from the interface register is added to the current intermediate frequency phase, and the intermediate frequency phase shift in the interface register is set to 0. The CPU 105 copies the current intermediate frequency phase in the IFNCO 202 into an intermediate frequency lock phase and the value is updated based on the signal S212.

[0032] When the CPU 105 writes a new value to the code frequency interface register in the CRNCO 200, an immediate signal is generated in the unit 207. When the CPU 105 writes a new value to the interface register for the code phase shift in the CRNCO 200, an immediate signal is generated in the unit 208. When the CPU 105 writes a new value to the register for the code frequency lock phase in the CRNCO 200, an immediate signal is generated in the unit 209. When the CPU 105 writes a new value to the interface register for the intermediate frequency in the IFNCO 202, an immediate signal is generated in the unit 210. When the CPU 105 writes a new value to the interface register for the intermediate frequency phase shift in the IFNCO 202, an immediate signal is generated in the unit 211. When the CPU 105 writes a new value to the interface register for the intermediate frequency lock phase in the IFNCO 202, an immediate signal is generated in the unit 212. The immediate signal is one clock cycle CLKnav.

[0033] In one embodiment, the CPU 105 controls the units 207, 208, 209, 210, 211, and 212 and generates update signals at the outputs of these units. Each of the units 207, 208, 209, 210, 211, and 212 has its own / independent control.

[0034] In one embodiment, the tick signal S107 and the integration period signal S206 are fed to the outputs of each of the units 207, 208, 209, 210, 211, and 212. A single clock / one clock signal can cause update signals to be output from the units 207, 208, 209, 210, 211, and 212.

[0035] In one embodiment, after a value is written into a register of one of the units 207, 208, 209, 210, 211, and 212 controlled by the CPU, an immediate signal is generated and output from the corresponding one of the controlled units. The integration period signal S206 is a signal indicating the end of the integration period and is generated by the integration period counter 203. The tick signal S107 is generated by the time scale generator 104. Table 1 shows the output signals of the units 207, 208, 209, 210, 211, and 212 based on the signals from the CPU 105.

[0036]

[0037] Table 1

[0038] Based on the tick signal S107, the current state of the integration period counter 203 is copied into the register of the locked state of the integration period counter.

[0039] The locked state of the integration period counter, the intermediate frequency locked phase in the IFNCO 202, and the locked phase register in the CRNCO 200 are used for pseudorange calculation and operate based on the tick signal S107. The IFNCO 202 generates and outputs two signals, namely, a cosine signal and a sine signal.

[0040] In one embodiment, Figure 3 The initialization of the shown channel is as follows. Before starting Figure 3 the operation of the channel, the CPU 105 adjusts the code generator 201, the converter 204, the units 209 and 212, and the strobe generator 213, and also performs the following operations. The CPU 105 sets the code frequency in the CRNCO 200. If necessary, the CPU 105 assigns a code phase shift in the CRNCO 200. The CPU 105 selects the units 207 and 208 as the update signal and the tick signal S107. The CPU 105 sets the intermediate frequency in the IFNCO 202. If necessary, the CPU 105 sets the intermediate frequency phase shift in the IFNCO 202. The CPU 105 selects the outputs of the units 210 and 211 as the update signal and the tick signal S107. The CPU 105 sets the duration of the integration period S206 in the integration period counter 203.

[0041] In one embodiment, Figure 3The operation of the channels shown is as follows. The tick signal S107 output from the time stamp generator 104 is input to the update frequency CRNCO 207, the update shift phase CRNCO 208, the update lock phase CRNCO 209, the update frequency IFNCO 210, the update shift phase IFNCO 211, the update lock phase IFNCO 212, the integration period counter 203, the correlator 205, and the CPU 105. The CRNCO 200 generates a code frequency based on the tick signal S107. The code frequency S215 is output from the CRNCO200 and input to the code generator 201, where a code signal S219 is generated using this frequency. The code frequency output from the CRNCO 200 is input to the integration period counter 203, where the integration period signal S206 counts the required duration using the received code frequency. The code signal S219 from the code generator 201 is input to the correlator 205 and the gating generator 213. The code phase signal S216 output from the CRNCO 200 is input to the gating generator 213. The gating generator 213 generates a gating signal S220, which is input to the correlator 205.

[0042] In one embodiment, the integration period signal S206 output from the integration period counter 203 is input to the correlator 205, the frequency update CRNCO 207, the shift phase update CRNCO 208, the lock phase update CRNCO 209, the frequency update IFNCO 210, the shift phase update IFNCO 211, the lock phase update IFNCO 212, and the CPU 105.

[0043] In one embodiment, the IFNCO 202 generates an intermediate frequency based on the tick signal S107. The intermediate frequency phase signals (signals COS S217 and SIN S218) output from the IFNCO 202 are input to the correlator 205.

[0044] In one embodiment, a digitized signal is output from the ADC 102 and the digitized signal is input to the converter 204. One of the selected signals output from the converter 204 is input to the correlator 205.

[0045] Figure 4 is shown Figure 3Details of the correlator 205 as shown. In one embodiment, the correlator 205 includes multiplication units 400, 401, 402, 403, 404, 405, accumulator I (Acc I) 406, accumulator Q (Acc Q) 407, accumulator dI (Acc dI) 408, accumulator dQ (Acc dQ)) 409, first-stage buffer I 410, first-stage buffer Q 411, first-stage buffer dI 412, first-stage buffer dQ 413, second-stage buffer I 414, second-stage buffer Q 415, second-stage buffer dI 416, and second-stage buffer dQ 417.

[0046] In the correlator 205, the intermediate-frequency phase signals (signals COS S217 and SIN S218) from the IFNCO 202 are multiplied by the digitized signals output from the converter 204 and the code signal S219 output from the code generator 201. Additionally, in the correlator 205, the intermediate-frequency phase signals (signals COS S217 and SIN S218) from the IFNCO 202 are multiplied by the digitized signals output from the converter 204 and the gating signal S220 output from the gating generator 213.

[0047] The products are accumulated and stored over a period of time, where the period is based on the integration period signal S206. The stored numbers are copied into the first-stage buffers 410, 411, 412, and 413 in the correlator 205 and set to zero according to the integration period signal S206. The correlator 205 generates components I, Q, dI, and dQ, which are read by the CPU 105. Values are copied from the first-stage buffers 410 / 411 / 412 / 413 to the second-stage buffers 414, 415, 416, and 417 based on the tick signal S107.

[0048] In one embodiment, if needed, the CPU 105 changes / allocates / reads the following during operation: changes the code frequency in the CRNCO 200, allocates the code phase shift in the CRNCO 200, changes the control of units 207, 208, 209, 210, 211, 212, changes the intermediate frequency in the IFNCO 202, allocates the intermediate-frequency phase shift in the IFNCO 202, reads the register of the code frequency lock phase in the CRNCO 200, reads the register of the intermediate-frequency lock phase in the IFNCO 202, reads the register of the lock state of the integration period counter 203, reads the first-stage buffers 410, 411, 412, and 413 in the correlator 205, and reads the second-stage buffers 414, 415, 416, and 417 in the correlator 205.

[0049] In one embodiment, the operation of the strobe generator 213 is as described for the general strobe generator 500 in U.S. Patent No. 7,764,226 with respect to Figure 2 as shown therein. U.S. Patent No. 7,764,226 is incorporated herein by reference.

[0050] In one embodiment, Figure 4 the correlator shown therein operates as follows. The digitized signal output from the transducer 204 and the cosine signal S217 output from the IFNCO 202 are input to the multiplication unit 400, where the signals are multiplied. The digitized signal output from the transducer 204 and the sine signal S218 output from the IFNCO 202 are input to the multiplication unit 401, where the signals are multiplied. The multiplication result generated by the unit 400 and the code signal S219 from the code generator 201 are input to the multiplication unit 402, where the signals are multiplied. The multiplication result generated by the unit 401 and the code signal S219 from the code generator 201 are input to the multiplication unit 403, where the signals are multiplied. The multiplication result generated by the unit 400 and the strobe signal S220 from the strobe generator 213 are input to the multiplication unit 404, where the signals are multiplied. The multiplication result generated by the unit 401 and the strobe signal S220 from the strobe generator 213 are input to the multiplication unit 405, where the signals are multiplied. The integration period signal S206 output from the integration period counter 203 is transmitted to the inputs of the units 406, 407, 408, 409, 410, 411, 412, and 413. The multiplication result generated by the unit 402 is input to the accumulator I 406, and the multiplication result generated by the unit 402 is stored in the accumulator I 406 during the action of the integration period signal S206. The multiplication result generated by the unit 403 is input to the accumulator Q 407, and the multiplication result generated by the unit 403 is stored in the accumulator Q 407 during the action of the integration period signal S206. The multiplication result generated by the unit 404 is input to the accumulator dI 408, and the multiplication result generated by the unit 404 is stored in the accumulator dI 408 during the action of the integration period signal S206. The multiplication result generated by the unit 405 is input to the accumulator dQ 409, and the multiplication result generated by the unit 405 is stored in the accumulator dQ 409 during the action of the integration period signal S206.

[0051] In one embodiment, based on the integration period signal S206: copy the stored value from accumulator I 406 to the first-stage buffer I 410, set the value stored in accumulator I 406 to value 0, copy the value stored in accumulator I 407 to the first-stage buffer Q 411, set the value stored in accumulator I 407 to 0, copy the value stored in accumulator I 408 to the first-stage buffer dI 412, set the value stored in accumulator I 408 to value 0, copy the value stored in accumulator I 409 to the first-stage buffer dQ 413, and set the value stored in accumulator I 409 to value 0.

[0052] In one embodiment, based on the tick signal S107 and the integration period signal S206: copy the value in the first-stage buffer I 410 to the second-stage buffer I 414, copy the value from the first-stage buffer Q 411 to the second-stage buffer Q 415, copy the value in the first-stage buffer dI 412 to the second-stage buffer dI 416, copy the value in the first-stage buffer dQ 413 to the second-stage buffer dQ 417.

[0053] In one embodiment, the CPU 105 reads values from the following locations: the first-stage buffer I 410, the first-stage buffer Q 411, the first-stage buffer dI 412, the first-stage buffer dQ 413, the second-stage buffer I 414, the second-stage buffer Q 415, the second-stage buffer dI 416, and the second-stage buffer dQ 417. The period of the tick signal S107 is selected to be less than the value of the minimum integration period signal S206 used. Storing the values in the second-stage buffers 414, 415, 416, and 417 during the period when the tick signal S107 acts ensures the reading of these values even if the values in the first-stage buffers 410, 411, 412, and 413 have changed (these values have been updated according to the integration period signal S206).

[0054] Figure 5A timing diagram is shown that illustrates the relationship between the display tick signal S107, the integration period S206, and the data in the first-stage buffers and the data in the second-stage buffers. If the values in the first-stage buffers 410, 411, 412, and 413 in channel 103 have changed during the periodic tick signal S107, new components are written into the correlators 205I, Q, dI, and dQ based on the integration period signal S206. Based on the tick signal S107, the values from the first-stage buffers 410, 411, 412, and 413 are copied to the second-stage buffers 414, 415, 416, and 417. The values from the cells 414, 415, 416, and 417 are read once in the next period of the tick signal S107, and the values read from the cells 414, 415, 416, and 417 are processed by the CPU 105.

[0055] Figure 6 A timing diagram is shown that illustrates the relationship between the display tick and the read operation, the processing operation, and the write operation. In one embodiment, the update of the control values for the intermediate frequency and the code frequency is based on the occurrence of the tick. Specifically, the correct generation of the raw data requires events to occur at precise known times. The integration of the code frequency and the intermediate frequency over time is used to form a copy in the correlator 205 of channel 103, and this copy is used to generate code and phase measurements. Any errors in the timing of the use and / or application of the new values of the intermediate frequency and the code frequency will result in cumulative errors in the raw data.

[0056] In one embodiment, the control signal itself is programmable and is generated by a tracking algorithm in the CPU 105. In one embodiment, the control signal is written into the interface register of channel 103 at a specific time. They are written starting from the tick signal (e.g., from the interface register update and / or copy to the buffer registers in the CRNCO 200 and IFNCO 202). This limitation may apply to the strict real-time requirements of the program components of the GNSS receiver. Additionally, the generation of the control signal can last for more than one tick duration and may be interrupted by different tasks, such as reading from channel 103, data exchange tasks, etc. The period used to form the tick event cannot be longer than the storage period of one code duration (e.g., 1 / 1023000 = 977 ms).

[0057] In one embodiment, adding a slack tick event that occurs a time delay of more than one or more ticks after the start of generating the control signal in the code frequency and the intermediate frequency allows reducing the execution time required by the signal tracking algorithm and avoiding unnecessary burdens to ensure the use of the new control values for the IFNCO and CRNCO. Figure 7 A timing diagram is shown that illustrates the relationship between the display slack tick and the read operation, the processing operation, and the write operation.

[0058] Figure 8 Shows a receiver that generates and utilizes a slack tick 416 according to one embodiment. Figure 8 The receiver shown in Figure 1 has components similar to those of the receiver shown in Figure 8 However, some of the components of the receiver shown in Figure 1 are different from the corresponding components of the receiver shown in Figure 8 The different components / signals of Figure 8 are identified by the term "modified". These differences allow Figure 8 the receiver shown in Figure 1 to generate and utilize a slack tick. The differences between the receiver shown in

[0059] Figure 9 are as follows. Channel 103(1, ……, N) is replaced by modified channel 110(1, ……, N). The time stamp generator 104 is replaced by a modified time stamp generator 111. A slack tick signal S108 is output from the modified time stamp generator 111. The slack tick signal S108 is input as an interrupt signal to the modified channel 110(1, ……, N) and the CPU 105. Figure 8 Shows the details of the modified time stamp generator 111 shown in

[0060] In one embodiment, the modified time stamp generator 111 operates as follows. Before operation, the CPU 105 assigns thresholds in the threshold clock counter 301 and in the slack tick counter 303. Additionally, before operation, the clock counter 300 and the slack tick counter 302 are at value 0. The clock counter 300 increments by 1 for each clock CLKnav.

[0061] The current value of the clock counter 300 is input to the unit 301. If the value of the clock counter 300 is equal to the threshold of the unit 301 assigned by the CPU105, the unit 301 outputs a value 1, otherwise, the unit 301 outputs a value 0. The output of the unit 301 is input as an interrupt signal to the channel 103, the clock counter 300, the slack tick counter 302, the AND gate 304, and the CPU 105. If the output value of the unit 301 is value 1, the clock counter 300 is reset at the next clock (i.e., the clock counter 300 is set to equal value 0 at the next clock).

[0062] The tick signal S107 is the output of the threshold clock counter 301. When the tick signal S107 is available, the slack tick counter 302 increments its value by 1. The value of the slack tick counter 302 is input to the input of unit 303. If the value in the slack tick counter 302 is equal to the threshold of the slack tick counter 303 assigned by the CPU 105, unit 303 outputs a value of 1; otherwise, unit 303 outputs a value of 0. The output of unit 303 is input to the AND gate 304. If the output signal of unit 303 and the tick signal S107 are available, the AND gate 304 outputs a value of 1; otherwise, the AND gate 304 outputs a value of 0. The output of unit 304 is input as an interrupt signal to the modified channel 110, the slack tick counter 302, and the CPU 105. If unit 304 outputs a value of 1, unit 302 is reset at the next clock (i.e., unit 302 is set to equal the value 0).

[0063] The slack tick signal S108 is output from the AND gate 304. The CPU 105 can read the value of unit 302. During the operation of the modified time scale generator 111, the CPU 105 can change the threshold of the slack tick counter 303 if needed.

[0064] Figure 10 is shown Figure 8 and Figure 9Details of the modified channel 110 as shown. The modified channel 110 includes the components and signals of channel 103 and the following differences: The update frequency CRNCO 207 is replaced by the modified update frequency CRNCO 2070. The update phase shift CRNCO 208 is replaced by the modified update phase shift CRNCO 2080. The update lock phase CRNCO 209 is replaced by the modified update lock phase CRNCO 2090. The update frequency IFNCO 210 is replaced by the modified update frequency IFNCO 2100. The update phase shift IFNCO 211 is replaced by the modified update phase shift IFNCO 2110. The update lock phase IFNCO 212 is replaced by the modified update lock phase IFNCO 2120. The modified CRNCO frequency update signal S2070 is output from the modified update frequency CRNCO 2070. The modified CRNCO phase shift update signal S2080 is output from the modified update phase shift CRNCO 2080. The modified CRNCO lock phase update signal S2090 is output from the modified update lock phase CRNCO 2090. The modified IFNCO frequency update signal S2100 is output from the modified update frequency IFNCO 2100. The modified IFNCO phase shift update signal S2110 is output from the modified update phase shift IFNCO 2110. The modified IFNCO lock phase update signal S2120 is the modified output from the update lock phase IFNCO 2120. The lock counter update signal S2140 is output from the update lock counter 2140.

[0065] In one embodiment, the CPU 105 controls the CRNCO 200 as follows: The CPU 105 sets the code frequency in the interface register, updates the value in the CRNCO 200 using the signal S2070 and / or copies the value in the CRNCO 200 from the interface register to a buffer (which operates with the clock CLKnav). The CPU 105 places the code phase shift in the interface register, copies the data from the interface register to a buffer register (which operates with the clock CLKnav), the code phase shift from the buffer register is added to the current code phase based on the signal S2080, and the code phase shift in the buffer register is set to equal 0. The current state of the code phase in the CRNCO 200 is copied to a register of the locked code phase, and this value is updated using the signal S2090.

[0066] In one embodiment, the CPU 105 controls the IFNCO 202 as follows: The CPU 105 sets the intermediate frequency in the interface register, updates the value of the IFNCO 202 via the signal S2100 and / or copies the value of the IFNCO 202 from the interface register to a buffer (which operates with the clock CLKnav). The CPU 105 sets the intermediate frequency phase shift in the interface register, copies the data from the interface register to a buffer register (which operates with the clock CLKnav), the intermediate frequency phase shift from the buffer register is added to the current intermediate frequency phase via the signal S2110, and the intermediate frequency phase shift in the buffer register is set to the value 0. The CPU 105 copies the current state of the intermediate frequency phase of the IFNCO 202 to the intermediate frequency lock phase register, and this value is updated via the signal S2120.

[0067] When the CPU 105 writes a new value to the interface register of the code frequency in the CRNCO 200, an immediate signal is generated in the unit 2070 operating with the clock CLKnav. When the CPU 105 writes a new value to the interface register of the code phase shift in the CRNCO 200, an immediate (phase shift) signal is generated in the unit 2080 operating with the clock CLKnav. When the CPU 105 writes a new value to the interface register of the lock phase in the CRNCO 200, an immediate (lock phase) signal is generated in the unit 2090 operating with the clock CLKnav. When the CPU 105 writes a new value to the interface register of the intermediate frequency in the IFNCO 202, an immediate signal is generated in the unit 2100 operating with the clock CLKnav. When the CPU 105 writes a new value to the interface register of the intermediate frequency (phase shift) in the IFNCO 202, an immediate signal is generated in the unit 2110 operating with the clock CLKnav. When the CPU 105 writes a new value to the interface register of the intermediate frequency lock phase in the IFNCO 202, an immediate signal is generated in the unit 2120.

[0068] In one embodiment, the CPU 105 controls the units 2070, 2080, 2090, 2100, 2110, and 2120 and outputs update signals from each unit. Each of the units 2070, 2080, 2090, 2100, 2110, and 2120 has its own independent control.

[0069] The tick signal S107, the slack tick signal S108, and the integration period signal S206 are fed to the outputs of each of the units 2070, 2080, 2090, 2100, 2110, and 2120. One of the following clock signals may be an update signal at the outputs of the units 2070, 2080, 2090, 2100, 2110, 2120: The immediate signal is a signal generated after writing to a register. The integration period signal S206 is a signal that identifies the end of an integration period, and the integration period signal S206 is generated by the integration period counter 203. The tick signal S107 is a signal generated by the time scale generator 111. The slack tick signal S108 is generated by the time scale generator 111. Table 2 shows the control of the units 2070, 2080, 2090, 2100, 2110, and 2120 and the signals output by these units based on the control signals.

[0070]

[0071] Table 2

[0072] The CPU 105 controls the unit 2140 to output an update signal. The tick signal S107 and the slack tick signal S108 are also output from the unit 2140. One of the following clock signals may be an update signal output from the unit 2140: The tick signal S107 is a signal generated by the modified time scale generator 111. The slack tick signal S108 is a signal generated by the modified time scale generator 111.

[0073] The current state of the integration period counter 203 is copied to the register that locks the integration period by the lock counter update signal S2140. Table 3 shows the control of the unit 2140 and the signals output by the unit 2140.

[0074]

[0075] Table 3

[0076] In one embodiment, the IFNCO 202 outputs two signals, namely COS S217 and SIN S218.

[0077] In one embodiment, Figure 10The initialization of the receiver shown in [Figure] is as follows. Before the receiver starts operation, the CPU 105 performs the following operations: The CPU 105 sets the code frequency in the CRNCO 200. If necessary, the CPU 105 also sets the code phase shift in the CRNCO 200. The CPU 105 selects the tick signal S107 as the update signal for the units 2070 and 2080. The CPU 105 sets the intermediate frequency in the IFNCO 202. If necessary, the CPU 105 also sets the intermediate frequency phase shift in the IFNCO 202. The CPU 105 selects the tick signal S107 as the update signal for the units 2100 and 2110. The CPU 105 adjusts the code generator 201 and sets the integration period signal S206 in the integration period counter 203. The CPU 105 adjusts the converter 204 and the units 2090, 2120, and 2140, and the strobe generator 213.

[0078] In one embodiment, Figure 10 the receiver shown in [Figure] operates as follows. The tick signal S107 output from the modified time scale generator 111 is input to the following: the modified CRNCO frequency update 2070, the modified CRNCO phase shift update 2080, the modified CRNCO locked phase update 2090, the modified IFNCO frequency update 2100, the modified IFNCO phase shift update 2110, the modified IFNCO locked phase update 2120, the locked counter update unit 2140, and the correlator 205.

[0079] In one embodiment, the slack tick signal S108 output from the modified time scale generator 111 is input to the following units: the modified CRNCO frequency update 2070, the modified CRNCO phase shift update 2080, the modified CRNCO locked phase update 2090, the modified IFNCO frequency update 2100, the modified IFNCO phase shift update 2110, the modified IFNCO locked phase update 2120, and the locked counter update unit 2140.

[0080] The CRNCO 200 generates a code frequency based on the tick signal S107. A code frequency signal S215 is output from the CRNCO 200 and the code frequency signal S215 is input to the code generator 201, and a code signal S219 is generated using this frequency. The code frequency output from the CRNCO 200 is input to the integration period counter 203, where the allocated duration of the integration period signal S206 is counted using this frequency. The code signal S219 from the code generator 201 is input to the correlator 205 and the gating generator 213. The code phase signal S216 output from the CRNCO 200 is input to the gating generator 213. The gating generator 213 generates a gating signal S220, which is input to the correlator 205. The integration period signal S206 output from the integration period counter 203 is input to the following: the correlator 205, the modified CRNCO frequency update 2070, the modified CRNCO phase shift update 2080, the modified CRNCO locked phase update 2090, the modified IFNCO frequency update 2100, the modified IFNCO phase shift update 2110, the modified IFNCO locked phase update 2120, the locked counter update unit 2140, and the CPU 105.

[0081] The IFNCO 202 generates an intermediate frequency based on the tick signal S107. An intermediate frequency phase (e.g., COS S217 and SIN S218 signals) is output from the unit IFNCO 202 and is input to the correlator 205. The digitized signal output from the ADC 102 is input to the converter 204. One of the selected digitized signals output from the converter 204 is input to the correlator 205.

[0082] In the correlator 205, the intermediate frequency phase from the IFNCO 202 is multiplied by the digitized signal output from the converter 204 and the code signal S219 output from the code generator 201.

[0083] In the correlator 205, the intermediate frequency phase from the unit IFNCO 202 is multiplied by the digitized signal output from the converter 204 and the gating signal S220 output from the gating generator 213.

[0084] The multiplication result is accumulated and stored within the duration of the integration period signal S206. Based on the integration period signal S206, the stored value is copied to the first-stage buffers 410, 411, 412, and 413 of the correlator 205 and is zeroed. The correlator 205 generates the components I, Q, dI, dQ, and the components I, Q, dI, dQ are read by the CPU 105. Based on the tick signal S107, the values are copied from the first-stage buffers 410, 411, 412, and 413 to the second-stage buffers 414, 415, 416, and 417.

[0085] After starting the modified channel 110, the CPU 105 selects the slack tick signal S108 as the update signal for the units 2070, 2080, 2100, and 2110. If necessary, the CPU 105 performs the following operations: change the code frequency in the CRNCO 200, set the code phase shift in the CRNCO 200, change the control in the units 2070, 2080, 2090, 2100, 2110, 2120, and 2140, change the intermediate frequency in the IFNCO 202, set the intermediate frequency phase shift in the IFNCO 202, read the register of the code frequency locked phase in the CRNCO 200, read the register of the intermediate frequency locked phase in the IFNCO 202, read the register of the locked state in the integration period counter 203, read the first-stage buffers 410, 411, 412, and 413 in the correlator 205, and read the second-stage buffers 414, 415, 416, and 417 in the correlator 205. In one embodiment, all update signals operate with the clock CLKnav.

[0086] Figure 11FIG. 0 shows a flowchart of a method 1100 for operating a navigation receiver according to an embodiment. The method steps are performed by components of the navigation receiver as described above. The method starts at step 1102, where GNSS signals are received. In one embodiment, the signals are received from an antenna at the RF path. In one embodiment, the GNSS signals are transferred from the RF path at an intermediate frequency. At step 1104, the GNSS signals are sampled at a frequency CLKnav. In one embodiment, the GNSS signals are sampled by an ADC that receives the GNSS signals from the RF path. At step 1106, a tick signal and a slack tick signal are generated. In one embodiment, the tick signal and the slack tick signal are generated by a time scale generator. At step 1108, a pulse with an intermediate frequency and an intermediate frequency phase is generated. In one embodiment, the pulse is generated by an IFNCO. At step 1110, a code rate NCO signal is generated. In one embodiment, the code rate NCO signal is generated by a code rate NCO and the code rate NCO signal has a frequency and a phase. At step 1112, a code signal is generated based on the code rate NCO frequency. In one embodiment, the code signal is generated by a code generator. At step 1114, a gating signal is generated based on the shape of the code signal and the code rate NCO phase. In one embodiment, the gating signal is generated by a gating generator. At step 1116, an integration period signal is generated based on the code rate NCO phase. In one embodiment, the integration period signal is generated by an integration period counter. At step 1118, signals are multiplied to generate a first product. In one embodiment, the multiplied signals include the signal output from a converter that receives the GNSS signals from the ADC. The multiplied signals also include the signal output from the code generator and the intermediate frequency phase from the IFNCO. In one embodiment, after the first product is generated, the first product is stored. At step 1120, signals are multiplied to generate a second product. In one embodiment, the multiplied signals include the signal output from the converter, the signal from the gating signal, and the intermediate frequency phase from the intermediate frequency NCO. In one embodiment, after the second product is generated, the second product is stored. At step 1122, the navigation receiver is controlled based on the tick signal, the slack tick signal, the first product, and the second product.

[0087] The foregoing detailed description should be understood to be illustrative and exemplary in every aspect and not restrictive, and the scope of the inventive concept disclosed herein should be construed in accordance with the full breadth permitted by patent law. It should be understood that the embodiments shown and described herein are merely illustrative of the principles of the inventive concept, and those skilled in the art can implement various modifications without departing from the scope and spirit of the inventive concept. Without departing from the scope and spirit of the inventive concept, those skilled in the art can achieve various other combinations of features.

Claims

1. A navigation receiver, the navigation receiver comprising: an RF path configured to receive GNSS signals from an antenna and transmit the GNSS signals at an intermediate frequency; an ADC configured to receive the GNSS signals from the RF path at the intermediate frequency and sample the GNSS signals at a frequency CLKnav; a time stamp generator configured to generate a tick signal and a slack tick signal; a channel configured to receive the GNSS signals from the ADC, the channel comprising: an intermediate frequency NCO configured to generate a pulse having the intermediate frequency and an intermediate frequency phase; a CRNCO configured to generate a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency; a code generator configured to generate a code signal based on the code rate NCO frequency; a gating generator configured to generate a gating signal based on the shape of the code signal and the code rate NCO phase; an integration period counter configured to generate an integration period signal based on the code rate NCO frequency; a transducer configured to receive the GNSS signals from the ADC; a correlator configured to: multiply a signal output from the transducer, a signal output from the code generator, and the intermediate frequency phase from the intermediate frequency NCO to generate a first product, and the correlator is configured to: store the first product during the integration period, and the correlator is configured to: multiply a signal output from the transducer, a signal from the gating signal, and the intermediate frequency phase from the intermediate frequency NCO to generate a second product, and the correlator is configured to: store the second product during the integration period; and a CPU that controls the navigation receiver and reads data from the correlator.

2. The navigation receiver according to claim 1, wherein The CRNCO is further configured to: generate the code rate NCO frequency based on one of: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from an update CRNCO.

3. The navigation receiver according to claim 1, wherein, The CRNCO is further configured to: generate the code rate NCO phase shift based on one of: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from an update CRNCO.

4. The navigation receiver according to claim 1, the navigation receiver further comprising an update locked phase CRNCO that communicates with the CRNCO, the update locked phase CRNCO being configured to generate a CRNCO locked phase update signal based on one of: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from an update CRNCO.

5. The navigation receiver according to claim 1, wherein, The intermediate frequency NCO frequency update signal is selected from one of the following: the tick signal, the slack tick signal, the integration period signal, and the immediate signal output from the updated intermediate frequency NCO.

6. The navigation receiver according to claim 1, wherein, The intermediate frequency NCO phase shift update signal is selected from one of the following: the tick signal, the slack tick signal, the integration period signal, and the immediate signal from the updated intermediate frequency NCO.

7. The navigation receiver according to claim 1, wherein the navigation receiver further comprises an updated frequency intermediate frequency NCO configured to generate an intermediate frequency NCO frequency update signal that causes the current intermediate frequency phase to be locked to the intermediate frequency NCO, and the intermediate frequency NCO frequency update signal is based on one of the tick signal, the slack tick signal, the integration period signal, and the immediate signal output from the updated intermediate frequency NCO.

8. The navigation receiver according to claim 1, wherein The CPU is configured to: copy the code frequency signal to the buffer register of the code rate NCO based on the update signal.

9. The navigation receiver according to claim 1, wherein, The CPU is configured to: copy the intermediate frequency control signal to the interface register of the buffer register in the intermediate frequency NCO based on the update signal.

10. The navigation receiver according to claim 1, wherein, The code rate NCO is further configured to: perform a phase shift on the code rate NCO code phase based on the update signal.

11. The navigation receiver according to claim 1, wherein, The intermediate frequency NCO is further configured to: perform a phase shift on the intermediate frequency in the intermediate frequency NCO based on the update signal.

12. The navigation receiver according to claim 1, wherein, The CPU is configured to: store the value of the first-stage buffer in the correlator during the integration period.

13. The navigation receiver according to claim 1, wherein, The CPU is configured to: copy data from the first-stage buffer based on the tick signal and store the data from the first-stage buffer into the second-stage buffer.

14. The navigation receiver according to claim 1, wherein, The period of the slack tick signal is a multiple of the period of the tick signal.

15. A method for operating a navigation receiver, the method comprising: Receiving GNSS signals; Sampling the GNSS signals at a frequency CLKnav; Generating a tick signal and a slack tick signal; Generating a pulse having an intermediate frequency and an intermediate frequency phase; Generating a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency; Generating a code signal based on the code rate NCO frequency; Generating a gating signal based on the shape of the code signal and the code rate NCO phase; Generating an integration period signal based on the code rate NCO frequency; Multiplying the signal output from the transducer for receiving the sampled GNSS signals, the code signal, and the intermediate frequency phase to generate a first product, which is stored during the period identified by the integration period signal; Multiplying the signal output from the transducer for receiving the sampled GNSS signals, the gating signal, and the intermediate frequency phase to generate a second product, which is stored during the period identified by the integration period signal; And Controlling the navigation receiver based on the tick signal, the slack tick signal, the first product, and the second product.

16. The method according to claim 15, wherein the method further comprises: The code rate NCO generates the code rate NCO frequency based on one of the following: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from one of an updated code rate NCO or an updated intermediate frequency NCO.

17. The method according to claim 15, the method further comprising: The code rate NCO generates the code rate NCO phase shift based on one of the following: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from one of an updated code rate NCO or an updated intermediate frequency NCO.

18. The method according to claim 15, the method further comprising: The intermediate frequency NCO generates the intermediate frequency NCO frequency based on one of the following: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from the updated intermediate frequency NCO.

19. The method according to claim 15, the method further comprising: The intermediate frequency NCO generates the intermediate frequency NCO phase shift based on one of the following: the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from the updated intermediate frequency NCO.

20. A navigation receiver, the navigation receiver comprising: means for receiving GNSS signals; means for sampling the GNSS signals at a frequency CLKnav; means for generating a tick signal and a slack tick signal; means for generating pulses having an intermediate frequency and an intermediate frequency phase; means for generating a code rate NCO signal having a code rate NCO phase and a code rate NCO frequency; means for generating a code signal based on the code rate NCO frequency; means for generating a gating signal based on the shape of the code signal and the code rate NCO phase; means for generating an integration period signal based on the code rate NCO frequency; means for multiplying a signal output from a transducer that receives the sampled GNSS signals, the code signal, and the intermediate frequency phase to generate a first product; means for storing the first product during a period identified by the integration period signal; means for multiplying a signal output from a transducer that receives the sampled GNSS signals, the gating signal, and the intermediate frequency phase to generate a second product; means for storing the second product during a period identified by the integration period signal; and means for controlling the navigation receiver based on the tick signal, the slack tick signal, the first product, and the second product.

21. The navigation receiver according to claim 20, the navigation receiver further comprising: means for generating the code rate NCO frequency based on one of the tick signal, the slack tick signal, the integration period signal, and an immediate signal output from an updated CRNCO.

22. The navigation receiver according to claim 20, the navigation receiver further comprising: Apparatus for generating the code rate NCO phase based on one of the tick signal, the slack tick signal, the integration period signal, and the immediate signal output from the updated CRNCO.

23. The navigation receiver according to claim 20, further comprising: Apparatus for generating the intermediate frequency NCO frequency based on one of the tick signal, the slack tick signal, the integration period signal, and the immediate signal output from the updated intermediate frequency NCO.

24. The navigation receiver according to claim 20, further comprising: Apparatus for generating the intermediate frequency NCO phase shift based on one of the tick signal, the slack tick signal, the integration period signal, and the immediate signal output from the updated intermediate frequency NCO.

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