A gate driving circuit and a display panel

Abstract

The application discloses a gate drive circuit and a display panel. The gate drive circuit comprises a plurality of cascaded GOA units. A first output end of a GOA circuit of an nth-stage GOA unit is connected with a scan control end of an nth-row pixel circuit to output an nth-stage scan signal. The first output end of the GOA circuit is also connected with a reset control end of an nth+m-row pixel circuit to output the nth-stage scan signal. A first input end of an internal compensation circuit of the nth-stage GOA unit is connected with the first output end of the GOA circuit of the nth-stage GOA unit to receive the nth-stage scan signal. A second input end of the internal compensation circuit is connected with a first output end of a GOA circuit of an nth-m-stage GOA unit to receive an nth-m-stage scan signal. A first output end of the internal compensation circuit is connected with a compensation control end of the nth-row pixel circuit to output a compensation control signal to the nth-row pixel circuit. The application reduces the number of transistors, and is conducive to realizing a narrow frame or a frameless display panel.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display panel driving, in particular to a gate driving circuit and a display panel. BACKGROUND

[0002] Gate Driver On Array (GOA) is a driving mode in which a gate row scanning driving signal circuit is manufactured on an array substrate by using an existing thin film transistor liquid crystal display array process to realize row-by-row driving of a gate.

[0003] A display device needs to meet the internal Vth compensation function in the working process of a Pixel Circuit, and the signal thereof needs driving signals such as a reset signal, a compensation control signal and a write signal. Due to the relatively large number of driving signals required, the number of transistors and clock signals (CK) is relatively large, resulting in a relatively wide Border space. SUMMARY

[0004] Embodiments of the present application provide a gate driving circuit and a display panel, which can reduce the occupied space of the gate driving circuit and achieve the narrow-border or borderless requirement of the display panel.

[0005] In a first aspect, the present application provides a gate driving circuit, comprising a plurality of cascaded GOA units, and an nth GOA unit comprising a GOA circuit and an internal compensation circuit.

[0006] A first output end of the GOA circuit is connected with a scan control end of an nth row of pixel circuits, for outputting an nth stage scan signal to the nth row of pixel circuits, and the first output end of the GOA circuit is also connected with a reset control end of an nth+m row of pixel circuits, for outputting the nth stage scan signal to the nth+m row of pixel circuits.

[0007] A first input end of the internal compensation circuit is connected with the first output end of the GOA circuit of the nth GOA unit, for receiving the nth stage scan signal; a second input end of the internal compensation circuit is connected with a first output end of a GOA circuit of an nth-m GOA unit, for receiving an nth-m stage scan signal; and a first output end of the internal compensation circuit is connected with a compensation control end of the nth row of pixel circuits, for outputting a compensation control signal to the nth row of pixel circuits.

[0008] Wherein, n and m are positive integers, and n > m.

[0009] In a second aspect, the present application further provides a display panel, comprising the gate driving circuit of the first aspect.

[0010] The gate drive circuit and the display panel provided by the application comprise a plurality of cascaded GOA units, the nth stage GOA unit comprises a GOA circuit and an internal compensation circuit, a first output end of the internal compensation circuit in the nth stage GOA unit is connected with a compensation control end of the nth row of pixel circuits to provide a compensation control signal, a first output end of the GOA circuit of the nth stage GOA unit is respectively connected with a scan control end of the nth row of pixel circuits, a reset control end of the nth+m row of pixel circuits, and a first input end of the internal compensation circuit in the nth stage GOA unit and the nth+m stage GOA unit to provide an nth stage scan signal, wherein the nth stage scan signal provided by the first output end of the GOA circuit of the nth stage GOA unit can be used as the scan signal of the nth row of pixel circuits or the reset signal of the nth+m row of pixel circuits, the number of transistors for generating the reset signal is reduced, thereby the width of the frame is reduced, which is beneficial to realize the narrow frame or frameless of the display panel and improve the specification of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0012] Figure 1 FIG. 1 is a structural schematic diagram of the gate drive circuit provided by the embodiment of the application;

[0013] Figure 2 FIG. 2 is a circuit schematic diagram of the GOA circuit of the nth stage GOA unit provided by the embodiment of the application;

[0014] Figure 3 FIG. 3 is a circuit schematic diagram of the internal compensation circuit of the nth stage GOA unit provided by the embodiment of the application;

[0015] Figure 4 FIG. 4 is a circuit schematic diagram of the nth row of pixel circuits provided by the embodiment of the application;

[0016] Figure 5 FIG. 5 is a timing schematic diagram of the gate drive circuit provided by the embodiment of the application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the application.

[0018] In the description of the application, it needs to be understood that the orientation or positional relationship indicated by the terms "one end", "the other end" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the application, the meaning of "a plurality of" is two or more, unless otherwise explicitly specified and limited.

[0019] In the description of the application, it needs to be understood that the terms "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be connected or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, or it can be the internal communication of two elements or the interaction relationship between two elements. For those skilled in the art, the specific meaning of the above terms in the application can be understood according to the specific circumstances.

[0020] The following disclosure provides many different embodiments or examples for implementing different structures of the application. In order to simplify the disclosure of the application, the components and arrangements of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the application. In addition, reference numerals and / or reference letters can be repeated in different examples in the application, and such repetition is for the purpose of simplification and clarity, and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In the above embodiments, the description of each embodiment is focused on, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0021] The display panel in the embodiments of the application can be used in mobile phones, tablet computers, desktop computers, laptop computers, e-readers, handheld computers, electronic display screens, notebook computers, ultra-mobile personal computers (UMPC), netbooks, and cellular phones, personal digital assistants (PDA), augmented reality (AR) \ virtual reality (VR) devices, media players, wearable devices, digital cameras, car navigation systems, etc.

[0022] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0023] Please see Figure 1 , Figure 1 This is a schematic diagram of the gate drive circuit provided in this application, as shown below. Figure 1 As shown, the gate drive circuit includes multiple cascaded GOA units, and the nth GOA unit includes: GOA circuit 100 and internal compensation circuit 200;

[0024] The first output terminal of the GOA circuit 100 is connected to the scan control terminal InA of the nth row pixel circuit, and is used to output the nth level scan signal Gn[n] to the nth row pixel circuit. The first output terminal of the GOA circuit 100 is also connected to the reset control terminal INI of the (n+m)th row pixel circuit, and is used to output the nth level scan signal Gn[n] to the (n+m)th row pixel circuit.

[0025] The first input terminal of the internal compensation circuit 200 is connected to the first output terminal of the GOA circuit 100 of the nth level GOA unit, and is used to receive the nth level scan signal Gn[n]; the second input terminal of the internal compensation circuit 200 is connected to the first output terminal of the GOA circuit 100 of the nm level GOA unit, and is used to receive the nm level scan signal Gn[nm]; the first output terminal of the internal compensation circuit 200 is connected to the compensation control terminal InB of the nth row pixel circuit, and is used to output the compensation control signal REF[n] to the nth row pixel circuit.

[0026] Where n and m are both positive integers, and n > m.

[0027] Specifically, each GOA unit includes a GOA circuit 100 and an internal compensation circuit 200, such as Figure 1As shown, the first output terminal of the internal compensation circuit 200 in the nth level GOA unit is connected to the compensation control terminal InB of the nth row pixel circuit to output a compensation control signal to the compensation control terminal InB of the nth row pixel circuit. A first branch L1 branches off from the first output terminal of the GOA circuit 100 in the nth level GOA unit and connects to the first input terminal of the internal compensation circuit 200 in the nth level GOA unit to output the nth level scan signal Gn[n] to the first input terminal of the internal compensation circuit 200 in the nth level GOA unit. A second branch L2 branches off from the first output terminal of the GOA circuit 100 in the nth level GOA unit and connects to the second input terminal of the internal compensation circuit 200 in the (n+m)th level GOA unit to output the nth level scan signal Gn[n] to the second input terminal of the internal compensation circuit 200 in the (n+m)th level GOA unit. Thus, the nth-level scan signal provided by the first output terminal of the GOA circuit 100 of the nth-level GOA unit can be used as the trigger control signal for the internal compensation circuit 200 of the nth-level GOA unit and the (n+m)th-level GOA unit. This triggers the internal compensation circuit 200 of the nth-level GOA unit to start working, providing a compensation control signal to the compensation control terminal InB of the nth row pixel circuit. At the same time, it triggers the internal compensation circuit 200 of the (n+m)th-level GOA unit to start working, providing a compensation control signal to the compensation control terminal InB of the (n+m)th row pixel circuit, thereby compensating for the timing of the m-row sequence.

[0028] In addition, such as Figure 1 As shown, in the nth-level GOA unit, the first output terminal of the GOA circuit 100 branches off a third branch L3 to connect to the scan control terminal InA of the nth row pixel circuit, so as to output the nth-level scan signal Gn[n] to the scan control terminal InA of the nth row pixel circuit. In the nth-level GOA unit, the first output terminal of the GOA circuit 100 branches off a fourth branch L4 to connect to the reset control terminal INI of the (n+m)th row pixel circuit, so as to output the nth-level scan signal Gn[n] to the reset control terminal INI of the (n+m)th row pixel circuit, so that the (n+m)th row pixel circuit multiplexes the nth-level scan signal Gn[n], so as to replace the required reset signal INI[n] with the nth-level scan signal Gn[n] to trigger the (n+m)th row pixel circuit to start the reset operation. Thus, the nth-level scan signal provided by the first output terminal of the GOA circuit 100 of the nth-level GOA unit can be used as the scan signal of the nth row pixel circuit or as the reset signal of the n+m row pixel circuit, reducing the number of transistors that generate the reset signal, thereby reducing the width of the bezel, which is beneficial to realizing a narrow bezel or bezel-less display panel and improving the specifications of the display panel.

[0029] In some embodiments, the GOA circuit 100 includes: a first pull-up module 110 and a first pull-down control module 120;

[0030] The first output end of the first pull-up module 110, the first output end and the second output end of the first pull-down control module 120 are all used as the first output end of the GOA circuit 100.

[0031] Specifically, the first output end of the first pull-up module 110, the first output end and the second output end of the first pull-down control module 120 are used as the first output end of the GOA circuit 100, and are connected with the first input end of the internal compensation circuit 200, the second input end of the internal compensation circuit 200, the scan control end InA of the nth row of pixel circuits and the reset control end INI of the nth+m row of pixel circuits. In this application, the reset signal generated in the GOA circuit 100 for triggering the nth+m row of pixel circuits to start the reset work is replaced by the nth stage scan signal, so that the number of transistors generating the reset signal in the GOA circuit 100 can be reduced, thereby reducing the width of the frame, which is conducive to realizing the narrow frame or frameless of the display panel and improving the specification of the display panel.

[0032] In some embodiments, the first pull-up module 110 comprises a first transistor T22.

[0033] The drain of the first transistor T22 is connected with a first clock signal end to receive a first clock signal group CKB1-CKB8, the source of the first transistor T22 is used as the first output end of the first pull-up module 110, and the gate of the first transistor T22 is connected with a first node Q[n].

[0034] Specifically, as shown in Figure 2 The gate of the first transistor T22 is connected with the first node Q[n], and the source of the first transistor T22 is used as the first output end of the first pull-up module 110. Since the first output end of the first pull-up module 110 is used as the first output end of the GOA circuit 100, the source of the first transistor T22 can output the nth stage scan signal Gn[n] as the first output end of the GOA circuit 100, and the drain of the first transistor T22 is connected with the first clock signal end to receive the first clock signal group CKB1-CKB8. When the first node Q[n] is pulled up to high level, the first transistor T22 is turned on or opened. When the first transistor T22 is opened and the first clock signal received by the first transistor T22 is high level, the nth stage scan signal Gn[n] output by the source of the first transistor T22 is high level.

[0035] In some embodiments, the first pull-down control module 120 comprises a second transistor T32A and a third transistor T32B.

[0036] The drain of the second transistor T32A serves as the first output terminal of the first pull-down control module 120. The gate of the second transistor T32A is connected to the second node QBA[n]. The source of the second transistor T32A is connected to the first low voltage terminal to receive the first power supply low voltage VGL1.

[0037] The drain of the third transistor T32B serves as the second output terminal of the first pull-down control module 120. The gate of the third transistor T32B is connected to the third node QBB[n]. The source of the third transistor T32B is connected to the first low voltage terminal to receive the first power supply low voltage VGL1.

[0038] Specifically, such as Figure 2 As shown, the drain of the second transistor T32A serves as the first output terminal of the first pull-down control module 120. Since the first output terminal of the first pull-down control module 120 serves as the first output terminal of the GOA circuit 100, the drain of the second transistor T32A can also serve as the first output terminal of the GOA circuit 100 to output the nth level scan signal Gn[n]. The drain of the third transistor T32B serves as the second output terminal of the first pull-down control module 120. Since the second output terminal of the first pull-down control module 120 serves as the first output terminal of the GOA circuit 100, the drain of the third transistor T32B can also serve as the first output terminal of the GOA circuit 100 to output the nth level scan signal Gn[n]. The gate of the second transistor T32A is connected to the second node QBA[n], and the gate of the third transistor T32B is connected to the third node QBB[n]. The sources of both the second transistor T32A and the third transistor T32B are connected to the first low-voltage terminal to receive the first low-voltage power supply VGL1. This application sets up a first pull-down control module 120 so that after the gate drive circuit outputs the nth level scan signal Gn[n], the potential of the first output terminal of the GOA circuit 100 can be pulled down to a low potential.

[0039] In some embodiments, the GOA circuit 100 further includes a pull-up control module 130, which includes an eighteenth transistor T11A and a nineteenth transistor T12A;

[0040] The drain of the eighteenth transistor T11A is connected with the n-kth stage transmission signal end to receive the n-kth stage transmission Cout[n-k], the gate of the eighteenth transistor T11A is connected with the drain of the eighteenth transistor T11A, and the source of the eighteenth transistor T11A is connected with the drain of the nineteenth transistor T12A. The gate of the nineteenth transistor T12A is connected with the n-kth stage transmission signal end to receive the n-kth stage transmission Cout[n-k], and the source of the nineteenth transistor T12A is connected with the first node Q[n]. The potential of the first node Q[n] is controlled by the pull-up control module 130, k is a positive integer, and k is less than n.

[0041] In some embodiments, the GOA circuit 100 further includes a first leakage prevention module 140, which includes a twentieth transistor T71_1 and a twenty-first transistor T7_2.

[0042] The gate of the twentieth transistor T71_1 and the gate of the twenty-first transistor T7_2 are connected with the first node Q[n], the source of the twentieth transistor T71_1 is connected with a control signal end N[n], the drain of the twentieth transistor T71_1 is connected with the source of the twenty-first transistor T7_2, and the drain of the twenty-first transistor T7_2 is connected with a first high voltage end to receive the first power supply high voltage VGH1. By setting the first leakage prevention module 140, the GOA circuit 100 can prevent leakage.

[0043] In some embodiments, the GOA circuit 100 further includes a third pull-down control module 101, which includes a twenty-second transistor T42B and a twenty-third transistor T41B. The source of the twenty-second transistor T42B is connected with a third low voltage end to receive a third power supply low voltage VGL3, the drain of the twenty-second transistor T42B is connected with the source of the twenty-third transistor T41B, and the drain of the twenty-third transistor T41B is connected with the first node Q[n]. The gate of the twenty-second transistor T42B and the gate of the twenty-third transistor T41B are both connected with an n+kth stage transmission signal end to receive an n+kth stage transmission Cout[n+k].

[0044] In some embodiments, the GOA circuit 100 further comprises a first inverter 150, the first inverter 150 comprising a twenty-fourth transistor T51A_1, a twenty-fifth transistor T51A_2, a twenty-sixth transistor T52A, a twenty-seventh transistor T53A, a twenty-eighth transistor T54A, a twenty-ninth transistor T56A, a gate and a drain of the twenty-fourth transistor T51A_1 and a gate of the twenty-fifth transistor T51A_2 and a drain of the twenty-seventh transistor T53A are connected with a first low-frequency clock signal end to receive a first low-frequency clock signal LC2, a source of the twenty-fourth transistor T51A_1 is connected with a drain of the twenty-fifth transistor T51A_2, a source of the twenty-fifth transistor T51A_2 is connected with a drain of the twenty-sixth transistor T52A and a gate of the twenty-seventh transistor T53A, a gate of the twenty-sixth transistor T52A and a gate of the twenty-eighth transistor T54A are connected with the first node Q[n], a source of the twenty-sixth transistor T52A is connected with a third low-voltage end to receive a third power low voltage VGL3, a source of the twenty-seventh transistor T53A is connected with the second node QBA[n], a drain of the twenty-eighth transistor T54A is connected with the second node QBA[n], a drain of the twenty-ninth transistor T56A is connected with the second node QBA[n], a source of the twenty-eighth transistor T54A is connected with the third low-voltage end to receive the third power low voltage VGL3, a source of the twenty-ninth transistor T56A is connected with the third low-voltage end to receive the third power low voltage VGL3, and a gate of the twenty-ninth transistor T56A is connected with an n-kth level transfer signal end to receive an n-kth level transfer Cout[n-k]. By setting the first inverter 150, the potentials of the first node Q and the second node QBA[n] are reversed, so that the circuit works normally.

[0045] In some embodiments, the GOA circuit 100 further comprises a second inverter 170, the second inverter 170 comprising a thirty-first transistor T51B_1, a thirty-second transistor T51B_2, a thirty-third transistor T52B, a thirty-fourth transistor T53B, a thirty-fifth transistor T54B, and a thirty-sixth transistor T56B, a gate and a drain of the thirty-first transistor T51B_1 and a gate of the thirty-second transistor T51B_2 and a drain of the thirty-third transistor T53B are connected with a second low-frequency clock signal end to receive a second low-frequency clock signal LC2, a source of the thirty-first transistor T51B_1 is connected with a drain of the thirty-second transistor T51B_2, a source of the thirty-second transistor T51B_2 is connected with a drain of the thirty-second transistor T52B and a gate of the thirty-third transistor T53B, a gate of the thirty-second transistor T52B and a gate of the thirty-fourth transistor T54B are connected with the first node Q[n], a source of the thirty-second transistor T52B is connected with a third low-voltage end to receive a third power low voltage VGL3, a source of the thirty-third transistor T53B is connected with the third node QBB[n], a drain of the thirty-fourth transistor T54B is connected with the third node QBB[n], a drain of the thirty-fifth transistor T56B is connected with the third node QBB[n], a source of the thirty-fourth transistor T54B is connected with the third low-voltage end to receive the third power low voltage VGL3, a source of the thirty-fifth transistor T56B is connected with the third low-voltage end to receive the third power low voltage VGL3, and a gate of the thirty-fifth transistor T56B is connected with an n-kth stage transfer signal end to receive an n-kth stage transfer Cout[n-k]. By setting the second inverter 170, the potentials of the first node Q and the third node QBB[n] are reversed, so that the circuit works normally.

[0046] In some embodiments, the GOA circuit 100 further comprises a second pull-up module 190, the second pull-up module 190 comprising a thirty-sixth transistor T21, a source of the thirty-sixth transistor T21 is connected with a second clock signal end to receive a second clock signal group CKA1-CKA8, a drain of the thirty-sixth transistor T21 is connected with an n-th stage transfer signal end to output an n-th stage transfer signal Cout[n], and a gate of the thirty-sixth transistor T21 is connected with the first node Q[n].

[0047] In some embodiments, the GOA circuit 100 further comprises a reset module 160, the reset module 160 comprising a thirty-seventh transistor T45 and a thirty-eighth transistor T46; a gate of the thirty-seventh transistor T45 and a gate of the thirty-eighth transistor T46 are connected with a global reset signal terminal VST; a drain of the thirty-seventh transistor T45 is connected with the first node Q[n], and a source of the thirty-seventh transistor T45 is connected with a drain of the thirty-eighth transistor T46; a source of the thirty-eighth transistor T46 is connected with a third low voltage terminal to receive a third power low voltage VGL3.

[0048] In some embodiments, the GOA circuit 100 further comprises a second pull-down maintaining module 180, the second pull-down maintaining module 180 comprising a thirty-ninth transistor T43A, a fortieth transistor T44A, a forty-first transistor T43B and a forty-second transistor T44B; a gate of the thirty-ninth transistor T43A and a gate of the fortieth transistor T44A are connected with a control signal terminal N[n], a drain of the thirty-ninth transistor T43A is connected with the first node Q[n], a source of the thirty-ninth transistor T43A is connected with a drain of the fortieth transistor T44A, and a source of the fortieth transistor T44A is connected with the third low voltage terminal to receive the third power low voltage VGL3. A gate of the forty-first transistor T43B and a gate of the forty-second transistor T44B are connected with the control signal terminal N[n], a drain of the forty-first transistor T43B is connected with the first node Q[n], a source of the forty-first transistor T43B is connected with a drain of the forty-second transistor T44B, and a source of the forty-second transistor T44B is connected with the third low voltage terminal to receive the third power low voltage VGL3.

[0049] In some embodiments, the internal compensation circuit 200 comprises a first pull-up control module 210, a second pull-down control module 220, a first pull-down maintaining module 230 and a compensation module 240.

[0050] The first control end of the second pull-down control module 220 and the first control end of the first pull-down maintaining module 230 are used as the first input end of the internal compensation circuit 200.

[0051] The first control end of the first pull-up control module 210, the second control end and the third control end of the first pull-down maintaining module 230 are used as the second input end of the internal compensation circuit 200.

[0052] The output end of the compensation module 240 is used as the first output end of the internal compensation circuit 200.

[0053] Specifically, the first control end of the second pull-down control module 220 and the first control end of the first pull-down maintaining module 230 are connected with the first output end of the GOA circuit 100 as the first input end of the internal compensation circuit 200, the first control end of the first pull-up control module 210, the second control end and the third control end of the first pull-down maintaining module 230 are connected with the first output end of the GOA circuit 100 as the second input end of the internal compensation circuit 200, and the output end of the compensation module 240 is connected with the compensation control end InB of the nth row of pixel circuits as the first output end of the internal compensation circuit 200, for outputting a compensation control signal REF[n] to the nth row of pixel circuits.

[0054] In some embodiments, the first pull-up control module 210 comprises a fourth transistor T11 and a fifth transistor T12.

[0055] The gate of the fourth transistor T11 and the gate of the fifth transistor T12 are connected as the first control end of the first pull-up control module 210.

[0056] The drain of the fourth transistor T11 is connected with a first high voltage end to receive a first power high voltage VGH1, and the source of the fourth transistor T11 is connected with the drain of the fifth transistor T12.

[0057] The source of the fifth transistor T12 is connected with a fourth node Q.

[0058] Specifically, as shown in Figure 3 The gate of the fourth transistor T11 and the gate of the fifth transistor T12 are connected as the first control end of the first pull-up control module 210, and since the first control end of the first pull-up control module 210 is the second input end of the internal compensation circuit 200, as shown in Figures 1 to 3 The gate of the fourth transistor T11 and the gate of the fifth transistor T12 are connected as the second input end of the internal compensation circuit 200 and the output end of the GOA circuit 100 of the nth-m level GOA unit to receive the nth-m level scanning signal Gn[n-m]. The drain of the fourth transistor T11 is connected with a first high voltage end to receive a first power high voltage VGH1, and the source of the fourth transistor T11 is connected with the drain of the fifth transistor T12, and the source of the fifth transistor T12 is connected with a fourth node Q. By setting the first pull-up control module 210, the potential of the fourth node Q can be controlled after the gate of the fourth transistor T11 and the gate of the fifth transistor T12 receive the nth-m level scanning signal Gn[n-m].

[0059] In some embodiments, the second pull-down control module 220 comprises a sixth transistor T41 and a seventh transistor T42.

[0060] The gate of the sixth transistor T41 and the gate of the seventh transistor T42 both serve as a first control end of the second pull-down control module 220.

[0061] The source of the sixth transistor T41 is connected with the first low-voltage end to receive the first power low voltage VGL1, the drain of the sixth transistor T41 is connected with the source of the seventh transistor T42, and the drain of the seventh transistor T42 is connected with the fourth node Q.

[0062] Specifically, as shown in FIG. 4, the gate of the sixth transistor T41 and the gate of the seventh transistor T42 both serve as the first control end of the second pull-down control module 220. Since the first control end of the second pull-down control module 220 serves as a first input end of the internal compensation circuit 200, as shown in FIG. 5, the gate of the sixth transistor T41 and the gate of the seventh transistor T42 serve as the first input end of the internal compensation circuit 200 to receive the nth-stage scan signal G[n]. Figure 3 Figures 1 to 3 The drain of the sixth transistor T41 is connected with the first high-voltage end to receive the first power high voltage VGH1, the source of the sixth transistor T41 is connected with the drain of the seventh transistor T42, and the source of the seventh transistor T42 is connected with the fourth node Q. By arranging the second pull-down control module 220, the potential of the fourth node Q can be controlled after the gate of the sixth transistor T41 and the gate of the seventh transistor T42 receive the nth-stage scan signal Gn[n].

[0063] In some embodiments, the first pull-down maintenance module 230 comprises an eighth transistor T57, a ninth transistor T58, a tenth transistor T51, an eleventh transistor T52, a twelfth transistor T53, a thirteenth transistor T54, a fourteenth transistor T56, and a fifteenth transistor T55.

[0064] The gate of the eighth transistor T57 and the gate of the ninth transistor T58 both serve as a second control end of the first pull-down maintenance module 230.

[0065] The source of the eighth transistor T57 is connected with the first low-voltage end to receive the first power low voltage VGL1, the drain of the eighth transistor T57 is connected with the source of the ninth transistor T58, and the drain of the ninth transistor T58 is connected with the fifth node T.

[0066] ​The gate of the tenth transistor T51 and the gate of the eleventh transistor T52 both serve as a first control end of the first pull-down maintenance module 230.

[0067] The drain of the tenth transistor T51 is connected with the gate of the tenth transistor T51, the source of the tenth transistor T51 is connected with the drain of the eleventh transistor T52, the source of the tenth transistor T51 is also connected with the source of the twelfth transistor T53, and the source of the eleventh transistor T52 is connected with the fifth node T.

[0068] The drain of the twelfth transistor T53 is connected with the first high voltage end to receive a first power supply high voltage VGH1, and the gate of the twelfth transistor T53 is connected with the fifth node T.

[0069] The gate of the thirteenth transistor T54 is connected with the fifth node T, the drain of the thirteenth transistor T54 is connected with the first high voltage end to receive the first power supply high voltage VGH1, and the source of the thirteenth transistor T54 is connected with the drain of the fourteenth transistor T56.

[0070] The gate of the fourteenth transistor T56 serves as a third control end of the first pull-down maintenance module 230, and the source of the fourteenth transistor T56 is connected with the first low voltage end to receive the first power supply low voltage VGL1.

[0071] The gate of the fifteenth transistor T55 is connected with the fourth node Q, the drain of the fifteenth transistor T55 is connected with the drain of the fourteenth transistor T56, and the source of the fifteenth transistor T55 is connected with the first low voltage end to receive the first power supply low voltage VGL1.

[0072] Specifically, the gates of the eighth transistor T57 and the ninth transistor T58 both serve as the second control terminals of the first pull-down sustaining module 230, and the gate of the fourteenth transistor T56 serves as the third control terminal of the first pull-down sustaining module 230. Since the second and third control terminals of the first pull-down sustaining module 230 are used as the second input terminals of the internal compensation circuit 200, the gates of the eighth transistor T57, the ninth transistor T58, and the fourteenth transistor T56 all serve as the second input terminals of the internal compensation circuit 200 to receive the nm-th level scan signal Gn[nm]. The gates of the tenth transistor T51 and the eleventh transistor T52 both serve as the first control terminals of the first pull-down sustaining module 230. Since the first control terminal of the first pull-down sustaining module 230 serves as the first input terminal of the internal compensation circuit 200, the gates of the tenth transistor T51 and the eleventh transistor T52 serve as the first input terminals of the internal compensation circuit 200 to receive the n-th level scan signal G[n].

[0073] In some embodiments, the compensation module 240 includes: a sixteenth transistor T24 and a seventeenth transistor T31;

[0074] The source of the sixteenth transistor T24 is connected to the drain of the seventeenth transistor T31, and serves as the output terminal of the compensation module 240.

[0075] The drain of the sixteenth transistor T24 is connected to the second high voltage terminal to receive the second power supply high voltage VGH2, and the gate of the sixteenth transistor T24 is connected to the fourth node Q.

[0076] The source of the seventeenth transistor T31 is connected to the second low voltage terminal to receive the second power supply low voltage VGL2, and the gate of the seventeenth transistor T31 is connected to the drain of the fourteenth transistor T56.

[0077] Specifically, such as Figures 1 to 3 As shown, the source of the sixteenth transistor T24 serves as the first output terminal of the compensation module 240, and the drain of the seventeenth transistor T31 serves as the second output terminal of the compensation module 240. Since both the first and second output terminals of the compensation module 240 serve as the first output terminals of the internal compensation circuit 200, the source of the sixteenth transistor T24 and the drain of the seventeenth transistor T31 serve as the first output terminals of the internal compensation circuit 200 to output the compensation control signal REF[n] to the compensation control terminal InB of the nth row pixel circuit. The circuit structure of the nth row pixel circuit is as follows. Figure 4 As shown.

[0078] In some embodiments, the internal compensation circuit 200 further comprises a second leakage prevention module 250, the second leakage prevention module 250 comprising: a forty-fifth transistor T61_1 and a forty-sixth transistor T6_2;

[0079] The gate of the forty-fifth transistor T61_1 and the gate of the forty-sixth transistor T6_2 are connected with the fourth node Q; the source of the forty-fifth transistor T61_1 is connected with a control signal end N[n], the drain of the forty-fifth transistor T61_1 is connected with the source of the forty-sixth transistor T6_2, and the drain of the forty-sixth transistor T6_2 is connected with a first high voltage end to receive the first power supply high voltage VGH1. By setting the second leakage prevention module 250, the internal compensation circuit 200 can prevent leakage.

[0080] In some embodiments, the internal compensation circuit 200 further comprises a fourth pull-down control module 260, the fourth pull-down control module 260 comprising: a forty-seventh transistor T43 and a forty-eighth transistor T44;

[0081] The gate of the forty-seventh transistor T43 and the gate of the forty-eighth transistor T44 are connected with the sixth node QB; the drain of the forty-seventh transistor T43 is connected with the fourth node Q, the source of the forty-seventh transistor T43 is connected with the drain of the forty-eighth transistor T44, and the source of the forty-eighth transistor T44 is connected with a first low voltage end to receive the first power supply low voltage VGL1. By setting the fourth pull-down control module 260, the potential of the fourth node Q is controlled.

[0082] In some embodiments, the nth row of pixel circuits comprises: a forty-ninth transistor T1, a fiftieth transistor T2, a fifty-first transistor T3, a fifty-second transistor T4, a storage capacitor Cst, and a light-emitting diode D1;

[0083] The gate of the fiftieth transistor T2 is connected with the first output end of the GOA circuit 100 in the nth-stage GOA unit to receive the nth-stage scanning signal G[n], the source of the fiftieth transistor T2 is connected with the data line to receive the data signal Data, and the drain of the fiftieth transistor T2 is connected with the first reset node K; the gate of the forty-ninth transistor T1 is connected with the first reset node K, the source of the forty-ninth transistor T1 is connected with the first voltage end to receive the constant-voltage high-level source VDD, and the drain of the forty-ninth transistor T1 is connected with the second reset node R; the gate of the fifty-second transistor T4 is connected with the first output end of the GOA circuit 100 in the nth-m-stage GOA unit to receive the nth-m-stage scanning signal G[n-m], the source of the fifty-second transistor T4 is connected with the second voltage end to receive the first reference potential Vini, and the drain of the fifty-second transistor T4 is connected with the second reset node R; the gate of the fifty-first transistor T3 is connected with the first output end of the internal compensation circuit 200 in the nth-stage GOA unit to receive the compensation control signal REF[n], the source of the fifty-first transistor T3 is connected with the third voltage end to receive the second reference potential Vref, and the drain of the fifty-first transistor T3 is connected with the first reset node K; the first plate of the storage capacitor Cst is connected with the first reset node K, and the second plate of the storage capacitor Cst is connected with the second reset node R.

[0084] The GOA circuit according to the present application is shown in FIG. 1, which comprises a GOA circuit 100 and an internal compensation circuit 200. Figures 1 to 4 The GOA circuit according to the present application is shown in FIG. 1, which comprises a GOA circuit 100 and an internal compensation circuit 200.

[0085] In some embodiments, the channel type of the transistors included in the GOA circuit 100 and the internal compensation circuit 200 is N type.

[0086] The GOA circuit according to the present application is shown in FIG. 1, which comprises a GOA circuit 100 and an internal compensation circuit 200. Figures 1 to 5As shown, during time period T1, when the nm-th level scan signal Gn[nm] is high and the n-th level scan signal G[n] is low, the fourth transistor T11 and the fifth transistor T12 in the n-th level GOA unit are turned on, causing the first power supply high voltage VGH1 to be written to the fourth node Q. In addition, the eighth transistor T57 and the ninth transistor T58 are turned on, causing the first power supply low voltage VGL1 to be written to the fifth node T. The fourteenth transistor T56 is turned on, causing the first power supply low voltage VGL1 to be written to the sixth node QB, thereby turning off the seventeenth transistor T31.

[0087] like Figures 1 to 5 As shown, during time period T2, since the sixth node QB is at a low level and the seventeenth transistor T31 is off, the nm-th level scan signal Gn[nm] generated by the first output terminal of the internal compensation circuit 200 is at a high level.

[0088] During time period T3, when the nm-th scan signal Gn[nm] is low and the n-th scan signal G[n] is high, the sixth transistor T41 and the seventh transistor T42 are turned on, pulling the potential of the fourth node Q down to the low voltage VGL1 of the first power supply. Furthermore, during time period T3, the tenth transistor T51 and the eleventh transistor T52 are turned on, writing the high level of the n-th scan signal G[n] to the fifth node T, thereby pulling up the potential of the sixth node QB, and thus turning on the seventeenth transistor T31. Therefore, the nm-th scan signal Gn[nm] generated at the first output terminal of the internal compensation circuit 200 is high.

[0089] For example, such as Figures 1 to 4As shown, taking k = 3 and m = 12 as an example, the charging difference of 12 rows of pixel circuits can meet the compensation time required by the internal compensation circuit 200. The application reduces the transistors used to generate the reset signal INI. The high and low level changes of the compensation control signal REF[n] output by the first output end of the internal compensation circuit 200 in the nth GOA unit are controlled by the nth-12th scanning signal Gn[n-12] generated by the first output end of the GOA circuit 100 of the nth-12th GOA unit and the nth scanning signal Gn[n] generated by the first output end of the GOA circuit 100 of the nth GOA unit. When the initial control signal STV received by the first GOA unit is high, the application can trigger a plurality of cascaded GOA units to generate corresponding nth scanning signals Gn[n] and compensation control signals REF[n]. The nth scanning signal provided by the first output end of the GOA circuit 100 of the nth GOA unit can be used as a trigger control signal for the internal compensation circuit 200 of the nth GOA unit and the nth+m GOA unit, to trigger the internal compensation circuit 200 of the nth GOA unit to start working to provide the compensation control signal to the compensation control end InB of the nth row of pixel circuits, and to trigger the internal compensation circuit 200 of the nth+m GOA unit to start working to provide the compensation control signal to the compensation control end InB of the nth+m row of pixel circuits, to achieve the compensation time of m rows of time. In addition, the nth scanning signal provided by the first output end of the GOA circuit 100 of the nth GOA unit can be used as the scanning signal of the nth row of pixel circuits, or as the reset signal of the nth+m row of pixel circuits, to reduce the number of transistors used to generate the reset signal, thereby reducing the width of the frame, which is beneficial to realize the narrow frame or frameless of the display panel, while maintaining the function and device requirements unchanged, and improving the specification of the display panel.

[0090] The application further provides a display panel, which comprises Figures 1 to 4 The gate drive circuit of the corresponding embodiment.

[0091] It should be noted that, Figures 1 to 4 In the application, a plurality of signals adopt the same reference numeral, for example, the control signal end N[n] includes a plurality of signal ends with the same reference numeral, but in practice, the signal ends with the same reference numeral are the same signal end, Figures 1 to 4In order to show and describe the connection of each element in the circuit, each connection end will be shown separately. The signal ends with the same reference signs are the same signal end. Similarly, the signal ends with the same reference signs are the same signal end. It can be understood that each signal end exists in multiple modules. Each signal end can be used as a component of each module, or each signal end can be used as an independent element that does not belong to each module. In order to facilitate the description, the application embodiments will limit whether the signal end belongs to each module. However, in practice, each signal end does not belong to a specific module.

[0092] It should be noted that the channel materials of these transistors are low-temperature polysilicon, which is beneficial to improve the dynamic performance of the gate drive circuit and the display panel, and is also beneficial to further simplify the manufacturing process, structure and cost. Among them, each transistor described above can be a low-temperature polysilicon thin film transistor as a preferred scheme, but it is not limited thereto. At least one of each transistor described above can also be an indium gallium zinc oxide thin film transistor.

[0093] The above describes in detail the gate drive circuit and the display panel provided by the application embodiments. The principles and implementation manners of the application are described by applying specific examples. The above description of the embodiments is only used to help understand the technical solutions of the application and the core ideas thereof. Those skilled in the art should understand that the technical solutions recorded in the above embodiments can be modified, or some technical features can be replaced equivalently. The modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the application.

Claims

1. A gate driving circuit, characterized in that, It includes multiple cascaded GOA units, and the nth level GOA unit includes: GOA circuit (100) and internal compensation circuit (200); The first output terminal of the GOA circuit (100) is connected to the scan control terminal of the nth row pixel circuit, and is used to output the nth level scan signal (Gn[n]) to the nth row pixel circuit. The first output terminal of the GOA circuit (100) is also connected to the reset control terminal of the (n+m)th row pixel circuit, and is used to output the nth level scan signal (Gn[n]) to the (n+m)th row pixel circuit. The first input terminal of the internal compensation circuit (200) is connected to the first output terminal of the GOA circuit (100) of the nth level GOA unit, and is used to receive the nth level scan signal (Gn[n]); the second input terminal of the internal compensation circuit (200) is connected to the first output terminal of the GOA circuit (100) of the nm level GOA unit, and is used to receive the nm level scan signal (Gn[nm]); the first output terminal of the internal compensation circuit (200) is connected to the compensation control terminal of the nth row pixel circuit, and is used to output a compensation control signal (REF[n]) to the nth row pixel circuit. Where n and m are both positive integers, and n > m.

2. The gate driving circuit according to claim 1, characterized in that, The GOA circuit includes: a first pull-up module (110) and a first pull-down control module (120); The first output terminal of the first pull-up module (110), the first output terminal and the second output terminal of the first pull-down control module (120) are both used as the first output terminal of the GOA circuit (100).

3. The gate driving circuit according to claim 2, characterized in that, The first pull-up module (110) includes: a first transistor (T22); The drain of the first transistor (T22) is connected to the first clock signal terminal to receive the first clock signal group (CKB1-CKB8), the source of the first transistor (T22) serves as the first output terminal of the first pull-up module (110), and the gate of the first transistor (T22) is connected to the first node (Q[n]).

4. The gate driving circuit according to claim 3, characterized in that, The first pull-down control module (120) includes: a second transistor (T32A) and a third transistor (T32B); The drain of the second transistor (T32A) serves as the first output terminal of the first pull-down control module (120). The gate of the second transistor (T32A) is connected to the second node (QBA[n]). The source of the second transistor (T32A) is connected to the first low voltage terminal to receive the first power supply low voltage (VGL1). The drain of the third transistor (T32B) serves as the second output terminal of the first pull-down control module (120). The gate of the third transistor (T32B) is connected to the third node (QBB[n]). The source of the third transistor (T32B) is connected to the first low voltage terminal to receive the first power supply low voltage (VGL1).

5. The gate driving circuit according to claim 1, characterized in that, The internal compensation circuit (200) includes: a first pull-up control module (210), a second pull-down control module (220), a first pull-down maintenance module (230), and a compensation module (240); The first control terminal of the second pull-down control module (220) and the first control terminal of the first pull-down sustaining module (230) both serve as the first input terminal of the internal compensation circuit (200); The first control terminal of the first pull-up control module (210), the second control terminal and the third control terminal of the first pull-down sustaining module (230) are all used as the second input terminals of the internal compensation circuit (200); The output terminal of the compensation module (240) serves as the first output terminal of the internal compensation circuit (200).

6. The gate driving circuit according to claim 5, characterized in that, The first pull-up control module (210) includes: a fourth transistor (T11) and a fifth transistor (T12); The gate of the fourth transistor (T11) and the gate of the fifth transistor (T12) both serve as the first control terminal of the first pull-up control module (210); The drain of the fourth transistor (T11) is connected to the first high voltage terminal to receive the first power supply high voltage (VGH1), and the source of the fourth transistor (T11) is connected to the drain of the fifth transistor (T12). The source of the fifth transistor (T12) is connected to the fourth node (Q).

7. The gate driving circuit according to claim 6, characterized in that, The second pull-down control module (220) includes: a sixth transistor (T41) and a seventh transistor (T42); The gate of the sixth transistor (T41) and the gate of the seventh transistor (T42) both serve as the first control terminal of the second pull-down control module (220); The source of the sixth transistor (T41) is connected to the first low voltage terminal to receive the first power supply low voltage (VGL1), the drain of the sixth transistor (T41) is connected to the source of the seventh transistor (T42), and the drain of the seventh transistor (T42) is connected to the fourth node (Q).

8. The gate driving circuit according to claim 7, characterized in that, The first pull-down sustaining module (230) includes: an eighth transistor (T57), a ninth transistor (T58), a tenth transistor (T51), an eleventh transistor (T52), a twelfth transistor (T53), a thirteenth transistor (T54), a fourteenth transistor (T56), and a fifteenth transistor (T55); The gate of the eighth transistor (T57) and the gate of the ninth transistor (T58) both serve as the second control terminal of the first pull-down sustaining module (230); The source of the eighth transistor (T57) is connected to the first low voltage terminal to receive the first power supply low voltage (VGL1), the drain of the eighth transistor (T57) is connected to the source of the ninth transistor (T58), and the drain of the ninth transistor (T58) is connected to the fifth node (T). The gate of the tenth transistor (T51) and the gate of the eleventh transistor (T52) both serve as the first control terminal of the first pull-down sustaining module (230); The drain of the tenth transistor (T51) is connected to the gate of the tenth transistor (T51), the source of the tenth transistor (T51) is connected to the drain of the eleventh transistor (T52), the source of the tenth transistor (T51) is also connected to the source of the twelfth transistor (T53), and the source of the eleventh transistor (T52) is connected to the fifth node (T). The drain of the twelfth transistor (T53) is connected to the first high voltage terminal to receive the first power supply high voltage (VGH1), and the gate of the twelfth transistor (T53) is connected to the fifth node (T). The gate of the thirteenth transistor (T54) is connected to the fifth node (T), the drain of the thirteenth transistor (T54) is connected to the first high voltage terminal to receive the first power supply high voltage (VGH1), and the source of the thirteenth transistor (T54) is connected to the drain of the fourteenth transistor (T56). The gate of the fourteenth transistor (T56) serves as the third control terminal of the first pull-down sustaining module (230), and the source of the fourteenth transistor (T56) is connected to the first low voltage terminal to receive the first power supply low voltage (VGL1). The gate of the fifteenth transistor (T55) is connected to the fourth node (Q), the drain of the fifteenth transistor (T55) is connected to the drain of the fourteenth transistor (T56), and the source of the fifteenth transistor (T55) is connected to the first low voltage terminal to receive the first power supply low voltage (VGL1).

9. The gate driving circuit according to claim 8, characterized in that, The compensation module (240) includes: a sixteenth transistor (T24) and a seventeenth transistor (T31); The source of the sixteenth transistor (T24) is connected to the drain of the seventeenth transistor (T31) and serves as the output terminal of the compensation module (240); The drain of the sixteenth transistor (T24) is connected to the second high voltage terminal to receive the second power supply high voltage (VGH2), and the gate of the sixteenth transistor (T24) is connected to the fourth node (Q). The source of the seventeenth transistor (T31) is connected to the second low voltage terminal to receive the second power supply low voltage (VGL2), and the gate of the seventeenth transistor (T31) is connected to the drain of the fourteenth transistor (T56).

10. A display panel, characterized in that, The display panel includes the gate driving circuit as described in any one of claims 1 to 9.

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