A method for preparing a TOPCon battery and a TOPCon battery

Abstract

The present invention relates to a method for preparing a TOPCon battery, comprising: depositing a wide-bandgap hydrogenated amorphous silicon oxide layer on an n-type silicon substrate by using PECVD, depositing an n+ amorphous silicon layer on the surface of the hydrogenated amorphous silicon oxide layer, and annealing to form a wide-bandgap polycrystalline silicon layer. The method of the present invention can reduce the parasitic absorption of the polycrystalline silicon layer without reducing the thickness of the polycrystalline silicon layer, improve the light absorption intensity of the TOPCon battery, and increase the current density. At the same time, oxygen atoms participate in promoting the formation of a silicon dioxide tunneling layer, and doping with more hydrogen atoms can effectively passivate defects and improve the open-circuit voltage, further improving the battery efficiency.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and particularly to a method for manufacturing a TOPCon cell and a TOPCon cell. Background Art

[0002] At present, as a representative of n-type cells, TOPCon cells are considered to be the mainstream in the photovoltaic market in the next 5 years. Among them, parasitic absorption in the polysilicon layer will cause a part of light energy loss, thereby reducing the absorption intensity of the n-type silicon substrate and affecting the photoelectric conversion efficiency. At present, reducing parasitic absorption by reducing the thickness of the polysilicon layer is considered to be a very effective way. However, if the polysilicon layer is too thin, it will affect the passivation effect, reduce the open-circuit voltage of the cell, and the photoelectric conversion efficiency will also decrease. Existing technologies reduce parasitic absorption by reducing the deposition thickness of the polysilicon layer to improve the performance of TOPCon cells. However, if the polysilicon layer is too thin, it will affect the passivation effect, reduce the open-circuit voltage of the cell, and the photoelectric conversion efficiency will decrease.

[0003] At present, a wide-bandgap hydrogenated amorphous silicon oxide layer has been reported for use in interface passivation of heterojunction cells. Summary of the Invention

[0004] To overcome the defects of the prior art, the present invention provides a method for manufacturing a TOPCon cell and a TOPCon cell.

[0005] The first aspect of the present invention provides a method for manufacturing a TOPCon cell, and the method includes the following steps:

[0006] S1 Deposit a wide-bandgap hydrogenated amorphous silicon oxide layer on the back surface of an n-type silicon substrate;

[0007] S2 Deposit an n + amorphous silicon layer on the surface of the hydrogenated amorphous silicon oxide layer obtained in step S1;

[0008] S3 Anneal the structure obtained in step S2 to form a silicon dioxide tunneling layer and a wide-bandgap polysilicon layer on the back surface of the n-type silicon substrate.

[0009] According to the method of the first aspect, wherein step S1 is carried out after texturing and boron diffusion on the front surface of the n-type silicon substrate and removing the boron diffusion layer on the back surface by backside plating.

[0010] According to the method of the first aspect, wherein the optical bandgap of the hydrogenated amorphous silicon oxide layer is 1.7 - 2.3 eV, preferably 1.9 - 2.1 eV.

[0011] According to the method of the first aspect, wherein the thickness of the hydrogenated amorphous silicon oxide layer is 2 - 5 nm, preferably 2 - 3 nm.

[0012] The method according to the first aspect, wherein the n + The thickness of the amorphous silicon layer is 80 to 110 nm, preferably 80 to 90 nm.

[0013] The method according to the first aspect, wherein in step S3, the annealing temperature is 850 to 1000 °C, preferably 900 to 950 °C; and / or the annealing time is 20 to 40 min, preferably 25 to 35 min.

[0014] The method according to the first aspect, wherein in step S1, the hydrogenated amorphous silicon oxide layer is deposited using SiH4, H2, and CO2 by PECVD;

[0015] Preferably, the flow rate ratio of the SiH4, H2, and CO2 gases [CO2]:[CO2+SiH4] = 1:1 to 1:10, preferably 1:3 to 1:5, and most preferably 1:5.

[0016] The method according to the first aspect, wherein in step S2, the n + amorphous silicon layer is deposited using SiH4, H2, and PH3 by PECVD.

[0017] The method according to the first aspect, wherein after the step S3, the following steps are further included:

[0018] S4 Removing the polycrystalline silicon and PSG deposited around the front of the substrate, and depositing an alumina layer;

[0019] S5 Depositing a silicon nitride layer on the wide-bandgap polycrystalline silicon layer obtained from step S3 and the alumina layer obtained from step S4;

[0020] S6 Preparing a positive electrode and a back electrode on the structure obtained from step S5 and sintering and annealing.

[0021] The second aspect of the present invention provides a TOPCon cell, and the TOPCon cell is prepared according to the method described in the first aspect.

[0022] In the present invention, a hydrogenated amorphous silicon oxide layer is first deposited by PECVD technology. Due to the doping of hydrogen atoms, the hydrogenated amorphous silicon oxide layer has a wider bandgap width. Then, an n + amorphous silicon layer is deposited on the wide-bandgap hydrogenated amorphous silicon oxide layer. After high-temperature annealing, the crystallization of the amorphous is completed. During this process, hydrogen atoms and oxygen atoms in the wide-bandgap hydrogenated amorphous silicon oxide layer are doped into the n +The amorphous silicon layer broadens the bandgap of the polycrystalline silicon layer, thereby reducing the parasitic absorption of the polycrystalline silicon layer without reducing the film thickness, increasing the light absorption intensity of the TOPCon cell, and increasing the current density. At the same time, oxygen atoms participate in promoting the formation of the silicon dioxide tunneling layer, and doping with more hydrogen atoms can effectively passivate defects and increase the open-circuit voltage, further improving the cell efficiency.

[0023] The preparation method of the TOPCon cell of the present invention has the following beneficial effects but is not limited to:

[0024] In the present invention, a broadband-gap hydrogenated amorphous silicon oxide layer is deposited, and then an amorphous silicon layer is deposited. The bandgap of the polycrystalline silicon layer is broadened by annealing; by preparing a polycrystalline silicon layer with a wider bandgap, the short-circuit current, open-circuit voltage of the TOPCon cell are increased, and the photoelectric conversion efficiency is correspondingly increased; by applying the broadband-gap hydrogenated amorphous silicon oxide layer deposited in the present invention to passivate the interface and anneal to prepare the polycrystalline silicon layer, the parasitic absorption of the polycrystalline silicon layer is reduced without reducing the thickness of the polycrystalline silicon layer, and the carrier lifetime of the TOPCon cell is increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Shows the structure of the TOPCon cell prepared by the method of the present invention.

[0026] Figure 2 Shows the hydrogenated amorphous silicon oxide layer and n during the annealing process + The process schematic of the amorphous silicon layer transforming into the silicon dioxide tunneling layer and the broadband-gap n + polycrystalline silicon.

[0027] Description of the reference numerals in the drawings:

[0028] 1. n-type silicon wafer; 2. Hydrogenated amorphous silicon oxide layer; 3. n + amorphous silicon layer; 4. Silicon dioxide tunneling layer; 5. Broadband-gap n + polycrystalline silicon layer; 6. Aluminum oxide layer; 7. Silicon nitride layer; 8. Positive electrode; 9. Back electrode. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] The following further details the present application through the drawings and embodiments. Through these descriptions, the features and advantages of the present application will become clearer and more definite.

[0030] The special term "exemplary" here means "serving as an example, embodiment, or illustrative". Any embodiment described as "exemplary" here does not have to be interpreted as superior to or better than other embodiments. Although various aspects of the embodiments are shown in the drawings, the drawings do not have to be drawn to scale unless otherwise specified.

[0031] In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0032] Before elaborating on the technical solution of the present invention, the terms used herein are defined as follows:

[0033] The term "TOPCon" refers to: Tunnel Oxide Passivating Contacts, i.e., tunneling oxide passivation contacts.

[0034] The term "PECVD" refers to: plasma enhanced chemical vapor deposition, i.e., plasma-enhanced chemical vapor deposition.

[0035] The term "n + amorphous silicon" refers to: phosphorus-doped amorphous silicon.

[0036] The term "n + polycrystalline silicon" refers to: phosphorus-doped polycrystalline silicon.

[0037] The term "ALD" refers to: atomic layer deposition, i.e., atomic layer deposition.

[0038] The term "BSG" refers to: borosilicate glass, i.e., borosilicate glass

[0039] The term "PSG" refers to: phosphorosilicate glass, i.e., phosphosilicate glass.

[0040] The term "texturing" refers to: forming a textured structure with different shapes and sizes on the surface of a silicon substrate using a chemical solution.

[0041] The present invention provides a method for manufacturing a TOPCon cell, and the method includes the following steps:

[0042] S1 Deposit a wide-bandgap hydrogenated amorphous silicon oxide layer on the back surface of the n-type silicon substrate;

[0043] S2 Deposit an n + amorphous silicon layer on the surface of the hydrogenated amorphous silicon oxide layer obtained in step S1;

[0044] S3 Anneal the structure obtained in step S2 to form a silicon dioxide tunneling layer and a wide-bandgap polycrystalline silicon layer on the back surface of the n-type silicon substrate.

[0045] As Figure 2 shown, the present invention deposits a wide-bandgap hydrogenated amorphous silicon oxide layer 2 on the back surface of an n-type silicon wafer 1 that has been textured, boron-diffused, and the boron diffusion layer on the back surface has been removed through PECVD technology, and then deposits an n+ Amorphous silicon layer 3. After high-temperature annealing, a part of the hydrogenated amorphous silicon oxide layer 2 is doped into the n + amorphous silicon layer 3 and crystallized to form a wide-bandgap n with widened bandgap + polycrystalline silicon layer 5, and the remaining part of the hydrogenated amorphous silicon oxide layer 2 forms a silicon dioxide tunneling layer 4. The method of the present invention can reduce the parasitic absorption of the polycrystalline silicon layer without reducing the thickness of the polycrystalline silicon thin film, thereby increasing the light absorption intensity of the TOPCon cell, increasing the current density, increasing the photoelectric conversion efficiency, and improving the performance of the TOPCon cell. At the same time, oxygen atoms participate in promoting the formation of the silicon dioxide tunneling layer, and doping with more hydrogen atoms can effectively passivate defects and increase the open-circuit voltage, further improving the cell efficiency.

[0046] In one embodiment, step S1 is carried out after texturing and boron diffusion on the front surface of the n-type silicon substrate and removing the boron diffusion layer plated around the back surface.

[0047] In one embodiment, the optical bandgap of the hydrogenated amorphous silicon oxide layer is 1.7 - 2.3 eV, preferably 1.9 - 2.1 eV.

[0048] In one embodiment, the thickness of the hydrogenated amorphous silicon oxide layer is 2 - 5 nm, preferably 2 - 3 nm.

[0049] In one embodiment, the n + amorphous silicon layer has a thickness of 80 - 110 nm, preferably 80 - 90 nm.

[0050] In a specific embodiment, the present invention first deposits a wide-bandgap hydrogenated amorphous silicon oxide layer with an optical bandgap of 1.95 eV and a thickness of 2.5 nm by PECVD technology, then deposits an amorphous silicon layer with a thickness of 85 nm, and prepares a polycrystalline silicon layer with a bandgap widened by more than 0.2 eV after annealing.

[0051] In one embodiment, in step S3, the annealing temperature is 850 - 1000 °C, preferably 900 - 950 °C; and / or

[0052] the annealing time is 20 - 40 min, preferably 25 - 35 min.

[0053] In one embodiment, in step S1, the wide-bandgap hydrogenated amorphous silicon oxide layer is deposited using PECVD with SiH4, H2, and CO2;

[0054] Preferably, the flow rate ratio of the SiH4, H2, and CO2 gases [CO2]:[CO2 + SiH4] = 1:1 - 1:10, preferably 1:3 - 1:5, and most preferably 1:5.

[0055] In a specific embodiment, in step S1, the deposition temperature is 100 to 250 °C, preferably 150 to 200 °C;

[0056] the deposition pressure is 100 to 300 mTorr, preferably 180 to 220 mTorr; and / or

[0057] the PECVD radio frequency power is 50 to 100 MHz, preferably 60 to 80 MHz.

[0058] In one embodiment, in step S2, the n-type amorphous silicon layer is deposited using SiH4, H2, and PH3 by PECVD. + Non - crystalline silicon layer.

[0059] In one embodiment, the deposition temperature is 400 to 450 °C, preferably 420 to 430 °C.

[0060] In one embodiment, after step S3, the following steps are further included:

[0061] S4 Remove the polycrystalline silicon and PSG deposited by over - plating on the front of the substrate, and deposit an alumina layer;

[0062] S5 Deposit a silicon nitride layer on the wide - bandgap polycrystalline silicon layer obtained from step S3 and the alumina layer obtained from step S4;

[0063] S6 Fabricate and sinter - anneal the positive electrode and the back electrode on the structure obtained from step S5.

[0064] In a specific embodiment, in step S4, the alumina layer is deposited by ALD.

[0065] In a specific embodiment, in step S5, the silicon nitride is deposited by PECVD.

[0066] In a specific embodiment, in step S6, the positive electrode and the back electrode are screen - printed.

[0067] In a specific embodiment, the positive electrode 8 can be a silver electrode or an aluminum electrode, and the negative electrode 9 is a silver electrode.

[0068] The preparation method of the wide - bandgap polycrystalline silicon layer of the TOPCon solar cell of the present invention is further described below with reference to embodiments.

[0069] Example 1

[0070] This example is used to illustrate the preparation method of the TOPCon cell of the present invention.

[0071] (1) After texturing and boron diffusion of the n - type silicon wafer 1, the boron diffusion layer deposited by over - plating on the back is etched away, and the BSG layer on the front is retained.

[0072] Place the cleaned n-type silicon wafer 1 into the PECVD deposition chamber, and use a vacuum pump to evacuate the deposition chamber to a low pressure to remove any residual gas.

[0073] Introduce precursor gases such as silane (SiH4), hydrogen (H2), and carbon dioxide (CO2) into the PECVD deposition chamber. Adjust the flow rates and ratios of these gases [CO2]:[CO2 + SiH4] = 1:5, control the pressure at 200 mTorr, the deposition temperature at 155 °C, and apply 70 MHz high-frequency power to the deposition chamber to generate plasma. The plasma will dissociate the precursor gases into reactive species. The reactive species in the plasma will react and deposit onto the n-type silicon wafer 1 to form a hydrogenated amorphous silicon oxide layer 2 with an optical bandgap of 1.95 eV. Adjust the deposition rate to Control the film thickness to 2.5 nm.

[0074] (2) Introduce precursor gases such as silane (SiH4), hydrogen (H2), and phosphine (PH3) into the PECVD deposition chamber, control the deposition temperature at 430 °C, and deposit an 85-nm-thick n + amorphous silicon layer 3 on the hydrogenated amorphous silicon oxide layer 2.

[0075] (3) After the deposition is completed, anneal at 910 °C. A part of the hydrogenated amorphous silicon oxide layer 2 is doped into the n + amorphous silicon layer 3 and crystallizes to form a wide-bandgap n + polycrystalline silicon 5. The remaining part of the hydrogenated amorphous silicon oxide layer 2 forms a silicon dioxide tunneling layer 4 with a thickness of about 1 nm.

[0076] After the annealing and crystallization process, the bandgap of the n + amorphous silicon layer 3, which is 1.7 - 1.9 eV, broadens to the wide-bandgap n + The bandgap of the polycrystalline silicon layer 5, which is 1.9 - 2.1 eV, broadens by 0.2 eV. This shows that under the synergistic effect of the hydrogenated amorphous silicon oxide layer and annealing, the bandgap of the polycrystalline silicon layer is successfully broadened, enabling the reduction of the parasitic absorption of the polycrystalline silicon layer without reducing the film thickness of the polycrystalline silicon layer.

[0077] (4) Etch away the edge-coated polycrystalline silicon and the front-side PSG, and deposit an aluminum oxide layer 6 on the front side using ALD technology.

[0078] (5) Deposit a silicon nitride layer 7 on the surface of the aluminum oxide layer 6 on the front side and the surface of the wide-bandgap n + polycrystalline silicon 5 on the back side using PECVD technology.

[0079] (6) Screen-print the front electrode 8 and the back electrode 9, sinter and anneal, and perform optical injection to obtain the TOPCon cell as Figure 1 shown.

[0080] The battery was tested under an AM1.5G simulated solar light source, and the test results are shown in Table 1 below.

[0081] Example 2

[0082] The TOPCon battery was prepared in the same manner as in Example 1, except that the annealing temperature after deposition was 950 °C.

[0083] Example 3

[0084] The TOPCon battery was prepared in the same manner as in Example 1, except that the annealing time after deposition was 40 min.

[0085] Comparative Example

[0086] The TOPCon battery was prepared in the same manner as in Example 1, except that in steps (1) - (3), 1 nm of silicon dioxide tunneling layer was prepared by depositing nitrous oxide using PECVD, and then 120 nm thick n + amorphous silicon was deposited to reduce parasitic absorption.

[0087] The test results of Examples 1 - 3 and the comparative example are shown in Table 1:

[0088] Table 1

[0089]

[0090] As can be seen from the above results:

[0091] 1. By depositing a layer of wide - bandgap hydrogenated amorphous silicon oxide layer and then depositing an amorphous silicon layer, the bandgap of the polycrystalline silicon prepared after annealing can be broadened by more than 0.2 eV.

[0092] 2. By preparing a polycrystalline silicon layer with a wider bandgap, the short - circuit current of the TOPCon battery is increased by 6 mA.

[0093] 3. By applying the method of preparing a polycrystalline silicon layer with a wider bandgap in the present invention, the open - circuit voltage of the TOPCon battery is increased by 5 mV, and the photoelectric conversion efficiency is increased by about 0.1%.

[0094] The above has described the present application in combination with preferred embodiments. However, these embodiments are only exemplary and only serve an illustrative purpose. On this basis, various substitutions and improvements can be made to the present application, and these all fall within the protection scope of the present application.

Claims

1. A method for preparing a TOPCon battery, characterized in that, The method includes the following steps: S1 Deposit a hydrogenated amorphous silicon oxide layer with a wide bandgap on the back surface of the n-type silicon substrate; Deposit an amorphous silicon layer n on the surface of the hydrogenated amorphous silicon oxide layer obtained from step S1 + an amorphous silicon layer; S3 Anneal the structure obtained from step S2 to form a silicon dioxide tunneling layer and a wide bandgap polysilicon layer on the back surface of the n-type silicon substrate; Among them, in step S1, the hydrogenated amorphous silicon oxide layer is deposited using SiH4, H2, and CO2 by PECVD.

2. The method according to claim 1, characterized in that Step S1 is carried out after texturing and boron diffusion on the front surface of the n-type silicon substrate and removing the boron diffusion layer plated around the back surface.

3. The method according to claim 1, wherein The optical bandgap of the hydrogenated amorphous silicon oxide layer is 1.7 - 2.3 eV.

4. The method according to claim 3, wherein The optical bandgap of the hydrogenated amorphous silicon oxide layer is 1.9 - 2.1 eV.

5. The method according to claim 1, wherein The thickness of the hydrogenated amorphous silicon oxide layer is 2 - 5 nm.

6. The method according to claim 5, wherein The thickness of the hydrogenated amorphous silicon oxide layer is 2 - 3 nm.

7. The method according to claim 1, wherein The said n + The thickness of the amorphous silicon layer is 80 to 110 nm.

8. The method according to claim 7, wherein The said n + The thickness of the amorphous silicon layer is 80 to 90 nm.

9. The method according to claim 1, wherein In step S3, the annealing temperature is 850 - 1000 °C; and / or the annealing time is 20 - 40 min.

10. The method according to claim 9, wherein In step S3, the annealing temperature is 900 - 950 °C; and / or the annealing time is 25 - 35 min.

11. The method according to claim 1, characterized in that, The flow rate ratio of the SiH4, H2, and CO2 gases [CO2]:[CO2 + SiH4] = 1:1 - 1:

10.

12. The method according to claim 1, wherein The flow rate ratio of the SiH4, H2, and CO2 gases [CO2]:[CO2 + SiH4] = 1:3 - 1:

5.

13. The method according to claim 1, wherein The flow rate ratio of the SiH4, H2, and CO2 gases [CO2]:[CO2 + SiH4] = 1:

5.

14. The method according to claim 1, characterized in that, In step S2, the amorphous silicon layer is deposited using SiH4, H2, and PH3 by PECVD. + ​ 15. The method according to any one of claims 1 to 14, characterized in that, After step S3, the following steps are further included: S4 Remove the polysilicon and PSG plated around the front surface of the substrate and deposit an alumina layer; S5 Deposit a silicon nitride layer on the wide bandgap polysilicon layer obtained from step S3 and the alumina layer obtained from step S4; S6 Prepare a positive electrode and a back electrode on the structure obtained from step S5 and sinter and anneal.

16. A TOPCon battery, characterized in that, The TOPCon cell is prepared according to the method described in any one of claims 1 to 15.

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