Pixel driving circuit, driving method and display panel

Abstract

An embodiment of the present application provides a pixel driving circuit, which includes at least one gate driving unit, at least one pixel unit, and at least one first switching unit. One end of one of the first switching units is electrically connected to one of the gate driving units, and the other end of the first switching unit is electrically connected to at least one of the pixel units. The first switching unit is configured to be disconnected in response to a first control signal, so that the pixel unit maintains the displayed grayscale value in at least two frames of images; the first control signal is a signal formed based on the difference between the grayscale values to be displayed by the pixel unit in at least two frames of images being less than or equal to a preset grayscale value, thereby avoiding repeated charging and discharging when the display content of a local area remains unchanged, thereby reducing power consumption.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit, a driving method and a display panel. Background Art

[0002] In many applications, such as mobile phones, laptops, and monitors, the display content in many areas of a display remains unchanged across multiple frames. Traditional driver architectures, however, require a continuous discharge and write cycle for all display content within each frame. This operation increases the power consumption of the display panel for areas where the content remains unchanged. Summary of the Invention

[0003] The present application provides a pixel driving circuit, a driving method and a display panel capable of reducing power consumption.

[0004] In a first aspect, an embodiment of the present application provides a pixel driving circuit, the pixel driving circuit comprising:

[0005] at least one gate driving unit;

[0006] at least one pixel unit;

[0007] At least one first switching unit, one end of the first switching unit is electrically connected to one of the gate driving units, and the other end of the first switching unit is electrically connected to at least one of the pixel units, and the first switching unit is configured to be disconnected in response to a first control signal so that the pixel unit maintains displaying a grayscale value in at least two frames of images; the first control signal is a signal formed based on the fact that the difference between the grayscale values to be displayed by the pixel unit in at least two frames of images is less than or equal to a preset grayscale value.

[0008] An embodiment of the present application provides a pixel driving circuit, which includes at least one gate driving unit, at least one pixel unit, and at least one first switching unit. One end of each of the first switching units is electrically connected to the gate driving unit, and the other end of the first switching unit is electrically connected to at least one of the pixel units. The first switching unit is configured to disconnect in response to a first control signal, so that the pixel unit maintains the displayed grayscale value in at least two frames; the first control signal is a signal formed based on the difference between the grayscale values to be displayed by the pixel unit in at least two frames being less than or equal to a preset grayscale value. Through the above design, when the difference between the grayscale values to be displayed by the pixel unit in at least two frames is less than or equal to the preset grayscale value, the first switching unit is disconnected, so that the pixel unit does not discharge or charge in at least two frames, thereby maintaining the displayed grayscale value, avoiding repeated charging and discharging when the displayed content in a local area remains unchanged, and reducing power consumption.

[0009] In an optional embodiment, the first switch unit is configured to be turned on in response to a second control signal, causing the pixel unit to discharge within each frame, wherein the second control signal is a signal generated based on the difference between the grayscale values to be displayed by the pixel unit in two adjacent frames being greater than the preset grayscale value. In an optional embodiment, the pixel unit further includes a storage capacitor, and the pixel driving circuit further includes at least one second switch unit, one end of the second switch unit being electrically connected to the storage capacitor, and the other end of the second switch unit being electrically connected to a common ground terminal, the second switch unit being configured to be turned off in response to the first control signal and turned on in response to the second control signal.

[0010] In an optional implementation, the maximum number of frames during which the pixel unit maintains displaying the grayscale value is less than or equal to (refresh rate / 60)*2 frames.

[0011] In an optional embodiment, the at least one pixel unit is arranged in at least one row, and the pixel units in one row are electrically connected to the other end of the first switch unit.

[0012] In an optional embodiment, the pixel driving circuit further includes at least one control line, the at least one gate driving unit is arranged in at least one column, the at least one pixel unit is arranged in multiple rows and columns, the at least one first switch unit is arranged in at least one column, at least two adjacent rows of the first switch units are electrically connected to the same control line, or, at least two adjacent odd rows of the first switch units are electrically connected to one control line, and at least two adjacent even rows of the first switch units are electrically connected to another control line, and the control line is used to provide the first control signal.

[0013] In a second aspect, an embodiment of the present application provides a driving method for a pixel driving circuit, which is applied to the above-mentioned pixel driving circuit, and the method includes:

[0014] Comparing the data voltages of the pixel unit in two adjacent frames;

[0015] If the data voltages in two adjacent frames are the same, a first control signal is generated, wherein the first control signal is configured to control a first switch unit electrically connected to the gate driving unit and the pixel unit to be disconnected, so that the pixel unit maintains displaying a grayscale value in at least two frames;

[0016] If the data voltages in two adjacent frames are different, a second control signal is generated, and the second control signal is configured to control the first switch unit electrically connected to the gate driving unit and the pixel unit to be turned on, so that the pixel unit is charged and discharged in each frame under the drive of the gate driving unit.

[0017] An embodiment of the present application provides a driving method for a pixel driving circuit, which compares the data voltages of a pixel unit in two adjacent frames; if the data voltages in the two adjacent frames are the same, a first control signal is generated, the first control signal being configured to control a first switch unit electrically connected to a gate driving unit and the pixel unit to be disconnected, so that the pixel unit maintains a displayed grayscale value in at least two frames; if the data voltages in the two adjacent frames are different, a second control signal is generated, the second control signal being configured to control a first switch unit electrically connected to the gate driving unit and the pixel unit to be turned on, so that the pixel unit is driven by the gate driving unit to charge and discharge in each frame. Through the above design, the data voltages in two adjacent frames are the same, so that the pixel unit does not discharge or charge in at least two frames, thereby maintaining the displayed grayscale value, avoiding repeated charging and discharging when the display content in a local area remains unchanged, and reducing power consumption.

[0018] In an optional implementation, before comparing the data voltages of the pixel units in two adjacent frames, the method further includes:

[0019] Dividing the plurality of pixel units into a plurality of groups, wherein the pixel units in each group are electrically connected to the same control line via at least one of the first switch units;

[0020] Comparing the data voltages of the pixel units in two adjacent frames includes:

[0021] The data voltages of each group of pixel units in two adjacent frames are compared.

[0022] In an optional implementation, if the data voltages in two adjacent frames of the pixel unit are the same, generating a first control signal includes:

[0023] If the data voltages in two adjacent frames of the pixel unit are the same, and the maximum number of frames during which the pixel unit maintains the displayed grayscale value is less than or equal to (refresh rate / 60)*2 frames, then generating a first control signal;

[0024] If the data voltages in two adjacent frames of the pixel unit are the same, and the maximum number of frames during which the pixel unit maintains the displayed grayscale value is greater than (refresh rate / 60)*2 frames, a second control signal is generated.

[0025] In a third aspect, an embodiment of the present application provides a display panel comprising the above-mentioned pixel driving circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a display diagram of updating the Nth frame to the N+1th frame under the traditional drive architecture;

[0028] Figure 2 is a schematic diagram of a pixel driving circuit of a display panel provided in an embodiment of the present application;

[0029] Figure 3 This is a partial schematic diagram of a pixel driving circuit when the display panel provided in an embodiment of the present application is an LCD display screen;

[0030] Figure 4 This is a partial schematic diagram of a pixel driving circuit when the display panel provided in an embodiment of the present application is an OLED display screen;

[0031] Figure 5 1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present application, which further includes a display control module and a data processing module;

[0032] Figure 6 This is a structural diagram of the pixel driving circuit provided by an embodiment of the present application further including a second switch unit electrically connected between the storage capacitor and the common ground terminal;

[0033] Figure 7 This is a partial schematic diagram of a pixel driving circuit in which each first switching unit is electrically connected to a control line according to an embodiment of the present application;

[0034] Figure 8 This is a diagram of a distributed architecture of a pixel driving circuit in a display panel provided by an embodiment of the present application;

[0035] Figure 9 This is another distribution architecture diagram of the pixel driving circuit provided in the display panel according to an embodiment of the present application;

[0036] Figure 10 The embodiment of the present application further provides a flowchart of a driving method of a pixel driving circuit;

[0037] Figure 11 The embodiment of the present application further provides a flowchart of another driving method of a pixel driving circuit;

[0038] Figure 12This is a display schematic diagram of the pixel driving circuit provided in an embodiment of the present application updating the Nth frame image to the N+1th frame image;

[0039] Figure 13 yes Figure 5 Provided circuit block diagram of the display panel;

[0040] Figure 14 The embodiment of the present application also provides a flowchart of step S200 in a driving method of a pixel driving circuit.

[0041] Description of labels:

[0042] Display panel 1000; pixel driving circuit 100; gate driving unit 10; pixel unit 20; first switch unit 30; peripheral wiring area 100a; display screen area 100b; sub-pixel area 100c; scan line 40; data line 50; driving TFT tube 21; storage capacitor 22; pixel electrode 23; light-emitting unit 24; display control module 60; data processing module 70; storage capacitor 22; second switch unit 80; common ground terminal 90; control line 110. DETAILED DESCRIPTION

[0043] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application. Mentioning "embodiment" or "implementation method" in this article means that the specific features, structures or characteristics described in conjunction with the embodiment or implementation method may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0044] It should be noted that the terms "first," "second," and so on in the specification, claims, and drawings of this application are used to distinguish different objects, rather than to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0045] Existing panel display technologies, whether liquid crystal display (LCD), organic light-emitting semiconductor (OLED), or Mini LED direct display (also known as Mini RGB display, which refers to the self-luminous display achieved by Mini LED with RGB primary color technology), have the same basic display driving principle: the display panel receives the input frame start signal (STV signal, which serves as the trigger signal of the GOA unit) and the clock pulse signal (CLK signal), and inputs the STV signal and CLK signal into each gate driver unit (Gate Driver on Array, GOA unit), and generates a GOUT signal corresponding to each row. This signal serves as the switching signal of the display driver TFT of each row to control the input of the display data voltage data in the pixel unit.

[0046] During the display process, at the end of a frame, the GOA unit turns on again and releases the data voltage stored in the capacitor through the discharge circuit, and then rewrites it in the next frame. Regardless of whether the data voltage in the pixel unit is the same in the previous frame and the next frame, the data voltage needs to be rewritten at the beginning of the new frame.

[0047] In many applications, such as mobile phones, laptops, and monitors, the content of many areas within a display remains unchanged across multiple frames. For example, when typing, only the layout of the display changes. Otherwise, the content remains unchanged when the display is still.

[0048] Under the traditional driving architecture, all display contents of each frame require continuous discharge and writing processes. Such operations are obviously redundant for the display area where the picture content remains unchanged.

[0049] See also Figure 1 , Figure 1 This is a display diagram of updating the Nth frame to the N+1th frame under a traditional drive architecture.

[0050] Figure 1 Figure a in the middle shows the display of frame N. Frame N is divided into three areas: area 1 displays red, area 2 displays green, and area 3 displays blue.

[0051] Figure 1 Figure b in the middle is a schematic diagram of discharging the entire display surface at the end of the Nth frame. At the end of the Nth frame, the entire display surface is discharged, that is, the data voltages in the pixel units in area 1, area 2 and area 3 are cleared.

[0052] Figure 1 Figure c in the middle shows the display of frame N+1. When frame N+1 is displayed, the pixel cells in areas 1, 2, and 3 are recharged, causing area 1 to display yellow and area 3 to display gray. The display contents of areas 1 and 3 in the current frame are different from those in the previous frame, while area 2 displays green, maintaining the same display content as in the previous frame. Area 2, however, was discharged once in frame N and recharged with the same data voltage in frame N+1, resulting in the same display content, resulting in wasted power.

[0053] See also Figure 2 , the present application provides a pixel driving circuit capable of reducing power consumption and a display panel having the pixel driving circuit. The display panel 1000 includes but is not limited to an LCD display screen, an OLED display screen, a Mini LED direct display screen, etc. The display panel 1000 can be applied to but is not limited to mobile phones, televisions, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, cameras, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, car displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays of rearview cameras in vehicles), electronic photos, electronic billboards or signs, projectors, etc.

[0054] See also Figure 2 The pixel driving circuit 100 includes at least one gate driving unit 10 , at least one pixel unit 20 and at least one first switching unit 30 .

[0055] Among them, see Figure 2 The gate drive unit 10, also known as a scan drive unit or GOA unit, is disposed in the peripheral wiring area 100a of the display panel 1000. The pixel units 20 are disposed in the display screen area 100b of the display panel 1000. Each pixel unit 20 is disposed within a sub-pixel region 100c. The pixel units 20 include a driving TFT, a storage capacitor, and the like.

[0056] See also Figure 2 The pixel driving circuit 100 further includes a plurality of scan lines 40 and a plurality of data lines 50. The plurality of scan lines 40 are arranged along a row direction D1 and are relatively parallel. The plurality of data lines 50 are arranged along a column direction D2 and are relatively parallel.

[0057] The scan lines 40 and data lines 50 are located on different layers and do not intersect or directly electrically connect. When viewed from above, the area between two adjacent scan lines 40 and two adjacent data lines 50 is defined as a sub-pixel region 100c. The display area 100b of the display panel 1000 includes a plurality of sub-pixel regions 100c arranged in a row and column array.

[0058] The scan line 40 is electrically connected to the gate driving unit 10 and a plurality of pixel units 20 arranged in rows.

[0059] See also Figure 3 The pixel unit 20 includes at least a driving TFT 21 and a storage capacitor 22. The gate of the driving TFT 21 is electrically connected to a scan line 40. The source of the driving TFT 21 is electrically connected to a data line 50. When the display panel 1000 is an LCD display, the drain of the driving TFT 21 is electrically connected to a pixel electrode 23 of the pixel unit 20 and the storage capacitor 22. The pixel electrode 23 and the common electrode are disposed on either side of the liquid crystal molecules. Changes in the pixel voltage of the pixel electrode 23 are used to control the deflection angle of the liquid crystal molecules, thereby controlling the light transmittance of the liquid crystal molecules and the display brightness.

[0060] See also Figure 4 When the display panel 1000 is an OLED display screen, the drain of the driving TFT tube 21 is electrically connected to the anode of the light-emitting unit 24 in the pixel unit 20 and the storage capacitor 22 .

[0061] In other words, the signal outputted by the gate driving unit 10 to the scan line 40 is used to control the on or off of the driving TFT tube 21 , thereby controlling the pixel unit 20 to load the data voltage and start charging.

[0062] In some embodiments, the driving TFT tube 21 is a P-type transistor, for example, a PMOS tube. The driving TFT tube 21 is turned on in response to a low-level signal received on its control end, that is, it is turned on; the driving TFT tube 21 is turned off in response to a high-level signal received on its control end, that is, it is turned off.

[0063] For another example, the driving TFT tube 21 is an N-type transistor, for example, an NMOS tube. The driving TFT tube 21 is turned on in response to a high-level signal received on its control end, that is, it is turned on; the driving TFT tube 21 is turned off in response to a low-level signal received on its control end, that is, it is turned off.

[0064] The embodiment of the present application uses the coordination relationship between a first switch unit 30, a gate drive unit 10 and a pixel unit 20 to illustrate the invention content of the present application, and does not limit the number of first switch units 30, gate drive units 10 and pixel units 20.

[0065] One end of each first switch unit 30 is electrically connected to one of the gate drive units 10, and the other end of the first switch unit 30 is electrically connected to at least one of the pixel units 20. In other words, the first switch unit 30 can be electrically connected between the gate drive unit 10 and the scan line 40. Optionally, the first switch unit 30 can be disposed in the peripheral wiring area 100a of the display panel 1000. Furthermore, the first switch unit 30 can be integrated into the chip where the gate drive unit 10 is located.

[0066] The present application does not make any specific limitation on the first switch unit 30. For example, the first switch unit 30 includes but is not limited to switch tubes such as thin film transistors, triodes, and MOS tubes.

[0067] The first switch unit 30 is configured to be disconnected in response to a first control signal, so that the pixel unit 20 keeps displaying the grayscale value in at least two frames.

[0068] For details, please refer to Figure 5 The two conductive ends of the first switch unit 30 are electrically connected to the gate driving unit 10 and the pixel unit 20, respectively. The control end of the first switch unit 30 receives a first control signal. The first control signal can be provided by the display control module 60 of the display panel 1000. In other words, the display control module 60 is electrically connected to the control end of the first switch unit 30 via a wiring.

[0069] When the first switch unit 30 is in the off state, the electrical connection between the gate drive unit 10 and the pixel unit 20 is disconnected. At this time, the pixel unit 20 includes a storage capacitor 22, and the storage capacitor 22 stores a data voltage to ensure that the voltage of the pixel electrode 23 in the pixel unit 20 remains unchanged in two adjacent frames (for example, the display panel 1000 is an LCD display), thereby achieving a constant voltage difference on both sides of the liquid crystal, and the liquid crystal does not deflect in two adjacent frames, or ensuring that the anode voltage of the light-emitting unit 24 electrically connected to the pixel unit 20 remains unchanged in two adjacent frames (for example, the display panel 1000 is an OLED display), and the light-emitting brightness of the light-emitting unit 24 remains unchanged, so that the pixel unit 20 maintains the display grayscale value in at least two frames.

[0070] The first control signal is a signal generated based on the difference between the grayscale values to be displayed by the pixel unit 20 in at least two frames being less than or equal to a preset grayscale value.

[0071] For details, please refer to Figure 5The display panel 1000 also includes a data processing module 70, which receives the data voltages (grayscale values to be displayed) of several frames sent by the logic chip. The data processing module 70 is used to compare the grayscale values to be displayed of the pixel unit 20 in two adjacent frames. If the difference between the grayscale values to be displayed of the pixel unit 20 in two adjacent frames is less than or equal to the preset grayscale value, a signal is sent to the display control module 60, and the display control module 60 sends a first control signal to the control end of the first switch unit 30. The preset grayscale value is the maximum value of the difference between the grayscale values to be displayed in two adjacent frames that cannot be distinguished by the human eye. Among them, the difference between the grayscale values to be displayed of the pixel unit 20 in two adjacent frames can be 0. That is, the data voltages to be loaded on the pixel unit 20 in two adjacent frames are the same, and the display control module 60 sends the first control signal to the control end of the first switch unit 30.

[0072] An embodiment of the present application provides a pixel driving circuit 100, which includes at least one gate driving unit 10, at least one pixel unit 20, and at least one first switching unit 30. One end of each of the first switching units 30 is electrically connected to the gate driving unit 10, and the other end of the first switching unit 30 is electrically connected to at least one of the pixel units 20. The first switching unit 30 is configured to disconnect in response to a first control signal, so that the pixel unit 20 maintains a displayed grayscale value in at least two frames; the first control signal is a signal generated based on the difference between the grayscale values to be displayed by the pixel unit 20 in at least two frames being less than or equal to a preset grayscale value. Through the above design, when the difference between the grayscale values to be displayed by the pixel unit 20 in at least two frames is less than or equal to the preset grayscale value, the first switching unit 30 is disconnected, so that the pixel unit 20 does not discharge or charge in at least two frames, thereby maintaining the displayed grayscale value, avoiding repeated charging and discharging when the displayed content in a local area remains unchanged, and reducing power consumption.

[0073] For example, the first switch unit 30 is a P-type transistor, for example, a PMOS tube. The first switch unit 30 is turned on in response to a low-level signal received on its control end, that is, it is turned on; the first switch unit 30 is disconnected in response to a high-level signal received on its control end, that is, it is turned off.

[0074] For another example, the first switch unit 30 is an N-type transistor, for example, an NMOS tube. The first switch unit 30 is turned on in response to a high-level signal received on its control end, that is, it is turned on; the first switch unit 30 is disconnected in response to a low-level signal received on its control end, that is, it is turned off.

[0075] Optionally, the first switch unit 30 is further configured to be turned on in response to a second control signal, so that the pixel unit 20 discharges in each frame.

[0076] The difference between the grayscale values to be displayed by the pixel unit 20 in two adjacent frames is greater than the preset grayscale value, which means that the grayscale values to be displayed by the pixel unit 20 in two adjacent frames are grayscale values that can be distinguished by the naked eye.

[0077] The control terminal of the first switch unit 30 receives a second control signal, wherein the second control signal may be provided by the display control module 60 of the display panel 1000 .

[0078] When the first switch unit 30 is in the on state, the electrical connection between the gate drive unit 10 and the pixel unit 20 is conducted. At this time, at the beginning of a frame, the gate drive unit 10 can output a high-level signal (the driving TFT tube 21 is an N-type transistor) to turn on the driving TFT tube 21 in the pixel unit 20, so that the data voltage is input to the storage capacitor 22, the pixel electrode 23 or the anode of the light-emitting unit 24 through the driving TFT tube 21. The data voltage is stored in the storage capacitor 22 to achieve charging of the pixel unit 20. In addition, when a frame is about to end, the gate drive unit 10 can control the storage capacitor 22 to be connected to the reference ground to discharge the voltage in the pixel unit 20 to achieve discharging of the pixel unit 20.

[0079] The second control signal is a signal generated based on the difference between the grayscale values to be displayed by the pixel unit 20 in two adjacent frames being greater than the preset grayscale value.

[0080] Specifically, the data processing module 70 receives the data voltages (grayscale values to be displayed) of several frames sent by the logic chip. The data processing module 70 is used to compare the grayscale values to be displayed of the pixel unit 20 in two adjacent frames. If the difference between the grayscale values to be displayed of the pixel unit 20 in two adjacent frames is greater than the preset grayscale value, a signal is sent to the display control module 60, and the display control module 60 sends a second control signal to the control end of the first switch unit 30. The preset grayscale value is the maximum value of the difference between the grayscale values to be displayed in two adjacent frames that cannot be distinguished by the human eye. Optionally, if the difference between the grayscale values to be displayed of the pixel unit 20 in two adjacent frames is greater than 0, that is, the data voltages to be loaded on the pixel unit 20 in two adjacent frames are different, the display control module 60 sends a second control signal to the control end of the first switch unit 30.

[0081] In this embodiment, before display, the data processing module 70 compares the difference between the grayscale values to be displayed of the pixel unit 20 in two adjacent frames and finds that the difference is greater than a preset grayscale value. For example, the grayscale values to be displayed of the two adjacent frames are different. The display control module 60 sends a second control signal to the control end of the first switch unit 30 to turn on the first switch unit 30, thereby causing the pixel unit 20 to charge at the beginning of a frame and discharge at the end of the frame under the drive of the gate driving unit 10, thereby achieving the pixel unit 20 refreshing the data voltage in one frame.

[0082] In this implementation, please refer to Figure 6 The pixel unit 20 further includes a storage capacitor 22. The pixel driving circuit 100 further includes at least one second switch unit 80. One end of the second switch unit 80 is electrically connected to the storage capacitor 22. The other end of the second switch unit 80 is electrically connected to a common ground terminal 90.

[0083] The second switch unit 80 is configured to be turned off in response to the first control signal, in which case the storage capacitor 22 is disconnected from the common ground terminal 90, and the discharge path of the storage capacitor 22 is disconnected. The second switch unit 80 is configured to be turned on in response to the second control signal, in which case the storage capacitor 22 is connected to the common ground terminal 90, and the discharge path of the storage capacitor 22 is connected, and the pixel unit 20 discharges.

[0084] Optionally, the maximum number of frames in which the pixel unit 20 maintains the displayed grayscale value is less than or equal to (refresh rate / 60)*2 frames. Because the pixel unit 20 relies on the voltage stored in the storage capacitor 22 to maintain the displayed grayscale value, and as the number of frames in which it remains undischarged increases, the voltage stored in the storage capacitor 22 decreases, and the grayscale value of the pixel unit 20 may decrease (due to leakage of the storage capacitor 22, etc.). Therefore, even if the number of frames in which the difference in the grayscale value to be displayed is less than or equal to the preset grayscale value is large, it is necessary to refresh again after the number of frames in which it remains undischarged reaches (refresh rate / 60)*2 frames, that is, the pixel unit 20 is charged and discharged again to avoid the grayscale value of the pixel unit 20 from decreasing due to the voltage stored in the storage capacitor 22; this can ensure that the pixel unit 20 can maintain the stability of its display brightness even when the grayscale to be displayed remains unchanged for a long time.

[0085] The above is an example of the connection and control relationship between a first switch unit 30, a gate driver unit 10, and a pixel unit 20 to illustrate the present invention. Of course, when the data voltage to be loaded on the plurality of pixel units 20 remains unchanged, the plurality of pixel units 20 can be controlled to maintain the data voltage unchanged within multiple frames without discharging.

[0086] Optionally, the at least one pixel unit 20 is arranged in at least one row. The pixel units 20 in a row are electrically connected to the other end of the first switch unit 30. In this embodiment, a row of pixel units 20 is controlled by one first switch unit 30, so that when the data voltage to be loaded on the pixel units 20 in a row remains unchanged, the pixel units 20 in a row can be controlled to maintain the data voltage unchanged for multiple frames and not discharge.

[0087] Further, see Figure 7 The pixel driving circuit 100 further includes at least one control line 110. The control line 110 is electrically connected to the display control module 60. The control line 110 is used to provide the first control signal or the second control signal.

[0088] The at least one gate driving unit 10 is arranged in at least one column. The at least one pixel unit 20 is arranged in multiple rows and multiple columns. The at least one first switch unit 30 is arranged in at least one column.

[0089] Optionally, the gate drive units 10 are arranged in two columns. The two columns of gate drive units 10 are respectively provided on both sides (e.g., both sides in the width direction) of the display screen area 100b. Each end of each scan line 40 is electrically connected to a gate drive unit 10. The at least one first switch unit 30 is arranged in a column. Each first switch unit 30 is electrically connected to a gate drive unit 10 and a row of pixel units 20.

[0090] In an alternative embodiment, see Figure 7 Each first switch unit 30 is electrically connected to a control line 110. In other words, each row of pixel units 20 can be individually controlled to remain in a non-charging / discharging state for multiple frames. That is, any row can be controlled not to refresh (not charge / discharge) in the next frame while the display content of the next frame remains unchanged, maintaining its displayed grayscale.

[0091] In another alternative embodiment, see Figure 5 At least two adjacent rows of the first switch units 30 are electrically connected to the same control line 110. For example, the multiple rows of pixel units 20 electrically connected to the at least two adjacent rows of the first switch units 30 electrically connected to the same control line 110 can be individually controlled to remain in a non-charged / discharged state for multiple frames. When the display content of the pixel units 20 in this area remains unchanged in the next frame, the pixel units 20 in this area can be controlled not to refresh (not charge / discharge) in the next frame, maintaining their displayed grayscale.

[0092] The present application does not limit the number of rows of the multiple rows of pixel units 20 electrically connected to the same control line 110. Optionally, the number of rows of the multiple rows of pixel units 20 includes 100 rows, 200 rows, 300 rows, 400 rows, 500 rows, 600 rows, 700 rows, 800 rows, 900 rows, 1000 rows, etc.

[0093] See also Figure 8 , Figure 8 This diagram shows the distributed architecture of the pixel driver circuit 100 within the display panel 1000. 100 rows of pixel cells 20 form a group, which is the minimum area used to determine whether two adjacent frames are identical. The first switch units 30 in each row within this group are electrically connected to the same control line 110. The next 100 rows of pixel cells 20 form the next group, and the first switch units 30 in each row within this group are electrically connected to a different control line 110.

[0094] Alternatively, see Figure 9 The gate drive units 10 are arranged in two columns. The two columns of gate drive units 10 are respectively provided on both sides of the display screen area 100b (e.g., on both sides in the width direction). One end of the scan lines 40 in the odd rows is electrically connected to one column of gate drive units 10, and one end of the scan lines 40 in the even rows is electrically connected to the other column of gate drive units 10. The plurality of first switch units 30 are arranged in two columns. One column of first switch units 30 electrically connects one column of gate drive units 10 to the scan lines 40 in the odd rows, and the other column of first switch units 30 electrically connects the other column of gate drive units 10 to the scan lines 40 in the even rows.

[0095] There are at least two control lines 110 , wherein at least two adjacent odd-numbered rows of the first switch units 30 are electrically connected to one control line 110 , and at least two adjacent even-numbered rows of the first switch units 30 are electrically connected to another control line 110 .

[0096] For example, the pixel units 20 in a plurality of adjacent odd-numbered rows electrically connected to the same control line 110 can be individually controlled to remain in a non-charged / discharged state for multiple frames. If the display content of the pixel units 20 in the next frame remains unchanged, the pixel units 20 in the region can be controlled not to refresh (not charge / discharge) in the next frame, maintaining their displayed grayscale. The pixel units 20 in a plurality of adjacent even-numbered rows electrically connected to the same control line 110 can be individually controlled to remain in a non-charged / discharged state for multiple frames. If the display content of the pixel units 20 in the next frame remains unchanged, the pixel units 20 in the region can be controlled not to refresh (not charge / discharge) in the next frame, maintaining their displayed grayscale.

[0097] The pixel driving circuit 100 and the display panel 1000 provided in the embodiment of the present application are a low-power driving architecture. The pixel driving circuit 100 controls the conduction and disconnection between the gate driving unit 10 and the pixel unit 20 by setting a first switch unit 30, thereby controlling the charging and discharging of the pixels in the row, thereby controlling whether the display image in the display area is refreshed. When the display content of a certain area remains unchanged, the image in the area is not charged or discharged, and the area maintains the previous frame image, thereby reducing the display power consumption of the display panel 1000.

[0098] See also Figure 10 , combined with Figures 1-9 The embodiment of the present application further provides a driving method of the pixel driving circuit 100, which is applied to the pixel driving circuit 100 described in any of the above embodiments. The method includes but is not limited to the following steps.

[0099] Step S100 : comparing the data voltages of the pixel unit 20 in two adjacent frames.

[0100] For example, when the voltage of the data to be loaded on a pixel unit 20 remains unchanged, the pixel unit 20 is controlled not to be charged or discharged in the next frame and to maintain the displayed grayscale value.

[0101] Specifically, the display panel 1000 further includes a data processing module 70, which receives the data voltages (grayscale values to be displayed) to be loaded for several frames of images sent by the logic chip. The data processing module 70 is used to compare the grayscale values to be displayed of the pixel unit 20 in two adjacent frames of images.

[0102] Step S200: If the data voltages (data voltages to be loaded) in two adjacent frames are the same, a first control signal is generated. The first control signal is configured to control the first switch unit 30 electrically connected to the gate drive unit 10 and the pixel unit 20 to disconnect, so that the pixel unit 20 maintains the displayed grayscale value for at least two frames.

[0103] Specifically, if the data voltage to be loaded on the pixel unit 20 in two adjacent frames is the same, the display control module 60 sends a first control signal to the control end of the first switch unit 30, the first switch unit 30 is disconnected, and the gate drive circuit is disconnected from the pixel unit 20. The discharge signal and the charging signal sent by the gate drive circuit cannot reach the pixel unit 20, the discharge path of the pixel unit 20 is disconnected, and the storage capacitor 22 enables the pixel unit 20 to maintain its display grayscale value.

[0104] Step S300: If the data voltages (data voltages to be loaded) in two adjacent frames are different, a second control signal is generated. The second control signal is configured to control the first switch unit 30 electrically connected to the gate drive unit 10 and the pixel unit 20 to be turned on, so that the pixel unit 20 is driven by the gate drive unit 10 to charge and discharge within each frame.

[0105] Specifically, if the data voltages to be loaded on the pixel unit 20 in two adjacent frames are different, the display control module 60 sends a second control signal to the control end of the first switch unit 30, the first switch unit 30 is turned on, and the gate drive circuit and the pixel unit 20 are connected. The discharge signal and the charging signal sent by the gate drive circuit can reach the pixel unit 20, so that the pixel unit 20 is charged at the beginning of a frame and discharged at the end of a frame.

[0106] The present application provides a driving method for a pixel driving circuit 100. The method compares the data voltages of a pixel unit 20 in two adjacent frames. If the data voltages in the two adjacent frames are the same, a first control signal is generated. The first control signal is configured to control a first switch unit 30 electrically connected to a gate driving unit 10 and the pixel unit 20 to be disconnected, so that the pixel unit 20 maintains a displayed grayscale value in at least two frames. If the data voltages in the two adjacent frames are different, a second control signal is generated. The second control signal is configured to control a first switch unit 30 electrically connected to the gate driving unit 10 and the pixel unit 20 to be connected, so that the pixel unit 20 is driven by the gate driving unit 10 to charge and discharge in each frame. With the above design, when the data voltages in two adjacent frames are the same, the pixel unit 20 does not discharge or charge in at least two frames, thereby maintaining the displayed grayscale value. This avoids repeated charging and discharging when the displayed content in a local area remains unchanged, thereby reducing power consumption.

[0107] See also Figure 11 , step S100: comparing the data voltages of the pixel unit 20 in two adjacent frames. The method further includes:

[0108] Step S400 : Divide the plurality of pixel units 20 into a plurality of groups. Each group of pixel units 20 is electrically connected to the same control line 110 via at least one first switch unit 30 .

[0109] The at least one gate driving unit 10 is arranged in at least one column. The at least one pixel unit 20 is arranged in multiple rows and multiple columns. The at least one first switch unit 30 is arranged in at least one column.

[0110] Optionally, the gate drive units 10 are arranged in two columns. The two columns of gate drive units 10 are respectively provided on both sides (e.g., both sides in the width direction) of the display screen area 100b. Each end of each scan line 40 is electrically connected to a gate drive unit 10. The at least one first switch unit 30 is arranged in a column. Each first switch unit 30 is electrically connected to a gate drive unit 10 and a row of pixel units 20.

[0111] In an optional embodiment, each first switch unit 30 is electrically connected to a control line 110. That is, one first switch unit 30 constitutes a group. In other words, each row of pixel units 20 can be individually controlled to remain in a non-charging / discharging state for multiple frames. That is, any row can be controlled not to refresh (not charge / discharge) in the next frame, maintaining its displayed grayscale, provided that the display content of the next frame remains unchanged.

[0112] In another optional embodiment, at least two adjacent rows of first switch units 30 are electrically connected to the same control line 110. That is, multiple rows of adjacent first switch units 30 constitute a group. For example, the multiple rows of pixel units 20 electrically connected to at least two adjacent rows of first switch units 30 electrically connected to the same control line 110 can be individually controlled to remain in a non-charged or non-discharged state for multiple frames. If the display content of the pixel units 20 in this area remains unchanged in the next frame, the pixel units 20 in this area can be controlled not to refresh (not charge or discharge) in the next frame, maintaining their displayed grayscale.

[0113] Optionally, the gate drive units 10 are arranged in two columns. The two columns of gate drive units 10 are respectively provided on both sides of the display screen area 100b (for example, on both sides in the width direction). One end of the scan line 40 of the odd row is electrically connected to one column of gate drive units 10, and one end of the scan line 40 of the even row is electrically connected to the other column of gate drive units 10. The plurality of first switch units 30 are arranged in two columns. One column of first switch units 30 is electrically connected to one column of gate drive units 10 and the scan lines 40 of the odd row, and the other column of first switch units 30 is electrically connected to the other column of gate drive units 10 and the scan lines 40 of the even row. That is, a plurality of adjacent odd-numbered rows of first switch units 30 are a group. That is, a plurality of adjacent even-numbered rows of first switch units 30 are a group.

[0114] There are at least two control lines 110 , wherein at least two adjacent odd-numbered rows of the first switch units 30 are electrically connected to one control line 110 , and at least two adjacent even-numbered rows of the first switch units 30 are electrically connected to another control line 110 .

[0115] For example, the pixel units 20 in a plurality of adjacent odd-numbered rows electrically connected to the same control line 110 can be individually controlled to remain in a non-charged / discharged state for multiple frames. If the display content of the pixel units 20 in the next frame remains unchanged, the pixel units 20 in the region can be controlled not to refresh (not charge / discharge) in the next frame, maintaining their displayed grayscale. The pixel units 20 in a plurality of adjacent even-numbered rows electrically connected to the same control line 110 can be individually controlled to remain in a non-charged / discharged state for multiple frames. If the display content of the pixel units 20 in the next frame remains unchanged, the pixel units 20 in the region can be controlled not to refresh (not charge / discharge) in the next frame, maintaining their displayed grayscale.

[0116] Step S100: Compare the data voltages of the pixel unit 20 in two adjacent frames.

[0117] Step S110 : comparing the data voltages of each group of pixel units 20 in two adjacent frames.

[0118] Specifically, the data processing module 70 compares the voltages of the data to be loaded in two adjacent frames, determines the regions with the same voltages of the data to be loaded and the regions with different voltages of the data to be loaded in the two frames, and sends the determination result to the display control module 60 .

[0119] The display control module 60 sends a first control signal to the control end of the first switch unit 30 electrically connected to the pixel unit 20 in the same area of the two frames. For example, the first switch unit 30 is an N-type transistor. The first control signal is a low level. The first switch unit 30 electrically connected to the pixel unit 20 in the same area of the two frames is turned off, and the pixels in the corresponding area are not refreshed, and this frame of the picture is maintained. The display control module 60 sends a second control signal to the control end of the first switch unit 30 electrically connected to the pixel unit 20 in different areas of the two frames. For example, the first switch unit 30 is an N-type transistor. The second control signal is a high level. The first switch unit 30 electrically connected to the pixel unit 20 in different areas of the two frames is turned on. The gate drive unit 10 inputs the GOUT signal of each row to the driving TFT tube 21 in the pixel unit 20, controls the driving TFT tube 21 to turn on or off, and the picture is refreshed normally.

[0120] See also Figure 12 , Figure 12 This is a display schematic diagram of the pixel driving circuit 100 provided in an embodiment of the present application updating the Nth frame image to the N+1th frame image.

[0121] Figure 1 Figure a in the middle shows the display of frame N. Frame N is divided into three areas: area 1 displays red, area 2 displays green, and area 3 displays blue.

[0122] Figure 1 Figure b in the middle shows the discharge of regions 1 and 3 near the end of frame N. A comparison reveals that when the N+1 frame is displayed, the images displayed in regions 1 and 3 are different, while the image displayed in region 1 is the same. The first switch units 30 corresponding to regions 1 and 3 are turned on, while the first switch unit 30 corresponding to region 2 is turned off. At the end of frame N, regions 1 and 3 discharge, while region 2 does not, and the image remains unchanged.

[0123] Figure 1 Figure c in the middle shows the display of frame N+1. When frame N+1 is displayed, area 1 is yellow and area 3 is gray. The contents of areas 1 and 3 in frame N+1 are different from those in frame N. Area 2 is green, and its contents in frame N+1 are the same as those in frame N.

[0124] See also Figure 13 , Figure 13 yes Figure 5 A circuit block diagram of a display panel 1000 is provided. Data voltages to be loaded from adjacent frames are input to a data processing module 70. The data processing module 70 groups the data voltages to be loaded by panel region, compares the data voltages to be loaded from each group of adjacent frames to determine if they are identical, and transmits the comparison results to the display control module 60. Based on the data comparison results, the display control module 60 outputs corresponding high and low level control signals to the first switch unit 30, turning the first switch unit 30 on and off.

[0125] See also Figure 14 Step S200: If the data voltages in two adjacent frames of the pixel unit 20 are the same, a first control signal is generated.

[0126] Step S210: If the data voltages in two adjacent frames of the pixel unit 20 are the same and the maximum number of frames for the pixel unit 20 to maintain the displayed grayscale value is less than or equal to (refresh rate / 60)*2 frames, then generate a first control signal.

[0127] Optionally, the maximum number of frames in which the pixel unit 20 maintains the displayed grayscale value is less than or equal to (refresh rate / 60)*2 frames. Because the pixel unit 20 relies on the voltage stored in the storage capacitor 22 to maintain the displayed grayscale value, and as the number of frames in which it remains undischarged increases, the voltage stored in the storage capacitor 22 decreases, and the grayscale value of the pixel unit 20 may decrease (due to leakage of the storage capacitor 22, etc.). Therefore, even if the number of frames in which the difference in the grayscale value to be displayed is less than or equal to the preset grayscale value is large, it is necessary to refresh again after the number of frames in which it remains undischarged reaches (refresh rate / 60)*2 frames, that is, the pixel unit 20 is charged and discharged again to avoid the grayscale value of the pixel unit 20 from decreasing due to the voltage stored in the storage capacitor 22; this can ensure that the pixel unit 20 can maintain the stability of its display brightness even when the grayscale to be displayed remains unchanged for a long time.

[0128] Therefore, the display control module 60 generates a first control signal when the data voltages in two adjacent frames of the pixel unit 20 are the same and the maximum number of frames for the pixel unit 20 to maintain the displayed grayscale value is less than or equal to (refresh rate / 60)*2 frames.

[0129] Step S220: If the data voltages in two adjacent frames of the pixel unit 20 are the same, and the maximum number of frames during which the pixel unit 20 maintains the displayed grayscale value is greater than (refresh rate / 60)*2 frames, then a second control signal is generated.

[0130] Therefore, the display control module 60 generates a second control signal when the data voltages in two adjacent frames of the pixel unit 20 are the same, and the maximum number of frames in which the pixel unit 20 maintains the displayed grayscale value is greater than (refresh rate / 60)*2 frames. Even if the difference in the grayscale value to be displayed is less than or equal to the preset grayscale value for a large number of frames, the pixel unit 20 is refreshed again after the number of frames in which the battery is not discharged reaches (refresh rate / 60)*2 frames, i.e., the pixel unit 20 is charged and discharged again, to avoid a decrease in the grayscale value of the pixel unit 20 due to a drop in the voltage stored in the storage capacitor 22. This ensures that the pixel unit 20 can maintain stable display brightness even when the grayscale to be displayed remains unchanged for a long time.

[0131] The above are some implementation methods of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications are also considered to be within the scope of protection of the present application.

Claims

1. A pixel driving circuit, characterized in that: The pixel driving circuit includes: at least one gate driving unit; at least one pixel unit, wherein the pixel unit further comprises a storage capacitor; at least one first switch unit, one end of each first switch unit being electrically connected to one of the gate driving units, and the other end of each first switch unit being electrically connected to at least one of the pixel units; at least one second switch unit, one end of the second switch unit being electrically connected to the storage capacitor, and the other end of the second switch unit being electrically connected to a common ground; a display control module, electrically connected to a control end of the first switch unit and a control end of the second switch unit; a data processing module, the data processing module receiving grayscale values to be displayed for several frames of images sent by the logic chip; the data processing module being configured to compare the grayscale values to be displayed of the pixel unit in two adjacent frames; and if the difference between the grayscale values to be displayed of the pixel unit in the two adjacent frames is less than or equal to a preset grayscale value, sending a signal to the display control module, the display control module being configured to send a first control signal when the difference between the grayscale values to be displayed of the pixel unit in the two adjacent frames is less than or equal to the preset grayscale value and the maximum number of frames for which the pixel unit maintains the displayed grayscale value is less than or equal to (refresh rate / 60)*2 frames; The display control module is configured to enable the pixel unit to maintain a maximum number of frames displaying a grayscale value greater than (refresh rate / 60)*2 frames, and to send a second control signal when the data voltages in two adjacent frames are the same; and to send a second control signal when the difference between the grayscale values to be displayed in two adjacent frames is greater than a preset grayscale value. The first switch unit is configured to be disconnected in response to the first control signal, and the second switch unit is configured to be disconnected in response to the first control signal of the display control module, so that the pixel unit maintains the displayed grayscale value in at least two frames; the preset grayscale value is the maximum value of the difference between the to-be-displayed grayscale values in two adjacent frames that cannot be distinguished by the human eye; The first switch unit is configured to be turned on in response to the second control signal, and the second switch unit is configured to be turned on in response to the second control signal of the display control module, so that the pixel unit performs a charge and discharge.

2. The pixel driving circuit according to claim 1, wherein: The at least one pixel unit is arranged in at least one row, and the pixel units in one row are electrically connected to the other end of the first switch unit.

3. The pixel driving circuit according to claim 2, wherein: The pixel driving circuit also includes at least one control line, the at least one gate driving unit is arranged in at least one column, the at least one pixel unit is arranged in multiple rows and columns, the at least one first switch unit is arranged in at least one column, at least two adjacent rows of the first switch units are electrically connected to the same control line, or, at least two adjacent odd rows of the first switch units are electrically connected to one control line, and at least two adjacent even rows of the first switch units are electrically connected to another control line, and the control line is used to provide the first control signal.

4. A driving method for a pixel driving circuit, characterized in that: Applied to the pixel driving circuit according to any one of claims 1 to 3, the method comprises: Receive the grayscale values of several frames to be displayed sent by the logic chip; Comparing the data voltages of the pixel unit in two adjacent frames; If the data voltages in two adjacent frames are the same and the maximum number of frames in which the pixel unit maintains displaying the grayscale value is less than or equal to (refresh rate / 60)*2 frames, a first control signal is generated, wherein the first control signal is configured to control a first switch unit electrically connected to the gate driving unit and the pixel unit to be disconnected, so that the pixel unit maintains displaying the grayscale value in at least two frames; If the data voltages in two adjacent frames are the same and the maximum number of frames during which the pixel unit maintains the displayed grayscale value is greater than (refresh rate / 60)*2 frames, a second control signal is generated; If the data voltages in two adjacent frames are different, a second control signal is generated, and the second control signal is configured to control the first switch unit electrically connected to the gate driving unit and the pixel unit to be turned on, so that the pixel unit is charged and discharged in each frame under the drive of the gate driving unit.

5. The driving method according to claim 4, wherein: Before comparing the data voltages of the pixel units in two adjacent frames, the method further includes: Dividing the plurality of pixel units into a plurality of groups, wherein the pixel units in each group are electrically connected to the same control line via at least one of the first switch units; Comparing the data voltages of the pixel units in two adjacent frames includes: The data voltages of each group of pixel units in two adjacent frames are compared.

6. A display panel, characterized in that: The device comprises the pixel driving circuit according to any one of claims 1 to 3.

Images