Mini direct-view circuit driving system, LCD panel and display device

Abstract

This application relates to a driving system for a Mini direct-view circuit, a liquid crystal display panel, and a display device, comprising: a power supply module, a control module, a first driving module, a second driving module, and a display module; the power supply module is connected to the control module, the first driving module, the second driving module, and the display module; the first output terminal of the control module is connected to the input terminal of the first driving module, and the second output terminal of the control module is connected to the input terminal of the second driving module; the output terminal of the first driving module is connected to the first input terminal of the display module; and the output terminal of the second driving module is connected to the second input terminal of the display module. An FPGA chip is used as the control module, and voltage conversion is performed through the first driving module. The pixel data of the display panel is amplified and output through the second driving module to achieve the purpose of driving the Mini direct-view circuit. Therefore, the technical effect of rapidly driving the Mini direct-view circuit can be achieved.

Description

Technical Field

[0001] This application relates to the field of display panel control, and more particularly to a driving system for a Mini direct-view circuit, a liquid crystal display panel, and a display device. Background Technology

[0002] Liquid crystal displays (LCDs) currently hold the vast majority of the market share in the display industry, approximately 75% according to industry research. Organic light-emitting diode (OLED) technology is gradually emerging in the industry, achieving a 20% market share.

[0003] Because LCDs require backlighting, which accounts for the majority of power consumption, OLEDs do not use backlighting. However, over time, OLED aging leads to decreased luminous efficiency and uneven brightness, which becomes particularly noticeable. Therefore, Mini direct-view displays and Mini backlighting technologies have begun to be developed. Mini backlighting applications have already appeared in the market to a small extent, but research on the driving circuits for Mini direct-view displays is still in its infancy. Summary of the Invention

[0004] In view of this, in order to solve the above-mentioned technical problem of how to drive the Mini direct display circuit, this application provides a driving system for the Mini direct display circuit, a liquid crystal display panel and a display device.

[0005] In a first aspect, embodiments of this application provide a driving system for a Mini direct-view circuit, applied to a liquid crystal display panel, comprising:

[0006] The power supply module, control module, first drive module, second drive module, and display module;

[0007] The power module is connected to the control module, the first drive module, the second drive module and the display module respectively, and is used to provide power to each module;

[0008] The first output terminal of the control module is connected to the input terminal of the first driving module, and the second output terminal of the control module is connected to the input terminal of the second driving module. The control module is used to output a scan control signal to the first driving module and to output a pixel control signal to the second driving module.

[0009] The output terminal of the first driving module is connected to the first input terminal of the display module. The first driving module is used to output a scan driving signal to the display module so that the display module can start the row scanning operation of the display panel based on the scan driving signal.

[0010] The output terminal of the second driving module is connected to the second input terminal of the display module. The second driving module is used to output a pixel driving signal to the display module so that the display module displays the image based on the pixel driving signal.

[0011] In one possible implementation, the control module is a field-programmable gate array (FPGA) chip. Based on the FPGA chip, a write control signal is output to the first driving module, so that the first driving module outputs a line scan signal to the display module; and based on the FPGA chip, a pixel control signal is output to the second driving module, so that the second driving module outputs a pixel driving signal.

[0012] In one possible implementation, the first driving module includes: a first level conversion unit, a second level conversion unit, a third level conversion unit, and a fourth level conversion unit, each of the level conversion units being used to convert the level of the DC scanning control signal input by the control module into an AC scanning driving signal;

[0013] The input terminals of the first level conversion unit, the second level conversion unit, the third level conversion unit, and the fourth level conversion unit are respectively connected to the first output terminal of the control module;

[0014] The output terminals of the first level conversion unit, the second level conversion unit, the third level conversion unit, and the fourth level conversion unit are respectively connected to the first input terminal of the display module.

[0015] In one possible implementation, the second driving module includes: a digital-to-analog converter unit and an operational amplifier unit;

[0016] The first input terminal of the digital-to-analog converter is connected to the second output terminal of the control module, the second input terminal of the digital-to-analog converter is connected to the third output terminal of the control module, and the third input terminal of the digital-to-analog converter is connected to the fourth output terminal of the control module.

[0017] The first output terminal of the digital-to-analog converter is connected to the first input terminal of the operational amplifier unit, the second output terminal of the digital-to-analog converter is connected to the second input terminal of the operational amplifier unit, and the third output terminal of the digital-to-analog converter is connected to the third input terminal of the operational amplifier unit. The digital-to-analog converter is used to convert the analog pixel control signal output by the control module into a digital pixel control signal.

[0018] The output terminal of the operational amplifier unit is connected to the second input terminal of the display module. The operational amplifier unit is used to amplify the digital pixel control signal output by the digital-to-analog converter unit and then output the digital pixel drive signal.

[0019] In one possible implementation, the digital-to-analog conversion unit includes: a first digital-to-analog conversion subunit, a second digital-to-analog conversion subunit, and a third digital-to-analog conversion subunit;

[0020] The input terminal of the first digital-to-analog converter subunit is connected to the second output terminal of the control module, and the output terminal of the first digital-to-analog converter subunit is connected to the first input terminal of the operational amplifier unit.

[0021] The input terminal of the second digital-to-analog converter subunit is connected to the third output terminal of the control module, and the output terminal of the second digital-to-analog converter subunit is connected to the second input terminal of the operational amplifier unit;

[0022] The input terminal of the third digital-to-analog converter subunit is connected to the fourth output terminal of the control module, and the output terminal of the first digital-to-analog converter subunit is connected to the third input terminal of the operational amplifier unit.

[0023] In one possible implementation, the first digital-to-analog converter (DAC) subunit receives the first primary color data signal from the three primary colors output by the control module, and inputs the first primary color data signal to the operational amplifier unit for amplification; the second DAC subunit receives the second primary color data signal from the three primary colors output by the control module, and inputs the second primary color data signal to the operational amplifier unit for amplification; the third DAC subunit receives the third primary color data signal from the three primary colors output by the control module, and inputs the third primary color data signal to the operational amplifier unit for amplification.

[0024] In one possible implementation, the operational amplifier unit includes: a first operational amplifier subunit, a second operational amplifier subunit, and a third operational amplifier subunit, wherein the first operational amplifier subunit, the second operational amplifier subunit, and the third operational amplifier subunit are respectively used to output a pixel driving signal of one of the three primary colors to the display module;

[0025] The input terminal of the first operational amplifier subunit is connected to the first output terminal of the digital-to-analog converter unit, and the output terminal of the first operational amplifier subunit is connected to the second output terminal of the display module.

[0026] The input terminal of the second operational amplifier subunit is connected to the second output terminal of the digital-to-analog converter unit, and the output terminal of the second operational amplifier subunit is connected to the second output terminal of the display module;

[0027] The input terminal of the third operational amplifier subunit is connected to the third output terminal of the digital-to-analog converter unit, and the output terminal of the third operational amplifier subunit is connected to the second output terminal of the display module.

[0028] In one possible implementation, the first operational amplifier subunit, the second operational amplifier subunit, and the third operational amplifier subunit each include a plurality of operational amplifiers, so that the first operational amplifier subunit, the second operational amplifier subunit, and the third operational amplifier subunit contain the same number of operational amplifiers;

[0029] The multiple operational amplifiers in the first operational amplifier subunit will receive the first primary color data signal from the three primary colors input by the digital-to-analog converter unit, and after amplifying the first primary color data signal through the multiple operational amplifiers in the first operational amplifier subunit, output the first primary color driving signal to the display module.

[0030] The multiple operational amplifiers in the second operational amplifier subunit receive the second primary color data signal from the three primary colors input by the digital-to-analog converter unit, and after amplifying the second primary color data signal through the multiple operational amplifiers in the second operational amplifier subunit, output the second primary color driving signal to the display module.

[0031] The multiple operational amplifiers in the third operational amplifier subunit will receive the third primary color data signal from the three primary colors input by the digital-to-analog converter unit, and after amplifying the third primary color data signal through the multiple operational amplifiers in the third operational amplifier subunit, output the third primary color driving signal to the display module.

[0032] In a second aspect, embodiments of this application provide a liquid crystal display panel, including an array substrate and a color filter substrate disposed opposite each other, wherein a liquid crystal layer is disposed between the array substrate and the color filter substrate, and the panel includes a driving system having a Mini direct display circuit as described in any of the first aspects on the array substrate.

[0033] Thirdly, embodiments of this application provide a display device, including: a housing, a backlight module disposed within the housing, and a liquid crystal display panel as described in the second aspect.

[0034] The driving system for the Mini direct-view circuit provided in this application embodiment comprises a power supply module, a control module, a first driving module, a second driving module, and a display module. The power supply module is connected to the control module, the first driving module, the second driving module, and the display module, providing power to each module. The first output terminal of the control module is connected to the input terminal of the first driving module, and the second output terminal of the control module is connected to the input terminal of the second driving module. The control module outputs a scan control signal to the first driving module and a pixel control signal to the second driving module. The output terminal of the first driving module is connected to the first input terminal of the display module, outputting a scan driving signal to the display module to enable the display module to perform row scanning operation on the display panel. The output terminal of the second driving module is connected to the second input terminal of the display module, outputting a pixel driving signal to the display module to display the image. An FPGA chip is used as the control module, and the first driving module performs voltage conversion, while the second driving module amplifies and outputs the pixel data from the display panel, thus achieving the purpose of driving the Mini direct-view circuit. This solution can achieve the technical effect of quickly driving the Mini direct display circuit. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0036] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0038] Figure 1 A schematic diagram of the structure of a driving system for a Mini direct-view circuit provided in an embodiment of this application;

[0039] Figure 2 A schematic diagram of the driving system for another Mini direct-view circuit provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram of the structure of a liquid crystal display panel provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] The terms "comprising" and "having" in the embodiments of this application are used to indicate an open-ended inclusion, meaning that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second," etc., are used only as labels and are not intended to limit the number of objects. Furthermore, the different elements and areas in the drawings are only schematic, therefore this application is not limited to the dimensions or distances shown in the drawings.

[0044] To facilitate understanding of the embodiments of this application, the following will provide further explanation and description with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application.

[0045] A Field-Programmable Gate Array (FPGA) is a programmable integrated circuit chip composed of programmable logic units that can be programmed to implement various digital circuit functions.

[0046] Figure 1 This is a schematic diagram of a driving system for a Mini direct-view circuit provided in an embodiment of this application. It illustrates the driving process of a Mini direct-view circuit applied to a liquid crystal display panel. According to... Figure 1 The provided diagram shows the specific structure of the driving system for the Mini direct-view circuit, including:

[0047] The power supply module 11, control module 12, first drive module 13, second drive module 14, and display module 15.

[0048] The power module 11 is connected to the control module 12, the first drive module 13, the second drive module 14 and the display module 15 respectively, and is used to provide power to each module.

[0049] The first output terminal of the control module 12 is connected to the input terminal of the first driving module 13, and the second output terminal of the control module 12 is connected to the input terminal of the second driving module 14. The control module 12 is used to output a scan control signal to the first driving module 13 and to output a pixel control signal to the second driving module 14.

[0050] The output terminal of the first driving module 13 is connected to the first input terminal of the display module 15. The first driving module 13 is used to output a scan driving signal to the display module 15 so that the display module 15 can start the row scanning operation of the display panel based on the scan driving signal.

[0051] The output terminal of the second driving module 14 is connected to the second input terminal of the display module 15. The second driving module 14 is used to output pixel driving signals to the display module 15 so that the display module 15 can display the screen based on the pixel driving signals.

[0052] The control module 12 is a field-programmable gate array (FPGA) chip. Based on the FPGA chip, it outputs write control signals to the first driving module 13, which causes the first driving module 13 to output line scan signals to the display module 15; and based on the FPGA chip, it outputs pixel control signals to the second driving module 14, which causes the second driving module 14 to output pixel driving signals.

[0053] The power module supplies power to other modules, and the control module is an FPGA chip. Utilizing the FPGA chip's multi-functional I / O for programmable logic language output and its self-programmable nature, the system display can be programmed in real-time to achieve desired effects, offering a high degree of flexibility. According to... Figure 1 The provided diagram shows that the FPGA chip is connected to the first driving module. The FPGA chip outputs a write control signal to the first driving module, and the first driving module converts the input DC signal to AC signal, which in turn controls the display module to start scanning line operation. Simultaneously, the FPGA chip is connected to the second driving module and outputs a pixel control signal to it. The second driving module performs digital-to-analog conversion and amplification of the pixel data before outputting a pixel driving signal, which is then displayed on the display module to show the pixel information, thus completing the drive control of the Mini direct-view circuit.

[0054] The driving system for the Mini direct-view circuit provided in this application embodiment comprises a power supply module, a control module, a first driving module, a second driving module, and a display module. The power supply module is connected to the control module, the first driving module, the second driving module, and the display module to provide power to each module. The first output terminal of the control module is connected to the input terminal of the first driving module, and the second output terminal of the control module is connected to the input terminal of the second driving module. The control module outputs scan control signals to the first driving module and pixel control signals to the second driving module. The output terminal of the first driving module is connected to the first input terminal of the display module, and the first driving module outputs scan drive signals to the display module, enabling the display module to initiate row scanning operations on the display panel based on the scan drive signals. The output terminal of the second driving module is connected to the second input terminal of the display module, and the second driving module outputs pixel drive signals to the display module, enabling the display module to display the image based on the pixel drive signals. An FPGA chip is used as the control module, and voltage conversion is performed through the first driving module. The pixel data of the display panel is amplified and output through the second driving module to achieve the purpose of driving the Mini direct-view circuit. This solution achieves the technical effect of rapidly driving the Mini direct-view circuit.

[0055] Figure 2 This is a schematic diagram of the driving system of another Mini direct display circuit provided in an embodiment of this application. Figure 2 Is Figure 1 This introduction is based on [the previous information]. Figure 2 The provided diagram shows the specific structure of the driving system for the Mini direct-view circuit, including:

[0056] The power supply module 11, control module 12, first drive module 13, second drive module 14, and display module 15.

[0057] according to Figure 2 The provided diagram shows that the first driving module 13 in the driving system of the Mini direct display circuit includes: a first level conversion unit 131, a second level conversion unit 132, a third level conversion unit 133 and a fourth level conversion unit 134. Each level conversion unit is used to convert the level of the DC scanning control signal input by the control module into an AC scanning driving signal.

[0058] The input terminals of the first level conversion unit 131, the second level conversion unit 132, the third level conversion unit 133, and the fourth level conversion unit 134 are respectively connected to the first output terminal of the control module 12.

[0059] The output terminals of the first level conversion unit 131, the second level conversion unit 132, the third level conversion unit 133, and the fourth level conversion unit 134 are respectively connected to the first input terminal of the display module 15.

[0060] according to Figure 2 The provided diagram shows that the first level conversion unit 131, the second level conversion unit 132, the third level conversion unit 133, and the fourth level conversion unit 134 are configured as four IC functional chips (e.g., IC1, IC2, IC3, IC4) for level conversion. The FPGA chip inputs write control signals (i.e., WR input signals) to the first level conversion unit 131, the second level conversion unit 132, the third level conversion unit 133, and the fourth level conversion unit 134. The write control signals are input to the level conversion chips IC1-IC4 to convert the DC signal and output an AC signal (i.e., WR output signal) that meets the requirements of the display module.

[0061] In one possible example scenario, the Mini direct display screen is selected with a minimum area of ​​40*40 pixels. The FPGA's general-purpose I / O ports are defined to output WR input signals. These signals are used by level conversion chips IC1 to IC4, each controlling 10 sets of electrical signals. After level conversion by the four level conversion chips, WR output signals are output, totaling 40 sets, serving as the WR input for the Panel display signals. The WR high-level output range is adjustable from 19 to 35V, and the WR low-level range is adjustable from -6 to -12V, serving as the horizontal scan enable signal.

[0062] according to Figure 2 The provided diagram shows that the second driving module 14 in the driving system of the Mini direct display circuit includes: a digital-to-analog converter unit 141 and an operational amplifier unit 142.

[0063] The first input terminal of the digital-to-analog converter 141 is connected to the second output terminal of the control module 12, the second input terminal of the digital-to-analog converter 141 is connected to the third output terminal of the control module 12, and the third input terminal of the digital-to-analog converter 141 is connected to the fourth output terminal of the control module 12.

[0064] The first output terminal of the digital-to-analog converter unit 141 is connected to the first input terminal of the operational amplifier unit 142, the second output terminal of the digital-to-analog converter unit 141 is connected to the second input terminal of the operational amplifier unit 142, and the third output terminal of the digital-to-analog converter unit 141 is connected to the third input terminal of the operational amplifier unit 142. The digital-to-analog converter unit 141 is used to convert the analog pixel control signal output by the control module 12 into a digital pixel control signal.

[0065] The output terminal of the operational amplifier unit 142 is connected to the second input terminal of the display module 15. The operational amplifier unit 142 is used to amplify the digital pixel control signal output by the digital-to-analog converter unit 141 and then output the digital pixel drive signal.

[0066] according to Figure 2 The provided diagram shows that the pixel control signal is output through the FPGA chip, and the analog-to-digital converter 141 converts the pixel control signal into a digital signal. The output digital signal is then processed and amplified to output a pixel drive signal that drives the display module to display the pixels. The display module drives the display interface through the pixel drive signal, thus completing the fast drive display operation of the Mini direct display.

[0067] according to Figure 2 The provided diagram shows that the digital-to-analog converter unit 141 in the driving system of the Mini direct display circuit includes: a first digital-to-analog converter subunit 411, a second digital-to-analog converter subunit 412, and a third digital-to-analog converter subunit 413.

[0068] The input terminal of the first digital-to-analog converter subunit 411 is connected to the second output terminal of the control module 12, and the output terminal of the first digital-to-analog converter subunit 411 is connected to the first input terminal of the operational amplifier unit 142.

[0069] The input terminal of the second digital-to-analog converter subunit 412 is connected to the third output terminal of the control module 12, and the output terminal of the second digital-to-analog converter subunit 412 is connected to the second input terminal of the operational amplifier unit 142.

[0070] The input terminal of the third digital-to-analog converter subunit 413 is connected to the fourth output terminal of the control module 12, and the output terminal of the first digital-to-analog converter subunit 413 is connected to the third input terminal of the operational amplifier unit 142.

[0071] Specifically, the first digital-to-analog converter (DAC) subunit 411 receives the first primary color data signal R_OUT from the three primary colors output by the control module 12, and inputs the first primary color data signal R_OUT to the operational amplifier unit 142 for amplification; the second DAC subunit 412 receives the second primary color data signal G_OUT from the three primary colors output by the control module, and inputs the second primary color data signal G_OUT to the operational amplifier unit 142 for amplification; the third DAC subunit 413 receives the third primary color data signal B_OUT from the three primary colors output by the control module, and inputs the third primary color data signal B_OUT to the operational amplifier unit 142 for amplification.

[0072] according to Figure 2The provided illustration uses a Mini direct-view display with a pixel size of 40*40. The first analog-to-digital converter (ADC) subunit 411, the second ADC subunit 412, and the third ADC subunit 413 control the pixel data of different primary colors from the three primary colors. The first ADC subunit 411 receives the first primary color data signal R_OUT from the control module 12; the second ADC subunit 412 receives the second primary color data signal G_OUT from the control module 12; and the third ADC subunit 413... The conversion subunit 413 receives the third primary color data signal B_OUT from the three primary colors output by the control module. The order of these pixels can be arbitrarily changed; that is, the first digital-to-analog conversion subunit 411 can receive the third primary color data signal B_OUT from the three primary colors output by the control module 12, the second digital-to-analog conversion subunit 412 can receive the first primary color data signal R_OUT from the three primary colors output by the control module, and the third digital-to-analog conversion subunit 413 can receive the second primary color data signal G_OUT from the three primary colors output by the control module. Based on the pixel size of the Mini direct display screen, the first digital-to-analog conversion subunit 411 controls 40 sets of first primary color data signals R_OUT, the second digital-to-analog conversion subunit 412 controls 40 sets of second primary color data signals G_OUT, and the third digital-to-analog conversion subunit 413 controls 40 sets of third primary color data signals B_OUT, thereby obtaining 40 sets of RGB pixel data.

[0073] In one possible example scenario, the FPGA chip outputs stable pixel control signals through clock signals, namely, 40 sets of first primary color data signals R_OUT through the first clock signal CLK1, 40 sets of second primary color data signals G_OUT through the second clock signal CLK2, and 40 sets of third primary color data signals B_OUT through the third clock signal CLK3.

[0074] according to Figure 2 The provided diagram shows that the operational amplifier unit 142 in the driving system of the Mini direct display circuit includes: a first operational amplifier subunit 421, a second operational amplifier subunit 422, and a third operational amplifier subunit 423. The first operational amplifier subunit 421, the second operational amplifier subunit 422, and the third operational amplifier subunit 423 are respectively used to output a pixel driving signal of one of the three primary colors to the display module 15.

[0075] The input terminal of the first operational amplifier subunit 421 is connected to the first output terminal of the digital-to-analog converter unit 141, and the output terminal of the first operational amplifier subunit 422 is connected to the second output terminal of the display module 15.

[0076] The input terminal of the second operational amplifier subunit 422 is connected to the second output terminal of the digital-to-analog converter unit 141, and the output terminal of the second operational amplifier subunit 422 is connected to the second output terminal of the display module 15.

[0077] The input terminal of the third operational amplifier subunit 423 is connected to the third output terminal of the digital-to-analog converter unit 141, and the output terminal of the third operational amplifier subunit 423 is connected to the second output terminal of the display module 15.

[0078] according to Figure 2 The provided diagram shows that the first operational amplifier subunit 421, the second operational amplifier subunit 422, and the third operational amplifier subunit 423 in the driving system of the Mini direct display circuit each contain multiple operational amplifiers, and the first operational amplifier subunit 421, the second operational amplifier subunit 422, and the third operational amplifier subunit 423 contain the same number of operational amplifiers.

[0079] The multiple operational amplifiers in the first operational amplifier subunit 421 receive the first primary color data signal R_OUT from the three primary colors input by the digital-to-analog converter unit 141, and after amplifying the first primary color data signal R_OUT through the multiple operational amplifiers in the first operational amplifier subunit 421, output the first primary color driving signal ROUT to the display module 15.

[0080] The multiple operational amplifiers in the second operational amplifier subunit 422 receive the second primary color data signal G_OUT from the three primary colors input by the digital-to-analog converter unit 141, and after amplifying the second primary color data signal G through the multiple operational amplifiers in the second operational amplifier subunit 422, output the second primary color driving signal GOUT to the display module 15.

[0081] The multiple operational amplifiers in the third operational amplifier subunit 423 receive the third primary color data signal B_OUT from the digital-to-analog converter unit 141, and after amplifying the third primary color data signal B_OUT through the multiple operational amplifiers in the third operational amplifier subunit 423, output the third primary color driving signal BOUT to the display module 15.

[0082] according to Figure 2 The provided diagram shows that integrated operational amplifier chips IC8-IC37 are selected, and ten operational amplifier chips IC8-IC17 are selected in the first operational amplifier subunit 421 to control the first primary color data signal R_OUT. Ten operational amplifier chips IC18-IC27 are selected in the second operational amplifier subunit 422 to control the second primary color data signal G_OUT. Ten operational amplifier chips IC28-IC37 are selected in the third operational amplifier subunit 423 to control the third primary color data signal B_OUT.

[0083] In one possible scenario, the first digital-to-analog converter (DAC) subunit 411 uses chip IC5, the second DAC subunit 412 uses chip IC6, and the third DAC subunit 413 uses chip IC7. The general-purpose I / O ports of the FPGA chip are defined as SPI communication ports. The DAC unit 141 receives clock signals and digital data from the FPGA chip. After the internal program functions of chips IC5-IC7 are executed, it outputs 40 sets of RGB pixels, which serve as the gate signals for controlling the TFTs of each column of light-emitting devices. To avoid insufficient output RGB as gate control signals, an operational amplifier unit 142 is added. The internal operational amplifier subunit is integrated with IC8-IC37 to act as operational amplifiers, increasing the signal drive for each channel. At this time, the operational amplifier unit 142 outputs three sets of pixel drive signals ROUT, GOUT, and BOUT, which serve as the actual gate drive signals for the light-emitting TFTs.

[0084] according to Figure 2 The provided diagram illustrates a possible scenario where, in one example, the Mini direct-view display's driving circuit, driven by the FPGA chip, outputs 40 sets of write control signals. These 40 sets of write control signals are then input to four level conversion chips (IC1-IC4) to convert DC-level signals into AC-level signals, thereby outputting 40 sets of write drive signals as horizontal scan enable signals, providing horizontal scan signals for the display to be illuminated. Simultaneously, the FPGA chip outputs pixel control signals, including 40 sets of red, 40 sets of green, and 40 sets of blue control signals. The first digital-to-analog converter (DAC) chip (IC5) inputs the 40 sets of red control signals to 10 selected operational amplifier chips (e.g., IC8-IC17). After amplification by the operational amplifiers, 40 sets of red drive signals are output to drive the display module. Similarly, the second DAC chip (IC6) inputs the 40 sets of green control signals to 10 selected operational amplifier chips (e.g., IC8-IC17). After being amplified by operational amplifiers (IC18-IC27), the output provides 40 sets of green drive signals to drive the display module. Additionally, 40 sets of blue control signals are input to 10 selected operational amplifier chips (e.g., IC28-IC37) via the third digital-to-analog converter chip IC7. After amplification by these operational amplifiers, the output provides 40 sets of blue drive signals to drive the display module. These 40 sets of red drive signals, 40 sets of green drive signals, and 40 sets of blue drive signals are then used to display the Mini direct display, enabling rapid on / off driving.

[0085] This application provides a driving system for a Mini direct-view circuit. It utilizes an FPGA chip as a control module to output write control signals and pixel control signals. A level conversion module converts the DC write control signals into AC write drive signals, which are then used as the row scanning signals in the display module. The pixel control signals are input into three magic conversion units, undergo analog-to-digital conversion, and then amplified to obtain stable pixel drive signals, thereby achieving the purpose of lighting up the Mini direct-view circuit and realizing the technical effect of driving the Mini direct-view circuit.

[0086] Figure 3 This is a schematic diagram of a liquid crystal display panel provided in an embodiment of this application. The liquid crystal display panel 1000 includes an array substrate and a color filter substrate disposed opposite each other, with a liquid crystal layer (not shown) disposed between the array substrate and the color filter substrate. The array substrate has, for example,... Figure 1-2 The driving system of any of the Mini direct-view circuits described herein. The driving system of the Mini direct-view circuit consists of a plurality of pixel modules 100 and a driving module (not shown in the figure), wherein the pixel module 100 includes a plurality of sub-pixel electrodes 10 arranged in an array.

[0087] Figure 4 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Figure 4 The provided illustration shows that the display device includes: a housing, a backlight module disposed within the housing, and such as... Figure 3 The liquid crystal display panel described herein.

[0088] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A driving system for a Mini direct-view circuit, applied to a liquid crystal display panel, characterized in that, include: The power supply module, control module, first drive module, second drive module, and display module; The power module is connected to the control module, the first drive module, the second drive module and the display module respectively, and is used to provide power to each module; The first output terminal of the control module is connected to the input terminal of the first driving module, and the second output terminal of the control module is connected to the input terminal of the second driving module. The control module is used to output a scan control signal to the first driving module and to output a pixel control signal to the second driving module. The output terminal of the first driving module is connected to the first input terminal of the display module. The first driving module is used to output a scan driving signal to the display module so that the display module can start the row scanning operation of the display panel based on the scan driving signal. The output terminal of the second driving module is connected to the second input terminal of the display module. The second driving module is used to output a pixel driving signal to the display module so that the display module displays the image based on the pixel driving signal. The control module is a field-programmable gate array (FPGA) chip. Based on the FPGA chip, a write control signal is output to the first driving module, which causes the first driving module to output a line scan signal to the display module. And based on the FPGA chip, a pixel control signal is output to the second driving module, so that the second driving module outputs a pixel driving signal; The second driving module includes: a digital-to-analog converter unit and an operational amplifier unit; The first input terminal of the digital-to-analog converter is connected to the second output terminal of the control module, the second input terminal of the digital-to-analog converter is connected to the third output terminal of the control module, and the third input terminal of the digital-to-analog converter is connected to the fourth output terminal of the control module. The first output terminal of the digital-to-analog converter is connected to the first input terminal of the operational amplifier unit, the second output terminal of the digital-to-analog converter is connected to the second input terminal of the operational amplifier unit, and the third output terminal of the digital-to-analog converter is connected to the third input terminal of the operational amplifier unit. The digital-to-analog converter is used to convert the analog pixel control signal output by the control module into a digital pixel control signal. The output terminal of the operational amplifier unit is connected to the second input terminal of the display module. The operational amplifier unit is used to amplify the digital pixel control signal output by the digital-to-analog converter unit and output the digital pixel drive signal. The digital-to-analog conversion unit includes: a first digital-to-analog conversion subunit, a second digital-to-analog conversion subunit, and a third digital-to-analog conversion subunit; The input terminal of the first digital-to-analog converter subunit is connected to the second output terminal of the control module, and the output terminal of the first digital-to-analog converter subunit is connected to the first input terminal of the operational amplifier unit. The input terminal of the second digital-to-analog converter subunit is connected to the third output terminal of the control module, and the output terminal of the second digital-to-analog converter subunit is connected to the second input terminal of the operational amplifier unit; The input terminal of the third digital-to-analog converter subunit is connected to the fourth output terminal of the control module, and the output terminal of the first digital-to-analog converter subunit is connected to the third input terminal of the operational amplifier unit. The first digital-to-analog converter (DAC) receives the first primary color data signal from the three primary colors output by the control module, and inputs the first primary color data signal to the operational amplifier unit for amplification. The second DAC receives the second primary color data signal from the three primary colors output by the control module, and inputs the second primary color data signal to the operational amplifier unit for amplification. The third DAC receives the third primary color data signal from the three primary colors output by the control module, and inputs the third primary color data signal to the operational amplifier unit for amplification. The operational amplifier unit includes a first operational amplifier subunit, a second operational amplifier subunit, and a third operational amplifier subunit, wherein the first operational amplifier subunit, the second operational amplifier subunit, and the third operational amplifier subunit are respectively used to output a pixel driving signal of one of the three primary colors to the display module; The input terminal of the first operational amplifier subunit is connected to the first output terminal of the digital-to-analog converter unit, and the output terminal of the first operational amplifier subunit is connected to the second output terminal of the display module. The input terminal of the second operational amplifier subunit is connected to the second output terminal of the digital-to-analog converter unit, and the output terminal of the second operational amplifier subunit is connected to the second output terminal of the display module; The input terminal of the third operational amplifier subunit is connected to the third output terminal of the digital-to-analog converter unit, and the output terminal of the third operational amplifier subunit is connected to the second output terminal of the display module. The FPGA chip outputs a first primary color data signal through a first clock signal, a second primary color data signal through a second clock signal, and a third primary color data signal through a third clock signal.

2. The system according to claim 1, characterized in that, The first driving module includes: a first level conversion unit, a second level conversion unit, a third level conversion unit, and a fourth level conversion unit. Each level conversion unit is used to convert the level of the DC scanning control signal input by the control module into an AC scanning driving signal. The input terminals of the first level conversion unit, the second level conversion unit, the third level conversion unit, and the fourth level conversion unit are respectively connected to the first output terminal of the control module; The output terminals of the first level conversion unit, the second level conversion unit, the third level conversion unit, and the fourth level conversion unit are respectively connected to the first input terminal of the display module.

3. The system according to claim 1, characterized in that, The first operational amplifier subunit, the second operational amplifier subunit, and the third operational amplifier subunit each contain a plurality of operational amplifiers, and the first operational amplifier subunit, the second operational amplifier subunit, and the third operational amplifier subunit contain the same number of operational amplifiers; The multiple operational amplifiers in the first operational amplifier subunit will receive the first primary color data signal from the three primary colors input by the digital-to-analog converter unit, and after amplifying the first primary color data signal through the multiple operational amplifiers in the first operational amplifier subunit, output the first primary color driving signal to the display module. The multiple operational amplifiers in the second operational amplifier subunit receive the second primary color data signal from the three primary colors input by the digital-to-analog converter unit, and after amplifying the second primary color data signal through the multiple operational amplifiers in the second operational amplifier subunit, output the second primary color driving signal to the display module. The multiple operational amplifiers in the third operational amplifier subunit will receive the third primary color data signal from the three primary colors input by the digital-to-analog converter unit, and after amplifying the third primary color data signal through the multiple operational amplifiers in the third operational amplifier subunit, output the third primary color driving signal to the display module.

4. A liquid crystal display panel, comprising an array substrate and a color filter substrate disposed opposite each other, wherein a liquid crystal layer is disposed between the array substrate and the color filter substrate, characterized in that, include: The array substrate has a driving system for the Mini direct display circuit as described in any one of claims 1-3.

5. A display device, characterized in that, include: The housing contains a backlight module and a liquid crystal display panel as described in claim 4.

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