A digital programmable gain integrated instrument amplifier

Abstract

The present application discloses a digital programmable gain integrated instrument amplifier, which includes: an amplification module connected to an input signal for amplifying the input signal; a resistor array including a plurality of resistors, wherein a plurality of resistors in the plurality of resistors constitute one or more signal channels, and each of the signal channels corresponds to an amplification gain; a logic controller outputs a control signal for controlling the conduction of one of the one or more signal channels according to the amplification factor of the proportional amplifier. The present application can realize selectable gain through a logic controller and a resistor array; at the same time, the resistors in the resistor array use metal film resistors with low temperature coefficients, and the resistors are integrated inside the circuit to solve the problem of mismatch of external gain resistors, so that the amplifier gain has a low temperature drift characteristic.

Description

Technical Field

[0001] The present application relates to the technical field of amplifiers, and in particular to a digital programmable gain integrated instrument amplifier. Background Art

[0002] The instrumentation amplifier (IA) is a modified version of the differential amplifier. It has an input buffer, which makes it unnecessary to match the input impedance, so it is very suitable for measurement and electronic instruments. As a precision differential voltage amplifier, the instrumentation amplifier is derived from the operational amplifier and is superior to the operational amplifier in many aspects. The instrumentation amplifier has two structures: two op amps and three op amps. The instrumentation amplifier with a three op amp structure is superior to the two op amp structure in terms of input impedance, common mode rejection ratio, gain accuracy, etc. However, many three op amp structures in the prior art ( Figure 1 , Figure 2 , Figure 3 ) basically have the problem of large temperature drift. Summary of the invention

[0003] In view of the above-mentioned shortcomings of the prior art, an object of the present application is to provide a digital programmable gain integrated instrumentation amplifier to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives and other related objectives, a digital programmable gain integrated instrument amplifier is provided, the instrument amplifier comprising:

[0005] The emitter follower is connected to the input signal and is used to amplify the input signal;

[0006] A differential amplifier, whose input end is connected to the output end of the emitter follower, and is used to amplify the output signal of the emitter follower;

[0007] A proportional amplifier, wherein one input end is connected to the output end of the differential amplifier, and the other input end is connected to a resistor array, and is used to proportionally amplify the output signal of the differential amplifier; the resistor array includes a plurality of resistors, and a plurality of resistors in the plurality of resistors constitute one or more signal channels, and each of the signal channels corresponds to an amplification gain;

[0008] The logic controller outputs a control signal for controlling the conduction of one of the one or more signal channels according to the amplification factor of the proportional amplifier.

[0009] In one embodiment of the present invention, the emitter follower includes:

[0010] A first operational amplifier, comprising a first positive input terminal and a first negative output terminal;

[0011] A second operational amplifier comprises a second positive input terminal and a second negative output terminal;

[0012] The first positive input terminal is connected to the negative signal / positive signal of the input signal, the first reverse input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to one of the input terminals of the differential amplifier; the second positive input terminal is connected to the positive signal / negative signal of the input signal, the second reverse input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the other input terminal of the differential amplifier.

[0013] In one embodiment of the present invention, the first operational amplifier and the second operational amplifier have the same structure, and the first operational amplifier includes: first to seventeenth transistors, fifth to fifteenth resistors, a first capacitor, and a second capacitor;

[0014] The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is connected to the first voltage via the fifth resistor and the sixth resistor connected in series, the emitter of the second transistor is connected to the first voltage via the seventh resistor and the eighth resistor connected in series, the source of the first transistor is connected to the base and the collector of the fourth transistor respectively, the emitter of the fourth transistor is connected to the emitter of the third transistor and forms a first connection node, the base of the fourth transistor is connected to the base of the fifth transistor and the collector of the fifth transistor respectively, the collector of the third transistor is connected to the collector of the first transistor and forms a second connection node; the base of the sixth transistor is connected to the input signal via the ninth resistor; the collector of the sixth transistor is connected to the first voltage, and the sixth transistor is connected to the base of the fifth transistor and the collector of the fifth transistor respectively. The emitter of the transistor is connected to the collector of the seventh transistor, the emitter of the seventh transistor is connected to the collector of the eighth transistor, the emitter of the eighth transistor is connected to the second voltage via the tenth resistor, and the collector of the seventh transistor is connected to the base; the base of the third transistor is connected to the emitter of the sixth transistor; the first connection node is connected to the collector of the ninth transistor, and the emitter of the ninth transistor is connected to the second voltage via the eleventh resistor; the emitter of the tenth transistor is connected to the second voltage via the twelfth resistor, the collector of the tenth transistor is connected to the collector of the fourteenth transistor and forms a third connection node, the collector of the fourteenth transistor is connected to the base of the fourteenth transistor via the fourteenth resistor and the first capacitor connected in series, and the emitter of the fourteenth transistor is connected to The first voltage is connected to the base of the fourteenth transistor, the base of the fourteenth transistor is connected to the second connection node; the emitter of the eleventh transistor is connected to the second voltage via the thirteenth resistor, the collector of the eleventh transistor is connected to the emitter of the twelfth transistor, and the collector of the twelfth transistor is connected to the third voltage; the base of the twelfth transistor is connected to the third connection node; the base of the eighth transistor, the base of the ninth transistor, the base of the tenth transistor, and the base of the eleventh transistor are respectively connected to the first bias voltage; the base of the fifteenth transistor is connected to the third connection node, the collector of the fifteenth transistor is connected to the first voltage, the emitter of the fifteenth transistor is respectively connected to the base of the sixteenth transistor and the collector of the seventeenth transistor, the emitter of the seventeenth transistor is connected to the second voltage via the fifteenth resistor, and the base of the eighth transistor, the base of the ninth transistor, the base of the tenth transistor, and the base of the eleventh transistor are respectively connected to the first bias voltage. The base of the seventeenth transistor is connected to the second bias voltage, the collector of the sixteenth transistor is connected to the first voltage, the emitter of the sixteenth transistor is connected to the emitter of the eighteenth transistor, the collector of the eighteenth transistor is connected to the second voltage, the base of the eighteenth transistor is connected to the emitter of the twelfth transistor, and a second capacitor is connected in parallel between the collector and the base of the eighteenth transistor; the emitter of the thirteenth transistor is connected to the third connection node; the collector of the thirteenth transistor is connected to the base and then connected to the emitter of the eighteenth transistor and the emitter of the sixteenth transistor respectively and serve as the output end of the first operational amplifier; the emitter of the fifth transistor is connected to the base of the sixth transistor, and the base of the fifth transistor is connected to the collector and then connected to the output end of the first operational amplifier.

[0015] In one embodiment of the present invention, the differential amplifier comprises:

[0016] a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0017] A third operational amplifier comprises a third positive input terminal and a third negative input terminal;

[0018] The first resistor is connected between the output terminal of the first operational amplifier and the third reverse input terminal, the second resistor is connected between the output terminal of the second operational amplifier and the third positive input terminal, the third resistor is connected between the third reverse input terminal and the output terminal of the third operational amplifier, one end of the fourth resistor is connected to the third positive input terminal, the other end of the fourth resistor is externally connected to a fourth voltage, and the other end of the fourth resistor is connected to the resistor array.

[0019] In one embodiment of the present invention, the third operational amplifier includes: first to fourth transistors, ninth to seventeenth transistors, fifth to eighth resistors, eleventh to fifteenth resistors, a first capacitor, and a second capacitor;

[0020] The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is connected to the first voltage via the fifth resistor and the sixth resistor connected in series, the emitter of the second transistor is connected to the first voltage via the seventh resistor and the eighth resistor connected in series, the source of the first transistor is connected to the base and the collector of the fourth transistor respectively, the emitter of the fourth transistor is connected to the emitter of the third transistor and forms a first connection node, the base of the third transistor is connected to the first input signal, and the base of the fourth transistor is connected to the second input signal; the collector of the third transistor is connected to the collector of the first transistor and forms a second connection node; the first connection node is connected to the collector of the ninth transistor, and the emitter of the ninth transistor is connected to the second voltage via the eleventh resistor; the emitter of the tenth transistor is connected to the second voltage via the twelfth resistor, the collector of the tenth transistor is connected to the collector of the fourteenth transistor and forms a third connection node, the collector of the fourteenth transistor is connected to the base of the fourteenth transistor via the fourteenth resistor and the first capacitor connected in series, the emitter of the fourteenth transistor is connected to the second voltage, and the base of the fourteenth transistor is connected to the second connection node; the emitter of the eleventh transistor is connected to the second voltage via the thirteenth resistor The first transistor is connected to the second voltage, the collector of the eleventh transistor is connected to the emitter of the twelfth transistor, and the collector of the twelfth transistor is connected to the third voltage; the base of the twelfth transistor is connected to the third connection node; the bases of the ninth transistor, the tenth transistor, and the eleventh transistor are respectively connected to the first bias voltage; the base of the fifteenth transistor is connected to the third connection node, the collector of the fifteenth transistor is connected to the second voltage, the emitter of the fifteenth transistor is respectively connected to the base of the sixteenth transistor and the collector of the seventeenth transistor, and the emitter of the seventeenth transistor is connected to the first voltage via the fifteenth resistor, The base of the seventeenth transistor is connected to the second bias voltage, the collector voltage of the sixteenth transistor is connected to the second voltage, the emitter of the sixteenth transistor is connected to the emitter of the eighteenth transistor, the collector of the eighteenth transistor is connected to the second voltage, the base of the eighteenth transistor is connected to the emitter of the twelfth transistor, and a second capacitor is connected in parallel between the collector and the base of the eighteenth transistor; the emitter of the thirteenth transistor is connected to the third connection node; the collector and base of the thirteenth transistor are connected and then connected to the emitter of the eighteenth transistor and the emitter of the sixteenth transistor respectively and serve as the output end of the third operational amplifier.

[0021] In one embodiment of the present invention, the proportional amplifier comprises:

[0022] a fourth operational amplifier, comprising a fourth positive input terminal and a fourth negative input terminal;

[0023] A resistor array includes a logic control terminal, a first non-logic control terminal, and a second non-logic control terminal;

[0024] The fourth positive input terminal is connected to the output terminal of the differential amplifier, the fourth negative input terminal is connected to the logic control terminal, the first non-logic control terminal is connected to the fourth voltage, and the second non-logic control terminal is connected to the output terminal of the fourth operational amplifier.

[0025] In one embodiment of the present invention, the logic controller includes a first output terminal, a second output terminal, and a third output terminal, each outputting a control signal; the logic controller includes: an eighteenth transistor to a thirty-first transistor and a sixteenth resistor to a nineteenth resistor;

[0026] The base of the eighteenth transistor is connected to the third input signal via the tenth resistor, the base of the nineteenth transistor is connected to the base of the twentieth transistor and forms a fourth connection node, and the base of the twenty-first transistor is connected to the fourth input signal via the seventeenth resistor; the collector of the eighteenth transistor, the collector of the nineteenth transistor, the collector of the twentieth transistor, and the collector of the twenty-first transistor are respectively connected to the sixth voltage; the emitter of the eighteenth transistor is connected to the emitter of the nineteenth transistor and then to the collector of the twenty-second transistor, the fourth connection node is connected to the collector of the twenty-third transistor, the emitter of the twentieth transistor is connected to the emitter of the twenty-first transistor and then to the collector of the twenty-fourth transistor; the base of the twenty-second transistor, the base of the twenty-third transistor, and the base of the twenty-fourth transistor are connected to the first bias voltage, and the emitter of the twenty-second transistor, the emitter of the twenty-third transistor, and the emitter of the twenty-fourth transistor are connected and then connected to the fifth voltage via the eighteenth resistor; the base of the thirty-third transistor and the base of the thirty-second transistor are respectively connected to the second bias voltage, and the emitter of the thirty-third transistor and the emitter of the thirty-second transistor are respectively connected to the sixth voltage , the collector of the thirty-third transistor is respectively connected to the emitter of the twenty-fifth transistor and the emitter of the twenty-seventh transistor, the base of the twenty-sixth transistor is connected to the collector of the twenty-fourth transistor, and the collector of the twenty-sixth transistor is connected to the collector of the twenty-fifth transistor as the first output terminal; the emitter of the twenty-seventh transistor is used as the second output terminal, the base of the twenty-fifth transistor is connected to the collector of the twenty-second transistor, the collector of the thirty-second transistor is respectively connected to the emitter of the twenty-sixth transistor and the emitter of the twenty-eighth transistor, the base of the twenty-eighth transistor is connected to the base of the twenty-seventh transistor, and the collector of the twenty-eighth transistor is used as the third output terminal, the collector of the twenty-third transistor is respectively connected to the base of the twenty-eighth transistor and one end of the nineteenth resistor, the other end of the nineteenth resistor is respectively connected to the base and collector of the twenty-ninth transistor, the emitter of the twenty-ninth transistor is respectively connected to the collector and base of the thirtieth transistor, the emitter of the thirtieth transistor is connected to the emitter of the thirty-first transistor, the collector of the thirty-first transistor is connected to the sixth voltage, and the base of the thirty-first transistor is grounded.

[0027] In one embodiment of the present invention, the first bias voltage and the second bias voltage are output through a bias circuit, and the bias circuit includes: a first MOS transistor, a second MOS transistor, a twentieth resistor to a twenty-third resistor, and a thirty-second transistor to a thirty-eighth transistor;

[0028] The base of the thirty-second transistor is connected to the base of the thirty-third transistor, the collector of the thirty-second transistor is connected to the base, the emitter of the thirty-second transistor is connected to the collector of the thirty-fourth transistor and the base of the thirty-fifth transistor respectively, the emitter of the thirty-fourth transistor is connected to the seventh voltage, the emitter of the thirty-third transistor is connected to the base of the thirty-fourth transistor and the collector of the thirty-fifth transistor respectively, the emitter of the thirty-fifth transistor is connected to the seventh voltage via the twentieth resistor, the collector of the thirty-second transistor is connected to the source of the second MOS tube, the drain of the second MOS tube is connected to the source of the first MOS tube, the drain of the first MOS tube is connected to the eighth voltage. voltage, the gate of the first MOS tube and the gate of the second MOS tube are respectively connected to the ninth voltage; the collector of the thirty-third transistor is respectively connected to the base and the collector of the thirty-sixth transistor, the emitter of the thirty-sixth transistor is connected to the eighth voltage via the twenty-first resistor, the base of the thirty-sixth transistor is connected to the base of the thirty-seventh transistor and then outputs the first bias voltage, the emitter of the thirty-seventh transistor is connected to the eighth voltage via the twenty-second resistor, the collector of the thirty-seventh transistor is connected to the collector of the thirty-eighth transistor, and the emitter of the thirty-eighth transistor is connected to the seventh voltage via the twenty-third resistor; the base of the thirty-eighth transistor is connected to the collector and then outputs the second bias voltage.

[0029] In one embodiment of the present invention, the resistors in the resistor array are metal thin film resistors with low temperature coefficients.

[0030] As described above, the digital programmable gain integrated instrument amplifier provided by the present application has the following beneficial effects:

[0031] The present application discloses a digital programmable gain integrated instrument amplifier, the instrument amplifier comprising: an amplification module, connected to an input signal, for amplifying the input signal; a resistor array, comprising a plurality of resistors, a plurality of resistors among the plurality of resistors constituting one or more signal channels, each of the signal channels corresponding to an amplification gain; a logic controller, outputting a control signal, for controlling the conduction of one of the one or more signal channels according to the amplification factor of the proportional amplifier. The present application can realize selectable gain through a logic controller and a resistor array; at the same time, the resistors in the resistor array adopt metal film resistors with low temperature coefficients, and the resistors are integrated inside the circuit to solve the problem of mismatch of external gain resistors, so that the amplifier gain has a low temperature drift characteristic.

[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0034] Figure 1 This is the block diagram of the traditional three-op-amp instrumentation amplifier;

[0035] Figure 2 The block diagram of the three-op-amp instrumentation amplifier with internally integrated gain resistors;

[0036] Figure 3 The block diagram of the gain programmable three-op-amp instrumentation amplifier is shown below;

[0037] Figure 4 This is a structural block diagram of a digital programmable gain integrated instrumentation amplifier according to an embodiment of the present application;

[0038] Figure 5 A circuit structure diagram of a first operational amplifier according to an embodiment of the present application;

[0039] Figure 6 A circuit structure diagram of a third operational amplifier according to an embodiment of the present application;

[0040] Figure 7 A circuit structure diagram of a logic controller according to an embodiment of the present application;

[0041] Figure 8 This is a diagram of simulation results of an instrument amplifier according to an embodiment of the present application;

[0042] Fig. 9 FIG. 1 is a circuit diagram of a bias voltage according to an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0044] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present invention, and thus the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0045] Although the terms "first", "second", "A", "B", etc. may be used herein to describe various elements, these elements should not be limited by these terms and are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the following technology. The term "and / or" includes a combination of multiple related items or any item in the multiple related items.

[0046] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not exclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0047] Before describing the drawings in detail, it is intended to clarify that the division of components in this specification is divided only by the main function of each component. That is, two or more components to be described below can be combined into one component, or can be divided into two or more components according to more detailed functions. In addition to the main function of the component, each component to be described below can also perform some or all of the functions of other components, and some of the main functions of each component can be exclusively performed by other components.

[0048] The monolithic instrumentation amplifier is a precision analog integrated circuit used for the pickup, amplification, and transmission of various weak signals. It is widely used in various precision measurement fields such as instruments and medical equipment. The instrumentation amplifier has two structures: two op amps and three op amps. The instrumentation amplifier with a three op amp structure is superior to the two op amp structure in terms of input impedance, common mode rejection ratio, gain accuracy, etc., so it has a wider range of applications. Figure 1As shown in the figure, it is a typical three-op-amp instrumentation amplifier. An external resistor is required to determine the gain. A1 and A2 are used as buffer amplifiers to increase the input impedance. A3, R1, R2, R3, and R4 form component amplifiers. When R1=R2=R3=R4, the differential amplifier gain is 1, and the entire instrumentation amplifier gain G=1+2R / RG. The two internal R resistors are laser-corrected to meet the gain accuracy requirements of the circuit. R1 / / R3=R2 / / R4 are also laser-corrected to improve the common-mode rejection ratio (CMRR). The biggest problem with this instrumentation amplifier is that the temperature coefficient of the external resistor RG must be completely matched with the temperature coefficient of the internal gain resistor R of the chip, otherwise the gain temperature drift of the circuit will increase!

[0049] To solve Figure 1 Structural defects, improve the structure such as Figure 2 As shown, the external resistor RG is placed inside the chip. RG and R are made of the same material at the same time. When the temperature changes, RG and R change at the same time, and the gain temperature drift of the circuit remains almost unchanged.

[0050] Although this structure solves the gain temperature drift problem, its application is not flexible enough. To meet different gain requirements, users must modify the connection method on the hardware (application board).

[0051] against Figure 2 The shortcomings of the structure, further improvement of the structure such as Figure 3 As shown. The built-in RG and R are formed by resistors of different resistance values, and then a logic circuit (Logic) controls different combinations of RG and R to form different gains. The digital signal of the logic (compatible with CMOS or TTL signal) is input by the external MCU programming. When the user needs a different gain, there is no need to change the hardware structure, and it can be completed by programming the single-chip microcomputer (MCU). Figure 3 The structure is almost an ideal instrument amplifier! The only disadvantage is that the logic circuit structure and manufacturing process of processing the combination of RG and R are complex and costly!

[0052] In view of the above problems, this application provides a digital programmable gain integrated instrument amplifier, which mainly solves the problem of large temperature drift caused by mismatch of external gain resistors in existing instrument amplifiers, and designs programmable control gain selection. Please refer to Figure 4 , Figure 4 This is a structural block diagram of a digital programmable gain integrated instrumentation amplifier according to an embodiment of the present application. Figure 4 In the embodiment, the digital programmable gain integrated instrument amplifier comprises at least: an emitter follower 410, a differential amplifier 420, a proportional amplifier 430 and a logic controller 440; wherein,

[0053] The emitter follower 410 is connected to the input signal and is used to amplify the input signal;

[0054] A differential amplifier 420, whose input end is connected to the output end of the emitter follower, and is used to amplify the output signal of the emitter follower;

[0055] A proportional amplifier 430, wherein one input terminal is connected to the output terminal of the differential amplifier, and the other input terminal is connected to a resistor array, and is used to proportionally amplify the output signal of the differential amplifier; the resistor array includes a plurality of resistors, and a plurality of resistors in the plurality of resistors constitute one or more signal channels, and each of the signal channels corresponds to an amplification gain;

[0056] The logic controller 440 outputs a control signal for controlling one of the one or more signal channels to be turned on according to the gain of the proportional amplifier.

[0057] The present application can realize selectable gain through a logic controller and a resistor array. At the same time, the resistors in the resistor array use metal film resistors with low temperature coefficients, and the resistors are integrated inside the circuit to solve the problem of mismatching of external gain resistors, so that the amplifier gain has a low temperature drift characteristic.

[0058] The following is a detailed description of each component module.

[0059] Please continue reading Figure 4 , the emitter follower 410 comprises:

[0060] A first operational amplifier A1, comprising a first positive input terminal and a first negative output terminal;

[0061] A second operational amplifier A2, comprising a second positive input terminal and a second negative output terminal;

[0062] The first positive input terminal is connected to the negative signal / positive signal of the input signal, the first reverse input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to one of the input terminals of the differential amplifier; the second positive input terminal is connected to the positive signal / negative signal of the input signal, the second reverse input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the other input terminal of the differential amplifier.

[0063] In this embodiment, the emitter follower composed of the first operational amplifier A1 and the second operational amplifier A2 is used as a buffer amplifier, which can improve the input impedance.

[0064] Specifically, the first operational amplifier A1 and the second operational amplifier A2 have the same structure. Figure 5 , Figure 5 FIG. 1 is a circuit diagram of a first operational amplifier according to an embodiment of the present application. Figure 5In the embodiment, the first operational amplifier A1 includes: a first transistor Q1 to a seventeenth transistor Q17, a fifth resistor R5 to a fifteenth resistor R15, a first capacitor C1, and a second capacitor C2;

[0065] The base of the first transistor Q1 is connected to the base of the second transistor Q2, the emitter of the first transistor Q1 is connected to the first voltage via the fifth resistor R5 and the sixth resistor R6 connected in series, the emitter of the second transistor Q2 is connected to the first voltage via the seventh resistor R7 and the eighth resistor R8 connected in series, the source of the first transistor Q1 is connected to the base and the collector of the fourth transistor Q4, the emitter of the fourth transistor Q4 is connected to the emitter of the third transistor Q3 and forms a first connection node, the base of the fourth transistor Q4 is connected to the base of the fifth transistor Q5 and the collector of the fifth transistor Q5, the collector of the third transistor Q3 is connected to the collector of the first transistor Q1 and forms a second connection node; the base of the sixth transistor Q6 is connected to the ninth resistor R7 and the eighth resistor R8 connected in series, The resistor R9 is connected to the input signal; the collector of the sixth transistor Q6 is connected to the first voltage, the emitter of the sixth transistor Q6 is connected to the collector of the seventh transistor Q7, the emitter of the seventh transistor Q7 is connected to the collector of the eighth transistor Q8, the emitter of the eighth transistor Q8 is connected to the second voltage via the tenth resistor R10, and the collector and base of the seventh transistor Q7 are connected; the base of the third transistor Q3 is connected to the emitter of the sixth transistor Q6; the first connection node is connected to the collector of the ninth transistor Q9, and the emitter of the ninth transistor Q9 is connected to the second voltage via the eleventh resistor R11; the emitter of the tenth transistor Q10 is connected to the second voltage via the twelfth resistor R12, and the collector of the tenth transistor Q10 is connected to the collector of the fourteenth transistor Q14 and forms a The third connection node is formed, the collector of the fourteenth transistor Q14 is connected to the base of the fourteenth transistor Q14 via the fourteenth resistor R14 and the first capacitor C1 connected in series, the emitter of the fourteenth transistor Q14 is connected to the first voltage, and the base of the fourteenth transistor Q14 is connected to the second connection node; the emitter of the eleventh transistor Q11 is connected to the second voltage via the thirteenth resistor R13, the collector of the eleventh transistor Q11 is connected to the emitter of the twelfth transistor Q12, and the collector of the twelfth transistor Q12 is connected to the third voltage; the base of the twelfth transistor Q12 is connected to the third connection node; the base of the eighth transistor Q8, the base of the ninth transistor Q9, the base of the tenth transistor Q10, and the base of the eleventh transistor Q11 are respectively connected to the first bias voltage voltage; the base of the fifteenth transistor is connected to the third connection node, the collector of the fifteenth transistor is connected to the first voltage, the emitter of the fifteenth transistor is connected to the base of the sixteenth transistor Q16 and the collector of the seventeenth transistor Q17 respectively, the emitter of the seventeenth transistor Q17 is connected to the second voltage via the fifteenth resistor R15, the base of the seventeenth transistor Q17 is connected to the second bias voltage, the collector of the sixteenth transistor Q16 is connected to the first voltage, the emitter of the sixteenth transistor Q16 is connected to the emitter of the eighteenth transistor Q18, the collector of the eighteenth transistor Q18 is connected to the second voltage, the base of the eighteenth transistor Q18 is connected to the emitter of the twelfth transistor Q12, and the second capacitor C2 is connected in parallel between the collector and the base of the eighteenth transistor Q18;The emitter of the thirteenth transistor Q13 is connected to the third connection node; the collector and base of the thirteenth transistor Q13 are connected to the emitter of the eighteenth transistor Q18 and the emitter of the sixteenth transistor Q16 and serve as the output terminal of the first operational amplifier A1; the emitter of the fifth transistor Q5 is connected to the base of the sixth transistor Q6, and the base and collector of the fifth transistor Q5 are connected to the output terminal of the first operational amplifier A1.

[0066] like Figure 5 As shown, the first operational amplifier and / or the second operational amplifier is composed of three-stage amplification, the third transistor Q3 and the fourth transistor Q4 form an input differential pair, constitute the first stage amplification, output by the collector of the second transistor Q2, and then enter the second stage; wherein, the second stage amplification is composed of the tenth transistor Q10 and the fourteenth transistor Q14, and the sixteenth transistor Q16 and the eighteenth transistor Q18 form a push-pull output stage (third stage amplification). Different from the vast majority of operational amplifier input stages, this embodiment optimizes the structure of the first operational amplifier A1, adds a sixth transistor Q6 branch, the circuit input signal enters the base of the sixth transistor Q6, and then the emitter of the sixth transistor Q6 drives the base of the third transistor Q3, and the signal input to the base of the fourth transistor Q4 is exactly the same as the signal input to the base of the third transistor Q3. In this way, the input bias current (Ib), an important DC parameter indicator, can be reduced to avoid affecting the sensor of the front stage of the circuit when applied.

[0067] Please continue reading Figure 4 , the differential amplifier comprises:

[0068] A first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; a third operational amplifier A3, including a third positive input terminal and a third negative input terminal;

[0069] The first resistor R1 is connected between the output terminal of the first operational amplifier A1 and the third reverse input terminal, the second resistor R2 is connected between the output terminal of the second operational amplifier A2 and the third positive input terminal, the third resistor R3 is connected between the third reverse input terminal and the output terminal of the third operational amplifier A3, one end of the fourth resistor R4 is connected to the third positive input terminal, the other end of the fourth resistor R4 is externally connected to the fourth voltage Ref, and the other end of the fourth resistor R4 is connected to the resistor array.

[0070] When the resistance R1=R2=R3=R4, the gain G1 of the output of the third operational amplifier A3 is 1;

[0071] See also Figure 6 , Figure 6 FIG. 1 is a circuit diagram of a third operational amplifier according to an embodiment of the present application. Figure 6In the embodiment, the third operational amplifier A3 includes: a first transistor Q1 to a fourth transistor Q4, a ninth transistor Q9 to a seventeenth transistor Q17, a fifth resistor R5 to an eighth resistor R8, an eleventh resistor R11 to a fifteenth resistor R15, a first capacitor C1, and a second capacitor C2;

[0072] The base of the first transistor Q1 is connected to the base of the second transistor Q2, the emitter of the first transistor Q1 is connected to the first voltage via the fifth resistor R5 and the sixth resistor R6 connected in series, the emitter of the second transistor Q2 is connected to the first voltage via the seventh resistor R7 and the eighth resistor R8 connected in series, the source of the first transistor Q1 is connected to the base and the collector of the fourth transistor Q4 respectively, the emitter of the fourth transistor Q4 is connected to the emitter of the third transistor Q3 and forms a first connection node, the base of the third transistor Q3 is connected to the first input signal, and the base of the fourth transistor Q4 is connected to the second input signal; the collector of the third transistor Q3 is connected to the collector of the first transistor Q1 and forms a first connection node. a second connection node; a first connection node is connected to the collector of the ninth transistor Q9, and the emitter of the ninth transistor Q9 is connected to the second voltage via the eleventh resistor R11; an emitter of the tenth transistor Q10 is connected to the second voltage via the twelfth resistor R12, and the collector of the tenth transistor Q10 is connected to the collector of the fourteenth transistor Q14 and forms a third connection node, and the collector of the fourteenth transistor Q14 is connected to the base of the fourteenth transistor Q14 via the fourteenth resistor R14 and the first capacitor C1 connected in series, and the emitter of the fourteenth transistor Q14 is connected to the second voltage, and the base of the fourteenth transistor Q14 is connected to the second connection node; an emitter of the eleventh transistor Q11 is connected to the second voltage via the thirteenth resistor R1 3 is connected to the second voltage, the collector of the eleventh transistor Q11 is connected to the emitter of the twelfth transistor Q12, and the collector of the twelfth transistor Q12 is connected to the third voltage; the base of the twelfth transistor Q12 is connected to the third connection node; the base of the ninth transistor Q9, the base of the tenth transistor Q10, and the base of the eleventh transistor Q11 are respectively connected to the first bias voltage; the base of the fifteenth transistor is connected to the third connection node, the collector of the fifteenth transistor is connected to the second voltage, the emitter of the fifteenth transistor is respectively connected to the base of the sixteenth transistor Q16 and the collector of the seventeenth transistor Q17, the emitter of the seventeenth transistor Q17 is connected to the first voltage via the fifteenth resistor R15, and the base of the seventeenth transistor Q17 is connected to the first voltage. The base of the body transistor Q17 is connected to the second bias voltage, the collector voltage of the sixteenth transistor Q16 is connected to the second voltage, the emitter of the sixteenth transistor Q16 is connected to the emitter of the eighteenth transistor Q18, the collector of the eighteenth transistor Q18 is connected to the second voltage, the base of the eighteenth transistor Q18 is connected to the emitter of the twelfth transistor Q12, and the second capacitor C2 is connected in parallel between the collector and the base of the eighteenth transistor Q18; the emitter of the thirteenth transistor Q13 is connected to the third connection node; the collector and base of the thirteenth transistor Q13 are connected, and then connected to the emitter of the eighteenth transistor Q18 and the emitter of the sixteenth transistor Q16 respectively, and serve as the output end of the third operational amplifier A3.

[0073] Please continue reading Figure 4 , the proportional amplifier comprises:

[0074] A fourth operational amplifier A4, comprising a fourth positive input terminal and a fourth negative input terminal;

[0075] A resistor array includes a logic control terminal, a first non-logic control terminal, and a second non-logic control terminal;

[0076] The fourth positive input terminal is connected to the output terminal of the differential amplifier, the fourth negative input terminal is connected to the logic control terminal, the first non-logic control terminal is connected to the fourth voltage Ref, and the second non-logic control terminal is connected to the output terminal of the fourth operational amplifier A4.

[0077] It should be noted that the output end of the fourth operational amplifier A4 is also the output end of the entire instrumentation amplifier.

[0078] The resistor array includes resistors R5 (A-C) and R6 (A-C). The gain of the proportional amplifier is composed of resistors R5 (A-C) and R6 (A-C), and its gain G2 = 1 + R6 / R5, wherein R5 and R6 are composed of arrays with different resistance values, and the logic controller controls the combination ratio of resistors R5 (A-C) and R6 (A-C) to form different gains, and the input (digital) signal of the logic controller is controlled by the peripheral control signal.

[0079] From this we can see that the total circuit gain of the entire instrumentation amplifier is G=G1*G2.

[0080] See also Figure 7 , Figure 7 FIG. 1 is a circuit diagram of a logic controller according to an embodiment of the present application. Figure 7 In the embodiment, the logic controller includes a first output terminal, a second output terminal, and a third output terminal, each of which outputs a control signal; the logic controller includes: an eighteenth transistor Q18 to a thirty-first transistor Q31, a sixteenth resistor R16 to a nineteenth resistor R19;

[0081] The base of the eighteenth transistor Q18 is connected to the third input signal via the tenth resistor R10, the base of the nineteenth transistor Q19 is connected to the base of the twentieth transistor Q20 and forms a fourth connection node, the base of the twenty-first transistor Q21 is connected to the fourth input signal via the seventeenth resistor R17; the collector of the eighteenth transistor Q18, the collector of the nineteenth transistor Q19, the collector of the twentieth transistor Q20, and the collector of the twenty-first transistor Q21 are respectively connected to the sixth voltage; the emitter of the eighteenth transistor Q18 is connected to the emitter of the nineteenth transistor Q19 and then to the collector of the twenty-second transistor Q22, and the fourth connection node is connected to the collector of the twenty-third transistor Q23, The emitter of the twentieth transistor Q20 is connected to the emitter of the twenty-first transistor Q21 and then to the collector of the twenty-fourth transistor Q24; the base of the twenty-second transistor Q22, the base of the twenty-third transistor Q23, and the base of the twenty-fourth transistor Q24 are connected to the first bias voltage, and the emitter of the twenty-second transistor Q22, the emitter of the twenty-third transistor Q23, and the emitter of the twenty-fourth transistor Q24 are connected and then connected to the fifth voltage through the eighteenth resistor R18; the base of the thirty-third transistor Q33 and the base of the thirty-second transistor Q32 are respectively connected to the second bias voltage, and the emitter of the thirty-third transistor Q33 and the emitter of the thirty-second transistor Q32 are respectively connected to the sixth voltage. The collector of the thirty-third transistor Q33 is connected to the emitter of the twenty-fifth transistor Q25 and the emitter of the twenty-seventh transistor Q27 respectively, the base of the twenty-sixth transistor Q26 is connected to the collector of the twenty-fourth transistor Q24, and the collector of the twenty-sixth transistor Q26 is connected to the collector of the twenty-fifth transistor Q25 as the first output terminal; the emitter of the twenty-seventh transistor Q27 serves as the second output terminal, the base of the twenty-fifth transistor Q25 is connected to the collector of the twenty-second transistor Q22, the collector of the thirty-second transistor Q32 is connected to the emitter of the twenty-sixth transistor Q26 and the emitter of the twenty-eighth transistor Q28 respectively, and the emitter of the twenty-eighth transistor Q28 is connected to the base of the twenty-fifth transistor Q25. The base of the transistor Q28 is connected to the base of the twenty-seventh transistor Q27, the collector of the twenty-eighth transistor Q28 serves as the third output end, the collector of the twenty-third transistor Q23 is respectively connected to the base of the twenty-eighth transistor Q28 and one end of the nineteenth resistor R19, the other end of the nineteenth resistor R19 is respectively connected to the base and collector of the twenty-ninth transistor Q29, the emitter of the twenty-ninth transistor Q29 is respectively connected to the collector and base of the thirtieth transistor Q30, the emitter of the thirtieth transistor Q30 is connected to the emitter of the thirty-first transistor Q31, the collector of the thirty-first transistor Q31 is connected to the sixth voltage, and the base of the thirty-first transistor Q31 is grounded.

[0082] The logic controller is a digital gate circuit that converts the two input terminals S0 and S1 into three gain selection branches OUT1, OUT2, and OUT3. The input / output and gain relationship is as follows:

[0083] If S1 is 1 (high level) and S0 is 0 (low level), X1 is turned on, while X2 and X3 are turned off, and the gain G = 1 + R6A / R5A;

[0084] If S1 is 0 (low level) and S0 is 1 (high level), X2 is turned on, while X1 and X3 are turned off, and the gain G = 1 + R6B / R5B;

[0085] If S1 is 0 (low level) and S0 is 0 (low level), X3 is turned on, while X1 and X2 are turned off, and the gain G = 1 + R6C / R5C;

[0086] If S1 and S0 are both 1 (high level), X1 and X2 are turned on, X3 is turned off, and the gain is invalid. The gain multiple is selected according to the logic combination. The gain multiple can be selected as 1, 10 or 100 times, but the gain multiple is not limited to 10 or 100 times. The internal gain resistor can be adjusted to complete the gain design adjustment of 1-1000. Three gain multiple digital programming options are available.

[0087] See also Figure 8 , Figure 8 1 is a diagram showing the simulation results of an instrument amplifier according to an embodiment of the present application. Figure 8 As shown, the input signal Vin=100mV, the gain control terminal S0 adds a square wave signal with a period of 400us and an amplitude of 5V, and there is no delay; the gain control terminal S1 adds a square wave signal with a period of 400us and an amplitude of 5V, and the delay time is 100us.

[0088] The simulation results show that S1 is 0 (high level), S0 is 0 (low level), and the gain is 1 times;

[0089] The simulation results show that S1 is 1 (high level), S0 is 0 (low level), and the gain is 10 times;

[0090] The simulation results show that S1 is 0 (high level), S0 is 1 (low level), and the gain is 100 times;

[0091] The simulation results show that S1 is 1 (high level), S0 is 1 (low level), the gain is invalid, and the output is random.

[0092] In one embodiment, the first bias voltage and the second bias voltage are output through a bias circuit. Fig. 9 , Fig. 9 FIG. 1 is a circuit diagram of a bias voltage according to an embodiment of the present application. Fig. 9In the embodiment, the bias circuit includes: a first MOS tube, a second MOS tube, a twentieth resistor R20 to a twenty-third resistor R23, and a thirty-second transistor Q32 to a thirty-eighth transistor Q38;

[0093] The base of the thirty-second transistor Q32 is connected to the base of the thirty-third transistor Q33, the collector of the thirty-second transistor Q32 is connected to the base, the emitter of the thirty-second transistor Q32 is connected to the collector of the thirty-fourth transistor Q34 and the base of the thirty-fifth transistor Q35 respectively, the emitter of the thirty-fourth transistor Q34 is connected to the seventh voltage, the emitter of the thirty-third transistor Q33 is connected to the base of the thirty-fourth transistor Q34 and the collector of the thirty-fifth transistor Q35 respectively, the emitter of the thirty-fifth transistor Q35 is connected to the seventh voltage via the twentieth resistor R20, the collector of the thirty-second transistor Q32 is connected to the source of the second MOS tube, the drain of the second MOS tube is connected to the source of the first MOS tube, the drain of the first MOS tube is connected to the eighth voltage. voltage, the gate of the first MOS tube and the gate of the second MOS tube are respectively connected to the ninth voltage; the collector of the thirty-third transistor Q33 is respectively connected to the base and the collector of the thirty-sixth transistor Q36, the emitter of the thirty-sixth transistor Q36 is connected to the eighth voltage via the twenty-first resistor R21, the base of the thirty-sixth transistor Q36 is connected to the base of the thirty-seventh transistor Q37 and then outputs the first bias voltage, the emitter of the thirty-seventh transistor Q37 is connected to the eighth voltage via the twenty-second resistor R22, the collector of the thirty-seventh transistor Q37 is connected to the collector of the thirty-eighth transistor Q38, the emitter of the thirty-eighth transistor Q38 is connected to the seventh voltage via the twenty-third resistor R23; the base and collector of the thirty-eighth transistor Q38 are connected to output the second bias voltage.

[0094] The bias circuit provides a common constant voltage and current bias that does not change with temperature and voltage for the input stage, intermediate stage, and output stage of A1 to A3, so as to ensure the stability of the circuit's DC parameters.

[0095] It should be noted that, in this embodiment, the first voltage to the ninth voltage can be the same voltage or different voltages. For example, some of the voltages are VCC and others are GND. The amplitude and phase of the voltage can be set according to actual needs and are not limited in this embodiment.

[0096] In summary, the present invention provides a digital programmable gain integrated instrument amplifier, an emitter follower, connected to an input signal, for amplifying the input signal; a differential amplifier, whose input terminal is connected to the output terminal of the emitter follower, for amplifying the output signal of the emitter follower; a proportional amplifier, wherein one input terminal is connected to the output terminal of the differential amplifier, and the other input terminal is connected to a resistor array, for amplifying the output signal of the differential amplifier in proportion; the resistor array includes a plurality of resistors, wherein a plurality of resistors in the plurality of resistors constitute one or more signal channels, and each of the signal channels corresponds to an amplification gain; a logic controller, outputting a control signal, for controlling one of the one or more signal channels to be turned on according to the amplification factor of the proportional amplifier. In the scheme of the present invention, low temperature coefficient resistors are internally integrated (integrated on the same circuit board) to solve the problem of mismatch of external gain resistors, and the gain of the instrument amplifier has a low temperature drift characteristic; at the same time, through the combination of the logic controller (programmable digital logic module) and the resistor array, the instrument amplifier can realize optional gain. Moreover, the instrument amplifier of the present application has a simple structure and a small package size, and can provide a digital programmable gain integrated instrument amplifier for analog IC devices.

[0097] The above embodiments are merely illustrative of the principles and effects of the present application, and are not intended to limit the present application. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present application shall still be covered by the claims of the present application.

Claims

1. A digital programmable gain integrated instrument amplifier, characterized in that: The instrumentation amplifier comprises: The emitter follower is connected to the input signal and is used to amplify the input signal; A differential amplifier, whose input end is connected to the output end of the emitter follower, and is used to amplify the output signal of the emitter follower; A proportional amplifier, wherein one input end is connected to the output end of the differential amplifier, and the other input end is connected to a resistor array, and is used to proportionally amplify the output signal of the differential amplifier; the resistor array includes a plurality of resistors, and a plurality of resistors in the plurality of resistors constitute one or more signal channels, and each of the signal channels corresponds to an amplification gain; A logic controller, outputting a control signal for controlling one of the one or more signal channels to be turned on according to the amplification factor of the proportional amplifier; The emitter follower comprises: A first operational amplifier, comprising a first positive input terminal and a first negative output terminal; A second operational amplifier comprises a second positive input terminal and a second negative output terminal; The first positive input terminal is connected to the negative signal / positive signal of the input signal, the first reverse input terminal is connected to the output terminal of the first operational amplifier, and the output terminal of the first operational amplifier is connected to one of the input terminals of the differential amplifier; the second positive input terminal is connected to the positive signal / negative signal of the input signal, the second reverse input terminal is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier is connected to the other input terminal of the differential amplifier.

2. The digital programmable gain integrated instrument amplifier according to claim 1, characterized in that: The first operational amplifier and the second operational amplifier have the same structure, and the first operational amplifier includes: a first transistor to a seventeenth transistor, a fifth resistor to a fifteenth resistor, a first capacitor, and a second capacitor; The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is connected to the first voltage via the fifth resistor and the sixth resistor connected in series, the emitter of the second transistor is connected to the first voltage via the seventh resistor and the eighth resistor connected in series, the source of the first transistor is connected to the base and the collector of the fourth transistor respectively, the emitter of the fourth transistor is connected to the emitter of the third transistor and forms a first connection node, the base of the fourth transistor is connected to the base of the fifth transistor and the collector of the fifth transistor respectively, the collector of the third transistor is connected to the collector of the first transistor and forms a second connection node; the base of the sixth transistor is connected to the input signal via the ninth resistor; the collector of the sixth transistor is connected to the first voltage, and the sixth transistor is connected to the base of the fifth transistor and the collector of the fifth transistor respectively. The emitter of the transistor is connected to the collector of the seventh transistor, the emitter of the seventh transistor is connected to the collector of the eighth transistor, the emitter of the eighth transistor is connected to the second voltage via the tenth resistor, and the collector of the seventh transistor is connected to the base; the base of the third transistor is connected to the emitter of the sixth transistor; the first connection node is connected to the collector of the ninth transistor, and the emitter of the ninth transistor is connected to the second voltage via the eleventh resistor; the emitter of the tenth transistor is connected to the second voltage via the twelfth resistor, the collector of the tenth transistor is connected to the collector of the fourteenth transistor and forms a third connection node, the collector of the fourteenth transistor is connected to the base of the fourteenth transistor via the fourteenth resistor and the first capacitor connected in series, and the emitter of the fourteenth transistor is connected to The first voltage is connected to the base of the fourteenth transistor, the base of the fourteenth transistor is connected to the second connection node; the emitter of the eleventh transistor is connected to the second voltage via the thirteenth resistor, the collector of the eleventh transistor is connected to the emitter of the twelfth transistor, and the collector of the twelfth transistor is connected to the third voltage; the base of the twelfth transistor is connected to the third connection node; the base of the eighth transistor, the base of the ninth transistor, the base of the tenth transistor, and the base of the eleventh transistor are respectively connected to the first bias voltage; the base of the fifteenth transistor is connected to the third connection node, the collector of the fifteenth transistor is connected to the first voltage, the emitter of the fifteenth transistor is respectively connected to the base of the sixteenth transistor and the collector of the seventeenth transistor, the emitter of the seventeenth transistor is connected to the second voltage via the fifteenth resistor, and the base of the eighth transistor, the base of the ninth transistor, the base of the tenth transistor, and the base of the eleventh transistor are respectively connected to the first bias voltage. The base of the seventeenth transistor is connected to the second bias voltage, the collector of the sixteenth transistor is connected to the first voltage, the emitter of the sixteenth transistor is connected to the emitter of the eighteenth transistor, the collector of the eighteenth transistor is connected to the second voltage, the base of the eighteenth transistor is connected to the emitter of the twelfth transistor, and a second capacitor is connected in parallel between the collector and the base of the eighteenth transistor; the emitter of the thirteenth transistor is connected to the third connection node; the collector of the thirteenth transistor is connected to the base and then connected to the emitter of the eighteenth transistor and the emitter of the sixteenth transistor respectively and serve as the output end of the first operational amplifier; the emitter of the fifth transistor is connected to the base of the sixth transistor, and the base of the fifth transistor is connected to the collector and then connected to the output end of the first operational amplifier.

3. The digital programmable gain integrated instrument amplifier according to claim 1, characterized in that: The differential amplifier comprises: a first resistor, a second resistor, a third resistor, and a fourth resistor; A third operational amplifier comprises a third positive input terminal and a third negative input terminal; The first resistor is connected between the output terminal of the first operational amplifier and the third reverse input terminal, the second resistor is connected between the output terminal of the second operational amplifier and the third positive input terminal, the third resistor is connected between the third reverse input terminal and the output terminal of the third operational amplifier, one end of the fourth resistor is connected to the third positive input terminal, the other end of the fourth resistor is externally connected to a fourth voltage, and the other end of the fourth resistor is connected to the resistor array.

4. The digital programmable gain integrated instrumentation amplifier according to claim 3, characterized in that: The third operational amplifier includes: a first transistor to a fourth transistor, a ninth transistor to a seventeenth transistor, a fifth resistor to an eighth resistor, an eleventh resistor to a fifteenth resistor, a first capacitor and a second capacitor; The base of the first transistor is connected to the base of the second transistor, the emitter of the first transistor is connected to the first voltage via the fifth resistor and the sixth resistor connected in series, the emitter of the second transistor is connected to the first voltage via the seventh resistor and the eighth resistor connected in series, the source of the first transistor is connected to the base and the collector of the fourth transistor respectively, the emitter of the fourth transistor is connected to the emitter of the third transistor and forms a first connection node, the base of the third transistor is connected to the first input signal, and the base of the fourth transistor is connected to the second input signal; the collector of the third transistor is connected to the collector of the first transistor and forms a second connection node; the first connection node is connected to the collector of the ninth transistor, and the emitter of the ninth transistor is connected to the second voltage via the eleventh resistor; the emitter of the tenth transistor is connected to the second voltage via the twelfth resistor, the collector of the tenth transistor is connected to the collector of the fourteenth transistor and forms a third connection node, the collector of the fourteenth transistor is connected to the base of the fourteenth transistor via the fourteenth resistor and the first capacitor connected in series, the emitter of the fourteenth transistor is connected to the second voltage, and the base of the fourteenth transistor is connected to the second connection node; the emitter of the eleventh transistor is connected to the second voltage via the thirteenth resistor The first transistor is connected to the second voltage, the collector of the eleventh transistor is connected to the emitter of the twelfth transistor, and the collector of the twelfth transistor is connected to the third voltage; the base of the twelfth transistor is connected to the third connection node; the bases of the ninth transistor, the tenth transistor, and the eleventh transistor are respectively connected to the first bias voltage; the base of the fifteenth transistor is connected to the third connection node, the collector of the fifteenth transistor is connected to the second voltage, the emitter of the fifteenth transistor is respectively connected to the base of the sixteenth transistor and the collector of the seventeenth transistor, and the emitter of the seventeenth transistor is connected to the first voltage via the fifteenth resistor, The base of the seventeenth transistor is connected to the second bias voltage, the collector of the sixteenth transistor is connected to the second voltage, the emitter of the sixteenth transistor is connected to the emitter of the eighteenth transistor, the collector of the eighteenth transistor is connected to the second voltage, the base of the eighteenth transistor is connected to the emitter of the twelfth transistor, and a second capacitor is connected in parallel between the collector and the base of the eighteenth transistor; the emitter of the thirteenth transistor is connected to the third connection node; the collector and base of the thirteenth transistor are connected and then connected to the emitter of the eighteenth transistor and the emitter of the sixteenth transistor respectively and serve as the output end of the third operational amplifier.

5. The digital programmable gain integrated instrumentation amplifier according to claim 1, characterized in that: The proportional amplifier comprises: a fourth operational amplifier, comprising a fourth positive input terminal and a fourth negative input terminal; A resistor array includes a logic control terminal, a first non-logic control terminal, and a second non-logic control terminal; The fourth positive input terminal is connected to the output terminal of the differential amplifier, the fourth negative input terminal is connected to the logic control terminal, the first non-logic control terminal is connected to the fourth voltage, and the second non-logic control terminal is connected to the output terminal of the fourth operational amplifier.

6. The digital programmable gain integrated instrumentation amplifier according to claim 1, characterized in that: The logic controller comprises a first output terminal, a second output terminal and a third output terminal, each of which outputs a control signal; the logic controller comprises: an eighteenth transistor to a thirty-first transistor and a sixteenth resistor to a nineteenth resistor; The base of the eighteenth transistor is connected to the third input signal via the tenth resistor, the base of the nineteenth transistor is connected to the base of the twentieth transistor and forms a fourth connection node, and the base of the twenty-first transistor is connected to the fourth input signal via the seventeenth resistor; the collector of the eighteenth transistor, the collector of the nineteenth transistor, the collector of the twentieth transistor, and the collector of the twenty-first transistor are respectively connected to the sixth voltage; the emitter of the eighteenth transistor is connected to the emitter of the nineteenth transistor and then connected to the collector of the twenty-second transistor, the fourth connection node is connected to the collector of the twenty-third transistor, the emitter of the twentieth transistor is connected to the emitter of the twenty-first transistor and then connected to the collector of the twenty-fourth transistor; the base of the twenty-second transistor, the base of the twenty-third transistor, and the base of the twenty-fourth transistor are connected to the first bias voltage, and the emitter of the twenty-second transistor, the emitter of the twenty-third transistor, and the emitter of the twenty-fourth transistor are connected and then connected to the fifth voltage via the eighteenth resistor; the base of the thirty-third transistor and the base of the thirty-second transistor are respectively connected to the second bias voltage, and the emitter of the thirty-third transistor and the emitter of the thirty-second transistor are respectively connected to the sixth voltage, The collector of the thirty-third transistor is respectively connected to the emitter of the twenty-fifth transistor and the emitter of the twenty-seventh transistor, the base of the twenty-sixth transistor is connected to the collector of the twenty-fourth transistor, and the collector of the twenty-sixth transistor is connected to the collector of the twenty-fifth transistor as the first output terminal; the emitter of the twenty-seventh transistor serves as the second output terminal, the base of the twenty-fifth transistor is connected to the collector of the twenty-second transistor, the collector of the thirty-second transistor is respectively connected to the emitter of the twenty-sixth transistor and the emitter of the twenty-eighth transistor, the base of the twenty-eighth transistor is connected to the base of the twenty-seventh transistor, and the collector of the twenty-eighth transistor serves as the third output terminal, the collector of the twenty-third transistor is respectively connected to the base of the twenty-eighth transistor and one end of the nineteenth resistor, the other end of the nineteenth resistor is respectively connected to the base and collector of the twenty-ninth transistor, the emitter of the twenty-ninth transistor is respectively connected to the collector and base of the thirtieth transistor, the emitter of the thirtieth transistor is connected to the emitter of the thirty-first transistor, the collector of the thirty-first transistor is connected to the sixth voltage, and the base of the thirty-first transistor is grounded.

7. The digital programmable gain integrated instrumentation amplifier according to claim 2, 4 or 6, characterized in that: The first bias voltage and the second bias voltage are output through a bias circuit, wherein the bias circuit includes: a first MOS transistor, a second MOS transistor, twentieth to twenty-third resistors, and thirty-second to thirty-eighth transistors; The base of the thirty-second transistor is connected to the base of the thirty-third transistor, the collector of the thirty-second transistor is connected to the base, the emitter of the thirty-second transistor is connected to the collector of the thirty-fourth transistor and the base of the thirty-fifth transistor respectively, the emitter of the thirty-fourth transistor is connected to the seventh voltage, the emitter of the thirty-third transistor is connected to the base of the thirty-fourth transistor and the collector of the thirty-fifth transistor respectively, the emitter of the thirty-fifth transistor is connected to the seventh voltage via the twentieth resistor, the collector of the thirty-second transistor is connected to the source of the second MOS tube, the drain of the second MOS tube is connected to the source of the first MOS tube, the drain of the first MOS tube is connected to the eighth voltage. voltage, the gate of the first MOS tube and the gate of the second MOS tube are respectively connected to the ninth voltage; the collector of the thirty-third transistor is respectively connected to the base and the collector of the thirty-sixth transistor, the emitter of the thirty-sixth transistor is connected to the eighth voltage via the twenty-first resistor, the base of the thirty-sixth transistor is connected to the base of the thirty-seventh transistor and then outputs the first bias voltage, the emitter of the thirty-seventh transistor is connected to the eighth voltage via the twenty-second resistor, the collector of the thirty-seventh transistor is connected to the collector of the thirty-eighth transistor, and the emitter of the thirty-eighth transistor is connected to the seventh voltage via the twenty-third resistor; the base of the thirty-eighth transistor is connected to the collector and then outputs the second bias voltage.

8. The digital programmable gain integrated instrument amplifier according to claim 1, characterized in that: The resistors in the resistor array are metal film resistors with low temperature coefficients.

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