A time gain compensation circuit based on subthreshold region current source

Abstract

The application belongs to the technical field of analog integrated circuits, and particularly relates to a time gain compensation circuit based on a sub-threshold region current source. The application utilizes a VTC structure to convert a sampling differential voltage into two different time level signals Tn and Tp through constant gain; then the application utilizes a TVC structure to control the charging and discharging time of the sub-threshold region current source by using the phase difference of the two time level signals, realizes the conversion from time to voltage, the gain thereof changes exponentially with the gate-source voltage of the current source, and finally realizes the exponential gain compensation of the voltage signal. In the conversion process of gain compensation by utilizing voltage-time and time-voltage twice conversion, the conversion linearity is not affected by the input amplitude, the input swing is large, and the TGC circuit area can be reduced without complex analog circuit structure, the integration of the ultrasonic analog front-end circuit is improved, and thus the size of the ultrasonic imaging probe is reduced.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit technology, specifically relating to a time gain compensation circuit based on a subthreshold current source, which combines low complexity, high integration and high linearity. Background Technology

[0002] Time gain compensation (TGC) is a method used in the analog front-end circuit of ultrasound imaging to compensate for the exponential weakening of the signal caused by the propagation attenuation of ultrasonic energy. Since the propagation attenuation of the ultrasonic signal is exponentially related to time, the amplitude of the echo signal can be compensated by providing a gain that increases exponentially with time, resulting in echo signals with equal amplitude at different propagation distances. The reduced dynamic range of the signal after TGC compensation simplifies the design of subsequent ADC stages and improves the accuracy of ultrasound imaging.

[0003] Existing time-gain compensation circuits can be broadly categorized into discrete gain compensation and continuous gain compensation. Discrete gain compensation utilizes digital switches to control the gain step, typically employing a two-stage compensation method: coarse compensation with an LNA (Low Noise Amplifier) ​​followed by fine compensation with a PGA (Programmable Gain Amplifier). A problem with discrete gain compensation is that instantaneous gain switching can cause signal interruptions and interference, resulting in image artifacts. Reducing these artifacts requires increasing the discrete gain order, but this necessitates a significant increase in chip area. Continuous gain compensation utilizes amplifiers whose gain is exponentially related to the input. This is susceptible to PVT (process angle, voltage, temperature variations), and the amplifier and control voltage generation circuits are complex to design and occupy a large area. Furthermore, the input swing of existing TGC circuits is limited by the op-amp input swing, and their linearity also varies with the input swing.

[0004] In summary, existing time gain compensation circuits suffer from problems such as large area, complex design, and limited input swing. Summary of the Invention

[0005] To address the aforementioned problems or shortcomings, this invention provides a time gain compensation circuit based on a subthreshold current source to solve the problems of large area, complex design, and limited input swing in existing TGC circuits.

[0006] A time gain compensation circuit based on a subthreshold current source (as shown in the attached diagram) Figure 1 As shown, it consists of a VTC (voltage-to-time converter) module 100 and a TVC (time-to-voltage converter) module 101: specifically including a constant current source I with equal current value. D1 I D2 Dynamic comparator C OMP1 C OMP2 Phase detector PD, four subthreshold current sources I with equal current valuesd1 , I d2 , I d3 , I d4 and capacitor C s1 , C s2 , C cp1 , C cp2 .

[0007] The VTC module comprises: a dynamic comparator C OMP1 , C OMP2 , a conventional constant current source I D1 , I D2 and a capacitor C s1 , C s2 . The positive input terminal of the dynamic comparator C OMP1 and C OMP2 is connected to V CM (the flip level of the dynamic comparator), the negative input terminal of the dynamic comparator C OMP1 is connected to the differential ultrasonic signal V inn , C s1 and I D1 , the negative input terminal of the dynamic comparator C OMP2 is connected to the differential ultrasonic signal V inp , C s2 and I D2 , the switch S1 is located between the upper plate of C S1 and the negative input terminal of the dynamic comparator C OMP1 , the switch S2 is located between the constant current source I D1 and the negative input terminal of the dynamic comparator C OMP1 , the switch S3 is located between the upper plate of C S2 and the negative input terminal of the dynamic comparator C OMP2 , the switch S4 is located between the constant current source I D2 and the negative input terminal of the dynamic comparator C OMP2 ; the output terminal of the dynamic comparator C OMP1 outputs a signal Tn, the output terminal of the dynamic comparator C OMP2 outputs a signal Tp, and the output signals Tn and Tp are respectively connected to the two input terminals of the phase detector PD.

[0008] The TVC module comprises: a phase detector PD, four sub-threshold region current sources I d1 , I d2 , I d3 , I d4 and capacitors C cp1 , C cp2 . The output terminal UP signal of the phase detector PD is connected to the control terminal of the switch S5 and S8, the output terminal DN signal of the phase detector PD is connected to the control terminal of the switch S6 and S7, the switch S5 is located between the sub-threshold region current source I d1 and the output signal Voutn between the output signal V d2 and the output signal V outp between the output signal V d3 and the output signal V outn between the output signal V d4 and the output signal V outp ; the upper plate of the capacitor C CP1 is connected to the output signal V outn , and the lower plate is connected to ground; the upper plate of the capacitor C CP2 is connected to the output signal V outp , and the lower plate is connected to ground.

[0009] The specific working process of the time gain compensation circuit based on the sub-threshold region current source is as follows:

[0010] The sampled ultrasonic input signal V inn is stored on the upper plate of the capacitor C S1 , and the sampled ultrasonic input signal V inp is stored on the upper plate of the capacitor C S2 ; after the S1, S2, S3, and S4 switches are simultaneously turned on, the constant current source I D1 charges the capacitor C S1 linearly, and the constant current source I D2 charges the capacitor C S2 linearly, until the negative input terminals of the two dynamic comparators C OMP1 and C OMP2 are charged to the same flip level V CM , after which the two dynamic comparators C OMP1 and C OMP2 output signals Tn and Tp, respectively, and Tn and Tp flip from a low level to a high level. The phase detector PD outputs two control signals UP and DN according to the phase difference of the rising edges of the two signals Tn and Tp, and the UP signal controls the opening and closing of the switches S5 and S8, and the DN signal controls the opening and closing of the switches S6 and S7.

[0011] When the phase difference between Tp and Tn is positive, the UP signal is high, the switches S5 and S8 are turned on, the sub-threshold region current source I d1 charges the capacitor C cp1 , and the sub-threshold region current source I d4 discharges the capacitor C cp2 ; when the phase difference between Tp and Tn is negative, the DN signal is high, the switches S6 and S7 are turned on, the sub-threshold region current source I d2 charges the capacitor C cp2 , and the sub-threshold region current source I d3 discharges the capacitor C cp1Discharge begins. Charging and discharging ends when both UP and DN signals are low, and the data is stored in C. cp1 and C cp2 Differential voltage V on outn V outp As the output of the entire time gain compensation circuit.

[0012] The principle of this invention is as follows: Using a VTC structure composed of a constant current source charging circuit and a dynamic comparator circuit, the sampled differential voltage is converted into two different time-level signals Tn and Tp through a constant gain. The constant gain expression of VTC is: (where ΔT is the time difference between Tn and Tp, and ΔV) in_VTC The input differential signal V of VTC inn and V inp The voltage difference). Then, through a TVC structure composed of a phase detector, a subthreshold current source, and a capacitor, the charging and discharging time of the subthreshold current source is controlled by the phase difference of the two time-level signals, realizing the conversion from time to voltage. Its gain changes exponentially with the gate-source voltage of the current source, and the gain expression is: (ΔV out_TVC The output signal V of TVC outn V outp The voltage difference, ΔT is the time delay difference between Tn and Tp, I d For the exponential form of the current from the subthreshold current source, C cp For capacitor C cp1 Capacitor C cp2 The capacitance value, and C cp1 =C cp2 ),in (I0 is I) d The initial value of the current, α is a constant compensation coefficient, V GS (This represents the gate-source voltage of the subthreshold MOSFET). Through the above structure, exponential gain compensation of the voltage signal is ultimately achieved, with the compensation gain being: (V out It is the output of the overall circuit, i.e., signal V. outn V outp The voltage difference, V in It is the input of the overall circuit, i.e., the differential signal V. inn and V inp (voltage difference), substituted into V in =V0e -at (V0 is the initial value of the input signal, and a is the constant attenuation coefficient of the input signal.) get Control V GS =at / α can compensate for an exponentially decaying input signal to a constant output signal.

[0013] In summary, the present application adopts the gain compensation by twice conversion of voltage-time and time-voltage, in the conversion process, the conversion linearity is not affected by the input amplitude, the input swing is large, and the TGC circuit area can be reduced without complex analog circuit structure, the integration of the ultrasonic analog front-end circuit is improved, thereby the size of the ultrasonic imaging probe is reduced. The present application effectively solves the problems of large area, complex design and limited input swing of the existing TGC circuit. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 Circuit diagram of the present application

[0015] Figure 2 Waveform diagram of each signal in the embodiment. DETAILED DESCRIPTION

[0016] The present application will be further described in detail below in combination with the drawings and embodiments, taking the application of the TGC method in electrocardio-ultrasound as an example.

[0017] A time gain compensation circuit based on sub-threshold region current source, comprising: a constant current source I D1 , I D2 , a dynamic comparator C OMP1 , C OMP2 , a phase detector PD, four sub-threshold region current sources I d1 , I d2 , I d3 , I d4 and capacitors C s1 , C s2 , C cp1 , C cp2 .

[0018] When the ultrasonic wave propagates in the medium, it will be absorbed by different degrees by each tissue and organ of the human body, resulting in amplitude drop. Due to the existence of propagation attenuation, the echo signal from the deep tissue propagates for a longer time and has a smaller amplitude. Overall, the echo signal presents an exponential relationship of amplitude with time: V t = V0e -at (V0 is the initial voltage of the input signal), taking the acoustic wave signal with a center frequency of 5MHz as an example, a is about 2ln10*10 4 , then

[0019] According to the principle of the present application, V GS = at / α needs to be controlled to meet the compensation requirements, where α is the sub-threshold region transfer characteristic slope of the MOS tube: α = d(lnI Dsub ) / dV GS , which is about 28 (dec / V), then VGS ≈1.64*10 3 t(V).

[0020] Let I D1 =I D2 =25uA, C s1 =C s2 =800fF, dynamic comparator C OMP1 C OMP2 positive input terminal V CM The voltage is 300mV. The VTC module processes the signal as follows (see attached). Figure 2 As shown): The sampled differential input signal V inn V inp Through constant current source I D1 I D2 Charge until the dynamic comparator reaches its reference level V. CM Then, the output signals Tp and Tn of the dynamic comparator flip from low to high, and its gain is...

[0021] Let C cp1 =C cp2 =0.8pF, V GS ≈1.64*10 3 t(V), I0 = 2.5nA, because Therefore The TVC module processes signals as follows (see attached). Figure 2 As shown): The output signals Tp and Tn of the VTC module are sent to the phase detector. When the edge of the Tp signal is earlier than that of the Tn signal, the UP signal flips first. When the edge of the Tp signal arrives, the DN signal flips. The combinational logic makes the reset signal valid, and the UP and DN signals become 0. When the edge of the Tn signal is earlier than that of the Tp signal, the DN signal flips first. When the edge of the Tp signal arrives, the UP signal flips. Then the two signals are reset.

[0022] The UP and DN signals control the subthreshold current source I. d1 I d2 I d3 I d4 When the UP signal is high, I is enabled. d1 Current source to C cp1 Charging, I d4 Current source to C cp2 Discharge; when the DN signal is high, I d2 Current source to C cp2 Charging, I d3 Current source to C cp1 Discharge generates an output differential voltage. During this process, the time-voltage gain is...

[0023] After the signal passes through the VTC and the TVC, the voltage amplitude generated is:

[0024]

[0025] As shown in the above examples, the ultrasonic signal exponentially attenuated with time is compensated to an equal-amplitude signal by the method of twice conversion of voltage-time and time-voltage, and the circuit structure required for realizing the method is simple and the linearity is not affected by the input swing.

Claims

1. A time gain compensation circuit based on sub-threshold region current source, characterized in that: consisting of a voltage-to-time converter VTC module and a time-to-voltage converter TVC module, in particular comprising a constant current source I D1 , D2 a dynamic comparator C OMP1 , OMP2 a phase detector PD, four sub-threshold region constant current sources I d1 , d2 , d3 , d4 and a capacitor C s1 , s2 , cp1 , cp2 ; The voltage time converter VTC module comprises a dynamic comparator C OMP1 , OMP2 , a constant current source I D1 , D2 , and a capacitor C s1 , s2 ; the positive input terminal of the dynamic comparator C OMP1 and C OMP2 is connected to V CM , the negative input terminal of the dynamic comparator C OMP1 is connected to the differential ultrasonic signal V inn , C s1 and I D1 , the negative input terminal of the dynamic comparator C OMP2 is connected to the differential ultrasonic signal V inp , C s2 and I D2 , the switch S1 is located between the upper plate of C S1 and the negative input terminal of the dynamic comparator C OMP1 , the switch S2 is located between the constant current source I D1 and the negative input terminal of the dynamic comparator C OMP1 , the switch S3 is located between the upper plate of C S2 and the negative input terminal of the dynamic comparator C OMP2 , the switch S4 is located between the constant current source I D2 and the negative input terminal of the dynamic comparator C OMP2 ; the output terminal of the dynamic comparator C OMP1 outputs a signal Tn, the output terminal of the dynamic comparator C OMP2 outputs a signal Tp, and the output signals Tn and Tp are respectively connected to the two input terminals of the phase detector PD. The time-voltage converter TVC module comprises a phase detector PD, four sub-threshold region current sources I d1 , d2 , d3 , d4 and a capacitor C cp1 , C cp2 ; the output UP of the phase detector PD is connected to the control end of switches S5 and S8, the output DN of the phase detector PD is connected to the control end of switches S6 and S7, the switch S5 is located between the sub-threshold region current source I d1 and the output signal V outn , the switch S6 is located between the sub-threshold region current source I d2 and the output signal V outp , the switch S7 is located between the sub-threshold region current source I d3 and the output signal V outn , the switch S8 is located between the sub-threshold region current source I d4 and the output signal V outp ; the upper plate of the capacitor C CP1 is connected to the output signal V outn , and the lower plate is connected to the ground; the upper plate of the capacitor C CP2 is connected to the output signal V outp , and the lower plate is connected to the ground.

2. The time gain compensation circuit based on sub-threshold region current source as claimed in claim 1 wherein, The specific working process is: sampled ultrasonic input signal V inn stored in C S1 the upper plate of the capacitor, the sampled ultrasonic input signal V inp stored in C S2 the upper plate of the capacitor, S1, S2, S3, S4 switches are turned on at the same time through the constant current source I D1 to C S1 linear charging of the capacitor, I D2 to C S2 linear charging of the capacitor, until the dynamic comparator C OMP1 , C OMP2 the negative input end of the dynamic comparator is charged to the same flip level V CM , the two dynamic comparators C OMP1 , C OMP2 output signals Tn, Tp respectively, Tn, Tp flip from low to high level; the phase detector PD outputs two control signals UP, DN according to the phase difference of the rising edge of the two signals Tn, Tp, the UP signal controls the opening and closing of the switches S5 and S8, and the DN signal controls the opening and closing of the switches S6 and S7; When the phase difference of Tp, Tn is positive, UP signal is high, switches S5 and S8 are on, sub-threshold region current source I d1 charges C cp1 , sub-threshold region current source I d4 discharges C cp2 ; when the phase difference of Tp, Tn is negative, DN signal is high, switches S6 and S7 are on, sub-threshold region current source I d2 charges C cp2 , sub-threshold region current source I d3 discharges C cp1 ; when UP and DN signals are both low, the charging and discharging ends, the differential voltage V cp1 , V cp2 stored on C outn and C outp is the output of the whole time gain compensation circuit.

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