Circuit detection method, device, electronic device and computer-readable storage medium

Abstract

A circuit detection method, circuit detection device, electronic device, and computer-readable storage medium. The circuit detection method comprises: obtaining a design file to be detected, the design file including information about multiple circuit components; identifying, based on the information about the multiple circuit components, at least one initial detection circuit from the design file that meets the structural characteristics of a cross-reset domain circuit; and outputting the initial detection circuit that does not meet constraint conditions as a target detection circuit, wherein the constraint conditions include at least one of reset signal sequence constraints, timing constraints, and component type constraints. This method can reuse the processes used in traditional chip design, avoiding the need to maintain multiple sets of constraint files, filtering out reasonable cross-reset domain structures, and improving designer inspection efficiency.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a circuit detection method, apparatus, electronic device, and computer-readable storage medium. Background Art

[0002] In today's VLSI designs, hundreds of reset signals may exist within a single chip, driven by functionality and power consumption requirements. These signals may originate from external pins, on-chip power-on resets, or software configurations. Each reset signal has a different scope of operation. The group of triggers it affects is called a reset domain. Different reset domains inevitably interact with each other, and the logic that allows signals to cross from one reset domain to another is called reset domain crossing (RDC). Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a circuit detection method, comprising: obtaining a design file to be detected, wherein the design file includes information of multiple circuit elements; based on the information of the multiple circuit elements, identifying at least one initial detection circuit from the design file that meets the structural characteristics of a cross-reset domain circuit; and outputting an initial detection circuit that does not meet a constraint condition among the at least one initial detection circuit as a target detection circuit, wherein the constraint condition includes at least one of a sequence constraint condition, a timing constraint condition, and an element type constraint condition of a reset signal.

[0004] For example, in the circuit detection method provided by at least one example of the above embodiments of the present disclosure, the multiple circuit elements include multiple registers, and the design file includes pin information and connection relationship information of the multiple registers.

[0005] For example, in the circuit detection method provided in at least one example of the above-mentioned embodiments of the present disclosure, the cross-reset domain circuit includes a first circuit element and a second circuit element, and the output of the first circuit element is connected to the input of the second circuit element; the structural features of the cross-reset domain circuit include that the first circuit element includes a first asynchronous reset terminal, and the second circuit element does not include an asynchronous reset terminal or includes a second asynchronous reset terminal, wherein the reset signal received by the second asynchronous reset terminal is different from the reset signal received by the first asynchronous reset terminal.

[0006] For example, in the circuit detection method provided in at least one example of the above-mentioned embodiments of the present disclosure, based on the information of the multiple circuit elements, at least one initial detection circuit that meets the structural characteristics of the cross-reset domain circuit is identified from the design file, including: based on the information of the multiple circuit elements, a first list is obtained, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element; each circuit element with an asynchronous reset terminal is used as the first circuit element, and the following operations are performed for each first circuit element: at least one second circuit element corresponding to the first circuit element is determined from the multiple circuit elements; based on the first list, whether the first circuit element and each of the second circuit elements meet the structural characteristics of the cross-reset domain circuit.

[0007] For example, in the circuit detection method provided in at least one example of the above-mentioned embodiments of the present disclosure, based on the information of the multiple circuit elements, at least one initial detection circuit that meets the structural characteristics of the cross-reset domain circuit is identified from the design file, including: based on the information of the multiple circuit elements, a first list is obtained, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element; each of the circuit elements is used as the second circuit element, and the following operations are performed for each of the second circuit elements: determining at least one first circuit element corresponding to the second circuit element from the multiple circuit elements; based on the first list, determining whether the second circuit element and each of the first circuit elements meet the structural characteristics of the cross-reset domain circuit.

[0008] For example, in the circuit detection method provided in at least one example of the above-mentioned embodiments of the present disclosure, the initial detection circuit that does not meet the constraint conditions in the at least one initial detection circuit is output as the target detection circuit, including: filtering out the first part of the initial detection circuits that meet the sequence constraint conditions or the element type constraint conditions from the at least one initial detection circuit to obtain the remaining second part of the initial detection circuits; determining a third part of the initial detection circuits from the second part of the initial detection circuits, wherein, for each initial detection circuit in the third part of the initial detection circuits, the reset signal of the asynchronous reset end of the first circuit element is synchronized with the clock signal of the first circuit element and the clock signal of the first circuit element is synchronized with the clock signal of the second circuit element; for each initial detection circuit in the third part of the initial detection circuits, determining whether the initial detection circuit meets the timing constraint conditions; taking the initial detection circuit that does not meet the timing constraint conditions in the third part of the initial detection circuits as the target detection circuit, and taking the other initial detection circuits in the second part of the initial detection circuits except the third part of the initial detection circuits as the target detection circuits.

[0009] For example, in the circuit detection method provided by at least one example of the above-mentioned embodiments of the present disclosure, the sequence constraint condition includes that the reset signal received by the asynchronous reset end of the first circuit element is later than the reset signal received by the asynchronous reset end of the second circuit element; the timing constraint condition includes a setup time condition and a hold time condition; the element type constraint condition includes that the second circuit element is an element set to solve the cross-reset domain problem.

[0010] At least one embodiment of the present disclosure provides a circuit detection device, including an acquisition module, a first detection module, and a second detection module, wherein the acquisition module is configured to acquire a design file to be detected, wherein the design file includes information of multiple circuit elements; the first detection module is configured to identify, based on the information of the multiple circuit elements, at least one initial detection circuit that meets the structural characteristics of a cross-reset domain circuit from the design file; and the second detection module is configured to output an initial detection circuit that does not meet a constraint condition among the at least one initial detection circuit as a target detection circuit, wherein the constraint condition includes at least one of a sequence constraint condition, a timing constraint condition, and an element type constraint condition of a reset signal.

[0011] For example, in the circuit detection device provided by at least one example of the above embodiments of the present disclosure, the multiple circuit elements include multiple registers, and the design file includes pin information and connection relationship information of the multiple registers.

[0012] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the cross-reset domain circuit includes a first circuit element and a second circuit element, and the output of the first circuit element is connected to the input of the second circuit element; the structural features of the cross-reset domain circuit include that the first circuit element includes a first asynchronous reset terminal, and the second circuit element does not include an asynchronous reset terminal or includes a second asynchronous reset terminal, wherein the reset signal received by the second asynchronous reset terminal is different from the reset signal received by the first asynchronous reset terminal.

[0013] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the first detection module is configured to: obtain a first list based on the information of the multiple circuit elements, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element; take each circuit element with an asynchronous reset terminal as the first circuit element, and perform the following operations for each first circuit element: determine at least one second circuit element corresponding to the first circuit element from the multiple circuit elements; based on the first list, determine whether the first circuit element and each of the second circuit elements meet the structural characteristics of the cross-reset domain circuit.

[0014] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the first detection module is configured to: obtain a first list based on the information of the multiple circuit elements, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element; take each of the circuit elements as the second circuit element, and perform the following operations for each of the second circuit elements: determine at least one first circuit element corresponding to the second circuit element from the multiple circuit elements; based on the first list, determine whether the second circuit element and each of the first circuit elements meet the structural characteristics of the cross-reset domain circuit.

[0015] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the second detection module is configured to: filter out the first part of the initial detection circuits that meet the sequence constraint condition or the element type constraint condition from the at least one initial detection circuit to obtain the remaining second part of the initial detection circuit; determine the third part of the initial detection circuit from the second part of the initial detection circuit, wherein, for each initial detection circuit in the third part of the initial detection circuit, the reset signal of the asynchronous reset end of the first circuit element is synchronized with the clock signal of the first circuit element and the clock signal of the first circuit element is synchronized with the clock signal of the second circuit element; for each initial detection circuit in the third part of the initial detection circuit, determine whether the initial detection circuit meets the timing constraint condition; use the initial detection circuit in the third part of the initial detection circuit that does not meet the timing constraint condition as the target detection circuit, and use the other initial detection circuits in the second part of the initial detection circuit except the third part of the initial detection circuit as the target detection circuit.

[0016] At least one embodiment of the present disclosure provides an electronic device, comprising a processor; a memory storing one or more computer program modules; wherein the one or more computer program modules are configured to be executed by the processor to implement the circuit detection method provided in any embodiment of the present disclosure.

[0017] At least one embodiment of the present disclosure provides a computer-readable storage medium storing non-transitory computer-readable instructions. When the non-transitory computer-readable instructions are executed by a computer, the circuit detection method provided by any embodiment of the present disclosure can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0019] Figure 1 A schematic diagram of a cross-reset domain circuit is shown;

[0020] Figure 2 A flow chart of a circuit detection method provided by at least one embodiment of the present disclosure is shown;

[0021] Figure 3 A flowchart of identifying an initial detection circuit provided by at least one embodiment of the present disclosure is shown;

[0022] Figure 4 A flowchart of another circuit for identifying an initial detection provided by at least one embodiment of the present disclosure is shown;

[0023] Figure 5 A flow chart of determining a target detection circuit provided by at least one embodiment of the present disclosure is shown;

[0024] Figure 6 A schematic block diagram of a circuit detection device provided by at least one embodiment of the present disclosure is shown;

[0025] Figure 7 A schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure is shown;

[0026] Figure 8 A schematic block diagram showing another electronic device provided by at least one embodiment of the present disclosure; and

[0027] Figure 9 A schematic diagram of a computer-readable storage medium provided by at least one embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0028] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0029] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0030] Figure 1 A schematic diagram of a cross-reset domain circuit is shown.

[0031] like Figure 1As shown, registers REG1 and REG2 are reset by two asynchronous reset signals RST1 and RST2 respectively (or, register REG1 is reset by the asynchronous reset signal RST1, and the asynchronous reset signal RST2 does not exist), and the clock signals CLK1 and CLK2 received by registers REG1 and REG2 respectively can be synchronous or asynchronous.

[0032] When the asynchronous reset signal RST1 is effective in resetting register REG1 and register REG2 is still working normally, since the reset signal RST1 is asynchronous, it may occur in the data sampling window of register REG2, causing register REG2 to produce a metastable state, which may cause instability of the entire chip.

[0033] Therefore, like clock domain crossing (CDC), reset domain crossing can also cause metastability issues, causing circuit malfunction. However, unlike clock domain crossing, the reset signal has a lower toggle rate than the clock signal. Therefore, if a problem occurs after silicon, it is difficult to reproduce and locate. Therefore, pre-silicon reset circuit inspection is very important.

[0034] RDC checking technology can quickly, automatically, and comprehensively check the structure of the design code and analyze cross-reset domain signal transmission problems. Designers can locate, verify, and repair RDC defects in the design earlier, speed up project progress, and truly improve product reliability.

[0035] One feasible method is to use relevant tools from third-party EDA (Electronic Design Automation) companies to perform RTL (Register Transfer Level) level checks. However, using this method, you first need to purchase the tool software separately and then deploy the relevant environment locally.

[0036] Furthermore, if you use a third-party EDA tool to check cross-reset domain circuits, you must provide a design constraint file for that tool. This design constraint file may not be consistent with the design constraint file used in the existing process due to issues such as tool vendor or version inconsistency, resulting in the need to maintain multiple sets of design constraint files.

[0037] Furthermore, not all cross-reset domain structures will cause cross-reset domain issues. Some cross-reset domain structures, if they pass appropriate timing checks, will not actually cause cross-reset domain issues. Third-party checking tools can only check cross-reset domain structures and cannot report timing information. In such cases, it is still necessary to query and confirm with tools such as PrimeTime. Migrating information between different tools will introduce new work costs and may cause loss of checking integrity due to tool differences.

[0038] At least one embodiment of the present disclosure provides a circuit detection method, circuit detection apparatus, electronic device, and computer-readable storage medium. The circuit detection method includes: obtaining a design file to be detected, wherein the design file includes information about multiple circuit elements; based on the information about the multiple circuit elements, identifying at least one initial detection circuit from the design file that meets the structural characteristics of a cross-reset domain circuit; and outputting the initial detection circuit that does not meet the constraint conditions as a target detection circuit, wherein the constraint conditions include at least one of a reset signal sequence constraint condition, a timing constraint condition, and a component type constraint condition.

[0039] This circuit detection method is based on a gate-level netlist and detects cross-reset domain circuits. It can reuse the processes used in traditional chip design without the need for additional inspection tools. It also maintains the consistency of design constraint files, avoids the need to maintain multiple sets of constraint files, reduces the workload of designers, and avoids omissions and false positives caused by differences between multiple sets of constraint files. The text-based filtering process for reset sequence, component type, and timing inspection can specify design intent, filter out reasonable cross-reset domain structures, and improve designer inspection efficiency. Existing timing inspection tools can be fully reused, eliminating the need to purchase and deploy third-party EDA software. Existing timing constraint files can be reused, and relevant timing information can be reported in a timely manner, reducing constraint differences and migration costs between different tools.

[0040] Figure 2 A flow chart of a circuit detection method provided by at least one embodiment of the present disclosure is shown.

[0041] like Figure 2 As shown, the method may include steps S210 to S230.

[0042] Step S210: Obtain the design file to be tested.

[0043] Step S220: Based on the information of the plurality of circuit elements, at least one initial detection circuit that meets the structural characteristics of a cross-reset domain circuit is identified from the design file.

[0044] Step S230: Outputting the initial detection circuit that does not meet the constraint condition among the at least one initial detection circuit as a target detection circuit. The constraint condition includes at least one of a sequence constraint condition of a reset signal, a timing constraint condition, and a component type constraint condition.

[0045] For example, the design file to be tested is a netlist file, which is used to describe the physical information of a physical unit, such as a register, a logic gate, or other circuit element.

[0046] For example, the design file to be tested includes information about multiple circuit elements, which may include multiple registers. The design file includes pin information, connection relationship information, etc. of the multiple registers. In addition, the multiple circuit elements may also include logic gates (AND, OR, NOT gates), memory, etc.

[0047] For example, in step S210, a test environment is established. For example, a netlist file is read in so that the netlist file can be tested in subsequent steps. In addition, a constraint file can be read in, which includes information such as sequence constraints, timing constraints, and component type constraints for reset signals. A timing library file (lib file) can also be read in to describe the timing information of the physical unit, such as the delay information between the input and output of the physical unit, and the delay information from one physical unit to another.

[0048] For example, in step S220, the structural features of the cross-reset domain circuit are identified from the netlist file, and the cross-reset domain circuit is detected and obtained as the aforementioned initial detection circuit. For example, the cross-reset domain circuit includes a first circuit element and a second circuit element, where the output of the first circuit element is connected to the input of the second circuit element. The structural features of the cross-reset domain circuit include the first circuit element including a first asynchronous reset terminal, and the second circuit element not including the asynchronous reset terminal or including a second asynchronous reset terminal, wherein the reset signal received by the second asynchronous reset terminal is different from the reset signal received by the first asynchronous reset terminal.

[0049] For example, taking the example that the first circuit element and the second circuit element are both registers, the first circuit element can be called a front register, the second circuit element can be called a rear register, and the output of the front register can reach the rear register.

[0050] For example, reset ports are categorized as asynchronous and synchronous. An asynchronous reset port refers to a port that receives an asynchronous reset signal. The duration of the asynchronous reset signal is independent of the clock signal; the component is reset as long as the asynchronous reset signal is asserted, regardless of whether a clock edge has occurred. In other words, an asynchronous reset is independent of the clock; the time at which the reset is asserted has no clear phase relationship with the clock. An asynchronous reset signal may or may not be synchronized with the clock signal. A synchronous reset port refers to a port that receives a synchronous reset signal. The duration of the synchronous reset signal is dependent on the clock signal, and the synchronous reset signal is asserted only when a clock edge has occurred. These two types of reset ports can be configured based on actual needs. For example, some registers may have an asynchronous reset port, some may not, and some may have both an asynchronous and a synchronous reset port. Asynchronous and synchronous reset ports have different port identifiers.

[0051] For example, for a circuit that crosses the reset domain, its preceding circuit element has an asynchronous reset terminal, and its following circuit element has an asynchronous reset terminal or does not have an asynchronous reset terminal.

[0052] For example, taking a register as an example, the structure of the cross-reset domain circuit has the following characteristics (1) to (3):

[0053] (1) The structure consists of two registers, called the front register and the back register;

[0054] (2) The front register has an asynchronous reset or asynchronous set terminal, and the asynchronous reset or asynchronous set terminal has two situations: a) the asynchronous reset or asynchronous set terminal is synchronous with the clock; b) the asynchronous reset or asynchronous set terminal is asynchronous with the clock;

[0055] (3) There are two cases for the rear register: a) There is also an asynchronous reset terminal or an asynchronous set terminal, but it is different from the reset terminal or set terminal of the front register, that is, the asynchronous reset signal received by the asynchronous reset terminal of the rear register is different from the asynchronous reset signal received by the asynchronous reset terminal of the front register; b) There is no asynchronous reset terminal or asynchronous set terminal.

[0056] For example, in step S230, after identifying the cross-reset domain circuit, the detected cross-reset domain circuit (i.e., the initial detection circuit) is screened and filtered using the constraint conditions to identify a circuit with a cross-reset domain problem (i.e., the target detection circuit). A circuit with a cross-reset domain problem refers to a circuit in which the reset operation received by the front circuit element (such as the front register) has an adverse effect on the rear circuit element (such as the rear register). For example, the reset operation of the front circuit element (such as the front register) occurs in the data sampling window of the rear circuit element (such as the rear register), that is, the signal jumps during the sampling window of the rear circuit element (such as the rear register), resulting in the failure to meet the setup and hold time, causing the output of the circuit element to be in a probabilistic indeterminate state, resulting in a metastable state. After determining the target detection circuit with problems, the information of each target detection circuit can be output to the designer to notify the designer to check and modify this part of the circuit.

[0057] In the disclosed embodiment, a detection method for cross-reset domain circuits based on gate-level netlist is provided, which can reuse the process in traditional chip design without introducing additional inspection tools, and can also maintain the consistency of design constraint files, avoid maintaining multiple sets of constraint files, reduce the workload of designers, and avoid omissions and false alarms caused by differences between multiple sets of constraint files. The filtering process of reset sequence, component type and timing inspection based on text processing can specify design intent, filter out reasonable cross-reset domain structures, and improve the inspection efficiency of designers. Existing timing inspection tools can be fully reused, without the need to purchase and deploy third-party EDA software, and existing timing constraint files can be reused, and relevant timing information can be reported in a timely manner, reducing constraint differences and migration costs between different tools.

[0058] Figure 3 A flowchart for identifying an initial detection circuit provided by at least one embodiment of the present disclosure is shown.

[0059] like Figure 3 As shown, for example, in some embodiments, in step S220, based on information of multiple circuit elements, at least one initial detection circuit that meets the structural characteristics of the cross-reset domain circuit is identified from the design file, which may include steps S221 to S222.

[0060] Step S221: Based on the information of multiple circuit elements, a first list is obtained, where the first list is used to record whether each circuit element has an asynchronous reset terminal. For each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element.

[0061] Step S222: Take each circuit element having an asynchronous reset terminal as a first circuit element, and perform the following operations for each first circuit element: determine at least one second circuit element corresponding to the first circuit element from multiple circuit elements; and determine, based on the first list, whether the first circuit element and each second circuit element meet the structural characteristics of a cross-reset domain circuit.

[0062] For example, taking registers as an example, register list A is obtained, and register list A lists the identifiers of all registers in the netlist file. For each register in register list A, the pin of the register is obtained, and it is determined whether there is an asynchronous reset terminal (or asynchronous set terminal) in the pin of the register. If it exists, it is further determined whether the asynchronous reset terminal (or asynchronous set terminal) is synchronized with the clock of the register, and the information is recorded in the first list B. The first list B can be a hash table indexed by the register name (with uniqueness). The first list B may include, for example, the following fields: register name, whether there is an asynchronous reset terminal, the name of the asynchronous reset terminal, and the relationship between the register asynchronous reset and the clock. The relationship between the register asynchronous reset and the clock may refer to whether the asynchronous reset signal of the register is synchronized with the clock signal or not.

[0063] For example, the first list records the information of registers b1 to bn (n is an integer greater than or equal to 1). At least some of registers b1 to bn have asynchronous reset terminals (or asynchronous set terminals). For each register bi (i is an integer greater than or equal to 1 and less than or equal to n) with an asynchronous reset terminal (or asynchronous set terminal), the following operations are performed one by one: tracing back all registers to which its output reaches to obtain a second list C; for all registers c1 to cm (m is an integer greater than or equal to 1) in the second list C, querying their asynchronous reset terminal or asynchronous set terminal information through the first list B; if the asynchronous set terminal or asynchronous reset terminal of cj (j is an integer greater than or equal to 1 and less than or equal to m) is different from that of bi, or if cj does not have an asynchronous set terminal or asynchronous reset terminal, then registers bi and cj meet the structural characteristics of a cross-reset domain circuit and can be used as an initial detection circuit. If the asynchronous set terminal or asynchronous reset terminal of cj is the same as that of bi, then registers bi and cj do not meet the structural characteristics of a cross-reset domain circuit, and the next register is checked. Based on the above process, multiple initial detection circuits can be obtained, and these multiple initial detection circuits are recorded in Table D. Each row in Table D can correspond to an initial detection circuit. The fields of Table D may include: the name of the front register, the name of the asynchronous reset terminal of the front register, the relationship between the asynchronous reset of the front register and the clock, the name of the back register, the name of the asynchronous reset terminal of the back register, and whether the clocks of the front and back registers are synchronized.

[0064] For example, by first detecting the front register with an asynchronous reset terminal, and then detecting the rear register with a different asynchronous reset terminal or the rear register without an asynchronous reset terminal for each front register with an asynchronous reset terminal, the cross-reset domain circuit can be efficiently detected, the detection efficiency is improved, and the detection time is shortened.

[0065] Figure 4 A flowchart for identifying another initial detection circuit provided by at least one embodiment of the present disclosure is shown.

[0066] like Figure 4 As shown, for example, in other embodiments, in step S220, based on information of multiple circuit elements, at least one initial detection circuit that meets the structural characteristics of the cross-reset domain circuit is identified from the design file, which may include steps S223 to S224.

[0067] Step S223: Based on the information of multiple circuit elements, a first list is obtained, where the first list is used to record whether each circuit element has an asynchronous reset terminal. For each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element.

[0068] Step S224: Take each circuit element as a second circuit element, and perform the following operations for each second circuit element: determine at least one first circuit element corresponding to the second circuit element from multiple circuit elements; based on the first list, determine whether the second circuit element and each first circuit element meet the structural characteristics of the cross-reset domain circuit.

[0069] For example, the description of step S221 in the above embodiment of step S223 will not be repeated here. In step S224, the reset information of the rear register can be first found, and then the reset information of the front register of its driving source can be traced back to identify the cross-reset domain circuit. For example, the rear register of the cross-reset domain circuit may have an asynchronous reset terminal or may not have an asynchronous reset terminal. Therefore, each register in the first list can be used as a rear register. For each rear register, each front register belonging to its driving source and having an asynchronous reset terminal is determined to obtain a cross-reset domain circuit.

[0070] For example, in step S220, it is also determined whether the asynchronous reset signal of the front register is synchronized with the clock signal, and whether the clock signals of the front and rear registers are synchronized. If the asynchronous reset signal of the front register in the cross-reset domain circuit is synchronized with the clock signal and the clock signals of the front and rear registers are synchronized, then it is possible to determine whether there is a problem with the cross-reset domain circuit by performing a timing check on the front and rear registers. If the front and rear registers meet the timing requirements, then although the circuit belongs to a cross-reset domain circuit, it will not actually cause a cross-reset domain problem, that is, the reset of the front register will not have an adverse effect on the rear register. If the asynchronous reset signal of the front register in the cross-reset domain circuit is not synchronized with the clock signal or the clock signals of the front and rear registers are not synchronized, since the asynchronous reset signal has uncertainty, the action time of the asynchronous reset signal is uncertain, and thus the timing check of the front and rear registers cannot be performed.

[0071] For example, the sequence constraint may include that the reset signal received by the asynchronous reset terminal of the first circuit element is later than the reset signal received by the asynchronous reset terminal of the second circuit element; the timing constraint includes a setup time condition and a hold time condition; the element type constraint includes that the second circuit element is an element set up to solve the cross-reset domain problem.

[0072] For example, for a cross-reset domain circuit, if the rear register receives the reset signal first, the rear register enters the reset state first, and the front register receives the reset signal later. When the front register is reset, the rear register is in the reset state instead of the working state, so the reset operation of the front register will not have an adverse effect on the rear register. Therefore, when the asynchronous reset signal of the front register is later than the asynchronous reset signal of the rear register, that is, when the reset time of the front register is later than the reset time of the rear register, it will not cause a cross-reset domain problem (or metastable problem).

[0073] For example, as described above, for a cross-reset domain circuit, if the asynchronous reset signal and clock signal of the front register are synchronized, and the clock signals of the front and back registers are synchronized, then a timing check of the front and back registers can be performed to determine whether there is a problem with the cross-reset domain circuit. If the front and back registers meet the timing requirements, then although the circuit is a cross-reset domain circuit, it will not actually cause a cross-reset domain problem. The timing check includes setup time and hold time checks. If the asynchronous reset signal and clock signal of the front register are synchronized, the clock signals of the front and back registers are synchronized, and the front and back registers meet the setup time and hold time requirements, then the cross-reset domain circuit does not have a cross-reset domain problem. Setup time refers to the time before the rising edge of the trigger clock signal arrives, the data is stable and unchanged. If the setup time is insufficient, the data will not be entered into the trigger on this rising edge of the clock. Hold time refers to the time after the rising edge of the trigger clock signal arrives, the data is stable and unchanged. If the hold time is insufficient, the data will also not be entered into the trigger. Meeting the setup time and hold time requirements means that the setup time and hold time are sufficient to ensure that data can be transmitted and processed normally.

[0074] For example, to address cross-reset domain issues (metastability issues) in some cross-reset domain circuits, some intermediate registers can be added between the front and rear registers of the cross-reset domain circuit to eliminate or mitigate the metastability issues. For example, two or three levels of intermediate registers can be provided. In step S220, the front register and the intermediate register are identified as cross-reset domain circuits (in such cross-reset domain circuits, the intermediate registers are treated as rear registers). In step S230, such circuits can be filtered out.

[0075] Figure 5 A flow chart for determining a target detection circuit provided by at least one embodiment of the present disclosure is shown.

[0076] like Figure 5 As shown, for example, in step S230, an initial detection circuit that does not meet the constraint condition in at least one initial detection circuit is output as a target detection circuit, which may include steps S231 to S234.

[0077] Step S231: filtering out a first portion of initial detection circuits that meet a sequence constraint or a component type constraint from at least one initial detection circuit to obtain a remaining second portion of initial detection circuits.

[0078] Step S232: Determine a third part of the initial detection circuit from the second part of the initial detection circuit, wherein, for each initial detection circuit in the third part of the initial detection circuit, the reset signal of the asynchronous reset end of the first circuit element is synchronized with the clock signal of the first circuit element and the clock signal of the first circuit element is synchronized with the clock signal of the second circuit element.

[0079] Step S233: for each initial detection circuit in the third part of initial detection circuits, determine whether the initial detection circuit meets the timing constraint condition.

[0080] Step S234: the initial detection circuits in the third part of the initial detection circuits that do not meet the timing constraint conditions are used as target detection circuits, and the other initial detection circuits in the second part of the initial detection circuits except the third part of the initial detection circuits are used as target detection circuits.

[0081] For example, after identifying the cross-reset domain structural features, at least one initial detection circuit that may have a cross-reset domain problem is obtained. In step S230, the at least one initial detection circuit is filtered to filter out circuits with real problems, reduce redundant and invalid information, and facilitate confirmation by designers.

[0082] For example, step S230 may include three sub-stages: filtering based on reset sequence, filtering based on component type, and filtering based on timing check. For example, a reset sequence constraint file is read in, which defines the allowable sequence relationship between different reset signals, and an intermediate register list file is read in, which defines the intermediate registers pre-set in the target design and added to solve the cross-reset domain problem. The entries in Table D are checked one by one to see if they comply with the sequence relationship defined in the reset sequence constraint file. If so, the entry is deleted from Table D; otherwise, it is retained for subsequent inspection. For the remaining entries in Table D, the rear register is checked one by one to see if it is a register in the intermediate register list file. If so, the entry is deleted from Table D; otherwise, it is retained for subsequent inspection. For the remaining entries in Table D, the entries whose asynchronous reset signal of the front register is synchronized with the clock signal and the clock signals of the front and rear registers are synchronized are filtered out, and the filtered entries are subjected to timing checks one by one. The remaining entries (i.e., the entries whose asynchronous reset signal of the front register is not synchronized with the clock signal or the clock signals of the front and rear registers are not synchronized) are retained in Table D. For each filtered entry that meets the timing constraints (setup and hold times), it is deleted from Table D. Entries that do not meet the timing constraints remain in Table D. After the filtering steps, Table D is used as the final file G, which includes the cross-reset domain circuits found to have cross-reset domain issues. This file G is output for careful review by the designer.

[0083] For example, in the above embodiment, the reset sequence is checked first, then the component type, and finally the timing. However, there is no mandatory order between the three conditions, and the above embodiment is a more efficient process. In other embodiments, the order of checking these three conditions can be set according to actual needs. For example, the component type can be checked first, then the reset sequence, and finally the timing. Alternatively, the timing can be checked first, then the reset sequence, and finally the component type.

[0084] According to at least one embodiment of the present disclosure, detection of circuits across asynchronous domains based on a gate-level netlist can be implemented, and reset sequence, component type, and timing check filtering can be implemented to reduce redundant information and facilitate continued review by designers.

[0085] According to at least one embodiment of the present disclosure, the process in traditional chip design is reused without introducing additional inspection tools.

[0086] According to at least one embodiment of the present disclosure, the consistency of design constraint files can be maintained, avoiding the need to maintain multiple sets of constraint files, and reducing the workload of designers; at the same time, the problems of missed reports and false positives caused by differences between multiple sets of constraint files can be avoided.

[0087] According to at least one embodiment of the present disclosure, a filtering process based on reset sequence, component type, and timing inspection for text processing can specify design intent, filter out reasonable cross-reset domain structures, and improve designer inspection efficiency.

[0088] According to at least one embodiment of the present disclosure, the timing check process in traditional chip design can be reused to filter out cross-reset domain structures whose timing can be guaranteed, thereby further improving the checking efficiency of designers.

[0089] According to at least one embodiment of the present disclosure, cross-reset domain structures are characterized based on a gate-level netlist, thereby identifying all potential cross-reset domain issues. Combining cross-reset domain checking with timing checking streamlines steps and improves efficiency.

[0090] Figure 6 A schematic block diagram of a circuit detection device 600 provided by at least one embodiment of the present disclosure is shown.

[0091] For example, Figure 6As shown, the circuit detection device 600 includes an acquisition module 610, a first detection module 620 and a second detection module 630. These components are interconnected via a bus system and / or other forms of connection mechanisms (not shown). For example, these modules can be implemented by hardware (e.g., circuit) modules, software modules, or any combination thereof. The following embodiments are the same and will not be described in detail. For example, these units can be implemented by a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a field programmable gate array (FPGA), or other forms of processing units with data processing capabilities and / or instruction execution capabilities, as well as corresponding computer instructions. It should be noted that Figure 6 The components and structure of the circuit detection device 600 shown are merely exemplary and non-limiting. The circuit detection device 600 may also have other components and structures as needed.

[0092] The acquisition module 610 is configured to acquire a design file to be tested, wherein the design file includes information of a plurality of circuit elements. The acquisition module 610 may, for example, execute Figure 2 Step S210 described.

[0093] The first detection module 620 is configured to identify at least one initial detection circuit that meets the structural characteristics of the cross-reset domain circuit from the design file based on the information of the multiple circuit elements. The first detection module 620 can, for example, perform Figure 2 Step S220 described.

[0094] The second detection module 630 is configured to output the initial detection circuit that does not meet the constraint conditions in the at least one initial detection circuit as a target detection circuit, wherein the constraint conditions include at least one of the sequence constraint conditions, timing constraint conditions and component type constraint conditions of the reset signal. The second detection module 630 can, for example, execute Figure 2 Step S230 described.

[0095] For example, the acquisition module 610, the first detection module 620, and the second detection module 630 can be hardware, software, firmware, or any feasible combination thereof. For example, the acquisition module 610, the first detection module 620, and the second detection module 630 can be dedicated or general-purpose circuits, chips, or devices, or can be a combination of a processor and memory. The embodiments of the present disclosure do not limit the specific implementation of each of the above-mentioned units.

[0096] For example, the acquisition module 610, the first detection module 620, and the second detection module 630 may include codes and programs stored in a memory; the processor may execute the codes and programs to implement some or all of the functions of the acquisition module 610, the first detection module 620, and the second detection module 630 as described above. For example, the acquisition module 610, the first detection module 620, and the second detection module 630 may be dedicated hardware devices used to implement some or all of the functions of the acquisition module 610, the first detection module 620, and the second detection module 630 as described above. For example, the acquisition module 610, the first detection module 620, and the second detection module 630 may be a circuit board or a combination of multiple circuit boards used to implement the functions described above. In an embodiment of the present disclosure, the circuit board or the combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-temporary memories connected to the processors; and (3) firmware stored in the memory that is executable by the processor.

[0097] It should be noted that in the embodiment of the present disclosure, the various units of the circuit detection device 600 correspond to the various steps of the aforementioned circuit detection method. For the specific functions of the circuit detection device 600, please refer to the relevant description of the circuit detection method, which will not be repeated here. Figure 6 The components and structure of the circuit detection device 600 shown are merely exemplary and non-restrictive. The circuit detection device 600 may also include other components and structures as needed. The circuit detection device 600 may include more or fewer circuits or units, and the connections between the various circuits or units are not limited and can be determined based on actual needs. The specific configuration of each circuit or unit is not limited and may be composed of analog devices, digital chips, or other suitable configurations based on circuit principles.

[0098] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the plurality of circuit elements include a plurality of registers, and the design file includes pin information and connection relationship information of the plurality of registers.

[0099] For example, in the circuit detection device provided in at least one example of the above-mentioned embodiments of the present disclosure, the cross-reset domain circuit includes a first circuit element and a second circuit element, and the output of the first circuit element is connected to the input of the second circuit element; the structural features of the cross-reset domain circuit include that the first circuit element includes a first asynchronous reset terminal, and the second circuit element does not include the asynchronous reset terminal or includes a second asynchronous reset terminal, wherein the reset signal received by the second asynchronous reset terminal is different from the reset signal received by the first asynchronous reset terminal.

[0100] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the first detection module is configured to: obtain a first list based on information of multiple circuit elements, wherein the first list is used to record whether each circuit element has an asynchronous reset terminal, and for each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element; take each circuit element with an asynchronous reset terminal as a first circuit element, and perform the following operations for each first circuit element: determine at least one second circuit element corresponding to the first circuit element from multiple circuit elements; based on the first list, determine whether the first circuit element and each second circuit element meet the structural characteristics of the cross-reset domain circuit.

[0101] For example, in the circuit detection device provided by at least one example of the above-mentioned embodiments of the present disclosure, the first detection module is configured to: obtain a first list based on information of multiple circuit elements, wherein the first list is used to record whether each circuit element has an asynchronous reset terminal, and for each circuit element with an asynchronous reset terminal, the first list is also used to record the identifier of the asynchronous reset terminal of the circuit element, and the timing relationship between the reset signal received by the asynchronous reset terminal and the clock signal received by the circuit element; treat each circuit element as a second circuit element, and perform the following operations for each second circuit element: determine at least one first circuit element corresponding to the second circuit element from multiple circuit elements; based on the first list, determine whether the second circuit element and each first circuit element meet the structural characteristics of the cross-reset domain circuit.

[0102] For example, in the circuit detection device provided in at least one example of the above-mentioned embodiments of the present disclosure, the second detection module is configured to: filter out the first part of the initial detection circuits that meet the sequence constraint or the element type constraint from at least one initial detection circuit to obtain the remaining second part of the initial detection circuit; determine the third part of the initial detection circuit from the second part of the initial detection circuit, wherein, for each initial detection circuit in the third part of the initial detection circuit, the reset signal of the asynchronous reset end of the first circuit element is synchronized with the clock signal of the first circuit element and the clock signal of the first circuit element is synchronized with the clock signal of the second circuit element; for each initial detection circuit in the third part of the initial detection circuit, determine whether the initial detection circuit meets the timing constraint; take the initial detection circuit in the third part of the initial detection circuit that does not meet the timing constraint as the target detection circuit, and take the other initial detection circuits in the second part of the initial detection circuit except the third part of the initial detection circuit as the target detection circuit.

[0103] For example, in the circuit detection device provided in at least one example of the above-mentioned embodiments of the present disclosure, the sequence constraint condition includes that the reset signal received by the asynchronous reset terminal of the first circuit element is later than the reset signal received by the asynchronous reset terminal of the second circuit element; the timing constraint condition includes a setup time condition and a hold time condition; and the element type constraint condition includes that the second circuit element is an element set to solve the cross-reset domain problem.

[0104] At least one embodiment of the present disclosure also provides an electronic device, which includes a processor and a memory, and the memory stores one or more computer program modules. The one or more computer program modules are configured to be executed by the processor to implement the above-mentioned circuit detection method. The electronic device can reuse the process in traditional chip design without introducing additional inspection tools, and can also maintain the consistency of the design constraint files, avoid maintaining multiple sets of constraint files, reduce the workload of designers, and avoid omissions and false alarms caused by differences between multiple sets of constraint files. The filtering process of reset sequence, component type and timing inspection based on text processing can specify design intent, filter out reasonable cross-reset domain structures, and improve the inspection efficiency of designers. Existing timing inspection tools can be fully reused, without the need to purchase and deploy third-party EDA software, and existing timing constraint files can be reused, and relevant timing information can be reported in a timely manner, reducing constraint differences and migration costs between different tools.

[0105] Figure 7 This is a schematic block diagram of an electronic device provided in some embodiments of the present disclosure. Figure 7 As shown, the electronic device 700 includes a processor 710 and a memory 720. The memory 720 stores non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 is used to execute non-transitory computer-readable instructions, and the non-transitory computer-readable instructions are executed by the processor 710 to execute one or more steps in the circuit detection method described above. The memory 720 and the processor 710 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown). For the specific implementation of each step of the circuit detection method and the related explanations, please refer to the embodiment of the circuit detection method described above, and the repeated parts will not be repeated here.

[0106] It should be noted that Figure 7 The components of the electronic device 700 shown are merely exemplary and non-limiting. The electronic device 700 may also have other components according to actual application requirements.

[0107] For example, the processor 710 and the memory 720 may communicate with each other directly or indirectly.

[0108] For example, the processor 710 and the memory 720 may communicate via a network. The network may include a wireless network, a wired network, and / or any combination of a wireless network and a wired network. The processor 710 and the memory 720 may also communicate with each other via a system bus, which is not limited in this disclosure.

[0109] For example, the processor 710 and the memory 720 may be provided on a server side (or a cloud side).

[0110] For example, the processor 710 can control other components in the electronic device 700 to perform desired functions. For example, the processor 710 can be a central processing unit (CPU), a graphics processing unit (GPU), or other processing units with data processing capabilities and / or program execution capabilities. For example, the central processing unit (CPU) can be an X86 or ARM architecture. The processor 710 can be a general-purpose processor or a dedicated processor, and can control other components in the electronic device 700 to perform desired functions.

[0111] For example, the memory 720 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, an erasable programmable read-only memory (EPROM), a portable compact disk read-only memory (CD-ROM), a USB memory, a flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processor 710 may execute one or more computer program modules to implement various functions of the electronic device 700. Various applications and various data, as well as various data used and / or generated by the applications, may also be stored in the computer-readable storage medium.

[0112] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the electronic device 700 can be referred to the above description of the circuit detection method, which will not be repeated here.

[0113] Figure 8 This is a schematic block diagram of another electronic device provided in some embodiments of the present disclosure. The electronic device 800 is suitable for implementing the circuit detection method provided in the embodiments of the present disclosure. The electronic device 800 may be a terminal device, etc. It should be noted that, Figure 8 The electronic device 800 shown is merely an example and does not limit the functions and scope of use of the embodiments of the present disclosure.

[0114] like Figure 8As shown, the electronic device 800 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 810, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 820 or a program loaded from a storage device 880 into a random access memory (RAM) 830. Various programs and data required for the operation of the electronic device 800 are also stored in the RAM 830. The processing device 810, the ROM 820, and the RAM 830 are connected to each other via a bus 840. An input / output (I / O) interface 850 is also connected to the bus 840.

[0115] Typically, the following devices may be connected to the I / O interface 850: an input device 860 including, for example, a touch screen, a touchpad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 870 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 880 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 890. The communication device 890 may allow the electronic device 800 to communicate with other electronic devices wirelessly or by wire to exchange data. Although Figure 8 The electronic device 800 is shown with various devices, but it should be understood that it is not required to implement or possess all of the devices shown, and the electronic device 800 may alternatively implement or possess more or fewer devices.

[0116] For example, according to an embodiment of the present disclosure, the above-mentioned circuit detection method can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program includes program code for executing the above-mentioned circuit detection method. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 890, or installed from the storage device 880, or installed from the ROM 820. When the computer program is executed by the processing device 810, the functions defined in the circuit detection method provided in the embodiment of the present disclosure can be implemented.

[0117] At least one embodiment of the present disclosure also provides a computer-readable storage medium, which stores non-temporary computer-readable instructions, and when the non-temporary computer-readable instructions are executed by a computer, the above-mentioned circuit detection method can be implemented. By using this computer-readable storage medium, the process in traditional chip design can be reused without introducing additional inspection tools. The consistency of the design constraint files can also be maintained, avoiding the maintenance of multiple sets of constraint files, reducing the workload of designers, and avoiding the problems of missed reports and false positives caused by differences between multiple sets of constraint files. The filtering process of reset sequence, component type and timing inspection based on text processing can specify design intent, filter out reasonable cross-reset domain structures, and improve the inspection efficiency of designers. Existing timing inspection tools can be fully reused without the need to purchase and deploy third-party EDA software, and existing timing constraint files can be reused. Relevant timing information can be reported in a timely manner, reducing constraint differences and migration costs between different tools.

[0118] Figure 9 A schematic diagram of a storage medium provided in some embodiments of the present disclosure. Figure 9 As shown, the storage medium 900 stores non-transitory computer-readable instructions 910. For example, when the non-transitory computer-readable instructions 910 are executed by a computer, one or more steps in the circuit detection method described above are performed.

[0119] For example, the storage medium 900 can be applied to the electronic device 700. Figure 7 The memory 720 in the electronic device 700 is shown. For example, the description of the storage medium 900 can be referred to Figure 7 The corresponding description of the memory 720 in the electronic device 700 is shown and will not be repeated here.

[0120] The above description is merely a preferred embodiment of the present disclosure and an illustration of the technical principles employed. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by the specific combination of the above-mentioned technical features, but also includes other technical solutions formed by any combination of the above-mentioned technical features or their equivalents without departing from the above-mentioned disclosed concepts. For example, a technical solution formed by replacing the above-mentioned features with (but not limited to) technical features with similar functions disclosed in this disclosure.

[0121] In addition, although each operation is described in a specific order, this should not be understood as requiring these operations to be performed in the specific order shown or in a sequential order. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details have been included in the above discussion, these should not be interpreted as limiting the scope of the present disclosure. Some features described in the context of a separate embodiment can also be implemented in a single embodiment in combination. On the contrary, the various features described in the context of a single embodiment can also be implemented in multiple embodiments individually or in any suitable sub-combination mode.

[0122] Although the subject matter has been described in language specific to structural features and / or methodological logical acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

[0123] Regarding this disclosure, the following points need to be explained:

[0124] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to conventional designs.

[0125] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to form new embodiments.

[0126] The above description is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. The protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A circuit detection method, comprising: Acquire a design file to be tested, wherein the design file is a netlist file and includes information of a plurality of circuit elements; Based on the information of the plurality of circuit elements, identifying at least one initial detection circuit that meets structural characteristics of a cross-reset domain circuit from the design file, wherein the cross-reset domain circuit includes a first circuit element and a second circuit element, and an output of the first circuit element is connected to an input of the second circuit element; The at least one identified initial detection circuit is screened and filtered using constraint conditions to identify a target detection circuit with a cross-reset domain problem; the initial detection circuit that does not meet the constraint conditions in the at least one initial detection circuit is output as the target detection circuit, wherein the constraint conditions include at least one of a sequence constraint condition, a timing constraint condition, and an element type constraint condition of the reset signal, wherein the sequence constraint condition includes that the reset signal received by the first asynchronous reset end of the first circuit element is later than the reset signal received by the second asynchronous reset end of the second circuit element, and the timing constraint condition includes a setup time condition and a hold time condition.

2. The circuit detection method according to claim 1, wherein: The multiple circuit elements include multiple registers, and the design file includes pin information and connection relationship information of the multiple registers.

3. The circuit detection method according to claim 1 or 2, wherein: The reset signal received by the second asynchronous reset terminal is different from the reset signal received by the first asynchronous reset terminal.

4. The circuit detection method according to claim 3, wherein: Based on the information of the plurality of circuit elements, identifying from the design file at least one initial detection circuit that meets the structural characteristics of a cross-reset domain circuit, comprising: Based on the information of the plurality of circuit elements, a first list is obtained, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element having an asynchronous reset terminal, the first list is further used to record an identifier of the asynchronous reset terminal of the circuit element, and a timing relationship between a reset signal received by the asynchronous reset terminal and a clock signal received by the circuit element; Each circuit element having an asynchronous reset terminal is used as the first circuit element, and the following operations are performed on each first circuit element: determining at least one second circuit element corresponding to the first circuit element from the plurality of circuit elements; Based on the first list, it is determined whether the first circuit element and each of the second circuit elements meet the structural characteristics of the cross-reset domain circuit.

5. The circuit detection method according to claim 3, wherein: Based on the information of the plurality of circuit elements, identifying from the design file at least one initial detection circuit that meets the structural characteristics of a cross-reset domain circuit, comprising: Based on the information of the plurality of circuit elements, a first list is obtained, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element having an asynchronous reset terminal, the first list is further used to record an identifier of the asynchronous reset terminal of the circuit element, and a timing relationship between a reset signal received by the asynchronous reset terminal and a clock signal received by the circuit element; Each of the circuit elements is used as the second circuit element, and the following operations are performed on each of the second circuit elements: determining at least one first circuit element corresponding to the second circuit element from the plurality of circuit elements; Based on the first list, it is determined whether the second circuit element and each of the first circuit elements meet the structural characteristics of the cross-reset domain circuit.

6. The circuit detection method according to claim 3, wherein: Outputting an initial detection circuit that does not satisfy the constraint condition among the at least one initial detection circuit as a target detection circuit includes: filtering out a first portion of initial detection circuits that meet the sequence constraint or the component type constraint from the at least one initial detection circuit to obtain a remaining second portion of initial detection circuits; determining a third portion of initial detection circuits from the second portion of initial detection circuits, wherein, for each initial detection circuit in the third portion of initial detection circuits, a reset signal at an asynchronous reset terminal of a first circuit element is synchronized with a clock signal of the first circuit element and the clock signal of the first circuit element is synchronized with a clock signal of the second circuit element; For each initial detection circuit in the third part of initial detection circuits, determining whether the initial detection circuit meets the timing constraint condition; The initial detection circuits in the third part of the initial detection circuits that do not meet the timing constraint conditions are used as the target detection circuits, and the other initial detection circuits in the second part of the initial detection circuits except the third part of the initial detection circuits are used as the target detection circuits.

7. The circuit detection method according to claim 6, wherein: The sequence constraint condition includes that the reset signal received by the asynchronous reset terminal of the first circuit element is later than the reset signal received by the asynchronous reset terminal of the second circuit element; The timing constraints include setup time conditions and hold time conditions; The component type constraint condition includes that the second circuit element is an element provided to solve a cross-reset domain problem.

8. A circuit detection device comprising: an acquisition module configured to acquire a design file to be tested, wherein the design file is a netlist file and includes information of a plurality of circuit elements; a first detection module configured to identify, from the design file, at least one initial detection circuit that meets structural characteristics of a cross-reset domain circuit based on information of the plurality of circuit elements, wherein the cross-reset domain circuit includes a first circuit element and a second circuit element, and an output of the first circuit element is connected to an input of the second circuit element; The second detection module is configured to use constraint conditions to screen and filter the at least one identified initial detection circuit to identify a target detection circuit with a cross-reset domain problem; and output the initial detection circuit that does not meet the constraint conditions in the at least one initial detection circuit as the target detection circuit, wherein the constraint conditions include at least one of the sequence constraint conditions, timing constraint conditions and element type constraint conditions of the reset signal, wherein the sequence constraint conditions include that the reset signal received by the first asynchronous reset end of the first circuit element is later than the reset signal received by the second asynchronous reset end of the second circuit element, and the timing constraint conditions include setup time conditions and hold time conditions.

9. The circuit detection device according to claim 8, wherein: The multiple circuit elements include multiple registers, and the design file includes pin information and connection relationship information of the multiple registers.

10. The circuit detection device according to claim 8 or 9, wherein: The reset signal received by the second asynchronous reset terminal is different from the reset signal received by the first asynchronous reset terminal.

11. The circuit detection device according to claim 10, wherein: The first detection module is configured as follows: Based on the information of the plurality of circuit elements, a first list is obtained, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element having an asynchronous reset terminal, the first list is further used to record an identifier of the asynchronous reset terminal of the circuit element, and a timing relationship between a reset signal received by the asynchronous reset terminal and a clock signal received by the circuit element; Each circuit element having an asynchronous reset terminal is used as the first circuit element, and the following operations are performed on each first circuit element: determining at least one second circuit element corresponding to the first circuit element from the plurality of circuit elements; Based on the first list, it is determined whether the first circuit element and each of the second circuit elements meet the structural characteristics of the cross-reset domain circuit.

12. The circuit detection device according to claim 10, wherein: The first detection module is configured as follows: Based on the information of the plurality of circuit elements, a first list is obtained, wherein the first list is used to record whether each of the circuit elements has an asynchronous reset terminal, and for each circuit element having an asynchronous reset terminal, the first list is further used to record an identifier of the asynchronous reset terminal of the circuit element, and a timing relationship between a reset signal received by the asynchronous reset terminal and a clock signal received by the circuit element; Each of the circuit elements is used as the second circuit element, and the following operations are performed on each of the second circuit elements: determining at least one first circuit element corresponding to the second circuit element from the plurality of circuit elements; Based on the first list, it is determined whether the second circuit element and each of the first circuit elements meet the structural characteristics of the cross-reset domain circuit.

13. The circuit detection device according to claim 10, wherein: The second detection module is configured as follows: filtering out a first portion of initial detection circuits that meet the sequence constraint or the component type constraint from the at least one initial detection circuit to obtain a remaining second portion of initial detection circuits; determining a third portion of initial detection circuits from the second portion of initial detection circuits, wherein, for each initial detection circuit in the third portion of initial detection circuits, a reset signal at an asynchronous reset terminal of a first circuit element is synchronized with a clock signal of the first circuit element and the clock signal of the first circuit element is synchronized with a clock signal of the second circuit element; For each initial detection circuit in the third part of initial detection circuits, determining whether the initial detection circuit meets the timing constraint condition; The initial detection circuits in the third part of the initial detection circuits that do not meet the timing constraint conditions are used as the target detection circuits, and the other initial detection circuits in the second part of the initial detection circuits except the third part of the initial detection circuits are used as the target detection circuits.

14. An electronic device comprising: processor; a memory storing one or more computer program modules; The one or more computer program modules are configured to be executed by the processor to implement the circuit detection method according to any one of claims 1 to 7. 15 . A computer-readable storage medium storing non-transitory computer-readable instructions, wherein when the non-transitory computer-readable instructions are executed by a computer, the circuit detection method according to claim 1 can be implemented.

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