Current limiting circuit for LDO, LDO, chip, and electronic equipment

Abstract

A current limiting circuit applied to an LDO, an LDO, a chip, and an electronic device, belonging to the technical field of power supply. Due to being connected with a power tube, the gate of a second PMOS tube is connected with the drain of the second PMOS tube, the negative electrode of the second current source, and the source of the first PMOS tube; the gate of a fourth PMOS tube, the drain of the fourth PMOS tube, the negative electrode of the fourth current source, and the source of a third PMOS tube are connected and jointly constitute a driving voltage output end of the current limiting circuit, which is connected with the gate of the power tube to output a driving voltage; the gate of the first PMOS tube, the drain of the first PMOS tube, the gate of the third PMOS tube, and the positive electrode of the first current source are connected and jointly constitute a first regulating current output end of the current limiting circuit to output a first regulating current; the response speed and stability of the LDO are improved and the layout area is reduced.

Description

Technical Field

[0001] The present application belongs to the field of power supply technology, and in particular, relates to a current limiting circuit applied to an LDO, an LDO, a chip, and an electronic device. Background Art

[0002] The related low dropout regulator (LDO) usually limits the output current to avoid chip damage caused by large output current. The more common current limiting method is to proportionally reduce the output current of the power tube and compare it with the internal reference current of the circuit. When the output current is greater than the limit value, the LDO internal loop is adjusted to limit the gate-source voltage of the power tube, and finally the output current of the power tube is limited to a certain range. This method requires the introduction of a loop for current limiting, and the response speed and stability of the loop need to be carefully designed.

[0003] Therefore, the related current limiting circuit applied to LDO has slow response speed, poor stability and large layout area. Summary of the invention

[0004] The purpose of the present application is to provide a current limiting circuit and an image sensor applied to LDO, aiming to solve the problems of slow response speed, poor stability and large layout area of ​​the related current limiting circuit applied to LDO.

[0005] The embodiment of the present application provides a current limiting circuit applied to an LDO, connected to a power tube, including a first current source, a second current source, a third current source, a fourth current source, a first PMOS tube, a second PMOS tube, a third PMOS tube, and a fourth PMOS tube;

[0006] The positive electrode of the second current source, the positive electrode of the fourth current source, the source electrode of the second PMOS tube and the source electrode of the fourth PMOS tube are connected to the first power supply;

[0007] The gate of the second PMOS tube is connected to the drain of the second PMOS tube, the negative electrode of the second current source and the source of the first PMOS tube;

[0008] The gate of the fourth PMOS tube, the drain of the fourth PMOS tube, the negative electrode of the fourth current source and the source of the third PMOS tube are connected and together constitute the driving voltage output end of the current limiting circuit, which is connected to the gate of the power tube to output the driving voltage;

[0009] The gate of the first PMOS tube, the drain of the first PMOS tube, the gate of the third PMOS tube and the positive electrode of the first current source are connected and together constitute a first regulating current output end of the current limiting circuit to output a first regulating current;

[0010] The drain of the third PMOS tube is connected to the positive electrode of the third current source, and the negative electrode of the first current source and the negative electrode of the third current source are connected to the power ground.

[0011] In one embodiment, the power tube is a P-type power tube;

[0012] The drain of the P-type power tube constitutes the output end of the LDO to output the output voltage;

[0013] The gate of the P-type power tube is connected to the driving voltage.

[0014] In one embodiment, the P-type power tube and the fourth PMOS tube form a first current mirror.

[0015] In one embodiment, the power tube is an N-type power tube;

[0016] The current limiting circuit applied to the LDO further includes a fifth PMOS tube and a first NMOS tube;

[0017] The gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the negative electrode of the fourth current source, the source of the third PMOS tube and the gate of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the first power supply, the drain of the fifth PMOS tube, the gate of the first NMOS tube and the drain of the first NMOS tube are connected and together constitute the driving voltage output end of the current limiting circuit, and is connected to the gate of the N-type power tube to output the driving voltage;

[0018] The source of the first NMOS tube and the source of the N-type power tube are connected and together constitute the output end of the LDO to output an output voltage;

[0019] The drain of the N-type power tube is connected to the first power supply;

[0020] The gate of the N-type power tube is connected to the driving voltage.

[0021] In one embodiment, the N-type power tube and the first NMOS tube form a second current mirror, and the fifth PMOS tube and the fourth PMOS tube form a third current mirror.

[0022] In one embodiment, the first current source, the second current source, the third current source and the fourth current source are bias currents mirrored from a reference current source.

[0023] An embodiment of the present invention further provides an LDO, wherein the LDO includes the above-mentioned current limiting circuit applied to the LDO.

[0024] In one embodiment, the LDO further comprises:

[0025] a voltage-current amplifying circuit, connected to the current limiting circuit, and configured to output a first regulating voltage according to the first regulating current;

[0026] a voltage amplifier circuit, connected to the voltage-current amplifier circuit, and configured to output a first feedback voltage according to a reference voltage and the first adjustment voltage;

[0027] The voltage divider circuit is connected to the power tube and the voltage amplifier circuit, and is configured to output an output voltage based on the feedback voltage.

[0028] In one of the embodiments, the voltage divider circuit is further configured to sample the output voltage to output a second feedback voltage;

[0029] The voltage amplification circuit is further configured to output a second regulated voltage according to the reference voltage and the second feedback voltage;

[0030] The voltage-current amplification circuit is further configured to output a second regulated current according to the second regulated voltage;

[0031] Among them, the gate of the first PMOS tube, the drain of the first PMOS tube, the gate of the third PMOS tube and the positive electrode of the first current source are connected and together constitute the second regulating current input terminal of the current limiting circuit to access the second regulating current.

[0032] An embodiment of the present invention further provides an electronic device, wherein the electronic device includes the above-mentioned LDO.

[0033] An embodiment of the present invention further provides a chip, wherein the chip includes the above-mentioned LDO.

[0034] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: when the load current increases to a certain extent, the current of the third current source is equal to the saturation current of the current mirror of the third current source, and the driving voltage is clamped; thus, after the load current reaches the rated value, the driving circuit is clamped by the current limiting circuit integrated inside the LDO, thereby limiting the current flowing through the power tube, without the need for an external feedback loop, with fast response speed, high stability and small layout area. In addition, when the load current increases, the first regulating current is output, which provides the possibility of establishing a feedback loop of the first regulating current, and improves the flexibility of the current limiting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0036] Figure 1 An exemplary circuit schematic diagram of a current limiting circuit applied to an LDO provided in an embodiment of the present application;

[0037] Figure 2 Another exemplary circuit schematic diagram of a current limiting circuit applied to an LDO provided in an embodiment of the present application;

[0038] Figure 3 A schematic diagram of the structure of an LDO provided in one embodiment of the present application;

[0039] Figure 4 Another partial exemplary circuit schematic diagram of a voltage and current amplifier circuit in an LDO provided in an embodiment of the present application;

[0040] Figure 5 Another partial exemplary circuit schematic diagram of a voltage amplifier circuit in an LDO provided in an embodiment of the present application;

[0041] Figure 6 A partial exemplary circuit schematic diagram of a voltage divider circuit in an LDO provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0043] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0044] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0045] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0046] Figure 1 The structure diagram of the current limiting circuit applied to LDO provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0047] The current limiting circuit applied to LDO is connected to the power tube, including a first current source Ir1, a second current source Ir2, a third current source Ir3, a fourth current source Ir4, a first P-channel metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS) tube Mp1, a second PMOS tube Mp2, a third PMOS tube Mp3 and a fourth PMOS tube Mp4.

[0048] The positive electrode of the second current source Ir2, the positive electrode of the fourth current source Ir4, the source of the second PMOS transistor Mp2 and the source of the fourth PMOS transistor Mp4 are commonly connected to the first power source VAA.

[0049] The gate of the second PMOS transistor Mp2 is connected to the drain of the second PMOS transistor Mp2, the cathode of the second current source Ir2, and the source of the first PMOS transistor Mp1.

[0050] The gate of the fourth PMOS tube Mp4, the drain of the fourth PMOS tube Mp4, the negative electrode of the fourth current source Ir4 and the source of the third PMOS tube Mp3 are connected and together constitute the driving voltage output end of the current limiting circuit, which is connected to the gate of the power tube to output the driving voltage Vp.

[0051] The gate of the first PMOS transistor Mp1, the drain of the first PMOS transistor Mp1, the gate of the third PMOS transistor Mp3 and the positive electrode of the first current source Ir1 are connected and together constitute a first regulating current output terminal of the current limiting circuit to output the first regulating current Iin1.

[0052] The drain of the third PMOS transistor Mp3 is connected to the positive electrode of the third current source Ir3 , and the negative electrode of the first current source Ir1 and the negative electrode of the third current source Ir3 are connected to the power ground.

[0053] It should be noted that the P-type power transistor MP and the fourth PMOS transistor Mp4 form a first current mirror.

[0054] It can be understood that the power tube is also connected to the load and the load capacitor Cload, wherein the current flowing through the load is the load current Iload.

[0055] The following is combined with the working principle Figure 1 The current limiting circuit shown is further explained:

[0056] when Figure 1 When the output voltage of the LDO has been established and the load current Iload is 0, the first regulating current Iin1 is 0. At this time, the gate voltage Vc of the first PMOS tube Mp1 and the gate voltage Vc of the third PMOS tube Mp3 are relatively high, and since the first current source Ir1 to the fourth current source I4 are usually MOS current mirrors, the third current source Ir3 is in the linear region.

[0057] Assuming that the currents flowing through the first current source Ir1 to the fourth current source I4 are equal to I1 to I4 respectively, and the currents flowing through the first PMOS transistor to the fourth PMOS transistor Mp4 are equal to Ip1 to Ip4 respectively, then

[0058] I3=I4+Ip4 <Ilimit

[0059] Wherein Ilimit is the saturation current of the current mirror of the third current source Ir3.

[0060] If the load current increases, the gate voltage Vp of the power tube decreases, and the drain voltage V LDO The current flowing through the fourth PMOS transistor Mp4 and the third PMOS transistor Mp3 increases with the load capacitance, so Vc decreases. At this time, the stable state of the circuit is broken, the first regulating current Iin1 increases and the current flows out of the current limiting circuit.

[0061] When the load current increases to a certain extent, I3 is equal to Ilimit, Vp is clamped, and the current flowing through the power tube Mp no longer increases. Assuming that the mirror ratio between the fourth PMOS tube Mp4 and the power tube is 1:m, the maximum current I of the power tube can be obtained. p,max :

[0062] I p,max =m·(I limit –I4)

[0063] If the load current continues to increase, the current flowing through the power tube Mp is still equal to I p,max , the additional current is provided by the load capacitor, the LDO loop (not shown in the figure) cannot work, and the output voltage V LDO is pulled to 0. At this time, the first regulating current Iin1 reaches the saturation value, the current flowing through Mp1 reaches the maximum value, and Vc is clamped.

[0064] In one embodiment, if Figure 1 As shown, the power tube is a P-type power tube MP; the drain of the P-type power tube Mp constitutes the output end of the LDO to output the output voltage V LDO ; The source of the P-type power tube MP is connected to the first power supply VAA; The gate of the P-type power tube MP is connected to the driving voltage Vp.

[0065] In one embodiment, if Figure 2 As shown, the power tube is an N-type power tube MN; the current limiting circuit applied to the LDO further includes a fifth PMOS tube Mp5 and a first N-channel metal oxide semiconductor (N-metal-oxide-semiconductor, NMOS) tube Mn1.

[0066] The gate of the fourth PMOS tube Mp4 is connected to the drain of the fourth PMOS tube Mp4, the negative electrode of the fourth current source Ir4, the source of the third PMOS tube Mp3 and the gate of the fifth PMOS tube Mp5. The source of the fifth PMOS tube Mp5 is connected to the first power supply VAA. The drain of the fifth PMOS tube Mp5, the gate of the first NMOS tube Mn1 and the drain of the first NMOS tube Mn1 are connected and together constitute the driving voltage output end of the current limiting circuit, which is connected to the gate of the N-type power tube Mn to output the driving voltage Vn. The source of the first NMOS tube Mn1 and the source of the N-type power tube Mn are connected and together constitute the output end of the LDO to output the output voltage V LDO ; The drain of the N-type power tube Mn is connected to the first power supply VAA; and the gate of the N-type power tube is connected to the driving voltage.

[0067] The N-type power transistor Mn and the first NMOS transistor Mn1 form a second current mirror, and the fifth PMOS transistor Mp5 and the fourth PMOS transistor Mp4 form a third current mirror.

[0068] It should be noted that in Figure 1 and Figure 2In the embodiment, the first current source Ir1, the second current source Ir2, the third current source Ir3 and the fourth current source Ir4 can all be bias currents mirrored from the reference current source, thereby ensuring the accuracy of the current limiting circuit.

[0069] The following is combined with the working principle Figure 2 The current limiting circuit shown is further explained:

[0070] Figure 2 and Figure 1 The difference is that Figure 2 A fourth current mirror (including the fifth PMOS tube Mp5 and the fourth PMOS tube Mp4) is added, and the fifth PMOS tube Mp5 and the first NMOS tube Mn1 are used to Figure 1 The driving voltage in the circuit is inverted.

[0071] when Figure 2 When the LDO output voltage has been established and the load current Iload is 0, the first regulating current Iin1 is 0. At this time, the gate voltage Vc of the first PMOS tube Mp1 and the gate voltage Vc of the third PMOS tube Mp3 are relatively high. Since the first current source Ir1 to the fourth current source I4 are usually MOS current mirrors, the third current source Ir3 is in the linear region.

[0072] Assuming that the currents flowing through the first current source Ir1 to the fourth current source I4 are equal to I1 to I4 respectively, and the currents flowing through the first PMOS transistor to the fourth PMOS transistor Mp4 are equal to Ip1 to Ip4 respectively, then

[0073] I3=I4+Ip4 limit

[0074] Among them I limit is the saturation current of the current mirror of the third current source Ir3.

[0075] If the load current increases, the gate voltage Vn of the power tube Mn increases, and the drain voltage V LDO The current flowing through the fifth PMOS tube Mp5 and the first NMOS tube Mn1 increases with the load capacitance, and the current flowing through the fourth PMOS tube Mp4 and the third PMOS tube Mp3 increases accordingly, so Vc decreases. At this time, the stable state of the current limiting circuit is broken, the first regulating current Iin1 increases, and the current flows out of the current limiting circuit.

[0076] When the load current increases to a certain extent, I3 is equal to Ilimit, Vn is clamped, and the current flowing through the power tube Mp no longer increases. Assuming that the mirror ratio between the fourth PMOS tube Mp4 and the fifth PMOS tube Mp5 is 1:m, and the mirror ratio between the first NMOS tube Mn1 and the power tube Mn is 1:n, the maximum current I of the power tube Mn can be obtained. n,max ​:

[0077] I n,max =m·n·(I limit –I4)

[0078] If the load current continues to increase, the current flowing through the power tube Mn is still equal to I n,max , the additional current is provided by the load capacitor, the LDO loop (not shown in the figure) cannot work, and the output voltage V LDO is pulled to 0. At this time, the first regulating current Iin1 reaches the saturation value, the current flowing through Mp1 reaches the maximum value, and Vc is clamped.

[0079] The embodiment of the present application also provides an LDO, which includes a power tube and the above-mentioned current limiting circuit applied to the LDO.

[0080] like Figure 3 As shown, the above LDO further includes a voltage and current amplifying circuit 02 , a voltage amplifying circuit 03 and a voltage dividing circuit 04 .

[0081] The voltage-current amplifying circuit 02 is connected to the current limiting circuit and is configured to output a first regulating voltage according to the first regulating current.

[0082] The voltage amplifier circuit 03 is connected to the voltage-current amplifier circuit 02 and is configured to output a first feedback voltage according to a reference voltage and a first adjustment voltage.

[0083] The voltage divider circuit 04 is connected to the power tube and the voltage amplifier circuit 03 and is configured to output an output voltage based on the feedback voltage.

[0084] By establishing the feedback loop of the first regulating current, the output voltage follows the change of the first regulating current, thereby reducing the output voltage V when the load current increases. LDO , thereby reducing the load current and improving the stability of the LDO output.

[0085] It is worth emphasizing that the voltage divider circuit 04 is also configured to output the voltage V LDO Sampling is performed to output a second feedback voltage.

[0086] The voltage amplifying circuit 03 is further configured to output a second regulated voltage according to the reference voltage and the second feedback voltage.

[0087] The voltage and current amplification circuit 02 is further configured to output a second regulated current according to the second regulated voltage;

[0088] Among them, the gate of the first PMOS transistor Mp1, the drain of the first PMOS transistor Mp1, the gate of the third PMOS transistor Mp3 and the positive electrode of the first current source Ir1 are connected and together constitute the second regulating current input terminal of the current limiting circuit to access the second regulating current.

[0089] By establishing the above-mentioned output voltage feedback loop, the second regulating current follows the output voltage change and the driving voltage changes with the second regulating current. Therefore, when the output voltage increases and the third current source Ir3 is not saturated, the output current is reduced by the current limiting circuit, and then the output voltage is reduced, forming a stable LDO negative feedback loop.

[0090] Figure 4 A partial exemplary circuit structure of a voltage and current amplifier circuit in an LDO provided by an embodiment of the present invention is shown. Figure 5 FIG. 1 shows a partial exemplary circuit structure of a voltage amplifier circuit in an LDO provided by an embodiment of the present invention. Figure 6 A partial exemplary circuit structure of a voltage divider circuit in an LDO provided by an embodiment of the present invention is shown. For ease of explanation, only the part related to the embodiment of the present invention is shown, which is described in detail as follows:

[0091] like Figure 4 As shown, the voltage and current amplifier circuit 02 includes a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a seventh field effect transistor M7, an eighth field effect transistor M8 and a ninth field effect transistor M9.

[0092] The sources of the seventh field effect transistor M7, the eighth field effect transistor M8 and the ninth field effect transistor M9 are connected to the fourth power supply VDD. The drain of the ninth field effect transistor M9 is connected to the sources of the fifth field effect transistor M5 and the sixth field effect transistor M6.

[0093] The gate of the fifth field effect transistor M5 and the gate of the sixth field effect transistor M6 serve together as the first regulated voltage output terminal and the second regulated voltage input terminal of the voltage and current amplifier circuit 02, and are connected to the voltage amplifier circuit 03 to access the second regulated voltage or output the first regulated voltage.

[0094] The drain of the fifth field effect transistor M5 is connected to the drain of the first field effect transistor M1, the gate of the first field effect transistor M1 and the gate of the fourth field effect transistor M4, the drain of the sixth field effect transistor M6 is connected to the drain of the second field effect transistor M2, the gate of the second field effect transistor M2 and the gate of the third field effect transistor M3, and the gate of the seventh field effect transistor M7 is connected to the drain of the seventh field effect transistor M7, the drain of the third field effect transistor M3 and the gate of the eighth field effect transistor M8.

[0095] The drain of the eighth field effect transistor M8 is connected to the drain of the fourth field effect transistor M4 and constitutes the first regulating current input terminal of the voltage-current amplifier circuit 02 and the second regulating current output terminal of the voltage-current amplifier circuit 02, and is connected to the current limiting circuit to receive the first regulating current or output the second regulating current.

[0096] The source of the first field effect transistor M1 , the source of the second field effect transistor M2 , the source of the third field effect transistor M3 , and the source of the fourth field effect transistor M4 are connected to the power ground.

[0097] like Figure 5 As shown, the voltage amplifier circuit 03 includes a fifth current source I5, a tenth field effect transistor M10, an eleventh field effect transistor M11, a twelfth field effect transistor M12, a thirteenth field effect transistor M13, a first resistor R1 and a second resistor R2.

[0098] The source of the tenth field effect transistor M10 and the source of the tenth field effect transistor M1 are commonly connected to the fifth power source VEE.

[0099] The gate of the tenth field effect transistor M10 is connected to the drain of the tenth field effect transistor M10 , the anode of the fifth current source I5 , and the gate of the eleventh field effect transistor M11 .

[0100] The drain of the eleventh field effect transistor M11 is connected to the source of the twelfth field effect transistor M12 and the source of the thirteenth field effect transistor M13 .

[0101] The gate of the eleventh field effect transistor M11 forms a reference voltage input terminal of the voltage amplifier circuit 03 to receive the reference voltage.

[0102] The gate of the twelfth field effect transistor M12 constitutes the first feedback voltage output terminal of the voltage amplifier circuit 03 and the second feedback voltage input terminal of the voltage amplifier circuit 03 , and is connected to the voltage divider circuit 04 to receive the second feedback voltage or output the first feedback voltage.

[0103] The drain of the twelfth field effect transistor M12, the first end of the first resistor R1, the drain of the thirteenth field effect transistor M13 and the first end of the second resistor R2 together constitute the first regulating voltage input end of the voltage amplifier circuit 03 and the second regulating voltage output end of the voltage amplifier circuit 03, which are connected to the voltage-current amplifier circuit 02 and receive the first regulating voltage or output the second regulating voltage.

[0104] A cathode of the fifth current source I5 , a second end of the first resistor R1 , and a second end of the second resistor R2 are commonly connected to a power ground.

[0105] like Figure 6 As shown, the voltage divider circuit 04 includes a third resistor R3 and a fourth resistor R4.

[0106] The first end of the third resistor R3 constitutes the output voltage output end of the voltage divider circuit 04 and the output voltage input end of the voltage divider circuit 04, and is connected to the power tube to access the output voltage or output the output voltage.

[0107] The second end of the third resistor R3 and the first end of the fourth resistor R4 are connected and together constitute a first feedback voltage input end and a second feedback voltage output end of the voltage divider circuit 04, and are connected to the voltage amplifier circuit 03 to access the first feedback voltage or output the second feedback voltage.

[0108] A second end of the fourth resistor R4 is connected to the power ground.

[0109] The following is a combination of working principles Figure 1 , Figures 4 to 6 As shown for further explanation:

[0110] Figure 1 , Figures 4 to 6 The circuit shown works in two ways.

[0111] The first case is as follows: when the load current Iload increases, the current limiting circuit outputs the first regulating current Iin1 to the first regulating current input terminal of the voltage-current amplifier circuit 02, the first field effect tube M1 and the second field effect tube M2 have the same size, the third field effect tube M3 and the fourth field effect tube M4 have the same size, and the seventh field effect tube M7 and the eighth field effect tube M8 have the same size. When the first regulating current Iin1 flows into the voltage-current amplifier circuit 02, the current of the eighth field effect tube M8 is less than the current of the fourth field effect tube M4. According to the current mirror relationship, the current of the first field effect tube M1 is greater than the current of the second field effect tube M2. Therefore, the gate voltage Vop of the fifth field effect transistor M5 increases relative to the gate voltage Von of the sixth field effect transistor M6, and the voltage difference (the voltage difference between the gate voltage Vop of the fifth field effect transistor M5 and the gate voltage Von of the sixth field effect transistor M6) is the first adjustment voltage (Vop1 and Von1). The first adjustment voltage (Vop1 and Von1) is input to the first adjustment voltage input terminal of the voltage amplifier circuit 03. Since the drain voltage of the thirteenth field effect transistor M13 is greater than the drain voltage of the twelfth field effect transistor M12, the gate voltage of the thirteenth field effect transistor M13 is less than the gate voltage of the twelfth field effect transistor M12, that is, the gate of the thirteenth field effect transistor M13 outputs the reduced first feedback voltage Vfb1 to the first feedback voltage input terminal of the voltage divider circuit 04, so that the voltage divider circuit 04 outputs the reduced output voltage V from the first end of the third resistor R3. LDO , thereby reducing the load current.

[0112] The second case is as follows: When the output voltage V LDOWhen the current increases, the voltage divider circuit 04 outputs the increased second feedback voltage Vfb2 to the second feedback voltage input terminal of the voltage amplifier circuit 03, the gate voltage of the thirteenth field effect transistor M13 is greater than the gate voltage of the twelfth field effect transistor M12, the drain voltage of the thirteenth field effect transistor M13 is less than the drain voltage of the twelfth field effect transistor M12, and the voltage difference (the voltage difference between the drain voltage of the thirteenth field effect transistor M13 and the drain voltage of the twelfth field effect transistor M12) is the second adjustment voltage (Vop2 and Von2), and the second adjustment voltage (Vop2 and Von2) is input to the voltage and current amplifier circuit 02 The second regulating voltage input terminal of the fifth field effect tube M5, the gate voltage Vop2 of the fifth field effect tube M5 is reduced relative to the gate voltage Von2 of the sixth field effect tube M6, the first field effect tube M1 and the second field effect tube M2 are of the same size, the third field effect tube M3 and the fourth field effect tube M4 are of the same size, the seventh field effect tube M7 and the eighth field effect tube M8 are of the same size, so according to the current mirror relationship, it can be known that the current of the eighth field effect tube M8 is less than the current of the fourth field effect tube M4, and the voltage-current amplifier circuit 02 outputs the second regulating current Iin2 to the current limiting circuit (the second regulating current Iin2 is a negative value). When the third current source Ir3 is not saturated, the driving voltage is increased through the current limiting circuit, thereby reducing the output current, thereby reducing the output voltage V LDO , forming a stable LDO negative feedback loop.

[0113] An embodiment of the present invention further provides a chip, which includes the above-mentioned LDO.

[0114] An embodiment of the present invention further provides an electronic device, which includes the above-mentioned LDO.

[0115] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0116] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A current limiting circuit applied to LDO, connected to a power tube, characterized in that: It includes a first current source, a second current source, a third current source, a fourth current source, a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; The positive electrode of the second current source, the positive electrode of the fourth current source, the source electrode of the second PMOS tube and the source electrode of the fourth PMOS tube are connected to the first power supply; The gate of the second PMOS tube is connected to the drain of the second PMOS tube, the negative electrode of the second current source and the source of the first PMOS tube; The gate of the fourth PMOS tube, the drain of the fourth PMOS tube, the negative electrode of the fourth current source and the source of the third PMOS tube are connected and together constitute the driving voltage output end of the current limiting circuit, which is connected to the gate of the power tube to output the driving voltage; The gate of the first PMOS tube, the drain of the first PMOS tube, the gate of the third PMOS tube and the positive electrode of the first current source are connected and together constitute a first regulating current output end of the current limiting circuit to output a first regulating current; The drain of the third PMOS tube is connected to the positive electrode of the third current source, and the negative electrode of the first current source and the negative electrode of the third current source are connected to the power ground.

2. The current limiting circuit for LDO according to claim 1, characterized in that: The power tube is a P-type power tube; The drain of the P-type power tube constitutes the output end of the LDO to output the output voltage; The gate of the P-type power tube is connected to the driving voltage.

3. The current limiting circuit applied to LDO as claimed in claim 2, characterized in that: The P-type power tube and the fourth PMOS tube form a first current mirror.

4. The current limiting circuit for LDO according to claim 1, characterized in that: The power tube is an N-type power tube; The current limiting circuit applied to the LDO further includes a fifth PMOS tube and a first NMOS tube; The gate of the fourth PMOS tube is connected to the drain of the fourth PMOS tube, the negative electrode of the fourth current source, the source of the third PMOS tube and the gate of the fifth PMOS tube, the source of the fifth PMOS tube is connected to the first power supply, the drain of the fifth PMOS tube, the gate of the first NMOS tube and the drain of the first NMOS tube are connected and together constitute the driving voltage output end of the current limiting circuit, and is connected to the gate of the N-type power tube to output the driving voltage; The source of the first NMOS tube and the source of the N-type power tube are connected and together constitute the output end of the LDO to output an output voltage; The drain of the N-type power tube is connected to the first power supply; The gate of the N-type power tube is connected to the driving voltage.

5. The current limiting circuit applied to LDO as claimed in claim 4, characterized in that: The N-type power tube and the first NMOS tube form a second current mirror, and the fifth PMOS tube and the fourth PMOS tube form a third current mirror.

6. The current limiting circuit for LDO according to claim 1, characterized in that: The first current source, the second current source, the third current source and the fourth current source are bias currents mirrored from a reference current source.

7. An LDO, characterized in that: The LDO comprises a power tube and a current limiting circuit applied to the LDO as claimed in any one of claims 1 to 6.

8. The LDO according to claim 7, wherein: Also includes: a voltage-current amplifying circuit, connected to the current limiting circuit, and configured to output a first regulating voltage according to the first regulating current; a voltage amplifier circuit, connected to the voltage-current amplifier circuit, and configured to output a first feedback voltage according to a reference voltage and the first adjustment voltage; The voltage divider circuit is connected to the power tube and the voltage amplifier circuit, and is configured to output an output voltage based on the feedback voltage.

9. The LDO according to claim 8, wherein: The voltage divider circuit is further configured to sample the output voltage to output a second feedback voltage; The voltage amplification circuit is further configured to output a second regulated voltage according to the reference voltage and the second feedback voltage; The voltage-current amplification circuit is further configured to output a second regulated current according to the second regulated voltage; Among them, the gate of the first PMOS tube, the drain of the first PMOS tube, the gate of the third PMOS tube and the positive electrode of the first current source are connected and together constitute the second regulating current input terminal of the current limiting circuit to access the second regulating current.

10. An electronic device, characterized in that: The electronic device comprises the LDO as claimed in any one of claims 7 to 9.

11. A chip, characterized in that: The chip comprises the LDO as claimed in any one of claims 7 to 9.

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