High-precision current limiting circuit of LDO with NMOS tube as power tube

Abstract

The invention provides a high-precision current limiting circuit of an LDO (Low Dropout Regulator) with an NMOS (N-channel Metal Oxide Semiconductor) tube as a power tube, which is applied to the technical field of current limiting circuits and comprises a voltage loop and a current loop, and the voltage loop is used for monitoring and stabilizing the output voltage VOUT of a power tube NM1; and the current loop is used for acquiring a sampling current according to the load current of the power tube NM1, comparing the sampling current with a reference current IREF, and when the sampling current is higher than the reference current IREF, driving and controlling the output voltage VOUT of the power tube NM1 to be reduced so as to limit the load current of the power tube NM1 to continue to rise. When the LDO works normally, the output voltage VOUT of the power tube NM1 is stabilized through the voltage loop, and when the load current is too high, the output voltage VOUT of the power tube NM1 is driven and controlled to be reduced through the current loop, so that the load current of the power tube NM1 is prevented from continuing to rise, and the stability and the safety of the LDO are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of current limiting circuits, and in particular relates to a high-precision current limiting circuit of an LDO whose power tube is an NMOS tube. Background Art

[0002] In circuit design, different DC voltages are usually required to power different devices. Among them, the most common is to use LDO voltage regulator chips to achieve different DC voltage outputs. Due to its low cost, good performance, and convenient use, the application of low-dropout linear regulators (hereinafter referred to as LDO) is increasing. In order to prevent the LDO load current from being too large and damaging the chip, the LDO load current needs to be limited.

[0003] The Chinese invention patent with the announcement number CN117519395A discloses a current limiting circuit applied to LDO. By integrating the current limiting function into the LDO loop, no resistance is added in the VDD to OUT path, so that the circuit can work at a lower power supply voltage, has a fast response speed, and a simple circuit structure. Specifically, it includes a second PMOS tube used as a power tube, the drain of the second PMOS tube is connected to the output voltage OUT terminal, the source of the second PMOS tube is connected to the power supply voltage VDD terminal, and the gates of the second PMOS tube and the first PMOS tube are interconnected and connected to the first PMOS tube. The drain of the S tube and the drain of the third NMOS tube, the source of the first PMOS tube and the input of the reference current source Iref are all connected to the power supply voltage VDD terminal, the third NMOS tube is interconnected with the gate of the second NMOS tube and then connected to the drain of the second NMOS tube and the output of the reference current source Iref respectively, the source of the third NMOS tube is interconnected with the second NMOS tube and then connected to the drain of the first NMOS tube, the gate of the first NMOS tube is connected to the output terminal of the error amplifier, the source is grounded, the positive input terminal of the error amplifier is connected to the reference voltage terminal, and the negative input terminal is connected to the output voltage OUT terminal.

[0004] The above invention patent is applied to LDO with PMOS as the power tube. Because the source of PMOS is connected to the power supply, the drive circuit design is relatively easy. However, PMOS is hole conductive, and the area is 2 to 3 times that of NMOS under the same current capacity. If NMOS is used, the gate to output is an emitter follower, unlike PMOS which is a common source amplification. Therefore, in addition to its small area, NMOS has natural advantages over PMOS in transient response and stability as the power tube. As the current of LDO is getting larger and larger, the voltage difference requirements of LDO are getting higher and higher. In many ultra-low voltage difference applications, NMOS is increasingly used as a power tube.

[0005] When the PMOS power tube works in the saturation region, the current formula is as follows: Ip = 0.5*up*COXp*Wp / Lp*(VSG-VTHp)*(VSG-VTHp), where up is the hole mobility, COXp is the gate oxide thickness, VTHp is the threshold voltage of PMOS, Wp and Lp are the width and length of PMOS, which are all determined parameters under the selected process. Therefore, the current size is related to the gate-source voltage. Since the source of PMOS is connected to the power supply VDD, when monitoring the current of the PMOS power tube, the source of the sampling tube is naturally connected to VDD. You only need to connect the gate of the sampling tube and the gate of the power tube to the same potential to achieve accurate sampling of the power tube current.

[0006] However, the drain of NMOS is connected to the power supply VDD, and the source is connected to the output VOUT. The current size In=0.5*un*COXn*Wn / Ln*(VGS-VTHn)*(VGS-VTHn), where un is the electron mobility, COXn is the gate oxide thickness, VTHn is the threshold voltage of NMOS, Wn and Ln are the width and length of NMOS, which are all determined parameters under the selected process. How to connect the source of the sampling tube to achieve accurate sampling of the current of the NMOS power tube and prevent the NMOS power tube from burning out when the current is too large is the problem we need to solve. Summary of the invention

[0007] In view of the above problems in the prior art, the purpose of the present invention is to provide a high-precision current limiting circuit for an LDO whose power tube is an NMOS tube. When the LDO is working normally, the output voltage V of the power tube NM1 is stabilized by a voltage loop. OUT When the load current is too high, the output voltage V of the power tube NM1 is controlled by the current loop. OUT Reduced, thereby limiting the load current of the power tube NM1 from continuing to increase, thereby improving the stability and safety of the LDO.

[0008] A high-precision current limiting circuit of an LDO whose power tube is an NMOS tube, comprising a voltage loop and a current loop, wherein the voltage loop is used to monitor and stabilize the output voltage V of the power tube NM1 OUT ; The output voltage V of the power tube NM1 OUT The voltage after the voltage divider network is divided by the error amplifier ERR1 and the reference voltage V REF By comparison, the error amplifier ERR1 output controls the gate of the power tube NM1 to stabilize the output voltage V of the power tube NM1. OUT At the preset value; the current loop is used to obtain the sampling current according to the load current of the power tube NM1, and compare the sampling current with the reference current I REF For comparison, when the sampling current is higher than the reference current I REFThe output voltage V of the driving control power tube NM1 is OUT The current loop includes an error amplifier ERR2, a sampling tube NM2, a MOS tube NM3 and a MOS tube NM4. The gate of the sampling tube NM2 is connected to the output end of the error amplifier ERR1, and the drain of the sampling tube NM2 is connected to the power supply voltage V DD The source of the sampling tube NM2 is connected to the drain of the MOS tube NM3 and connected to one input end of the error amplifier ERR2. The other input end of the error amplifier ERR2 is connected to the output voltage V of the power tube NM1. OUT The output end of the error amplifier ERR2 is connected to the gate of the MOS tube NM3 and the gate of the MOS tube NM4. The source of the MOS tube NM3 and the source of the MOS tube NM4 are grounded, and the drain of the MOS tube NM4 is connected to the current source.

[0009] Preferably, the current loop further includes a MOS tube NM5, the sampling tube NM2 and the power tube NM1 form a mirror structure to obtain a mirror sampling current of the load current of the power tube NM1, the MOS tube NM4 and the MOS tube NM3 form a mirror structure, the current of the sampling tube NM2 flows through the MOS tube NM3 and is mirror sampled by the MOS tube NM4; the mirror sampling current of the MOS tube NM4 is compared with the reference current I output by the current source REF For comparison, the source of the MOS tube NM5 is connected to form a common gate amplification structure, and the gate of the MOS tube NM5 is connected to the reference voltage V REF , the drain of MOS tube NM5 is connected to the gate of power tube NM1 and the gate of sampling tube NM2 respectively; when the current of MOS tube NM4 is greater than the reference current I output by the current source REF When MOS tube NM5 is turned on, the drain potential of MOS tube NM5 is reduced, thereby lowering the output voltage V of power tube NM1. OUT , to realize the function of reducing the load current of power tube NM1.

[0010] Preferably, the sampling current of the sampling tube NM2 is set to 1 / K of the load current of the power tube NM1, and the current of the MOS tube NM4 is 1 / N of the current of the MOS tube NM3. Then, the current of the MOS tube NM4 is 1 / K*N of the load current of the power tube NM1. Then, the current limit value I of the load current of the power tube NM1 is limt For I REF *K*N.

[0011] Preferably, the voltage divider network includes resistors R1 and R2, and the drain of the power tube NM1 is connected to the power supply voltage V DD , the output voltage V of the power tube NM1 OUTConnect one end of resistor R2 and one end of load resistor RL. The other end of load resistor RL is grounded. The other end of resistor R2 is connected to resistor R1 and connected to the negative input end of error amplifier ERR1. The other end of resistor R1 is grounded. The positive input end of error amplifier ERR1 is connected to reference voltage V REF The output end of the error amplifier ERR1 is connected to the gate of the power tube NM1 and the gate of the sampling tube NM2.

[0012] Preferably, the output voltage V of the power tube NM1 is OUT The preset value is (1+R2 / R1)*V REF .

[0013] The beneficial effects of the present invention are as follows: the high-precision current limiting circuit of the LDO whose power tube is an NMOS tube stabilizes the output voltage of the power tube NM1 through the voltage loop when the LDO works normally; when the load current is too high, the output voltage of the power tube NM1 is controlled to decrease through the current loop drive, thereby limiting the load current of the power tube NM1 from continuing to increase, thereby improving the stability and safety of the LDO.

[0014] Furthermore, according to the characteristics of the NMOS tube, the output end of the error amplifier ERR1 controls the power tube NM1 and the sampling tube NM2 at the same time, thereby ensuring that the source potential of the sampling tube NM2 keeps the same potential as the output voltage of the power tube NM1, so that the sampling tube NM2 can accurately copy the load current of the power tube NM1. Similarly, the current of the MOS tube NM3 is mirrored by the MOS tube NM4 to achieve accurate sampling, which can effectively improve the current limiting accuracy.

[0015] In addition, through the circuit design of sampling tube NM2, MOS tube NM3, and MOS tube NM4, the current limit value is I REF *K*N, the current limiting value is only related to the ratio between the reference current and the MOS tube, which can greatly reduce the influence of ambient temperature, component parameters, etc. on the current limiting accuracy of the current limiting circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0017] Figure 1 It is a circuit diagram of the present invention. DETAILED DESCRIPTION

[0018] like Figure 1As shown, a high-precision current limiting circuit of an LDO whose power tube is an NMOS tube includes a power tube NM1, a sampling tube NM2, a MOS tube NM3, a MOS tube NM4, a MOS tube NM5, a resistor R1, a resistor R2, a load resistor RL, an error amplifier ERR1, an error amplifier ERR2, and a reference voltage V REF and current source. It should be noted that the MOS tubes in this embodiment are all NMOS tubes.

[0019] On the one hand, the power tube NM1, the sampling tube NM2, the resistor R1, the resistor R2, the error amplifier ERR1 and the reference voltage V REF A voltage loop is formed to monitor and stabilize the output voltage V of the power tube NM1. OUT .

[0020] like Figure 1 As shown, the drain of the power tube NM1 and the drain of the sampling tube NM2 are connected to the power supply voltage V DD , the source output voltage of power tube NM1 is V OUT , output voltage V OUT The negative input terminal of the error amplifier ETT2, one end of the resistor R2, and one end of the load resistor RL are connected to the ground. The other end of the resistor R2 is connected to the resistor R1 and connected to the negative input terminal of the error amplifier ERR1. The other end of the resistor R1 is grounded. The positive input terminal of the error amplifier ERR1 is connected to the reference voltage V REF The output end of the error amplifier ERR1 is connected to the gate of the power tube NM1 and the gate of the sampling tube NM2.

[0021] Specifically, resistors R1 and R2 form a voltage divider network to divide the output voltage V OUT After voltage division, a lower voltage is obtained, and the voltage is added to the reference voltage V REF Connect to the error amplifier ERR1, and the reference voltage V REF With output voltage V OUT The error between the divided voltages is amplified and the gate of the power tube NM1 and the gate of the sampling tube NM2 are output controlled, and the output voltage V OUT Stable at the preset value, V OUT =(1+R2 / R1)*V REF .

[0022] In the voltage loop, the negative input terminal of the error amplifier ERR1 is connected to the voltage divider network composed of resistors R1 and R2 to detect the output voltage V of the power tube NM1. OUT The voltage divider value is connected to the reference voltage V REFThe voltage division value is detected and judged, and the output voltage V is monitored. OUT Whether it deviates from the set value. Then the error amplifier ERR1 is used to determine whether the output voltage V OUT The voltage divider and the reference voltage V REF The error between them outputs a control voltage to adjust the power tube NM1, thereby adjusting the conduction state of the power tube NM1 to adjust its output voltage V OUT size.

[0023] In addition, the sampling tube NM2 is used to sample the load current. The gate voltage of the sampling tube NM2 is adjusted by the error amplifier ERR1 to ensure that the source potential of the sampling tube NM2 is consistent with the output voltage V of the power tube NM1. OUT Keep it consistent so that the sampling current of the sampling tube NM2 can accurately replicate the load current of the power tube NM1 to achieve current sampling.

[0024] On the other hand, the sampling tube NM2, the MOS tube NM3, the MOS tube NM4, the MOS tube NM5, the error amplifier ERR2 and the current source form a current loop, which is used to limit the load current of the power tube NM1 to not exceed the current limit value I limt , to prevent the load current from continuing to increase and damaging the chip.

[0025] like Figure 1 As shown, the source of the sampling tube NM2 and the drain of the MOS tube NM3 are connected and connected to the positive input terminal of the error amplifier ERR2. The output terminal of the error amplifier ERR2 is connected to the gate of the MOS tube NM3 and the gate of the MOS tube NM4. The source of the MOS tube NM3 and the source of the MOS tube NM4 are grounded. The drain of the MOS tube NM4 is connected to the source of the MOS tube NM5 and the current source respectively. The other end of the current source is connected to the power supply voltage V DD , the output current of the current source is the reference current I REF , the gate of MOS tube NM5 is connected to the reference voltage V REF The drain of the MOS tube NM5 is connected to the gate of the power tube NM1 and the gate of the sampling tube NM2.

[0026] Through the mirror structure of power tube NM1 and sampling tube NM2, sampling tube NM2 samples the load current of power tube NM1. Since the current of sampling tube NM2 flows through MOS tube NM3, through the mirror structure of MOS tube NM3 and MOS tube NM4, MOS tube NM4 mirrors the current of MOS tube NM3. Compare the mirror current of MOS tube NM4 with the reference current I REF Compare and connect to the source of MOS tube NM5 to form common gate amplification. When the current of MOS tube NM4 is greater than the reference current I REFWhen the drain potential of MOS tube NM4 decreases, the source potential of MOS tube NM5 decreases. At this time, MOS tube NM5 is turned on, and the drain potential of MOS tube NM5 decreases, thereby lowering the output voltage V of power tube NM1. OUT , thereby reducing the load current of the power tube NM1 and achieving current limiting operation. Therefore, the reference current I REF The size of the load current of the power tube NM1 can be accurately controlled by the size of the load current of the power tube NM1.

[0027] Specifically, the sampling current of the sampling tube NM2 is set to 1 / K of the load current of the power tube NM1, and the current of the MOS tube NM4 is set to 1 / N of the current of the MOS tube NM3, then the load current of the power tube NM1 is limited to the preset current limit value I limt The following, among which, I limt =I REF *K*N.

[0028] The power tube is a high-precision current limiting circuit of the LDO of the NMOS tube. When the load current of the power tube NM1 is small and does not reach the set current limit value I limt When the source of MOS tube NM5 is at a high potential, the current loop does not work and the output voltage V OUT Rely on the voltage loop to stabilize at the set output value.

[0029] When the load resistance RL decreases, the load current of the power tube NM1 increases to reach the set current limit value I limt , the drain of MOS tube NM4 becomes low level, and MOS tube NM5 is turned on to pull down the gate potential of power tube NM1, so that the output voltage V OUT Reduce, thereby reducing the load current and preventing the load current from continuing to increase and damaging the chip. At this time, through the combined action of the voltage loop and the current loop, the load current is limited to below the preset value.

[0030] It should be noted that according to the current limit value I limt With reference current I REF The relationship I limt =I REF *K*N, we know that the current limit value I limt Only and reference current I REF And the ratio K and N between MOS tubes, where K and N can be achieved by using good device matching in the layout, and the current source is little affected by its process, power supply voltage, and temperature, so only the reference current I needs to be set. REF The value of can accurately limit the load current and is less affected by environmental factors.

[0031] Working principle: This power tube is a high-precision current limiting circuit of the LDO of the NMOS tube. When the low voltage drop linear regulator works normally, it starts to carry load but the load current is less than the set current limit value I limt When the current loop current limiting function is not started, the output voltage V of the power tube NM1 is controlled by the voltage loop. OUT Monitor and control the output voltage V of power tube NM1 through output OUT The gate voltage of the sampling tube NM2 is controlled to ensure that the source potential of the sampling tube NM2 is consistent with the output voltage V of the power tube NM1. OUT Keep it consistent so that the sampling current of the sampling tube NM2 can accurately replicate the load current of the power tube NM1 to achieve current sampling.

[0032] When the load resistance RL decreases, the load current of the power tube NM1 increases to reach the set current limit value I limt , the drain of MOS tube NM4 becomes low level, and MOS tube NM5 is turned on to pull down the gate potential of power tube NM1, so that the output voltage V OUT Reduce, thereby reducing the load current and preventing the load current from continuing to increase and damaging the chip.

[0033] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention is described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A high-precision current limiting circuit for an LDO whose power tube is an NMOS tube, characterized in that: It includes a voltage loop and a current loop. The voltage loop is used to monitor and stabilize the output voltage V of the power tube NM1. OUT ; The output voltage V of the power tube NM1 OUT The voltage after the voltage divider network is divided by the error amplifier ERR1 and the reference voltage V REF By comparison, the error amplifier ERR1 output controls the gate of the power tube NM1 to stabilize the output voltage V of the power tube NM1. OUT At preset value; The current loop is used to obtain a sampled current according to the load current of the power tube NM1, and compare the sampled current with the reference current I REF For comparison, when the sampling current is higher than the reference current I REF The output voltage V of the driving control power tube NM1 is OUT Reduce, thereby limiting the load current of the power tube NM1 from continuing to increase; The current loop includes an error amplifier ERR2, a sampling tube NM2, a MOS tube NM3 and a MOS tube NM4. The gate of the sampling tube NM2 is connected to the output end of the error amplifier ERR1, and the drain of the sampling tube NM2 is connected to the power supply voltage V DD The source of the sampling tube NM2 is connected to the drain of the MOS tube NM3 and connected to one input end of the error amplifier ERR2. The other input end of the error amplifier ERR2 is connected to the output voltage V of the power tube NM1. OUT The output end of the error amplifier ERR2 is connected to the gate of the MOS tube NM3 and the gate of the MOS tube NM4. The source of the MOS tube NM3 and the source of the MOS tube NM4 are grounded, and the drain of the MOS tube NM4 is connected to the current source.

2. The high-precision current limiting circuit of the LDO in which the power tube is an NMOS tube according to claim 1 is characterized in that: The current loop further includes a MOS tube NM5, the sampling tube NM2 and the power tube NM1 form a mirror structure to obtain a mirror sampling current of the load current of the power tube NM1, the MOS tube NM4 and the MOS tube NM3 form a mirror structure, and the current of the sampling tube NM2 flows through the MOS tube NM3 and is mirror sampled by the MOS tube NM4; The mirror sampling current of MOS tube NM4 and the reference current I output by the current source REF For comparison, the source of the MOS tube NM5 is connected to form a common gate amplification structure, and the gate of the MOS tube NM5 is connected to the reference voltage V REF , the drain of the MOS tube NM5 is connected to the gate of the power tube NM1 and the gate of the sampling tube NM2 respectively; When the current of MOS tube NM4 is greater than the reference current I output by the current source REF When MOS tube NM5 is turned on, the drain potential of MOS tube NM5 is reduced, thereby lowering the output voltage V of power tube NM1. OUT , to realize the function of reducing the load current of power tube NM1.

3. The high-precision current limiting circuit of the LDO in which the power tube is an NMOS tube according to claim 2, characterized in that: The sampling current of the sampling tube NM2 is set to 1 / K of the load current of the power tube NM1, and the current of the MOS tube NM4 is set to 1 / N of the current of the MOS tube NM3. Then the current of the MOS tube NM4 is 1 / K*N of the load current of the power tube NM1. The current limit value I of the load current of the power tube NM1 is limt For I REF *K*N.

4. The high-precision current limiting circuit of the LDO in which the power tube is an NMOS tube according to claim 1, characterized in that: The voltage divider network includes resistors R1 and R2. The drain of the power tube NM1 is connected to the power supply voltage V DD , the output voltage V of the power tube NM1 OUT Connect one end of resistor R2 and one end of load resistor RL. The other end of load resistor RL is grounded. The other end of resistor R2 is connected to resistor R1 and connected to the negative input end of error amplifier ERR1. The other end of resistor R1 is grounded. The positive input end of error amplifier ERR1 is connected to reference voltage V REF The output end of the error amplifier ERR1 is connected to the gate of the power tube NM1 and the gate of the sampling tube NM2.

5. The high-precision current limiting circuit of the LDO whose power tube is an NMOS tube according to claim 1, characterized in that: The output voltage V of the power tube NM1 OUT The preset value is (1+R2 / R1)*V REF .

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