A power chip automatic testing method and testing system

Abstract

The present invention discloses an automatic testing method and a testing system for a power chip. After generating and importing a test document, the method and the testing system can automatically complete the setting of instrument parameters, the reading, judgment and real-time display of test results, and fill the final test results into the test document. During the entire testing process, the tester does not need to understand the instrument parameter setting commands and the writing specifications of the test document. The tester only needs to configure the instrument parameters according to the prompts of the visual instrument control terminal interface, and generate a test file that can be recognized by the software test terminal with one key. The tester does not need to manually calibrate the instrument parameters for multiple times. The automatic testing system supports software self-calibration, and realizes self-calibration of predetermined voltage, current value and transient load jump through multi-instrument joint adjustment and parameter judgment, thereby ensuring that the test results are accurate and reliable.

Description

Technical Field

[0001] The present invention relates to the technical field of power chip testing, and in particular to an automatic testing method and a testing system for a power chip. Background Art

[0002] The power chip is responsible for the conversion, distribution, detection and other power management of electric energy in the electronic equipment system. The power chip is mainly used to power the subsequent devices. Its basic functional indicators can be measured through the input voltage pin and the output voltage pin. When testing the power chip, commonly used test instruments include DC power supply, electronic load, multimeter and oscilloscope.

[0003] Normally, each instrument needs to be configured to a specific state to perform the index test of the power chip, and the tester also needs to change the test topology to meet the test requirements of different indicators of the power chip. The index test of the power chip includes a variety of static indicators, which requires the tester to repeatedly adjust each instrument and change the test topology to complete the test of various indicators of the power chip.

[0004] At the same time, each instrument needs to be manually calibrated before each test, and the entire testing process will be very cumbersome and inefficient.

[0005] In addition, the hardware of existing test systems often does not support dynamic indicator testing of power chips, and is unable to provide the power chip with the jump voltage and jump AC load required for testing in a single test. Summary of the invention

[0006] The purpose of the present invention is to provide a power chip automatic testing method and testing system in view of the problems existing in the prior art. The method solves the above-mentioned technical problems by providing a complete testing method and hardware platform, and meets the needs of automatic testing of static and dynamic indicators of power chips.

[0007] To achieve the above object, the technical solution adopted by the present invention is:

[0008] A power chip automatic testing method comprises the following steps:

[0009] Generate a test document, the test document includes a setting column and a result column, the setting column is used for setting and calibrating instrument parameters, and the result column is used for reading instrument parameters;

[0010] Importing the test document, parsing the test behavior recorded in the test document, and setting parameters for instruments in the input module and the output module;

[0011] Read and analyze the test results of each instrument, display the test results in real time, and fill the test results into the test document.

[0012] Testers do not need to develop the software environment again, nor do they need to understand the instrument parameter setting commands and writing specifications of the test documents. They can directly configure the instrument parameters according to the prompts of the visual interface of the test file generation terminal, and generate the test document that can be recognized by the software test terminal with one click. After importing the test document into the software test terminal and running it with one click, they can complete the setting of instrument parameters, the reading of instrument results, the judgment of test results, and the automatic screenshot and saving of the oscilloscope, and finally fill in the results into the test document, which lowers the usage threshold for testers while improving test efficiency.

[0013] Preferably, each test item is divided into a plurality of the test documents according to the number of test items, or is generated in a plurality of forms based on the test documents; the parameter configuration of the instrument is changed according to the stimulus requirements of each test item, the priority of parameter traversal is adjusted according to the output requirements of the test results, and whether to perform parameter calibration is selected according to the accuracy requirements of the test results.

[0014] Preferably, according to the requirements of the test items, the setting values ​​and test values ​​of the instrument are selected to be read out, and the interval range is preset for the key test items to determine whether the test results of each test item are passed.

[0015] Preferably, the setting columns of different instruments are arranged according to the traversal priority. For the setting columns of the same instrument, the priority of the non-traversed setting columns is higher than the traversed setting columns. The result columns of different instruments are arranged according to the priority of the setting columns of each instrument, and the result columns of the same instrument will be arranged in sequence according to the preset order.

[0016] Data communication is used between the test file generation terminal and the software test terminal to achieve real-time transmission and synchronous updating of test results, ensuring the accuracy and consistency of test data. The test document processes and records abnormal situations that occur during the test to ensure the reliability and stability of the test. After the test is completed, the test results in the test document can be saved, saved as or exported for subsequent data analysis and processing.

[0017] Preferably, the chip to be tested is connected to the input module, the output module and the waveform capture module respectively, and the software test terminal calibrates the steady-state voltage and current of each instrument in the input module and the output module respectively, and calibrates the transient voltage jump provided by the input module and the transient load jump provided by the output module.

[0018] When testing the power chip, the input pin, input pin and ground pin of the chip to be tested can be directly connected to the hardware platform of the test system. The hardware platform of the test system can provide the chip to be tested with stable DC voltage, transient jump voltage, stable DC load and jump AC load. There is no need for testers to redevelop the hardware environment or change the test topology during the test, and the static and dynamic indicators of the chip to be tested can be automatically tested. This greatly simplifies the hardware development part of the power chip test, lowers the usage threshold for testers and improves the test efficiency.

[0019] Preferably, the steps of calibrating the steady-state voltage and the current are as follows: by comparing the preset parameters and the measured actual values, determine whether the accuracy requirements are met; if the accuracy requirements are not met, correct the preset parameters according to the difference between the preset parameters and the actual values.

[0020] Preferably, the calibration step of the transient load jump comprises:

[0021] The electronic load is set to a constant current mode and the load is drawn, and a preset current jump parameter of the electronic load is compared with the measured actual current to determine whether the actual current meets the accuracy requirement. If not, the preset current jump parameter is corrected according to the difference between the preset current jump parameter and the actual current, and the electronic load is turned off;

[0022] The second signal generator is set to DC mode, and it is determined whether the preset current jump parameter meets the accuracy requirement. If not, the DC voltage of the second signal generator is repeatedly adjusted until the preset current jump parameter meets the corresponding accuracy requirement, and the second signal generator is set to square wave mode.

[0023] When calibrating the transient load jump, first calibrate the current of the electronic load in the constant current mode to provide an accurate DC load for the chip to be tested. After completing the calibration of the electronic load, turn off the electronic load and turn on the second signal generator to turn on the second MOS tube.

[0024] Since the input module works normally, the current output by the chip under test will be directed to the resistance branch through the second MOS tube. By comparing the load current when the electronic load is working and the load current when the second signal generator is working, the high level of the second signal generator in the square wave mode is calibrated, so that the second signal generator can output an accurate voltage when a transient load jump is required to accurately turn on the second MOS tube.

[0025] Testers do not need to manually calibrate instrument parameters multiple times. The automated test system supports software self-calibration. Through multi-instrument joint adjustment and parameter determination, it can achieve self-calibration of predetermined voltage, current values ​​and transient load jumps, reduce test errors caused by the test environment, and ensure accurate and reliable test results.

[0026] A power chip automatic test system comprises an input module, an output module, a waveform capture module, a test file generation terminal and a software test terminal. The test file generation terminal is electrically connected to the software test terminal. The software test terminal sets and reads the test parameters and test results of each instrument in the input module, the output module and the waveform capture module.

[0027] Preferably, when testing the static indicators of the chip to be tested, the input module provides a stable DC voltage and the output module provides a stable DC load; when testing the dynamic indicators of the chip to be tested, the input module provides a transient voltage jump and the output module provides a transient load jump.

[0028] Preferably, during the test process, the waveform capture module will monitor the electrical parameters of the input module, the output module and the chip to be tested.

[0029] The automated test system does not need to use expensive instruments to meet transient test requirements. It only needs ordinary power supplies, signal generators, MOS tubes and diodes to achieve dynamic indicator test requirements with adjustable transient rate and slope.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] (1) When testing a power chip, the present invention can directly connect the input pin, input pin and ground pin of the chip to be tested to the hardware platform of the test system. The hardware platform of the test system can provide a stable DC voltage, a transient jump voltage, a stable DC load and a jump AC load for the chip to be tested. There is no need for the tester to redevelop the hardware environment or change the test topology during the test. The automatic test of the static indicators and dynamic indicators of the chip to be tested can be met, which greatly simplifies the hardware development part in the power chip test, lowers the usage threshold of the tester and improves the test efficiency.

[0032] (2) The present invention provides a test file generation terminal and a software test terminal. Testers do not need to redevelop the software environment, nor do they need to understand the instrument parameter setting commands and the writing specifications of the test documents. They can directly configure the instrument parameters according to the prompts of the visual interface of the test file generation terminal, generate a test document that can be recognized by the software test terminal with one click, import the test document into the software test terminal, run it with one click, and complete the setting of instrument parameters, reading of instrument results, judgment of test results, and automatic screenshot and storage of oscilloscopes. Finally, the results are filled in the test document, which lowers the usage threshold of testers and improves the test efficiency.

[0033] (3) The automated test system of the present invention does not require expensive instruments to meet transient test requirements. It only requires an ordinary power supply, a signal generator, a MOS tube and a diode to achieve dynamic indicator test requirements with adjustable transient rate and slope.

[0034] (4) In the present invention, the test personnel do not need to manually calibrate the instrument parameters multiple times. The automated test system supports software self-calibration. Through multi-instrument coordination and parameter determination, self-calibration of predetermined voltage, current values ​​and transient load jumps is achieved, thereby reducing the test errors caused by the test environment and ensuring that the test results are accurate and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A circuit diagram of a hardware platform of a power chip automatic test system according to an embodiment of the present invention;

[0036] Figure 2 A test flow chart of an automated test system for a power chip automated test system according to an embodiment of the present invention;

[0037] Figure 3 A flow chart of generating a test document of a power chip automatic test system according to an embodiment of the present invention;

[0038] Figure 4 A flowchart of calibrating instrument voltage or current of a power chip automatic test system according to an embodiment of the present invention;

[0039] Figure 5 A flow chart of calibrating transient voltage jump of a power chip automatic test system according to an embodiment of the present invention;

[0040] Figure 6 A flow chart of calibrating transient load jump of a power chip automatic test system according to an embodiment of the present invention;

[0041] Figure 7 An interface for a test file generation terminal of a power chip automatic test system according to an embodiment of the present invention;

[0042] Figure 8 This is an interface of a software test terminal of a power chip automatic test system according to an embodiment of the present invention. DETAILED DESCRIPTION

[0043] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] The flowcharts shown in the accompanying drawings are only examples and do not necessarily include all contents and operations / steps, nor do they have to be executed in the described order. For example, some operations / steps may be decomposed, combined or partially merged, so the actual execution order may change according to actual conditions.

[0045] like Figures 1 to 8 As shown, the specific scheme of the embodiment is as follows:

[0046] The present invention aims at the defects that the current power chip test system does not support the dynamic parameter measurement of the power chip, and the problem that the test topology needs to be changed many times to meet the different index test requirements of the power chip, and provides a power chip automatic test method and test system, which can test the static index and dynamic index test of the power chip separately in a single test without changing the test topology, and the static index includes output accuracy, linear regulation rate, load regulation rate, static current, overload ground current, leakage voltage, rated current and current limiting current, etc., and the dynamic index includes dynamic linear regulation rate and dynamic load regulation rate. At the same time, the technical solution is simple to operate and has a high coverage rate during actual use, the circuit of the hardware platform is simple and low-cost, and it can calibrate itself during the test process to improve the test accuracy.

[0047] A power chip automatic test system comprises a hardware platform and a software terminal. The hardware platform comprises an input module, an output module, a waveform capture module and a test pin terminal. The software terminal comprises a test file generation terminal and a software test terminal.

[0048] like Figure 1 As shown, the input pin, output pin and ground pin of the chip to be tested are respectively connected to the output port (vin terminal) of the input module, the output port (vout terminal) of the output module and the ground terminal through the ports of the test pin terminal. The test pin terminal also includes a spare port, which is used to connect the waveform capture module.

[0049] The input module comprises a first power supply, a second power supply, a first MOS tube (Q1), a first signal generator and a first multimeter, wherein the first power supply and the second power supply are two independent channels of a dual-channel power supply, a G pole of the first MOS tube (Q1) is connected to the first signal generator and the second power supply, a D pole of the first MOS tube (Q1) is connected to the first power supply, an S pole of the first MOS tube (Q1) is connected to an output port (vin end) of the input module and the second power supply, a capacitor C1 is arranged between the first signal generator and the first MOS tube (Q1), diodes D1 and D2 are arranged between the second power supply and the G pole and the S pole of the first MOS tube (Q1), respectively, and the conduction direction of the diodes D1 and D2 is consistent with the current output direction of the second power supply.

[0050] The first signal generator is used to control the transient voltage jump, the first multimeter is used to accurately measure the current size of the output port (vin terminal) of the input module, the capacitor C1 is used to isolate the DC and pass the AC, the diode is used for DC bias and to prevent the first power supply current from flowing back to the second power supply, and the first MOS tube (Q1) is used as a switch to control the DC voltage supply or the transient voltage jump.

[0051] When the first signal generator outputs a square wave with an amplitude of 22V, the input module can achieve a voltage jump within 22V. Since the LDO operating voltage range of the 12V system is 6V~28V, it can meet the test requirements.

[0052] The output module includes an electronic load, a resistance branch, a second MOS tube (Q2), a second signal generator, a capacitor C2, a second multimeter and a third multimeter. The resistance branch includes a sampling resistor R1 which is grounded.

[0053] The G pole of the second MOS tube (Q2) is connected to the second signal generator, the S pole of the second MOS tube (Q2) is connected to the sampling resistor R1, the D pole of the second MOS tube (Q2) is connected to the output port (vout end) of the output module, the electronic load and the capacitor C2, the capacitor C2 is grounded, and the capacitor C2 is connected in parallel with the electronic load.

[0054] The electronic load can realize the setting of any DC load value. The second signal generator provides light load current on the one hand and realizes the control of transient load jump on the other hand. The second multimeter and the third multimeter are used to accurately measure the voltage and current of the output port (vout end) of the output module respectively. The capacitor C2 is used to improve the output stability. The second MOS tube (Q2) is used as a switch to control the high-precision light load current or transient load jump. The sampling resistor R1 can indirectly indicate the current value of the transient load jump.

[0055] The first signal generator and the second signal generator are two independent channels of a dual-channel signal generator.

[0056] The waveform capture module includes a multi-channel oscilloscope. Four probes of the multi-channel oscilloscope are respectively connected to the spare port of the test pin end, the output port (vin end) of the input module, the output port (vout end) of the output module, and between the sampling resistor R1 and the second MOS tube (Q2). The multi-channel oscilloscope supports trigger mode and measurement mode. The measurement mode is used for testing static test items, and the trigger mode is used for testing transient test items.

[0057] The test file generation terminal and the software test terminal can be installed on a computer system, and a tester can start the test file generation terminal and the software test terminal on the computer system.

[0058] The test file generation terminal controls each instrument in the input module, the output module, and the waveform capture module through the software test terminal, and each instrument in the input module, the output module, and the waveform capture module transmits the measured test parameters to the test file generation terminal through the software test terminal.

[0059] like Figure 7 As shown, the test file generation terminal interface is divided into a file control area, an instrument configuration area, and a parameter reading area. The file control area is mainly used to generate test documents. Testers can choose to generate different test items into multiple test documents based on test requirements, or generate them in multiple forms based on the current test document.

[0060] The instrument configuration area includes parameter controls for multi-channel power supplies, multi-channel signal generators, electronic loads, multi-channel oscilloscopes, multimeters, temperature chambers, temperature impulses, and auxiliary currents. Testers can change the instrument's parameter configuration according to the stimulus requirements of the test items; adjust the priority of parameter traversal according to the output requirements of the test results; and choose whether to perform parameter calibration according to the accuracy requirements of the test results. The instrument's configuration items also include the startup time, which is mainly used to ensure that the instrument is ready.

[0061] The parameter reading area includes the parameter reading of power supply, electronic load, oscilloscope, multimeter, temperature chamber and temperature shock. Testers can choose to read the set value and test value of the instrument according to the requirements of the test items; in addition, testers can also fill in the interval range after the key test items for the software to automatically determine whether the test results pass.

[0062] like Figure 8 As shown, the software test terminal is mainly divided into a file control area, a test item control area, a test content display area and a test log area.

[0063] The file control area contains the functions of file opening, file saving, file saving as, starting test and stopping test. The tester can click the "Open" button and select the test document. The software will automatically read the parameters of the file and import the test items. After the test document is successfully imported, the tester can click the "Start" button to test. During the test, the tester can click the "Stop" button to temporarily terminate the test. After the test is completed, the tester can save the test result file directly or save it as another file.

[0064] The test item control area includes the display of test documents and forms. Only one test document can be opened, but multiple forms can be displayed. Testers can check different form pages to select test items to be automatically executed. Each form page is executed in sequence until all checked test items are completed.

[0065] The test content display area includes the instrument parameter setting area, the instrument parameter reading area and the result judgment area. The traversed test parameters are arranged according to priority, first traversing the low priority and then the high priority. When the test is in progress, the test results will be displayed in real time, which is convenient for the tester to know the correctness of the test results in advance during the test.

[0066] The test log display area includes file operation log, test progress log and instrument status log. The file operation log is mainly related to operations such as opening, saving and saving as test documents. The test progress log can display the percentage of test item completion in real time, which is convenient for testers to grasp the entire test process. The instrument status log is mainly convenient for testers to check the access status of the instrument. When the instrument required for the test is successfully connected, the instrument will be marked green, and when the instrument required for the test is not connected, the instrument will be marked red.

[0067] Both the test file generation terminal and the software test terminal use the layered design principle. From top to bottom, they are divided into UI (View) layer, control (Controller) layer, data (Mode) layer, instrument (Instrument) layer, and transport (Transport) layer. View and Model are implemented based on the Qt class library, and Controller, Instrument, and Transport are implemented based on the C++ language.

[0068] The instrument layer implements the test functions of specific instruments, including temperature chambers, electronic loads, multimeters, multi-channel power supplies, multi-channel oscilloscopes, etc. Most instruments can be controlled by commands based on the NI-VISA virtual interface, while the temperature chamber completes command control based on UART or TCP according to its own communication protocol.

[0069] A power chip automatic testing method comprises the following steps:

[0070] The chip to be tested is connected to the input module, the output module and the waveform capture module respectively, and the electrical parameters of the input module, the output module and the chip to be tested are monitored through the waveform capture module;

[0071] like Figure 2 As shown, before testing the chip to be tested, a test document is generated through a test file generation terminal according to the test requirements of the chip to be tested, and the test document is imported into a software test terminal. The software test terminal completes parameter settings for each instrument in the input module and the output module according to the test document.

[0072] like Figure 3 As shown, the model of the test document is established according to a certain format. The specific specifications are as follows:

[0073] 1. The instrument is divided into setting column and result column. The setting column is for instrument parameter setting and calibration, i.e. input; the result column is for instrument parameter reading, i.e. output;

[0074] 2. Different instruments have different setting columns and result columns. Simpler instruments may have 1 column, while more complex instruments may have multiple columns;

[0075] 3. The settings and results are listed in order. In the test document, all settings are listed first, and all results are listed last;

[0076] 4. The settings of different instruments are arranged according to the traversal priority. The instruments with higher traversal priority are in front, and the instruments with lower priority are in the back;

[0077] 5. The setting columns of the same instrument also need to be sorted, with non-traversal setting columns in front and traversal setting columns in the order of priority;

[0078] 6. The result columns of different instruments are sorted by the priority of the instrument setting column;

[0079] 7. The result columns of the same instrument will be sorted in a certain order.

[0080] The software test terminal calibrates the steady-state voltage and current of each instrument in the input module and the output module respectively, and calibrates the transient voltage jump provided by the input module and the transient load jump provided by the output module.

[0081] like Figure 4 As shown in the figure, the voltage and current calibration steps of each instrument in the input module and the output module are as follows: By comparing the preset parameter a and the measured actual value b, determine whether the accuracy requirement is met. If the accuracy requirement is not met, then according to formula 2 ab=a1 Rebalance the preset parameter a.

[0082] like Figure 5As shown in the figure, the specific steps for calibrating the transient voltage jump of the input module include:

[0083] Set the voltage jump parameters A1&B1 (A1>B1), call the first power supply and the second power supply to write the parameters A1&B1, call the signal generator to output a square wave amplitude of 22V, and use the oscilloscope to read the high and low level values ​​A2&B2 of the output port (vin end) of the input module to see if the voltage accuracy meets ±20%. If not, reconfigure the voltage jump parameter A3=2 A1-A2,B3=2 B1-B2, according to the test requirements, manually determine whether calibration is required and whether the voltage accuracy meets ±2%. If not, reconfigure the voltage jump parameter A3=2 A1-A2,B3=2 B1-B2, set the current calibration value to the test setting value, and the calibration is completed.

[0084] like Figure 6 As shown in the figure, the specific steps for calibrating the transient load jump of the output module include:

[0085] Set the electronic load of the output module to constant current mode and draw the load. By comparing the preset current jump parameter min (A&B) of the electronic load and the measured actual current I1, manually determine whether calibration is required according to the test requirements. If necessary, determine whether the accuracy requirement of ±1% is met. If not, correct the preset current jump parameter to I2 according to the difference between the preset current and the actual current I1, and turn off the electronic load.

[0086] Set the second signal generator to DC mode, set its DC voltage to V2, and determine whether I2 meets the accuracy requirement of ±30%. If not, use the formula X+(V2-X) SQRT (|AB| / I2) = V2a. V2 is calibrated to V2a, where X is the on-state voltage of the second MOS tube. In this embodiment, X is set to 0.7.

[0087] Determine whether I2 meets the accuracy requirement of ±10%. If not, when I2 < |AB|, V2a is calibrated to V2b according to the formula V2b = V2a + Z. When I2 > |AB|, V2a is calibrated to V2b according to the formula V2b = V2a - Z. After resetting the DC voltage to V2b, calibrate the accuracy of I2 again according to the above steps until I2 meets the accuracy requirement of ±10%. Z is a preset calibration parameter. The size of Z determines the calibration speed. In this embodiment, Z is set to 0.05.

[0088] Manually determine whether calibration is required. If necessary, determine whether I2 meets the accuracy requirement of ±1%. If not, when I2 < |AB|, V2b is calibrated to V3 according to the formula V3 = V2b + Y. When I2 > |AB|, V2b is calibrated to V3 according to the formula V3 = V2b - Y. After resetting the DC voltage to V3, calibrate the accuracy of I2 again according to the above steps until I2 meets the accuracy requirement of ±1%. Y is a preset calibration parameter. The size of Y determines the calibration speed. In this embodiment, Y is set to 0.01.

[0089] After the calibration is completed, the load of the electronic load in the constant current mode is I2, and when the second signal generator is set to the square wave mode, the high and low levels of the second signal generator are V3 and 0.

[0090] After the test starts, the software test terminal will read the test parameters measured by each instrument in the input module, output module and waveform capture module, and import the test parameters into the test file generation terminal, and the test file generation terminal will fill the test parameters into the test document.

[0091] When testing the static indicators of the chip under test, the chip under test requires a stable DC voltage. The software test terminal controls the first MOS tube (Q1) to be turned off through the first signal generator. The first MOS tube (Q1) will block the electrical connection between the first power supply and the chip under test. At this time, since the second power supply level is lower than the first power supply level, current backflow will not be formed through the body diode of the first MOS tube (Q1). The second power supply only supplies power to the output port (vin terminal) of the input module. The second power supply provides a stable DC voltage to the chip under test, and there will be no phenomenon that the voltage and current of the output port (vin terminal) of the input module do not match the voltage and current provided by the second power supply.

[0092] When testing the dynamic index of the chip under test, the chip under test needs a transient jump voltage. The software test terminal sets the levels of the first power supply and the second power supply of the input module to the high level and the low level of the jump level respectively. The first signal generator is set to the square wave mode, and the amplitude is greater than or equal to the difference between the high level and the low level. At this time, since the diode D2 is forward-conducting and reverse-cutoff, the G pole of the first MOS tube (Q1) has both the second power supply to provide a floating DC bias and the first signal generator to couple the AC signal through the capacitor C1, thereby forming a jump Vgs, and realizing the control of the conduction and shutdown of the first MOS tube (Q1) through the first signal generator.

[0093] When the first MOS tube (Q1) is turned on, the first power supply will not backflow to the second power supply because the diode D1 is reversely cut off. When the first MOS tube (Q1) is turned off, the first MOS tube (Q1) can be used to control the first power supply and the second power supply to supply power to the chip under test in turn. At this time, the input module provides a transient voltage jump to the chip under test.

[0094] When testing the static indicators of the chip under test, the chip under test needs a stable DC load. There are multiple ways to provide the required DC load. When the required load current is ≥2mA, the software test terminal calls the electronic load to provide the DC load, and the software test terminal controls the second MOS tube (Q2) to be turned off through the second signal generator, and the second MOS tube (Q2) blocks the electrical connection between the resistance branch and the chip under test;

[0095] If the required load current is ≤2mA and the electronic load cannot meet the high-precision requirements, the software test terminal will turn off the electronic load and call the second signal generator and the second MOS tube (Q2) to provide an accurate small load current. The specific operation is to operate the signal generator in DC mode, control the Vgs of the second MOS tube (Q2), and generate an accurate small current.

[0096] When testing the dynamic indicators of the chip under test, the chip under test needs a jumping AC load. The software test terminal will call the electronic load to provide the DC component of the jumping load for the chip under test, and set the second signal generator to the square wave mode. The conduction and shutdown of the second MOS tube (Q2) are controlled by the jumping Vgs. The resistance branch and the chip under test are repeatedly turned on and off by the second MOS tube (Q2), providing the AC component of the jumping load for the chip under test, thereby enabling the output module to provide the jumping AC load to the chip under test.

[0097] Since the critical on-resistance of the second MOS tube (Q2) is relatively small, a current jump of level A can be achieved, thus meeting the jump requirement of the LDO.

[0098] The sampling resistor R1 can convert the AC current signal into an AC voltage signal and display it on the oscilloscope, making it convenient for testers to observe.

[0099] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for automatic testing of power chip, It is characterized in that The following steps are involved: Generate a test document, the test document includes a setting column and a result column, the setting column is used for setting and calibrating instrument parameters, and the result column is used for reading instrument parameters; Importing the test document, parsing the test behavior recorded in the test document, and setting parameters for instruments in the input module and the output module; Read and analyze the test results of each instrument, display the test results in real time, and fill the test results into the test document; A waveform capture module and a software test terminal are set, and the chip to be tested is connected to the input module, the output module and the waveform capture module respectively, and the software test terminal is used to calibrate the steady-state voltage and current of each instrument in the input module and the output module respectively, and at the same time, the transient voltage jump provided by the input module is calibrated, and the transient load jump provided by the output module is calibrated; The calibration steps of the transient load jump include: The electronic load of the output module is set to a constant current mode and the load is drawn, and the preset current jump parameter of the electronic load is compared with the measured actual current I1 to determine whether the actual current meets the accuracy requirement. If not, the preset current jump parameter I2 is corrected according to the difference between the preset current jump parameter and the actual current I1, and the electronic load is turned off; The second signal generator is set to a DC mode, and it is determined whether the preset current jump parameter meets the accuracy requirement. If not, the DC voltage of the second signal generator is repeatedly adjusted until the preset current jump parameter meets the corresponding accuracy requirement, and the second signal generator is set to a square wave mode; The process of repeatedly adjusting the DC voltage of the second signal generator is as follows: setting its DC voltage to V2, determining whether I2 meets the accuracy requirement of ±30%, and if not, calibrating V2 to V2a according to the formula X+(V2-X)*SQRT(|AB| / I2)=V2a, where X is the on-voltage of the second MOS tube; Determine whether I2 meets the accuracy requirement of ±10%. If not, when I2<|AB|, calibrate V2a to V2b according to the formula V2b=V2a+Z; when I2>|AB|, calibrate V2a to V2b according to the formula V2b=V2a-Z. After resetting the DC voltage to V2b, calibrate the accuracy of I2 again until I2 meets the accuracy requirement of ±10%, where Z is the preset calibration parameter.

2. The method for automatically testing a power chip according to claim 1, It is characterized in that According to the number of test items, each test item is divided into multiple test documents, or multiple forms are generated based on the test documents; according to the stimulus requirements of each test item, the parameter configuration of the instrument is changed, according to the output requirements of the test results, the priority of parameter traversal is adjusted, and according to the accuracy requirements of the test results, whether to perform parameter calibration is selected.

3. The power chip automatic testing method according to claim 1, It is characterized in that According to the requirements of the test items, choose to read the instrument's set values ​​and test values, and preset interval ranges for key test items to determine whether the test results of each test item have passed.

4. The power chip automatic testing method according to claim 1, It is characterized in that The setting columns of different instruments are arranged according to the traversal priority. For the setting columns of the same instrument, the non-traversed setting columns have a higher priority than the traversed setting columns. The result columns of different instruments are arranged according to the priority of the setting columns of each instrument. The result columns of the same instrument will be arranged in sequence according to the preset order.

5. The power chip automatic testing method according to claim 1, It is characterized in that The steps of calibrating the steady-state voltage and the current are as follows: by comparing the preset parameters with the measured actual values, determine whether the accuracy requirements are met; if the accuracy requirements are not met, correct the preset parameters according to the difference between the preset parameters and the actual values.

6. A power chip automatic testing system, used to implement the method according to any one of claims 1 to 5, It is characterized in that It includes an input module, an output module, a waveform capture module, a test file generation terminal and a software test terminal. The test file generation terminal is electrically connected to the software test terminal. The software test terminal sets and reads the test parameters and test results of each instrument in the input module, the output module and the waveform capture module.

7. The power chip automatic testing system according to claim 6, It is characterized in that When testing the static indicators of the chip to be tested, the input module provides a stable DC voltage and the output module provides a stable DC load; when testing the dynamic indicators of the chip to be tested, the input module provides a transient voltage jump and the output module provides a transient load jump.

8. The power chip automatic testing system according to claim 6, It is characterized in that During the test process, the waveform capture module will monitor the electrical parameters of the input module, the output module and the chip to be tested.

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