Chip problem locating method, device and related equipment

Abstract

An embodiment of the present invention provides a chip problem location method, apparatus, and related equipment, wherein the method is applied to a simulation tool and includes: obtaining the original chip design code and tangible signal data of the chip, wherein the tangible signal data is defined in the original chip design code and is based on the chip's internal register data obtained by scanning the chip; performing computational processing on the original chip design code and the tangible signal data to obtain non-tangible signal data, wherein the non-tangible signal data is signal data defined in the original chip design code other than the tangible signal data; and locating the chip problem based on the tangible signal data and the non-tangible signal data. The technical solution provided by the embodiment of the present invention can effectively recover the non-tangible signal data and reduce the difficulty of locating chip problems.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a chip problem locating method, apparatus, and related equipment. Background Art

[0002] Chip problem location is a crucial step in the chip design process, ensuring the proper functioning of the chip. Chip problem location primarily involves locating the location of a problem (such as a functional or performance error) in the chip, allowing for repairs to be performed.

[0003] However, as chip design processes become increasingly complex, such as those for very large-scale digital integrated circuits, the original chip design code developed during front-end chip design is also becoming increasingly complex, making chip problem locating increasingly complex. Against this backdrop, finding a technical solution to recover more effective information from chip data and improve the efficiency of chip problem locating has become a pressing technical challenge for those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a chip problem locating method, apparatus, and related devices to recover more effective information from chip data and improve the efficiency of chip problem locating.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present invention provides a chip problem location method, which is applied to a simulation tool, comprising:

[0007] Obtaining original chip design code and substantiated signal data of a chip, wherein the substantiated signal data is defined in the original chip design code and is based on chip internal register data obtained by scanning the chip;

[0008] performing computational processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, wherein the non-substantiable signal data is signal data defined in the original chip design code other than the substantiable signal data;

[0009] Chip problem location is performed based on the tangible signal data and the non-tangible signal data.

[0010] In a second aspect, an embodiment of the present invention provides a chip problem locating device, which is applied to a simulation tool, comprising:

[0011] An input data acquisition module is used to acquire the original chip design code and substantiated signal data of the chip, wherein the substantiated signal data is defined in the original chip design code and is based on chip internal register data acquired through chip scanning;

[0012] a data operation module, configured to perform operation processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, wherein the non-substantiable signal data is signal data defined in the original chip design code other than the substantiable signal data;

[0013] The problem locating module is used to locate chip problems based on the substantiable signal data and the non-substantiable signal data.

[0014] In a third aspect, an embodiment of the present invention provides an electronic device, comprising a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the chip problem locating method as described in the first aspect.

[0015] In a fourth aspect, an embodiment of the present invention provides a storage medium storing a program, which, when executed, implements the chip problem locating method as described in the first aspect.

[0016] In a fifth aspect, an embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the chip problem locating method as described in the first aspect.

[0017] A chip problem locating method provided by an embodiment of the present invention is applied to a simulation tool, comprising: first, obtaining the original chip design code and materializable signal data of the chip, wherein the materializable signal data is defined in the original chip design code and is based on chip internal register data obtained by scanning the chip; then, performing computational processing on the original chip design code and the materializable signal data to obtain non-materializable signal data, wherein the non-materializable signal data is signal data defined in the original chip design code other than the materializable signal data; finally, performing chip problem locating based on the materializable signal data and the non-materializable signal data.

[0018] Therefore, in the chip problem locating method provided by the embodiment of the present invention, the obtained chip internal materializable signal data and the original chip design code are used for computational processing to obtain non-materializable signal data, thereby quickly restoring the signal data that cannot be reflected in the internal data of the chip and defined in the original chip design code, i.e., non-materializable signal data, in the simulation tool. Therefore, after the simulation tool computational processing is completed, all the signal data defined in the original chip design code can be obtained, and then the chip problem location can be performed based on the materializable signal data and the non-materializable signal data, thereby quickly realizing chip problem location using the simulation tool and improving the efficiency of the chip signal data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0020] Figure 1 This is a flow chart of a chip problem locating method provided by an embodiment of the present invention;

[0021] Figure 2 2 is another flowchart of the chip problem locating method provided by an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of an implementation process of a chip problem locating method provided by an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of a process for generating tangible signal data in a chip problem locating method provided by an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of a process for generating tangible signal data in a chip problem locating method provided by an embodiment of the present invention;

[0025] Figure 6 It is a structural diagram of a chip problem locating device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] The chip design process includes simulation verification before tape-out (i.e. pre-silicon simulation) and chip problem location after tape-out (i.e. post-silicon verification).

[0028] Among them, simulation verification usually simulates and analyzes the original chip design code of the chip design to determine where the operational errors occur in the original chip design code. Chip problem location, on the other hand, is to analyze the chip's behavior that does not conform to the predetermined working mode during physical chip testing after chip manufacturing is completed. Post-tapeout chip problem location usually operates one or more manufactured chips in an actual application environment to verify the correct behavior of the chip under specified operating conditions; the goal is to ensure that no vulnerabilities (bugs) are left in the field application. That is, simulation verification targets the chip design, and chip problem location targets the chip (the physical chip that has been manufactured).

[0029] As the complexity of the chip design process increases, so does the complexity of simulation verification and chip problem location. However, defects not detected during simulation verification are often detected during chip problem location. Therefore, chip problem location is a very important step in the chip design process.

[0030] The inventor believes that in chip problem location, only the signal data that can be materialized by being synthesized as registers inside the chip can be obtained. That is to say, the materialized signal data is only the data defined in the original chip design code and can be synthesized into physical hardware structures such as registers inside the chip; and the data defined in the original chip design code but cannot be synthesized into physical hardware structures inside the chip after the back-end manufacturing is completed, that is, the non-materialized signal data (such as the bus signal data of the linear type "wire" defined in the original chip design code and the intermediate data of the storage type "reg" that is not synthesized into registers) cannot be obtained. Therefore, in chip problem location, the chip front-end designer usually performs logical reasoning on the original chip design code, and then confirms the logical reasoning in combination with the materialized signal data to complete the chip problem location.

[0031] However, as chip front-end design continues to grow in complexity, the difficulty of logically reasoning about the original chip design code increases, further increasing the time required to locate subsequent chip issues. Therefore, recovering more internal chip information from the limited, tangible signal data available on the chip, thereby simplifying chip issue location, has become an urgent issue.

[0032] Based on this, an embodiment of the present invention provides a chip problem locating method. When analyzing the original chip design code, combined with the signal data that can be materialized as registers inside the chip (that is, materialized signal data), simulation tools are used to quickly calculate the non-materialized signal data that cannot be directly obtained in the chip, thereby improving the data processing efficiency in the chip problem locating process.

[0033] Please refer to Figure 1 , Figure 1 FIG1 is a flow chart of a chip problem location method provided by an embodiment of the present invention, wherein the method is applied to a simulation tool.

[0034] like Figure 1 As shown, the method includes the following steps:

[0035] Step S100 : obtaining the original chip design code and tangible signal data of the chip.

[0036] The tangible signal data is defined in the original chip design code and is based on chip internal register data obtained by scanning the chip.

[0037] The original chip design code mentioned above is the design code defined based on the chip's logical design requirements during the chip's front-end design. For example, the original chip design code is written in the hardware description language Verilog HDL, which uses code language to describe the functional implementation of each module inside the chip, that is, to describe the circuit structure inside the chip.

[0038] Based on the above introduction, it can be seen that the original chip design code can describe the functional implementation of each module inside the chip. From the perspective of hardware structure, the modules inside the chip can be buses, processors, or I / O interfaces. Therefore, describing the functional implementation of each module in the original chip design code is equivalent to using a hardware description language to describe the "pins" of each module and the connection method between the "pins" of each module, that is, the circuit structure. Therefore, in order to clearly describe the functional implementation of each module, the original chip design code will define multiple types of signal data to represent the signal data passing through or stored on different modules.

[0039] For example, for a module like a bus, since the bus transmits data between two adjacent modules, in the original chip design code, the bus is a memoryless module. In this case, the "wire" linear type can be used to define the bus signal data; and for a module with memory (such as memory), the "reg" storage type can be used to define the register signal data. At the same time, in the front-end design, since some signal data are intermediate variables, although they are defined as the storage type "reg" in the original chip design code, there will be no corresponding physical hardware structure in the chip, and no corresponding tangible signal data.

[0040] Therefore, the materializable signal data described in the embodiment of the present invention may refer to: signal data of the "reg" storage type defined in the original chip design code, and signal data with an actual hardware structure in the chip, such as register signal data.

[0041] In one embodiment, the tangible signal data can be stored in a chip's structural scan file, such as a scandump file. A scandump file is a file generated by scanning all registers within a chip using a scan chain for testability. The scandump file can reflect the actual hardware structure within the chip.

[0042] Step S101 : performing computation processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data.

[0043] The non-substantiable signal data is signal data defined in the original chip design code except the substantiable signal data.

[0044] During chip problem location, front-end chip designers typically first perform logical reasoning on the original chip design code to determine the possible problem location. This reasoning is then verified using the tangible signal data obtained from the chip. This logical reasoning process involves restoring all signal data defined in the original chip design code. However, as the design process complexity of the original chip design code increases, logical reasoning becomes increasingly difficult for front-end chip designers, increasing the time and difficulty of chip problem location.

[0045] Therefore, in the embodiments of the present invention, the tangible signal data is not used as the final step in the confirmation process of the reasoning result. Instead, it is used simultaneously during the initial logical reasoning of the original chip design code. At the same time, in order to quickly complete the logical reasoning of the original chip design code, the embodiments of the present invention use a simulation tool. The simulation tool performs calculations based on the input initial values (original chip design code and tangible signal data) to obtain non-tangible data, thereby quickly obtaining all the signal data defined in the original chip design code.

[0046] The non-materializable signal data may be the "wire" linear type signal data defined in the original chip design code as described in the aforementioned embodiment, and defined as the "reg" storage type, but not materialized (synthesized) as register signal data inside the chip.

[0047] To improve the reliability of non-substantiable signal data obtained by the simulation tool, in one embodiment, step S101 may include:

[0048] Based on the materializable signal data, a simulation control program applied to the simulation tool is defined, wherein the simulation control program at least includes a call command for calling the materializable signal data; the simulation control program and the original chip design code are run through the simulation tool to obtain non-materializable signal data.

[0049] Different simulation tools require different corresponding simulation control programs. Therefore, it is possible to establish a corresponding simulation control program based on the actual simulation tool selected for the application and the tangible signal data, so that the simulation control program can run better and more compatibly in the simulation tool, ensuring the reliability and efficiency of the operation processing.

[0050] In order to ensure that the simulation control program can run smoothly and be convenient for chip front-end designers to use to locate chip problems, in one embodiment, the simulation control program can also include simulation running commands and simulation result output commands. The simulation result output command defines the result output method, the signal display form and the displayed signal data in the defined result output method.

[0051] The simulation run command can control the execution of the simulation control program on the simulation tool, such as the execution time required to output the simulation results, i.e., non-substantiable signal data. The simulation result output command can control the output format of the substantiable signal data and the non-substantiable signal data, such as outputting the signal waveform in the form of a waveform file or outputting the data information in the form of a log file.

[0052] That is to say, the simulation control program can include the following three parts:

[0053] 1. Simulation result output command (that is, the setting of basic simulation options): define the FSDB waveform file as the output format of the materializable signal data and the non-materializable signal data; define the level of the dump waveform (that is, which materializable signal data and non-materializable signal data corresponding to the signal waveform to be saved in the output FSDB waveform file); and define the dump waveform (define the display format of the signal waveform); you can also define the "resume" processing method for the error when encountering a simulation error. For example, when subsequently confirming whether the register path information can be mapped to the original chip design code, you can choose the "resume" processing method, that is, even if a runtime error occurs (the register path information cannot be mapped to the original chip design code), you can still continue to execute the program (for example, output the register path information that cannot be mapped to the original chip design code) to ensure the normal operation of the simulation control program.

[0054] 2. A call command for calling the instantiable signal data.

[0055] For example, the tangible signal data parsed from the scandump structure scan file can be written into the simulation control program using the "forceXXX_reg value" syntax. This allows subsequent simulations to use this tangible signal data, calculate all the signal data defined in the original chip design code, and subsequently generate a waveform file containing all the signal data.

[0056] 3. Simulation run command.

[0057] For example, the simulation run command is defined as: run the simulation control program for 1ns, then call "finish" to end the simulation run program and output the run result once.

[0058] The above is only an example of a simulation control program. When defining the simulation control program, it can be defined according to the actual usage of the simulation tool, which can facilitate chip front-end designers to call and view, analyze and locate chip problems.

[0059] To enhance the flexibility of the chip problem location method provided by an embodiment of the present invention, in one embodiment, the simulation tool may include a compiled code simulation tool, and defining a simulation control program applied to the simulation tool based on the tangible signal data includes:

[0060] According to the compiled code simulation tool used, a simulation control script file is defined in combination with the instantiable signal data to obtain a simulation control program applied to the compiled code simulation tool.

[0061] The Verilog Compiled Simulator (VCS) can analyze, compile, and simulate hardware description language code. Therefore, it can run original chip design code written in a hardware description language. Furthermore, because the VCS simulation tool can compile and analyze, when creating a simulation control program, you can include a call command for individuated signal data in the simulation control program. During subsequent simulation runs and calculations, the VCS simulation tool can analyze the original chip design code in conjunction with the individuated signal data and calculate the non-individuated signal data.

[0062] When the simulation tool is VCS, the simulation control program can be written using a script command language (TCL, Tool Command Language), which can be run on various simulation tools. The simulation control program described in the above embodiment can be written using the TCL script command language.

[0063] Use the VCS simulation tool and the corresponding TCL-written simulation control program. The TCL script contains interactive simulation control commands (UCLI, Unified Command Line Interface) and runs on the VCS simulation tool to generate waveform files. This method has the following advantages:

[0064] 1) Only the original chip design code written in Verilog needs to be directly compiled using the VCS simulation tool, without the need to create and compile verification environment codes such as testbench test files, thus saving compilation time;

[0065] 2) The VCS simulation tool only requires one compilation of the original design code. Scandump files generated under different test scenarios only need to generate corresponding simulation control programs, eliminating the need to repeatedly compile the original design code, thus improving efficiency.

[0066] 3) The simulation control program written by TCL is designed to restore all information of the front-end design code. There are no additional redundant processes. In addition, there is no testbench and other verification environment codes occupying simulation resources. This process can quickly generate waveform files. Compared with the simulation waveform generation of the front-end design of very large-scale digital integrated circuits, the speed advantage is particularly obvious.

[0067] In some other embodiments, the simulation tool may include a hardware description language simulation tool, and defining a simulation control program applied to the simulation tool based on the substantiable signal data includes:

[0068] According to the hardware description language simulation tool used, the simulation control test file is defined in combination with the substantiable signal data to obtain a simulation control program applied to the hardware description language simulation tool.

[0069] Hardware description language simulation tools, such as Modelsim, are simulation tools with a single core that supports mixed simulation of VHDL and Verilog. They have the characteristics of fast compilation and simulation speed, and the compiled code is independent of the simulation platform.

[0070] When the simulation tool is a hardware description language simulation tool, the defined simulation control program can be a simulation control test file written in Verilog HDL language, such as a testbench test file. The testbench test file and the original chip design code are then input into the hardware description language simulation tool (such as Modelsim) for calculation and processing to generate non-materializable signal data.

[0071] Therefore, in an embodiment of the present invention, as long as the chip's tangible signal data and original chip design code can be input into the simulation tool, non-tangible signal data can be quickly calculated, thereby accelerating the processing efficiency of signal data in chip problem location.

[0072] The use of simulation tools can be selected according to the actual use process. Of course, the definition of the simulation control program can also be selected according to the actual simulation tools used or the coding language usage habits of writing the simulation control program. It is sufficient to be able to run the simulation control program containing the materialized signal data and the original chip design code on the simulation tool.

[0073] Please continue to refer to Figure 1 The method further includes: step S102, locating chip problems based on the tangible signal data and the non-tangible signal data.

[0074] After the simulation tool completes the calculation processing, by combining the materializable signal data in step S100 and the non-materializable signal data obtained by the simulation tool calculation processing, all the signal data defined in the original chip design code can be obtained; therefore, chip problems can be located based on the materializable signal data and the non-materializable signal data.

[0075] It can be seen that in the chip problem locating method provided by the embodiment of the present invention, the chip problem locating method provided by the embodiment of the present invention performs calculation processing based on the acquired chip internal materializable signal data and the original chip design code to obtain non-materializable signal data, so as to quickly restore the signal data that cannot be reflected in the internal data of the chip and defined in the original chip design code, that is, the non-materializable signal data, in the simulation tool. Therefore, after the simulation tool calculation processing is completed, all the signal data defined in the original chip design code can be obtained, and then the chip problem location can be performed based on the materializable signal data and the non-materializable signal data, thereby using the simulation tool to quickly realize chip problem location and improve the efficiency of chip signal data processing.

[0076] At the same time, since all signal data in the original design code are calculated and processed with the help of simulation tools, the present invention synchronizes the chip's internal tangible signal data and the original chip design code as the input initial values of the simulation tool, adjusts the order of use of the tangible signal data in the chip problem locating process, and uses the simulation tool to quickly restore the signal data that cannot be reflected in the internal data obtained in the chip test and is defined in the original chip design code, that is, the non-tangible signal data, thereby improving the chip's signal data processing efficiency and reducing the difficulty of signal data calculation when locating chip problems.

[0077] To facilitate chip front-end designers to locate chip problems based on the materializable signal data and the non-materializable signal data, in one embodiment, the materializable signal data and the non-materializable signal data can be subsequently processed to facilitate analysis by chip front-end designers.

[0078] Please refer to Figure 2 , Figure 2 This is another flowchart of the chip problem locating method provided by an embodiment of the present invention.

[0079] like Figure 2 As shown, the method includes the following steps:

[0080] Step S201 : obtaining the original chip design code and tangible signal data of the chip.

[0081] Step S202 : performing computational processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data.

[0082] Step S203 : generating a waveform file according to the substantiable signal data and the non-substantiable signal data.

[0083] Waveform files can display tangible signal data and non-tangible signal data through signal waveforms, making it convenient for chip front-end designers to analyze based on waveform display results and locate chip problems.

[0084] The waveform file can be an FSDB waveform file. The FSDB waveform file is a file used to describe the signal waveform corresponding to the signal data in the digital circuit design. It can record the data changes of the signal data in the form of a time series. By reading the FSDB waveform file, the signal waveform of the signal data in the original chip design code can be restored, and then various analyses and simulations can be performed.

[0085] Step S102 may include the following steps:

[0086] Step S204: locating chip problems based on the waveform file.

[0087] When chip front-end designers locate chip problems, they are more accustomed to considering the problem from the perspective of the original chip design code written in Verilog. In the embodiment of the present invention, the materializable signal data is integrated into the simulation process of the simulation tool, and the non-materializable signal data is calculated through the simulation process, and then output in the form of a waveform file (such as an FSDB waveform file), so that the chip front-end designer can directly open the waveform file and the original chip design code to analyze and locate the problem.

[0088] A signal waveform is generated by a simulation tool. For example, the VCS simulation tool can be controlled to perform simulation operation through the command line input interface of the VCS simulation tool. The specific command can be expressed as: "vcs_exe–ucli–i scandump.tcl", where "scandump.tcl" is the TCL script file (simulation control program) generated in the aforementioned embodiment. "vcs_exe" is the original chip design code (such as Verilog design source code) compiled by the VCS simulation tool. After the command is run, an FSDB waveform file will be generated. If the fsdb waveform file is opened with the VERDI command, the signal waveform of the original chip design code and the corresponding signal data (substantiable signal data and non-substantiable signal data) can be seen.

[0089] The original scan file contains only the chip's internal tangible signal data (register signal data), and only a portion of the signal data (signal variables) defined in the original chip design code is integrated and mapped to the chip's internal register signal data. This portion of register signal data can directly find the corresponding hardware structure (register) in the scan file, while more signal data, such as "wire" linear type signal data and "reg" storage type signal data that has not been integrated into a register, cannot be directly found from the scan file. The chip problem location method proposed in the embodiment of the present invention uses a simulation tool to calculate the original chip design code and the tangible signal data, and can calculate the signal data (non-tangible signal data) that is not in the scan file, thereby effectively solving this problem.

[0090] The non-materializable signal data calculated by the simulation tool and the materializable signal data in the scandump structure scan file are displayed through signal waveforms (FSDB waveform files), so that chip front-end designers can not only see the materializable signal data (register signal data) recorded in the scandump structure scan file, but also all the signal data defined in the original chip design code: "wire" linear type signal data and "reg" storage type signal data that has not been synthesized into registers.

[0091] For further explanation of the simulation tool's implementation of the original chip design code and the actual signal data processing, please refer to Figure 3 , Figure 3 The figure is a schematic diagram of an implementation process of a chip problem locating method provided by an embodiment of the present invention.

[0092] Figure 3 In the implementation process shown, the simulation tool is a compiled code simulation tool (VCS simulation tool), and UCLI control commands are used to run the TCL simulation control program as an example for explanation.

[0093] like Figure 3As shown, first, the register signal data of the "reg" storage type that is synthesized into a register (that is, the materialized signal data) recorded in the scandump structure scan file is forcibly assigned to the simulation control program written by TCL through UCLI (the materialized signal data parsed from the scandump structure scan file is called by the call command); then, the simulation control program written by TCL is run in the VCS simulation tool, and the called signal data of the "reg" storage type that is synthesized into a register (the materialized signal data) and the original chip design code are combined to calculate the remaining signal data (that is, non-materialized signal data) defined in the original chip design code except for the signal data of the "reg" storage type that is synthesized into a register.

[0094] Since the internal logical operations of ultra-large-scale digital integrated circuits are very complex, logical reasoning about the original chip design code is also very difficult. In the embodiment of the present invention, with the help of simulation tools, the tedious manual calculation process is avoided. All signal data defined in the original chip design code can be directly calculated by the calculation process of the simulation tool. At the same time, all signal data can be presented in the form of signal waveforms in the form of waveform files.

[0095] At the same time, in embodiments of the present invention, when displaying all signal data defined in the original chip design code via a waveform file, since the waveform file displays the signal waveform formed by each signal data, that is, the continuous changes of this signal data within a certain time sequence, the method of displaying the signal waveform formed by the signal data via a waveform file in embodiments of the present invention can also display multi-bit signal data and two-dimensional array signal data defined in the original chip design code. Since the scandump structure scan file provides the substantiated signal data in single-bit form, when the single-bit substantiated signal data recorded in the scandump structure scan file is desired to be described correspondingly for some substantiated buffers such as FIFOs, the chip front-end designer needs to later splice the multiple single-bit substantiated signal data. In embodiments of the present invention, the output is performed in the form of a waveform file, so that the continuous data changes of the signal data within a certain time sequence can be presented as a signal waveform. This can avoid the need for the chip front-end designer to manually splice the multiple single-bit substantiated signal data, thus facilitating the chip front-end designer's processing.

[0096] It can be seen that in the chip problem locating method provided by the embodiment of the present invention, waveform files are used to display the signal waveforms restored from the materializable signal data and the non-materializable signal data, so that the chip front-end designers can directly observe the waveforms and find the location where the chip problem occurs, further accelerating the efficiency of chip problem locating and reducing the difficulty of chip problem locating.

[0097] Please continue to refer to Figure 2 , the method may further include:

[0098] Step S200: Generate substantiable signal data.

[0099] Step S200 may include:

[0100] Obtain a structural scan file inside the chip, the structural scan file including register path information of each register inside the chip and register values stored in each register; perform file parsing on the structural scan file; extract the register path information of each register and the corresponding stored register value in the structural scan file to obtain register signal data; and generate tangible signal data inside the chip based on the extracted register signal data of each register.

[0101] The structure scan file may be the scanump structure scan file described in the aforementioned embodiment, which stores the substantiated signal data of the hardware structure (register) inside the chip, ie, register signal data.

[0102] Parsing the structure scan file (scandump structure scan file) facilitates the subsequent mapping of the tangible signal data recorded in the structure scan file to the original chip design code. For example, by parsing the scanump structure scan file, the register path information in the scanump structure scan file can be mapped to the original design code. At the same time, combined with the register value corresponding to the register path information, the "reg" storage type signal data defined in the original design code is formed, making it easier for chip front-end designers to use the information in the scanump structure scan file for subsequent processing.

[0103] To facilitate understanding of the generation of the substantiable structural data, that is, the implementation process of step S200 , the embodiment of the present invention is described by taking a scandump structural scanning file as an example.

[0104] Please refer to Figure 4 , Figure 4 The present invention provides a schematic diagram of a process for generating tangible signal data in a chip problem locating method according to an embodiment of the present invention.

[0105] like Figure 4As shown, the process may include the following steps:

[0106] Step S300: Obtain a structural scan file inside the chip.

[0107] Step S301: parsing the structure scan file.

[0108] In the process of parsing the structure scan file, the scandump structure scan file read in line by line can be parsed, wherein each line of the scandump structure scan file corresponds to a register signal data.

[0109] Step S302, determine whether the register inside the chip is the target register, if yes, execute step S303, if not, execute step S307.

[0110] The target register can be determined based on the chip for which chip problem location is currently being performed. For example, if the chip for which chip problem location is currently being performed is a south bridge, the target register can be a register in the south bridge.

[0111] Step S303: extract the signal data of the target register to obtain the register signal data.

[0112] The register signal data of the target register includes register path information of the target register and a corresponding stored register value.

[0113] When it is determined that the register being read is the target register, the signal data of the target register can be read.

[0114] For example, a regular expression may be used to extract register path information and register value of a target register from a scandump structure scan file as signal data of the target register to obtain register signal data.

[0115] Step S304 , confirm whether the register path information can be mapped to the original chip design code, if yes, execute step S305 , if not, execute step S308 .

[0116] Step S305 : generating substantiated signal data within the chip based on the extracted register path information of each register and the corresponding stored register value.

[0117] After confirming that the extracted register path information can be mapped to the original chip design code, the chip internal substantiable signal data can be generated according to the extracted register path information of each register and the corresponding stored register value.

[0118] To obtain accurate and tangible signal data, please refer to Figure 5 , Figure 5 It is a flow chart of generating tangible signal data in the chip problem locating method provided by an embodiment of the present invention.

[0119] like Figure 5 As shown, the implementation of step S305 may include:

[0120] To accurately generate tangible signal data, in one embodiment, please continue to refer to Figure 3 , the method may further include:

[0121] Step S400 , performing path conversion on the extracted register path information to obtain converted register path information.

[0122] The converted register path information is standard register path information defined in the original chip design code.

[0123] Since the syntax structure used in the original chip design code is different, the corresponding representation structure of the register path information is different. For example, the use of the generate syntax in the original chip design code written in Verilog HDL will cause the structural representation of the register path information in the scandump structure scan file to be relatively special. The extracted register path information can be processed and converted into the representation structure of the register path information commonly found in the original chip design code.

[0124] The standard register path information defined in the original chip design code in the embodiment of the present invention is register path information represented in a unified syntax structure. The unified syntax structure can be a syntax structure commonly used in the original chip design code or a syntax structure that is easy to understand.

[0125] Therefore, in order to unify the representation of path structure information and facilitate subsequent use, the register path information represented by a special syntax structure may be preprocessed and represented according to a general syntax structure.

[0126] In order to improve the practicality of register path information conversion, in one embodiment, step S400 can adopt a built-in special path conversion commonly used to process the original chip design code, which is used to process the path conversion processing corresponding to the more special syntax structure often used when the original chip design code is written.

[0127] In other embodiments, if the representation structure of the register path information is not caused by the use of a more special syntax structure in the original chip design code, but is caused by a user-defined syntax structure representation; in this case, when performing register path information conversion, a customized special path conversion prompt can be provided to the user, and the user can convert the corresponding path information to obtain the converted register path information.

[0128] Among them, whether to provide the user with a customized special path conversion prompt can be determined based on actual conditions.

[0129] Step S401: Determine the register type of the register corresponding to the converted register path information.

[0130] After the register path information having the special representation structure is converted, subsequent analysis and processing can be performed based on the register corresponding to the converted register path information.

[0131] For example, the register type of the register may be analyzed based on the register corresponding to the converted register path information determined at this time.

[0132] Step S402: calling a corresponding mapping method according to the determined register type.

[0133] After the register type is determined, path mapping in the original chip design code can be performed according to the corresponding mapping method.

[0134] Step S403: Map the converted register path information using the called mapping method to obtain original register path information.

[0135] For example, when it is determined that the register type is a single-bit register type, the mapping method of the single-bit register type is called to map the converted register path information of the single-bit register type to the original register path information; when it is determined that the register type is a multi-bit register type, the mapping method of the multi-bit register type is called to map the converted register path information of the multi-bit register type to the original register path information; when it is determined that the register type is a two-dimensional array register type, the mapping method of the two-dimensional array register type is called to map the converted register path information of the two-dimensional array register type to the original register path information.

[0136] Step S404 : generating substantiated signal data based on the original register path information of each register and the corresponding stored register value.

[0137] By performing path conversion on the register path information extracted from the scandump structure scan file, the converted register path information is made consistent with the standard register path information defined in the original chip design code, facilitating subsequent unified processing. Furthermore, selecting mapping methods corresponding to different register types can improve the reliability of the mapped original register path information.

[0138] Please continue to refer to Figure 4 , the method further comprises:

[0139] Step S306, determining whether the structure scan file has been parsed, if yes, executing step S307, if not, continuing to execute step S301.

[0140] Step S307, ending the analysis of the structure scan file.

[0141] Step S308 : Save the register path information that is not mapped to the original chip design code and the corresponding stored register values and generate a log file.

[0142] The register path information that cannot be mapped to the original chip design code mainly includes the signals inserted by the chip during the back-end manufacturing or verification process and the register path information generated by the cross-clock domain synchronizer. This is because the signals inserted during the back-end manufacturing or verification process do not exist in the original chip design code, and the cross-clock domain synchronizer forms a scanump structure during the chip scanning process. During the scanning file, the order in which the clock stops may cause unreliable values, so these two signals are ignored and printed out to the log file log.

[0143] The register signal data corresponding to the register path information that cannot be mapped to the original chip design code is stored and output, so that the simulation process will not be interrupted due to the inability to map to the original chip design code.

[0144] The embodiment of the present invention also provides a chip problem location device, which is used to implement the chip problem location method provided in the above embodiment. Figure 6 , Figure 6 The figure is a schematic diagram of a chip problem location device provided by an embodiment of the present invention, and is applied to a simulation tool.

[0145] like Figure 6 As shown, the device may include:

[0146] An input data acquisition module 51 is configured to acquire the original chip design code and tangible signal data of the chip, wherein the tangible signal data is defined in the original chip design code and is based on chip internal register data acquired through chip scanning;

[0147] a data operation module 52 configured to perform operation processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, wherein the non-substantiable signal data is signal data defined in the original chip design code other than the substantiable signal data;

[0148] The problem locating module 53 is configured to locate chip problems based on the substantiable signal data and the non-substantiable signal data.

[0149] It can be seen that in the chip problem locating device provided by the embodiment of the present invention, based on the obtained chip internal materializable signal data and the original chip design code, calculation processing is performed to obtain non-materializable signal data, so that the signal data that cannot be reflected in the internal data of the chip and defined in the original chip design code, that is, the non-materializable signal data, can be quickly restored in the simulation tool. Therefore, after the simulation tool calculation processing is completed, all the signal data defined in the original chip design code can be obtained, and then the chip problem location can be performed based on the materializable signal data and the non-materializable signal data, so that the chip problem location can be quickly realized using the simulation tool, and the efficiency of the chip signal data processing is improved.

[0150] Please continue to refer to Figure 6 In some embodiments, the apparatus may further include:

[0151] A waveform file generating module 54 is configured to generate a waveform file based on the substantiable signal data and the non-substantiable signal data;

[0152] The problem locating module is configured to locate chip problems based on the substantiable signal data and the non-substantiable signal data, and includes:

[0153] Chip problem location is performed based on the waveform file.

[0154] The waveform file presentation method makes it easier for chip front-end designers to visually observe the data changes of all signal data, reducing the difficulty of chip positioning problems.

[0155] Please continue to refer to Figure 6 In some embodiments, the apparatus may further include:

[0156] A substantiable signal data generating module 50, configured to generate substantiable signal data;

[0157] The substantiable signal data generating module 50 is configured to generate substantiable signal data, including:

[0158] Obtain a structural scan file inside the chip, the structural scan file including register path information of each register inside the chip and register values stored in each register; perform file parsing on the structural scan file; extract the register path information of each register and the corresponding stored register value in the structural scan file to obtain register signal data; and generate tangible signal data inside the chip based on the extracted register signal data of each register.

[0159] In some embodiments, the apparatus may further comprise:

[0160] The path information confirmation module is used to confirm whether the extracted register path information can be mapped to the original chip design code; if so, the module controls the tangible signal data generation module 50 to execute the generation of tangible signal data inside the chip based on the extracted register path information of each register and the corresponding stored register value; if not, the register path information mapped to the original chip design code and the corresponding stored register value are saved and a log file is generated.

[0161] In some embodiments, the data operation module 52 is configured to perform operation processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, including:

[0162] defining a simulation control program applied to the simulation tool according to the instantiable signal data, wherein the simulation control program at least includes a call command for calling the instantiable signal data;

[0163] The simulation control program and the original chip design code are run through a simulation tool to obtain non-substantiable signal data.

[0164] An embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the chip problem locating method as described in any of the aforementioned embodiments.

[0165] An embodiment of the present invention provides a storage medium storing a program. When the program is executed, the chip problem locating method as described in any of the aforementioned embodiments is implemented.

[0166] An embodiment of the present invention provides a computer program product, including a computer program, which, when executed by a processor, implements the chip problem location method as described in any of the above embodiments.

[0167] The above describes multiple embodiment schemes provided by the embodiments of the present invention. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present invention.

[0168] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A chip problem location method, characterized in that: Applied to a simulation tool, the method includes: Obtaining original chip design code and substantiated signal data of a chip, wherein the substantiated signal data is defined in the original chip design code and is based on chip internal register data obtained by scanning the chip; performing computational processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, wherein the non-substantiable signal data is signal data defined in the original chip design code other than the substantiable signal data; Chip problem location is performed based on the tangible signal data and the non-tangible signal data.

2. The chip problem locating method according to claim 1, characterized in that: After the step of performing computational processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, and before the step of locating a chip problem based on the substantiable signal data and the non-substantiable signal data, the method further includes: generating a waveform file according to the materializable signal data and the non-materializable signal data; The chip problem location based on the substantiable signal data and the non-substantiable signal data includes: Chip problem location is performed based on the waveform file.

3. The chip problem locating method according to claim 2, characterized in that: Before the step of obtaining the original chip design code and the substantiable signal data of the chip, the method further includes: generating tangible signal data; Generating the substantiable signal data includes: Acquire a structure scan file inside the chip, where the structure scan file includes register path information of each register inside the chip and register values stored in each register; Performing file parsing on the structure scan file; Extracting register path information and corresponding stored register values of each register in the structure scan file to obtain register signal data; Based on the extracted register signal data of each register, signal data that can be materialized inside the chip is generated.

4. The chip problem locating method according to claim 3, characterized in that: The extracting register path information of each register in the structure scan file and the corresponding stored register value to obtain register signal data includes: When it is determined that the register inside the chip is the target register, the signal data of the target register is extracted to obtain the register signal data.

5. The chip problem locating method according to claim 4, characterized in that: After the step of extracting the signal data of the target register to obtain the register signal data when determining that the register inside the chip is the target register, the method further includes: Confirm whether the extracted register path information can be mapped to the original chip design code; If yes, then executing the step of generating chip internal substantiable signal data based on the extracted register path information of each register and the corresponding stored register value; If not, the register path information that is not mapped to the original chip design code and the corresponding stored register values are saved and a log file is generated.

6. The chip problem locating method according to claim 5, characterized in that: If it is confirmed that the extracted register path information can be mapped to the original chip design code, the step of generating chip internal substantiable signal data based on the extracted register path information of each register and the corresponding stored register value includes: Performing path conversion on the extracted register path information to obtain converted register path information, where the converted register path information is standard register path information defined in the original chip design code; Determine the register type of the register corresponding to the converted register path information; Call the corresponding mapping method according to the determined register type; Mapping the converted register path information using the called mapping method to obtain original register path information; Substantiable signal data is generated based on original register path information of each register and the corresponding stored register value.

7. The chip problem locating method according to any one of claims 1 to 6, characterized in that: The performing computational processing on the original chip design code and the substantiable signal data to obtain the non-substantiable signal data includes: defining a simulation control program applied to the simulation tool according to the instantiable signal data, wherein the simulation control program at least includes a call command for calling the instantiable signal data; The simulation control program and the original chip design code are run through a simulation tool to obtain non-substantiable signal data.

8. The chip problem locating method according to claim 7, characterized in that: The simulation control program also includes a simulation running command and a simulation result output command. The simulation result output command defines a result output method, a signal display form in the defined result output method, and the displayed signal data.

9. The chip problem locating method according to claim 8, characterized in that: The simulation tool includes a compiled code simulation tool, and defining a simulation control program applied to the simulation tool according to the substantiable signal data includes: According to the compiled code simulation tool used, a simulation control script file is defined in combination with the instantiable signal data to obtain a simulation control program applied to the compiled code simulation tool.

10. The chip problem locating method according to claim 8, characterized in that: The simulation tool includes a hardware description language simulation tool, and the defining of a simulation control program applied to the simulation tool according to the substantiable signal data includes: According to the hardware description language simulation tool used, the simulation control test file is defined in combination with the substantiable signal data to obtain a simulation control program applied to the hardware description language simulation tool.

11. A chip problem locating device, characterized in that: Applications in simulation tools include: An input data acquisition module is used to acquire the original chip design code and substantiated signal data of the chip, wherein the substantiated signal data is defined in the original chip design code and is based on chip internal register data acquired through chip scanning; a data operation module, configured to perform operation processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, wherein the non-substantiable signal data is signal data defined in the original chip design code other than the substantiable signal data; The problem locating module is used to locate chip problems based on the substantiable signal data and the non-substantiable signal data.

12. The chip problem locating device according to claim 11, characterized in that: Also includes: A waveform file generating module, configured to generate a waveform file according to the substantiable signal data and the non-substantiable signal data; The problem locating module is configured to locate chip problems based on the substantiable signal data and the non-substantiable signal data, and includes: Chip problem location is performed based on the waveform file.

13. The chip problem locating device according to claim 12, characterized in that: Also includes: A substantiable signal data generating module, used for generating substantiable signal data; The substantiable signal data generating module, configured to generate substantiable signal data, includes: Obtain a structural scan file inside the chip, the structural scan file including register path information of each register inside the chip and register values stored in each register; perform file parsing on the structural scan file; extract the register path information of each register and the corresponding stored register value in the structural scan file to obtain register signal data; and generate tangible signal data inside the chip based on the extracted register signal data of each register.

14. The chip problem locating device according to claim 13, characterized in that: Also includes: A path information confirmation module is used to confirm whether the extracted register path information can be mapped to the original chip design code; If yes, the said materializable signal data generation module is controlled to generate materializable signal data inside the chip based on the extracted register path information of each register and the corresponding stored register value; if no, the register path information and the corresponding stored register value that are not mapped to the original chip design code are saved and a log file is generated.

15. The chip problem locating device according to any one of claims 11 to 14, characterized in that: The data operation module is used to perform operation processing on the original chip design code and the substantiable signal data to obtain non-substantiable signal data, including: defining a simulation control program applied to the simulation tool according to the instantiable signal data, wherein the simulation control program at least includes a call command for calling the instantiable signal data; The simulation control program and the original chip design code are run through a simulation tool to obtain non-substantiable signal data.

16. An electronic device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a program, and the processor calls the program stored in the memory to execute the chip problem locating method according to any one of claims 1 to 10.

17. A storage medium, characterized in that: The storage medium stores a program, and when the program is executed, the chip problem locating method according to any one of claims 1 to 10 is implemented.

18. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the chip problem locating method according to any one of claims 1 to 10 is implemented.

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