Timing control and row-column drive circuit, drive method, and display device

Abstract

Embodiments of the present disclosure provide a timing control and row-column driving circuit, a driving method and a display device. The circuit is used for driving an active matrix including pixel units. The circuit includes an odd-even frame determination circuit, odd and even frame counting circuits, a column data control circuit and a row selection circuit. The odd frame counting circuit uses first and second counters. The even frame counting circuit uses third and fourth counters. The column data control circuit sequentially provides display data corresponding to each row of pixel units to the corresponding data line by means of the first, second, third and fourth counters in odd and even frames respectively. The difference between the time when two adjacent bits in the display data are provided to the corresponding data line is equal to the sum of the product of the weight of the previous bit and the unit display time and k clock cycles. The difference between the time when the same bit of the display data corresponding to two adjacent rows of pixel units is provided to the corresponding data line is equal to a first preset time.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of display technology, and more specifically, to timing control and row / column driving circuits, driving methods, and display devices. Background Technology

[0002] With the development of display technology, expectations for display devices are increasing. For example, display devices are expected to have the following advantages: high refresh rate, high grayscale, minimal cache, no impact on the maximum brightness of light-emitting diodes (LEDs), a relatively low operating clock frequency, and a simple structure. How to achieve as many of these expected advantages as possible for different practical application scenarios is a direction that requires further research. Summary of the Invention

[0003] The embodiments described herein provide a timing control and row / column driving circuit, driving method, and display device.

[0004] According to a first aspect of this disclosure, a timing control and row / column driving circuit is provided. This timing control and row / column driving circuit is used to drive an active matrix. The active matrix includes pixel units defined by the intersection of N row selection lines and M data lines. The row selection lines extend along the row direction. The data lines extend along the column direction. The timing control and row / column driving circuit includes: an odd / even frame determination circuit, an odd frame counting circuit, an even frame counting circuit, a column data control circuit, and a row selection circuit. The odd / even frame determination circuit is configured to generate an odd frame indication signal and an even frame indication signal based on a field synchronization signal. During an odd frame period, the odd frame indication signal is at an active level. During an even frame period, the even frame indication signal is at an active level. The odd frame counting circuit is configured to: while the odd frame indication signal is at an active level, use a first counter to count the number of clock cycles per unit display time and use a second counter to count the number of unit display times within a single odd frame. The even-frame counting circuit is configured to: during the active level of the even-frame indicator signal, use a third counter to count the number of clock cycles per unit display time and a fourth counter to count the number of unit display times within a single even-frame. The column data control circuit is configured to: in odd-numbered frames, for each row of pixel units, sequentially provide the display data corresponding to that row of pixel units to the corresponding data lines bit by bit using a first counter and a second counter. In even-numbered frames, for each row of pixel units, sequentially provide the display data corresponding to that row of pixel units to the corresponding data lines bit by bit using a third counter and a fourth counter. The time difference between the provision of two adjacent bits of display data to the corresponding data lines is equal to the sum of the weight of the preceding bit multiplied by the unit display time and k clock cycles, and the time difference between the provision of the same bits of display data corresponding to two adjacent rows of pixel units to the corresponding data lines is equal to a first preset time. This first preset time is less than or equal to the unit display time and greater than or equal to one clock cycle. The row selection circuit is configured such that, for each row of pixel units, when display data corresponding to that row of pixel units is provided to the corresponding data line, the row selection line corresponding to that row of pixel units is scanned so that display data is provided to the corresponding pixel units. Here, N and M are natural numbers greater than 1, and k is an integer greater than or equal to 0.

[0005] In some embodiments of this disclosure, odd-numbered frame periods and even-numbered frame periods partially overlap.

[0006] In some embodiments of this disclosure, the field synchronization signal originates from external circuitry. Blanking time exists between identical image rows of two adjacent image frames. The blanking time is the same for different image rows of the same image frame. The timing control and row / column driving circuitry also includes a collision detection circuit. The collision detection circuitry is configured to determine, by means of a first counter and a third counter, whether predetermined times for the provision of bits of display data from two adjacent image frames to the data lines overlap, and, if the predetermined times for the provision of two bits to the data lines overlap, to determine the priority of the two bits provided to the data lines. The column data control circuitry is further configured to provide the data lines with the higher-priority bit of the two bits at predetermined times, and to provide the data lines with the lower-priority bit of the two bits after one or more clock cycles of the predetermined time.

[0007] In some embodiments of this disclosure, the priority of two bits provided to the data line is set according to one of the following criteria: the priority of bits belonging to even frames is higher than the priority of bits belonging to odd frames; the priority of bits belonging to odd frames is higher than the priority of bits belonging to even frames; the priority of higher weight bits is higher than the priority of lower weight bits; and the priority of lower weight bits is higher than the priority of higher weight bits.

[0008] In some embodiments of this disclosure, a reservation period is provided before each bit of the display data of each image row in each image frame is provided to the data line. The timing control and row / column driving circuitry further includes a parameter latch circuit. The parameter latch circuit is configured to: in response to an update of the display parameters for an image frame within a specified time period, store the updated display parameters, and update the display parameters of the bit plane corresponding to that bit with the stored display parameters within a reservation period corresponding to each bit of the display data of the first image row of the image frame; and in response to an update of the display parameters for an image frame within a non-specified time period, store the updated display parameters, and update the display parameters of the bit plane corresponding to that bit with the stored display parameters within a reservation period corresponding to each bit of the display data of the first image row of the next image frame. The specified time period is the time period before the first bit of the display data of the first image row of an image frame is provided to the data line within each frame period. The parameter latch circuit includes an odd-frame parameter latch sub-circuit and an even-frame parameter latch sub-circuit. The display parameters for odd-numbered frames are stored in the odd-frame parameter latch sub-circuit. The display parameters for even-numbered frames are stored in the even-numbered frame parameter latch circuit.

[0009] In some embodiments of this disclosure, the display data has K gray levels. The column data control circuit includes K sub-buffer circuits. The row selection circuit includes K row scanning circuits. K is a natural number greater than 1. The i-th sub-buffer circuit among the K sub-buffer circuits is configured to store the i-th bit of the display data to be provided to M data lines. The i-th row scanning circuit among the K row scanning circuits is configured to sequentially scan N row selection lines at a first preset time interval within the display time of one image frame, so that the i-th bit of the display data stored in the i-th sub-buffer circuit can be provided to the pixel unit of the corresponding row. Here, i is a natural number greater than or equal to 1 and less than or equal to K.

[0010] In some embodiments of this disclosure, the data stored in the i-th sub-buffer circuit corresponds to multiple rows of pixel units, and after the data corresponding to a row of pixel units is provided to that row of pixel units, the i-th sub-buffer circuit stores the data of the next row of pixel units corresponding to the multiple rows of pixel units.

[0011] In some embodiments of this disclosure, the data stored in the i-th sub-buffer circuit corresponds to a row of pixel units, and after the stored data is provided to the row of pixel units, the i-th sub-buffer circuit stores the data corresponding to the next row of pixel units.

[0012] In some embodiments of this disclosure, the row selection circuit further includes a blanking scan circuit. The blanking scan circuit is configured to: starting from the time when the last bit of the display data in the first image row of each image frame is displayed reaches the sum of the product of the weight of that bit and the unit display time and k clock cycles, sequentially scan N row selection lines at a first preset time interval, so that blanking data can be provided to the pixel units of the corresponding row.

[0013] In some embodiments of this disclosure, the timing control and row / column driving circuit further includes a frame buffer circuit. The frame buffer circuit is configured to store display data of at least half a frame of image and to provide display data to be displayed to the column data control circuit. The display data of each image row in the at least half-frame of image is divided bit-by-bit into multiple sub-display data rows. Each sub-display data row corresponds to the same bit of the display data of the same image row.

[0014] In some embodiments of this disclosure, the at least half-frame image is stored in units of image rows. Within each image row, multiple sub-display data rows are arranged in the same bit order. The bit order includes: ascending bit order, descending bit order, or random bit order.

[0015] In some embodiments of the present disclosure, the frame buffer circuit is further configured to: after all the sub-display data rows in an image row are sent to the column data control circuit, load the next image row of the last image row stored in the frame buffer circuit at the storage location of the image row.

[0016] In some embodiments of the present disclosure, the frame buffer circuit is further configured to: provide sub-display data rows corresponding to different bits to the column data control circuit through multiple ports.

[0017] In some embodiments of the present disclosure, the display data has K-bit gray scale, and the frame buffer circuit includes K frame buffer sub-circuits. Among them, the i-th frame buffer sub-circuit is used to store the i-th sub-display data row in each image row. Among them, K is a natural number greater than 1, and i is a natural number greater than or equal to 1 and less than or equal to K.

[0018] In some embodiments of the present disclosure, the display data has K-bit gray scale. K is a natural number greater than 1. In the case of 2 K <N and the vertical synchronization signal comes from the internal circuit, after the first preset time from when the first bit of the display data in the last image row of the current image frame is provided to the corresponding pixel unit, the first bit of the display data in the first image row of the next image frame is provided to the corresponding pixel unit.

[0019] In some embodiments of the present disclosure, the display data has K-bit gray scale. K is a natural number greater than 1. In the case of 2 K <N, the binary value of each display data is shifted left by S bits so that 2 (K+S) ≥N. Among them, S is a natural number greater than 1.

[0020] In some embodiments of the present disclosure, the display data has K-bit gray scale. K is a natural number greater than 1. In the case of 2 K <N, for each row of pixel units, the time difference between providing two adjacent bits in the display data corresponding to the pixel units of this row to the corresponding data line is amplified by P times. Among them, P≥N / 2 K .

[0021] In some embodiments of the present disclosure, the display data has K-bit gray scale. K is a natural number greater than 1. In the case of 2 K ≥N, after the blanking time from when the time when the last bit of the display data in the first image row of the current image frame is displayed reaches the product of the weight value of this bit and the unit display time plus the sum of k clock cycles, the first bit of the display data in the first image row of the next image frame is provided to the corresponding pixel unit.

[0022] In some embodiments of this disclosure, when the field synchronization signal comes from internal circuitry, the blanking time is greater than or equal to zero.

[0023] In some embodiments of this disclosure, for each row of pixel units, the display data corresponding to that row of pixel units is sequentially provided to the corresponding data lines in the same bit order. The bit order includes: ascending order, descending order, or random order.

[0024] According to a second aspect of this disclosure, a display device is provided. The display device includes the timing control and row / column driving circuitry described in the first aspect of this disclosure.

[0025] According to a third aspect of this disclosure, a driving method is provided. This driving method is used to drive an active matrix. The active matrix includes pixel units defined by the intersection of N row selection lines and M data lines. The row selection lines extend along the row direction. The data lines extend along the column direction. Wherein, N and M are natural numbers greater than 1. The driving method includes: generating an odd-frame indication signal and an even-frame indication signal based on a field synchronization signal, wherein the odd-frame indication signal is active during the odd-frame period and the even-frame indication signal is active during the even-frame period; during the period when the odd-frame indication signal is active, using a first counter to count the number of clock cycles per unit display time and using a second counter to count the number of unit display times within a single odd-frame; during the period when the even-frame indication signal is active, using a third counter to count the number of clock cycles per unit display time and using a fourth counter to count the number of unit display times within a single even-frame; dividing the display data of each image row of the image frame into multiple sub-display data rows bit by bit, each sub-display data row corresponding to the same bit of the display data of the same image row; within the odd-frame, for each row of pixel units, using the first counter and the second counter to divide the multiple sub-display data corresponding to that row of pixel units... The rows are sequentially provided to the corresponding data lines. In even frames, for each row of pixel units, multiple sub-display data rows corresponding to that row of pixel units are sequentially provided to the corresponding data lines by means of a third counter and a fourth counter. The time difference between the provision of two adjacent sub-display data rows in the same image row to the corresponding data lines is equal to the sum of the weight of the former of the two sub-display data rows multiplied by the unit display time and k clock cycles. The time difference between the provision of sub-display data rows with the same weight corresponding to two adjacent rows of pixel units to the corresponding data lines is equal to a first preset time. The first preset time is less than or equal to the unit display time and greater than or equal to one clock cycle, where k is an integer greater than or equal to 0. For each row of pixel units, when the sub-display data rows corresponding to that row of pixel units are provided to the corresponding data lines, the row selection line corresponding to that row of pixel units is scanned so that the sub-display data rows are provided to that row of pixel units.

[0026] In some embodiments of this disclosure, odd-numbered frame periods and even-numbered frame periods partially overlap.

[0027] In some embodiments of this disclosure, the field synchronization signal comes from an external circuit. The driving method further includes: setting a blanking time between the same image lines of two adjacent image frames, wherein the blanking time is the same for different image lines of the same image frame; determining, by means of a first counter and a third counter, whether predetermined times for providing sub-display data lines of two adjacent image frames to a data line overlap, and determining the priority of providing the two sub-display data lines to the data line if the predetermined times for providing the two sub-display data lines to the data line overlap; and providing the data line with the higher priority sub-display data line of the two sub-display data lines at predetermined times, and providing the data line with the lower priority sub-display data line of the two sub-display data lines to the data line after one or more clock cycles of the predetermined time.

[0028] In some embodiments of this disclosure, the priority of two sub-display data lines provided to the data line is set according to one of the following criteria: the sub-display data line belonging to an even-numbered frame has a higher priority than the sub-display data line belonging to an odd-numbered frame; the sub-display data line belonging to an odd-numbered frame has a higher priority than the sub-display data line belonging to an even-numbered frame; the sub-display data line with a higher weight has a higher priority than the sub-display data line with a lower weight; and the sub-display data line with a lower weight has a higher priority than the sub-display data line with a higher weight.

[0029] In some embodiments of this disclosure, for each row of pixel units, scanning the row selection line corresponding to that row of pixel units when the sub-display data row corresponding to that row of pixel units is provided to the corresponding data line to provide the sub-display data row to that row of pixel units includes: within a frame period, when the predetermined time for the sub-display data row of the current image frame to be provided to the data line does not overlap with the predetermined time for the sub-display data row of other image frames to be provided to the data line, for each sub-display data row with different weights in the first image row, scanning N row selection lines sequentially at a first preset time interval starting from when the sub-display data row is provided to the corresponding data line; and within a frame period, when the predetermined time for the i-th sub-display data row of the j-th image row of the current image frame to be provided to the data line overlaps with the predetermined time for the sub-display data row of other image frames to be provided to the data line, scanning the j-th row selection line when the i-th sub-display data row is provided to the corresponding data line; wherein, the display data has K gray levels, K is a natural number greater than 1, i is a natural number greater than or equal to 1 and less than or equal to K, and j is a natural number greater than or equal to 1 and less than or equal to N.

[0030] In some embodiments of the present disclosure, the driving method further includes: setting a retention period before each sub-display data row of each image line of each image frame is provided to the data line; in response to the display parameters for an image frame being updated within a specified period, storing the updated display parameters, and updating the display parameters of the bit plane corresponding to the sub-display data row within the retention period corresponding to each sub-display data row of the first image line of the image frame with the stored display parameters; and in response to the display parameters for an image frame being updated within a non-specified period, storing the updated display parameters, and updating the display parameters of the bit plane corresponding to the sub-display data row within the retention period corresponding to each sub-display data row of the first image line of the next image frame with the stored display parameters. Wherein, the specified period is the period before the first sub-display data row of the first image line of an image frame is provided to the data line within each frame period. The display parameters of odd frames and even frames are stored separately.

[0031] In some embodiments of the present disclosure, for each row of pixel units, sequentially providing a plurality of sub-display data rows corresponding to the pixel units of that row to the corresponding data lines includes: for each row of pixel units, sequentially providing the sub-display data rows corresponding to the pixel units of that row to the corresponding data lines in the same bit order. Wherein, the bit order includes: ascending order of bits, descending order of bits, or disordered order of bits.

[0032] In some embodiments of the present disclosure, the driving method further includes: starting from the time when the time when the last sub-display data row in the first image line of each image frame is displayed reaches the product of the weight value of the sub-display data row multiplied by the unit display time plus the sum of k clock cycles, sequentially scanning N row selection lines at a first preset time interval, so that blanking data can be provided to the pixel units of the corresponding row.

[0033] In some embodiments of the present disclosure, the display data has K-bit gray scale. K is a natural number greater than 1. The driving method further includes: when 2 K <N and the vertical synchronization signal comes from the internal circuit, after a first preset time from the time when the first sub-display data row in the last image line of the current image frame is provided to the corresponding pixel unit, providing the first sub-display data row in the first image line of the next image frame to the corresponding pixel unit.

[0034] In some embodiments of the present disclosure, the display data has K-bit gray scale. K is a natural number greater than 1. The driving method further includes: when 2 K <N, shifting the binary value of each display data to the left by S bits so that 2 (K+S) ≥N. Wherein, S is a natural number greater than 1.

[0035] In some embodiments of the present disclosure, the display data has K bits of gray scale. K is a natural number greater than 1. The driving method further includes: at 2 K <When N, for each row of pixel units, the time difference between two sub-display data rows in adjacent bits in the same image row provided to the corresponding data line is amplified by P times. Where P ≥ N / 2 K .

[0036] In some embodiments of the present disclosure, the display data has K bits of gray scale. K is a natural number greater than 1. The driving method further includes: at 2 K ≥ N, after the blanking time starts from the time when the last sub-display data row in the first image row of the current image frame is displayed and reaches the sum of the product of the weight of the last sub-display data row and the unit display time and k clock cycles, the first sub-display data row in the first image row of the next image frame is provided to the corresponding pixel unit.

[0037] In some embodiments of the present disclosure, when the vertical synchronization signal comes from an internal circuit, the blanking time is greater than or equal to zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0039] Figure 1 shows a schematic structural diagram of a timing control and row-column driving circuit according to an embodiment of the present disclosure;

[0040] Figure 2 is a timing diagram of some signals of a timing control and row-column driving circuit according to an embodiment of the present disclosure;

[0041] Figure 3 is a timing diagram of some other signals of a timing control and row-column driving circuit according to an embodiment of the present disclosure;

[0042] Figure 4 is another timing diagram of some other signals of a timing control and row-column driving circuit according to an embodiment of the present disclosure;

[0043] Figure 5 shows another schematic structural diagram of a timing control and row-column driving circuit according to an embodiment of the present disclosure;

[0044] Figure 6 is for Figure 5 the timing diagram of some signals of the timing control and row-column driving circuit shown;

[0045] Figure 7A further schematic diagram of the timing control and row / column drive circuitry according to an embodiment of the present disclosure is shown;

[0046] Figure 8 This is yet another schematic diagram of the timing control and row / column drive circuit according to an embodiment of the present disclosure;

[0047] Figure 9 These are schematic block diagrams of a display device according to embodiments of the present disclosure; and

[0048] Figure 10 This is a schematic flowchart of a driving method according to an embodiment of the present disclosure.

[0049] It should be noted that the elements in the attached diagram are schematic and not drawn to scale. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are also within the scope of protection of this disclosure.

[0051] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this subject matter pertains. It will be further understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the specification and in the related art, and shall not be interpreted in an idealized or overly formal form unless otherwise explicitly defined herein. As used herein, statements that “connect” or “couple” two or more parts together shall mean that these parts are directly joined together or joined through one or more intermediate components. Furthermore, terms such as “first” and “second” are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0052] For ease of description, spatial relative terms such as “above,” “below,” “left,” “right,” “top,” and “bottom” are used here to describe the spatial positional relationship of a device or element to other devices or elements, as shown in the figures. For example, the terms “on,” “above,” “above,” “on the upper surface of,” “above,” “positioned on,” or “positioned on top of” mean that a first element, such as a first structure, exists on a second element, such as a second structure, where an intermediate element may or may not be present between the first and second elements. The term “contact” means connecting a first element, such as a first structure, and a second element, such as a second structure, where there may or may not be other elements at the interface between the two elements. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation in addition to the orientation of the device as described in the figures. For example, if the device in the figures is inverted, a device described as “above” or “on top of” other devices or structures will subsequently be positioned “below” or “under” other devices or structures. Thus, the exemplary term “above” can include both orientations of “above” and “below”. The device can also be positioned in other different ways, rotated 90 degrees, or in other orientations, and the spatial relative descriptions used here are explained accordingly.

[0053] Existing scanning algorithms for display devices struggle to achieve high performance in terms of refresh rate, grayscale, buffering, maximum brightness, and operating clock frequency. For example, the common subfield bit-plane scanning method divides each image frame into multiple subfields (e.g., all 0 bits of the display data in the image frame constitute the first subfield, all 1 bits of the display data in the image frame constitute the second subfield, and so on). Scanning begins only after all rows in one subfield have been completed. In this scanning method, increasing the image grayscale also increases the frequency of the display device's operating clock, making it difficult to achieve high grayscale. Furthermore, this scanning method requires the display device to buffer more than one image frame.

[0054] The embodiments of this disclosure provide a display device that achieves the technical effects of high grayscale, low operating clock frequency, and high refresh rate by using a multi-line parallel scanning method. Figure 1 A schematic diagram of the timing control and row / column drive circuitry 100 in a display device according to an embodiment of the present disclosure is shown. Figure 1 The diagram also shows N row selection lines R1, R2, R3, ..., R extending along the row direction. N M data lines C1, C2, C3, ..., C3 extending along the column direction. MAnd an active matrix 10. Timing control and row / column drive circuitry 100 is coupled to and used to drive the active matrix 10. For example... Figure 1 As shown, the timing control and row / column drive circuit 100 may include: an odd / even frame determination circuit 140, an odd frame counting circuit 150, an even frame counting circuit 160, a column data control circuit 120, and a row selection circuit 130.

[0055] The active matrix 10 may include N×M pixel units defined by the intersection of N row selection lines and M data lines. Figure 1 In the example, pixel units are represented by shaded boxes. Each row of pixel units is coupled to a row select line above it. Each column of pixel units is coupled to a data line to the left of it. As a row select line is scanned, the pixel units in that row coupled to that row select line receive corresponding display data in parallel via M data lines. Each pixel unit may include: a switching transistor, a light-emitting device (e.g., LED, OLED, or Micro-LED), and a memory unit (e.g., SRAM). The memory unit can store the display data received by the pixel unit so that the display data is displayed until new display data is written to the pixel unit.

[0056] In some embodiments of this disclosure, the timing control and row / column driving circuitry 100 is separate from the active matrix 10. For example, the timing control and row / column driving circuitry 100 may be located in the driver chip of the display device, while the active matrix 10 may be located on the display substrate of the display device. In other embodiments of this disclosure, the display device is a microdisplay device. The timing control and row / column driving circuitry 100 and the switching transistors and memory cells in the active matrix 10 are co-arranged in the driver chip, and the light-emitting devices in the active matrix 10 are arranged in an optical chip. The driver chip and the optical chip are bonded together.

[0057] The input of the odd / even frame determination circuit 140 is provided with a field synchronization signal Vsync. The two outputs of the odd / even frame determination circuit 140 are coupled to an odd frame counting circuit 150 and an even frame counting circuit 160, respectively. The odd / even frame determination circuit 140 is configured to generate an odd frame indication signal OVLD and an even frame indication signal EVLD based on the field synchronization signal Vsync. Specifically, the odd frame indication signal OVLD is active during the odd frame period, and the even frame indication signal EVLD is active during the even frame period. Figure 2An exemplary timing diagram is shown for the field synchronization signal Vsync, the odd frame indicator signal OVLD, and the even frame indicator signal EVLD. At time t1, the field synchronization signal Vsync first flips to an active level (high level), marking the start of the first frame period, and the odd frame indicator signal OVLD also flips to an active level (high level). At time t3, the field synchronization signal Vsync flips to an active level (high level) for the second time, marking the start of the second frame period, and the even frame indicator signal EVLD also flips to an active level (high level). At time t6, the field synchronization signal Vsync flips to an active level (high level) for the third time, marking the start of the third frame period, and the odd frame indicator signal OVLD again flips to an active level (high level). It can be seen that in this scenario, the rising edge of the field synchronization signal Vsync is used to synchronize the rising edges of the odd frame indicator signal OVLD and the even frame indicator signal EVLD.

[0058] An input to the odd-frame counting circuit 150 is coupled to an output of the odd-even frame determination circuit 140 to receive the odd-frame indication signal OVLD. The odd-frame counting circuit 150 is configured to: use a first counter CNT1 to count the number of clock cycles within a unit display time (also referred to as a "time slice") and use a second counter CNT2 to count the number of unit display times within a single odd-frame while the odd-frame indication signal OVLD is active; in this context, T represents a unit display time and t represents a clock cycle. Assume T = t × n, where n is a positive integer. During the odd-frame period, the first counter CNT1 is used to count the number of clock cycles t. The time it takes for the first counter CNT1 to count from 1 to n is one unit display time T. Assume the length of the odd-frame period is m × T, where m is a positive integer. During the odd-frame period, the second counter CNT2 is used to count the number of unit display times T, and the time it takes for the second counter CNT2 to count from 1 to m is one odd-frame period.

[0059] The input of the even-frame counting circuit 160 is coupled to another output of the odd-even frame determination circuit 140 to receive the even-frame indication signal EVLD. The even-frame counting circuit 160 is configured to: use a third counter CNT3 to count the number of clock cycles per unit display time and use a fourth counter CNT4 to count the number of unit display times within a single even-frame while the even-frame indication signal EVLD is active; during an even-frame period, use the third counter CNT3 to count the number of clock cycles t; the time it takes for the third counter CNT3 to count from 1 to n is one unit display time T; and use the fourth counter CNT4 to count the number of unit display times T, the time it takes for the fourth counter CNT4 to count from 1 to m is one even-frame period.

[0060] The column data control circuit 120 is configured to: in odd-numbered frames, for each row of pixel units, sequentially provide the display data (also referred to as image row in the context) corresponding to that row of pixel units to the corresponding data lines bit by bit (in the context, "bit" refers to "weight bit") using a first counter CNT1 and a second counter CNT2; in even-numbered frames, for each row of pixel units, sequentially provide the display data corresponding to that row of pixel units to the corresponding data lines bit by bit using a third counter CNT3 and a fourth counter CNT4. The time difference between the provision of two adjacent bits of the display data to the corresponding data lines is equal to the sum of the weight of the preceding bit multiplied by the unit display time and k clock cycles, and the time difference between the provision of the same bit of the display data corresponding to two adjacent rows of pixel units to the corresponding data lines is equal to a first preset time. The first preset time is less than or equal to the unit display time and greater than or equal to one clock cycle.

[0061] Here, k is an integer greater than or equal to 0. During display, the value of k may vary depending on the actual display timing. For example, in some embodiments of this disclosure, k is typically 0. In cases where there is a timing conflict when two or more bits of display data are supplied to the data line, the value of k may be appropriately increased. Simply put, k is 0 when there is no timing conflict; and k is an integer greater than 1 when a timing conflict occurs. A description of timing conflicts will be provided below. Figures 4-6 Let me explain in detail.

[0062] The length of the frame period can be adjusted by setting a first preset time. A longer first preset time results in a longer frame period, and a shorter first preset time results in a shorter frame period. When the frame period is longer than one cycle of the field synchronization signal Vsync, odd-numbered frame periods partially overlap with even-numbered frame periods. (Reference) Figure 2 The first frame cycle ends at time t4, while the field synchronization signal Vsync indicates the start of the second frame cycle at time t3, which is before time t4. The second frame cycle ends at time t7, while the field synchronization signal Vsync indicates the start of the third frame cycle at time t6, which is before time t7. Thus, there is partial overlap between odd-numbered and even-numbered frame cycles.

[0063] In some embodiments of this disclosure, for each row of pixel units, the display data (image row) corresponding to that row of pixel units is sequentially provided to the corresponding data line in the same bit order. For example, the display data of each image row is divided into multiple sub-display data rows by bit. Each sub-display data row corresponds to the same bit of the display data of the same image row. Assuming the display data has K gray levels, bit 0 of the display data of each image row forms the first sub-display data row, bit 1 of the display data of each image row forms the second sub-display data row, and so on, with bit K-1 of the display data of each image row forming the Kth sub-display data row. The weight of the first sub-display data row is 2. 0 =1. The weight of the second sub-row displayed data is 2. 1 =2. And so on, the weight of the Kth sub-row of displayed data is 2. K-1 .

[0064] In some embodiments of this disclosure, for each row of pixel units, the sub-display data rows are sequentially provided to the corresponding data lines in ascending bit order. In an example where the display data has K gray levels, the first sub-display data row is provided to the corresponding data line first, then the second sub-display data row is provided to the corresponding data line, and so on, until the Kth sub-display data row is provided to the corresponding data line.

[0065] In some other embodiments of this disclosure, for each row of pixel units, the sub-display data rows are sequentially provided to the corresponding data lines in descending bit order. In an example where the display data has K gray levels, the Kth sub-display data row is provided to the corresponding data line first, then the (K-1)th sub-display data row is provided to the corresponding data line, and so on, until the first sub-display data row is finally provided to the corresponding data line.

[0066] In some further embodiments of this disclosure, for each row of pixel units, the sub-display data rows are sequentially provided to the corresponding data lines in a bit-random (i.e., arbitrary) order. In an example where the display data has K gray levels, for example, the second sub-display data row may be provided to the corresponding data line first, then the Kth sub-display data row may be provided to the corresponding data line, and similarly, other sub-display data rows may be provided to the corresponding data lines in an arbitrary order until all sub-display data rows are provided to the corresponding data lines.

[0067] The row selection circuit 130 is configured to, for each row of pixel units, scan the row selection line corresponding to that row of pixel units when display data corresponding to that row of pixel units is provided to the corresponding data line, so that display data is provided to the corresponding pixel units. In some embodiments of this disclosure, "scanning the row selection line corresponding to that row of pixel units when display data corresponding to that row of pixel units is provided to the corresponding data line" can be understood as the action of providing display data to the data line and the action of scanning the row selection line occurring simultaneously. In other embodiments of this disclosure, "scanning the row selection line corresponding to that row of pixel units when display data corresponding to that row of pixel units is provided to the corresponding data line" can be understood as the action of scanning the row selection line being performed immediately after the action of providing display data to the data line occurs, and these two actions can be considered to occur in parallel. "Display data corresponding to that row of pixel units being provided to the corresponding data line" may include: any bit of the display data corresponding to that row of pixel units being provided to the corresponding data line. "Scanning the row selection line corresponding to the row pixel unit when the display data corresponding to the row pixel unit is provided to the corresponding data line so that the display data is provided to the corresponding pixel unit" may include: scanning the row selection line corresponding to the row pixel unit when any bit in the display data corresponding to the row pixel unit is provided to the corresponding data line so that the bit in the display data is provided to the corresponding pixel unit.

[0068] Figure 3 Timing diagrams of other signals used in timing control and row / column drive circuitry according to embodiments of the present disclosure are shown below. Reference is made below to... Figure 3 This will further describe the operation of the timing control and row / column drive circuit 100. Figure 3In the example, the display data has 2 gray levels and the number of row selection lines is 3, but those skilled in the art will understand that the embodiments of this disclosure do not limit the number of gray levels and the number of row selection lines. R1 represents the first row selection line. R2 represents the second row selection line. R3 represents the third row selection line. CLK represents the clock signal. DATA represents the data transmitted on M data lines. The display data of the first image line in each image frame is divided into two sub-display data lines bit by bit. The display data of the second image line in each image frame is also divided into two sub-display data lines bit by bit. The display data of the third image line in each image frame is also divided into two sub-display data lines bit by bit. In the following, d10 represents the first sub-display data line of the first image line in the first image frame. d11 represents the second sub-display data line of the first image line in the first image frame. d20 represents the first sub-display data line of the second image line in the first image frame. d21 represents the second sub-display data line of the second image line in the first image frame. d30 represents the first sub-display data line of the third image line in the first image frame. d31 represents the second sub-display data line of the third image row in the first image frame. d'10 represents the first sub-display data line of the first image row in the second image frame. The second image frame is the image frame displayed immediately following the first image frame.

[0069] In each image row, the weight of the first sub-display data row is 2. 0 =1. The weight of the second sub-row displayed data is 2. 1 = 2. Therefore, d10, d20, d30, and d'10 need to be displayed for one unit of display time. d11, d21, and d31 need to be displayed for two units of display time.

[0070] At time t1, the first row selection line R1 is scanned, and the first row of pixel units is provided with d10. Since the time difference between providing the same bit of sub-display data to two adjacent rows of pixel units is equal to the first preset time fst, the second row selection line R2 is scanned at time t2, and the second row of pixel units is provided with d20. At time t3, the third row selection line R3 is scanned, and the third row of pixel units is provided with d30. Figure 3 In the example, assuming the first preset time fst is less than half the unit display time T, d20 and d30 are displayed within the same unit display time T as d10. Figure 3In the example, k = 0. That is, the time difference between the provision of two adjacent bits of data to their corresponding data lines is equal to the product of the weight of the preceding bit and the unit display time. At time t4, an interval of one unit display time T from time t1, the first row selection line R1 is scanned, and the first row pixel unit is provided as d11. From time t4, after a first preset time fst (time t5), the second row selection line R2 is scanned, and the second row pixel unit is provided as d21. Note that the time interval between time t5 and time t2 is equal to the unit display time T. At time t6, an interval of one preset time fst from time t5, the third row selection line R3 is scanned, and the third row pixel unit is provided as d31. Note that the time interval between time t6 and time t3 is equal to the unit display time T. Since d11 needs to be maintained for 2 unit display times T, the first row selection line R1 is not scanned during the unit display time T from time T3 to time T4.

[0071] After three display time units T from time t1, the first image row in the first image frame has been displayed, and the first image row in the second image frame can begin to be displayed. At time t7, the first row selection line R1 is scanned, and the first row pixel unit d'10 is provided. It should be noted that the time interval between time t7 and time t4 is equal to two display time units T. The timing of the second image frame is the same as that of the first image frame; therefore, subsequent timing is omitted. The timing control and row / column driving circuit according to embodiments of this disclosure can continue processing subsequent image frames in the manner described above.

[0072] from Figure 3 As can be seen, there is a display time interval T between d11 and d10. There is also a display time interval T between d21 and d20. There is also a display time interval T between d31 and d30. There is a first preset time interval fst between d20 and d10. There is also a first preset time interval fst between d30 and d20. The display time for d10, d20, and d30 is T, and the display time for d11, d21, and d31 is 2T.

[0073] It is important to note that Figure 3 The time durations shown are illustrative and not drawn to scale.

[0074] In some embodiments of this disclosure, a retention period is provided before each bit of the display data of the first image line of each image frame is provided to the data line. The retention period is... Figure 3 The text is marked as rt. For example... Figure 3 As shown, there is actually a retention period rt after the start time of each unit display time T (e.g., T1, T2, T3, T4). The retention period rt can be less than the unit display time T.

[0075] In some embodiments of this disclosure, for each row of pixel units, there may be a blanking time between two adjacent image frames. During the blanking time of each row of pixel units, the storage units (e.g., SRAM) in that row of pixel units are cleared (reset). For example, after d11 is displayed for 2T time, a blanking time is allowed before d'10 is displayed (so the time difference between time t7 and time t4 is equal to 2T + blanking time). That is, after time T4, there is a blanking time (in Figure 3 (not shown in the image), followed by the blanking time and then the retention period rt.

[0076] In the subfield bit-by-bit planar scanning method, scanning of the next subfield only begins after all rows in a subfield have been scanned. However, in the timing control and row / column driving circuit 100 according to an embodiment of this disclosure, for any image row, the i-th sub-display data row of that image row does not need to wait for the (i-1)-th sub-display data rows in all image rows to be scanned before scanning begins. For example, refer to... Figure 3 Within a unit display time T, d20 and d10 are spaced apart by a first preset time fst. Since the first preset time fst can be set very small, d20 and d10 can be considered to be scanned in parallel. When the displayed data has K gray levels, K rows of pixel units can be scanned in parallel. In the timing control and row / column driving circuit 100 according to embodiments of this disclosure, the parallel scanning method can greatly reduce the number of clock cycles within the display time of a single frame, thereby reducing the clock frequency. Compared to the subfield bit-plane scanning method, the parallel scanning method according to embodiments of this disclosure requires a significantly lower clock frequency. When the image gray level is increased, the increase in clock frequency in the parallel scanning method according to embodiments of this disclosure is also much smaller than the increase in clock frequency when using the subfield bit-plane scanning method. The lower the clock frequency, the lower the power consumption of the display device. At the same clock frequency, compared to the subfield bit-plane scanning method, the parallel scanning method according to embodiments of this disclosure can support a higher refresh rate, thereby improving user viewing comfort.

[0077] exist Figure 3 In the example, the first preset time fst is less than half the unit display time T, so d20 and d30 are displayed within the same unit display time T as d10. Alternatively, the first preset time fst can also be greater than half the unit display time T. Figure 4 The timing diagram for this scenario is shown. Since the first preset time fst can also be greater than half the unit display time T, d20 and d10 are displayed within the same unit display time T, while d30 will be displayed within the next unit display time T. That is, d30 and d11 are displayed within the same unit display time T. Figure 4In the example, the interval between time t4, when d30 is provided to the third row of pixel units, and time t2, when d20 is provided to the second row of pixel units, is fst. In this case, there will be partial overlap between odd-numbered frame periods and even-numbered frame periods. Figure 4 and Figure 3 The difference also lies in, Figure 4 The example shown uses data with 2 gray levels and N row selection lines. Figure 4 The diagram also shows that within a certain display time T, dpq is provided to the p-th row pixel unit at time t6, and d'xy is provided to the x-th row pixel unit at time t8.

[0078] It is important to note that Figure 4 The time durations shown are illustrative and not drawn to scale.

[0079] Since the odd-numbered frame periods and even-numbered frame periods partially overlap, the embodiments of this disclosure set counters for the odd-numbered frame periods and even-numbered frame periods respectively, so as to better implement the signal control logic during the overlapping time period of the odd-numbered frame periods and improve the computational efficiency in practice.

[0080] In some embodiments of this disclosure, the field synchronization signal Vsync may originate from an external circuit. As described above, there is a blanking time between identical image lines of two adjacent image frames. The blanking time is the same for different image lines of the same image frame. When the field synchronization signal Vsync originates from an external circuit, since the field synchronization signal Vsync is not from the local clock, it is possible that the field synchronization signal Vsync is not an integer multiple of the unit display time T. In practical applications, the number of rows N of the active matrix is ​​typically significantly higher than 2. K (K represents the grayscale level of the displayed data), see reference Figure 3 or Figure 4 If the field synchronization signal Vsync is not an integer multiple of the unit display time T, there may be a conflict in the scheduled display time of two image lines in two adjacent frames.

[0081] Therefore, some embodiments of this disclosure propose to include a collision detection circuit in the timing control and row / column drive circuits. Figure 5A schematic diagram of a timing control and row / column drive circuit 400 equipped with a collision detection circuit is shown. The collision detection circuit 470 is configured to: determine, by means of a first counter CNT1 and a third counter CNT3, whether the predetermined times for providing bits of display data of two adjacent image frames to the data lines (i.e., the predetermined display times of the two bits) overlap, and, if the predetermined times for providing the two bits to the data lines overlap, determine the priority of providing the two bits to the data lines. In one example, when the first counter CNT1 counts to a first predetermined value, the load flag for odd-numbered frames can be set. The load flag for odd-numbered frames is used to indicate that a bit of display data of an odd-numbered frame is provided to the data lines. When the third counter CNT3 counts to a second predetermined value, the load flag for even-numbered frames can be set. The load flag for even-numbered frames is used to indicate that a bit of display data of an even-numbered frame is provided to the data lines. If the load flags for odd-numbered frames and even-numbered frames are set simultaneously, it indicates that the predetermined times for providing the two bits to the data lines overlap.

[0082] refer to Figure 4 Assume the retention period rt is x clock cycles (rt = x × t). The scheduled time for dpq to be provided to the data line is the first clock cycle after the retention period rt (time t6), and the scheduled time for d'xy to be provided to the data line is the third clock cycle after the retention period rt (time t8). dpq represents the q-th sub-display data line of the p-th image row in a certain image frame, and d'xy represents the y-th sub-display data line of the x-th image row in the next image frame. When the first counter CNT1 counts to x+1, it indicates that the scheduled display time for dpq has elapsed. When the third counter CNT3 counts to x+3, it indicates that the scheduled display time for d'xy has elapsed. Since the starting counting time of the first counter CNT1 is affected by the blanking time between two frames (the blanking time after time T4), it is possible that when the first counter CNT1 counts to x+1, the third counter CNT3 counts to x+3, thus causing the scheduled display times for dpq and d'xy to overlap. Upon detecting such a collision, the collision detection circuit 470 determines the priority of the two bits provided to the data line. In some embodiments of this disclosure, the priority of the two bits provided to the data line is set according to one of the following criteria: bits belonging to even frames have a higher priority than bits belonging to odd frames; bits belonging to odd frames have a higher priority than bits belonging to even frames; higher-weighted bits have a higher priority than lower-weighted bits; and lower-weighted bits have a higher priority than higher-weighted bits.

[0083] In this configuration, the column data control circuit is configured to provide the higher-priority bit of the two bits to the data line at a predetermined time, and to provide the lower-priority bit of the two bits to the data line one clock cycle after the predetermined time.

[0084] Figure 6 This illustrates a solution for the case where the scheduled display times of dpq and d'xy overlap. For example... Figure 6 As shown, assuming dpq has a higher priority than d'xy, then dpq will be displayed at time t6 (at which time the p-th row selection line is scanned, and the p-th row selection line is not shown), and d'xy will be displayed at time t7 (at which time the x-th row selection line is scanned, and the x-th row selection line is not shown). If time t7 is still the scheduled display time for other sub-display data lines, then the display of d'xy or other sub-display data lines will be delayed according to the preset priority standard.

[0085] It is important to note that Figure 6 The time durations shown are illustrative and not drawn to scale.

[0086] In practice, the display parameters of an image frame may be updated at any time. If the updated display parameters take effect during scanning, it will affect the image display and cause flickering. Therefore, the display parameters need to be updated at the beginning of a frame (i.e., updates are only allowed when scanning is not in progress). However, with the parallel scanning scheme of this disclosure, if the display parameters are only updated at the beginning of a frame, the display parameters of the current frame may have already been updated before the previous frame has been scanned, which will also affect the image display and cause flickering.

[0087] Therefore, some embodiments of this disclosure propose setting parameter latching circuits in the timing control and row / column driving circuits. The parameter latching circuit is configured to: in response to an update of display parameters for an image frame within a specified time period, store the updated display parameters, and update the display parameters of the bit plane corresponding to that bit with the stored display parameters within a reserved time period corresponding to each bit of the display data of the first image row of the image frame; and in response to an update of display parameters for an image frame outside the specified time period, store the updated display parameters, and update the display parameters of the bit plane corresponding to that bit with the stored display parameters within a reserved time period corresponding to each bit of the display data of the first image row of the next image frame. The specified time period is the time period before the first bit of the display data of the first image row of the image frame is provided to the data line within each frame period. A bit plane refers to a plane composed of sub-display data rows with equal weights. For example, in... Figure 2 In the example, d10, d20, and d30 form the bit plane for bit 0. d11, d21, and d31 form the bit plane for bit 1.

[0088] In some embodiments of this disclosure, the parameter latching circuit includes an odd-frame parameter latching sub-circuit and an even-frame parameter latching sub-circuit. Display parameters for odd-numbered frames are stored in the odd-frame parameter latching sub-circuit. Display parameters for even-numbered frames are stored in the even-frame parameter latching sub-circuit. Thus, assuming the display parameters for odd-numbered frames are updated outside of a specified time period, the updated display parameters for the odd-numbered frames are stored in the odd-frame parameter latching sub-circuit. The currently displayed even-numbered frame can continue to be displayed using the display parameters for the even-numbered frames stored in the even-frame parameter latching sub-circuit, therefore the current display effect is not affected.

[0089] In a further embodiment of this disclosure, the parameter latch circuit may further include a global parameter latch sub-circuit. The global parameter latch sub-circuit can store initial display parameters for each frame. When the display parameters need to be updated, the display parameters stored in the global parameter latch sub-circuit are updated. Odd-frame parameter latch sub-circuits and even-frame parameter latch sub-circuits can retrieve updated display parameters from the global parameter latch sub-circuit during odd-frame and even-frame periods, respectively.

[0090] Figure 7 Show Figure 1 This is a schematic diagram illustrating an exemplary internal structure of the column data control circuit and row selection circuit in the timing control and row / column drive circuitry. In the following explanation, we will continue to use the example of displaying data with K gray levels. K is a natural number greater than 1. Figure 7 In the timing control and row / column drive circuit 800 shown, the column data control circuit 820 includes K sub-buffer circuits b1, ..., b2. K The row selection circuit 830 includes K row scanning circuits B1, ..., B2. K K sub-buffer circuits b1, ..., b K They are respectively coupled to K row scanning circuits B1, ..., B K For example, the first sub-buffer circuit b1 is coupled to the first row scan circuit B1. Similarly, the Kth sub-buffer circuit b... K Coupled to the Kth row scanning circuit B K .

[0091] K sub-buffer circuits b1, ..., b K Different sub-buffer circuits are used to store different bits (different sub-display data rows) of display data to be provided to M data lines. For example, K sub-buffer circuits b1, ..., b K The i-th sub-buffer circuit is configured to store the i-th bit (i-th sub-display data line) of the display data to be provided to the M data lines. The first sub-buffer circuit b1, for example, stores the first sub-display data line. And so on, the K-th sub-buffer circuit b... K For example, storing the Kth child display data row.

[0092] K row scanning circuits B1, ..., B K Different row scanning circuits in the array have the same scanning frequency but different start scanning times. For example, the i-th row scanning circuit in the K row scanning circuits is configured to scan N row selection lines sequentially at first preset time intervals within the display time of one image frame, so that the i-th bit of the display data stored in the i-th sub-buffer circuit can be provided to the pixel unit of the corresponding row. (Reference) Figure 3 For example, starting from time t1, the first row scanning circuit B1 sequentially scans N row selection lines at time intervals of a first preset time fst, so that the first sub-display data line stored in the first sub-buffer circuit b1 can be provided to the pixel unit of the corresponding row. Starting from time (t1+T) (time t4), the second row scanning circuit sequentially scans N row selection lines at time intervals of fst, so that the second sub-display data line stored in the second sub-buffer circuit can be provided to the pixel unit of the corresponding row.

[0093] In this context, i is a natural number greater than or equal to 1 and less than or equal to K.

[0094] The following is combined Figure 3 Examples are used to describe K sub-buffer circuits b1, ..., b K With K row scanning circuits B1, ..., B K The process is as follows: At time t1, the first row scanning circuit B1 scans the first row selection line R1, and d10 stored in the first sub-buffer circuit b1 is provided to the first row pixel unit. At time t2, an interval fst from time t1, the first row scanning circuit B1 scans the second row selection line R2, and d20 stored in the first sub-buffer circuit b1 is provided to the second row pixel unit. In this way, the first row scanning circuit B1 scans N row selection lines sequentially at a first preset time interval fst within the display time of one image frame, so that the first bit (bit 0) of the display data stored in the first sub-buffer circuit can be provided to the pixel unit of the corresponding row.

[0095] At time t4, the second row scanning circuit scans the first row selection line R1, and d11 stored in the second sub-buffer circuit is provided to the first row pixel unit. At time t5, an interval fst from time t4, the second row scanning circuit scans the second row selection line R2, and d21 stored in the second sub-buffer circuit is provided to the second row pixel unit. In this way, the second row scanning circuit scans N row selection lines sequentially at a first preset time interval fst within the display time of one image frame, so that the second bit (bit 1) of the display data stored in the second sub-buffer circuit can be provided to the pixel unit of the corresponding row.

[0096] Thus, there are K row scanning circuits B1, ..., B K Different row scanning circuits in the array have the same scanning frequency (scanning one row selection line every fst time interval) and the starting scanning times of two adjacent row scanning circuits differ by T. For each row scanning circuit, the scanning frequency is fixed and can therefore be implemented using a simple shift register.

[0097] Dedicated row scanning circuits for each bit of the displayed data simplify the scanning logic of the row selection circuit. Dedicated sub-buffer circuits for each bit of the displayed data simplify the control logic of the column data control circuit.

[0098] In some embodiments of this disclosure, in application scenarios where a blanking time is set between two adjacent image frames, the line selection circuit 830 may further include a blanking scan circuit. The blanking scan circuit is configured to: starting from the time when the last bit of the display data in the first image line of each image frame is displayed reaches the sum of the product of the bit's weight multiplied by the unit display time and k clock cycles, sequentially scan N line selection lines at first preset time intervals, so that blanking data can be provided to the pixel units of the corresponding line. Here, the blanking data is a fixed value, therefore, a dedicated sub-buffer circuit for the blanking data is not required.

[0099] In some embodiments of this disclosure, the data stored in the i-th sub-buffer circuit corresponds to multiple rows of pixel units (multiple i-th sub-display data rows), and after the data corresponding to a row of pixel units (an i-th sub-display data row) is provided to that row of pixel units, the i-th sub-buffer circuit stores (is shifted in) the data of the next row of pixel units corresponding to that multiple rows of pixel units. These multiple rows of pixel units are, for example, consecutive rows of pixel units. For example, the first sub-buffer circuit b1 stores d10 and d20. After d10 is provided to the first row of pixel units, the first sub-buffer circuit shifts in the first sub-display data row (which may be represented by d30) following d20 to cover d10. Because the data stored in the i-th sub-buffer circuit is redundant, the rate requirement for storing data to this sub-buffer circuit is not too stringent.

[0100] In other embodiments of this disclosure, the data stored in the i-th sub-buffer circuit corresponds to a row of pixel units (an i-th sub-display data row), and after the stored data is provided to that row of pixel units, the i-th sub-buffer circuit stores data corresponding to the next row of pixel units. For example, the first sub-buffer circuit b1 stores d10. After d10 is provided to the first row of pixel units, the first sub-buffer circuit can directly use d20 to overwrite d10. In this embodiment, the amount of data stored in the i-th sub-buffer circuit is smaller, which can save storage space and thus reduce the area of ​​the timing control and row / column drive circuit 800.

[0101] In some embodiments of this disclosure, the timing control and row / column driving circuitry further includes a frame buffer circuit. Figure 8 A schematic diagram of this timing control and row / column drive circuit is shown. Figure 8 In the timing control and row / column drive circuit 900, the frame buffer circuit 990 is coupled to the column data control circuit 820. The frame buffer circuit 990 is configured to store display data for at least half a frame of image and to provide display data to be displayed to the column data control circuit 820. "Display data to be displayed" can be understood here as the display data that is about to be displayed. "Display data for half a frame of image" here refers to half of the display data for one frame of image. "Display data for at least half a frame of image" here refers to at least half of the display data for one frame of image. Assuming one frame of image includes N image rows, then half a frame of image refers to N / 2 image rows, and at least half a frame of image refers to at least N / 2 image rows.

[0102] In some embodiments of this disclosure, the number of image rows stored in the frame buffer circuit 990 is related to the time difference between different image frames being loaded into the frame buffer circuit 990. When the time difference between different image frames being loaded into the frame buffer circuit 990 (which can be calculated as the difference between the time when the first image row of the next image frame is loaded into the frame buffer circuit 990 and the time when the last image row of the current image frame is loaded into the frame buffer circuit 990) is less than or equal to the time difference between different image rows within the same image frame being loaded into the frame buffer circuit 990, the frame buffer circuit 990 may store only half a frame's display data. When the time difference between different image frames being loaded into the frame buffer circuit 990 is greater than the time difference between different image rows within the same image frame being loaded into the frame buffer circuit 990, the frame buffer circuit 990 needs to store more than half a frame's display data to avoid image data loss.

[0103] In the frame buffer circuit 990, the display data of each image line is divided into multiple sub-display data lines bit by bit. Each sub-display data line corresponds to the same bit of the display data of the same image line. Assume a frame image includes 4 image lines and has 3-bit grayscale. Bit 0 of the display data of each image line forms the first sub-display data line, bit 1 of the display data of each image line forms the second sub-display data line, and bit 2 of the display data of each image line forms the third sub-display data line. Thus, the first image line is divided into three sub-display data lines d10, d11, and d12. The second image line is divided into three sub-display data lines d20, d21, and d22, and so on. Here, d10 represents the first sub-display data line of the first image line. d11 represents the second sub-display data line of the first image line. d12 represents the third sub-display data line of the first image line. d20 represents the first sub-display data line of the second image line. d21 represents the second sub-display data line of the second image line. d22 represents the third sub-display data row of the second image row. And so on.

[0104] In some embodiments of this disclosure, the at least half-frame image is stored in image rows. Multiple sub-display data rows are arranged bit-by-bit within each image row. In some embodiments of this disclosure, the multiple sub-display data rows are arranged in the same bit order within each image row. In one example, the multiple sub-display data rows are arranged in ascending bit order within each image row. For example, in frame buffer circuit 990, the display data of the at least half-frame image may be stored in the order d10, d11, d12, d20, d21, d22. In another example, the multiple sub-display data rows are arranged in descending bit order within each image row. For example, in frame buffer circuit 990, the display data of the at least half-frame image may be stored in the order d12, d11, d10, d22, d21, d20. In yet another example, the multiple sub-display data rows are arranged in random (arbitrary) bit order within each image row. For example, in the frame buffer circuit 990, the display data of at least half a frame of image can be stored in the order d11, d12, d10, d21, d22, d20. It should be noted that even if the sub-display data rows are arranged in a bit-out order, multiple sub-display data rows in each image row are still arranged in the same bit order.

[0105] In some embodiments of this disclosure, the frame buffer circuit 990 may be configured to load the next image row of the last image row already stored by the frame buffer circuit 990 at the storage location of an image row after all sub-display data rows of an image row have been sent to the column data control circuit. In the case where the frame buffer circuit 990 only stores display data for half a frame of image, in an example where a frame of image includes four image rows and has three grayscale levels, after all sub-display data rows (d10, d11, and d12) of the first image row have been sent to the column data control circuit 820, the storage location of the first image row is updated with the next image row (third image row) of the last image row (second image row) already stored by the frame buffer circuit 990. For example, the frame buffer circuit 990 initially stores d10, d11, d12, d20, d21, and d22. After d10, d11, and d12 are sent to the column data control circuit 820, the frame buffer circuit 990 is updated to store d20, d21, d22, d30, d31, and d32. d30 represents the first sub-display data row of the third image row. d31 represents the second sub-display data row of the third image row. d32 represents the third sub-display data row of the third image row. Since all sub-display data rows of the first image row have been sent to the column data control circuit when the third image row begins scanning, the frame buffer circuit 990 no longer needs to store the first image row. Therefore, the frame buffer circuit 990 can store at least half a frame of image, reducing the buffer area compared to the sub-field bit-by-bit plane scanning method, thereby reducing the area of ​​the timing control and row / column driving circuits. For Micro-LED display devices, the reduction in the area of ​​the timing control and row / column driving circuits can significantly reduce the size of the driver chip package. Furthermore, for some applications with high requirements for chip package size, the timing control and row / column driving circuits according to the embodiments of this disclosure can also bring significant area advantages.

[0106] In some embodiments of this disclosure, the frame buffer circuit 990 can be configured to provide sub-display data rows corresponding to different bits to the column data control circuit 820 through multiple ports. Multiple ports can perform read operations simultaneously, and the frame buffer circuit 990 supports addressing operations.

[0107] In some embodiments of this disclosure, the frame buffer circuit 990 may include K frame buffer sub-circuits. The i-th frame buffer sub-circuit is used to store the i-th sub-display data row in each image row. For example, the first frame buffer sub-circuit is used to store d10, d20, and d30. The second frame buffer sub-circuit is used to store d11, d21, and d31. The third frame buffer sub-circuit is used to store d12, d22, and d32, and so on. The K ports of the frame buffer circuit 990 correspond one-to-one with the K frame buffer sub-circuits, facilitating simultaneous read operations on all K ports and addressing operations by the frame buffer circuit 990.

[0108] Combined with Figure 3 Taking the example of Figure 3 , before time t1, the frame buffer circuit 990 can be addressed to the storage location of d10 and provide d10 to the first sub-buffer circuit b1 in the column data control circuit 820 through the first port. In parallel or before time t4, the frame buffer circuit 990 can be addressed to the storage location of d11 and provide d11 to the second sub-buffer circuit in the column data control circuit 820 through the second port. Before time t2, the frame buffer circuit 990 can be addressed to the storage location of d20 and provide d20 to the first sub-buffer circuit b1 in the column data control circuit 820 through the first port. And so on. Since different sub-display data rows are output through different ports, different sub-display data rows can be output in parallel, thereby achieving a faster reading speed to match the above parallel scanning method.

[0109] Assume that the display data in the image frame has K-bit gray scale, and the image frame includes N image rows. N and K are natural numbers greater than 1. Then there may be two cases of 2 K <N and 2 K ≥N.

[0110] In some embodiments of the present disclosure, in the case of 2 K ≥N, after the blanking time elapses starting from the time when the last bit of the display data in the first image row of the current image frame is displayed and reaching the sum of the product of the weight of this bit and the unit display time and k clock cycles (i.e., the display of the first image row ends), the first bit of the display data in the first image row of the next image frame is provided to the corresponding pixel unit. In this way, for each row of pixel units, if the blanking time is not considered, it can be considered that the displays of adjacent image frames are continuous in time. In some embodiments of the present disclosure, the blanking time can be zero.

[0111] In some embodiments of the present disclosure, in the case of 2 K <N, after the first preset time fst elapses starting from the time when the first bit of the display data in the last image row of the current image frame is provided to the corresponding pixel unit, the first bit of the display data in the first image row of the next image frame is provided to the corresponding pixel unit. In this way, the same bits of different image rows will not be scanned simultaneously, and the scanning logic is simpler. As described above, the time difference between the times when two adjacent bits in the display data are provided to the corresponding data lines is equal to the sum of the product of the weight of the previous bit of the two bits and the unit display time T and k clock cycles, that is, the time when the sub-display data row with a weight of 2 i is displayed is 2 i ×T + k×t. It can be obtained that the time when each image row is displayed is Approximately Since the time difference between the start times of two adjacent image lines for display is equal to fst, when the last image line starts to be displayed, the time from the start time of the first image line is (N - 1)×fst. Since 2 K <N, if the value of fst is set to be relatively large, (N - 1)×fst can be made greater than Therefore, when the last image line starts to be displayed, the first image line has already finished being displayed. Thus, for each row of pixel units, there is a period of non-display time between two adjacent image frames, resulting in a loss of overall display brightness.

[0112] Regarding the problem of loss of display brightness in the case of 2 K <N, some embodiments of the present disclosure propose a solution to expand the gray scale. The K-bit gray scale can be expanded into a (K + S)-bit gray scale. Here, S is a natural number greater than 1. In this solution, the binary value of each display data is shifted left by S bits to make 2 (K+S) ≥N. Thus, (N - 1)×fst is less than Therefore, when the last image line starts to be displayed, the first image line has not finished being displayed. For each row of pixel units, there is no such period of non-display time (only the preset blanking time) between two adjacent image frames, so there is no loss of overall display brightness.

[0113] Since the gray scale is expanded, S additional sub-buffer circuits and S additional row scanning circuits need to be added for the expanded S bits, resulting in an increase in the area of the timing control and row-column driving circuits. Some embodiments of the present disclosure further propose a solution that can avoid loss of display brightness without increasing the area of the timing control and row-column driving circuits. In this solution, for each row of pixel units, the time difference between two adjacent bits in the display data corresponding to this row of pixel units provided to the corresponding data line is magnified by P times. That is, the time for each sub-display data row to be displayed is magnified by P times. Here, P≥N / 2 K . Thus, the time for each image line to be displayed is Since P≥N / 2 K , therefore, (N - 1)×fst is less than Thus, when the last image line starts to be displayed, the first image line has not finished being displayed. For each row of pixel units, there is no such period of non-display time (only the preset blanking time) between two adjacent image frames, so there is no loss of overall display brightness.

[0114] Figure 9 Fig. shows a schematic block diagram of a display device 1000 according to an embodiment of the present disclosure. The display device 1000 may include as Figure 1The timing control and row / column drive circuit 100 is shown. The display device 1000 provided in this embodiment can be applied to any product with display function, such as electronic paper, mobile phones, tablet computers, televisions, laptops, digital photo frames, wearable devices, or navigators.

[0115] Figure 10 A schematic flowchart of a driving method 1100 according to an embodiment of the present disclosure is shown. Figure 10 The driving method 1100 shown can be used to drive an active matrix. The active matrix comprises pixel units defined by the intersection of N row selection lines and M data lines. The row selection lines extend along the row direction. The data lines extend along the column direction.

[0116] In driving method 1100, at block S1102, an odd-frame indicator signal OVLD and an even-frame indicator signal EVLD are generated based on the field synchronization signal Vsync. During the odd-frame period, the odd-frame indicator signal OVLD is at an active level, and during the even-frame period, the even-frame indicator signal EVLD is at an active level. In some embodiments of this disclosure, the odd-frame period and the even-frame period partially overlap.

[0117] At box S1104, while the odd frame indicator signal OVLD is at an active level, the first counter CNT1 is used to count the number of clock cycles per unit display time, and the second counter CNT2 is used to count the number of unit display times within a single odd frame.

[0118] At box S1106, while the even-numbered frame indicator signal EVLD is at an active level, the third counter CNT3 is used to calculate the number of clock cycles per unit display time, and the fourth counter CNT4 is used to calculate the number of unit display times within a single even-numbered frame.

[0119] At frame S1108, the display data of each image row of the image frame is divided into multiple sub-display data rows by bit, with each sub-display data row corresponding to the same bit of the display data of the same image row. For example, bit 0 of the display data of each image row forms the first sub-display data row, bit 1 of the display data of each image row forms the second sub-display data row, bit 2 of the display data of each image row forms the third sub-display data row, and so on. The weight of the first sub-display data row is 2. 0 =1. The weight of the second sub-row displayed data is 2. 1 =2. The weight of the third child data row is 2. 2 =4. And so on.

[0120] At frame S1110, for each row of pixel units, multiple sub-display data rows corresponding to that row of pixel units are sequentially provided to the corresponding data lines. Specifically, the time difference between providing two adjacent sub-display data rows within the same image row to the corresponding data line is equal to the sum of the weight of the former of the two sub-display data rows multiplied by the unit display time and k clock cycles. Furthermore, the time difference between providing sub-display data rows with the same weight to the corresponding data lines corresponding to two adjacent rows of pixel units is equal to a first preset time. The first preset time is less than or equal to the unit display time and greater than or equal to one clock cycle.

[0121] At box S1112, for each row of pixel units, when the sub-display data line corresponding to that row of pixel units is provided to the corresponding data line, the row selection line corresponding to that row of pixel units is scanned so that the sub-display data line is provided to that row of pixel units.

[0122] The action performed at box S1104 can be executed concurrently with the action performed at box S1106. The action performed at box S1112 can be executed in parallel with the action performed at box S1108.

[0123] In the following example, T represents the unit display time, and t represents the clock cycle. In driving method 1100, after the first sub-display data line in the first image line is displayed for (T+k×t) time, the second sub-display data line in the first image line is displayed for (2T+k×t) time. Then, the third sub-display data line in the first image line is displayed for (4T+k×t) time. And so on. After fst time elapses since the first sub-display data line in the first image line was displayed, the first sub-display data line in the second image line begins to be displayed. After fst time elapses since the first sub-display data line in the second image line was displayed, the first sub-display data line in the third image line begins to be displayed. And so on.

[0124] In some embodiments of this disclosure, the field synchronization signal Vsync comes from an external circuit. The driving method further includes: setting a blanking time between the same image lines of two adjacent image frames, wherein the blanking time is the same for different image lines of the same image frame; determining, by means of a first counter CNT1 and a third counter CNT3, whether predetermined times for providing sub-display data lines of two adjacent image frames to a data line overlap, and, if the predetermined times for providing sub-display data lines to a data line overlap, determining the priority of providing the two sub-display data lines to the data line; and providing the data line with the higher priority sub-display data line of the two sub-display data lines at predetermined times, and providing the data line with the lower priority sub-display data line of the two sub-display data lines to the data line after one or more clock cycles of the predetermined time.

[0125] In some embodiments of this disclosure, the priority of two sub-display data lines provided to the data line is set according to one of the following criteria: the sub-display data line belonging to an even-numbered frame has a higher priority than the sub-display data line belonging to an odd-numbered frame; the sub-display data line belonging to an odd-numbered frame has a higher priority than the sub-display data line belonging to an even-numbered frame; the sub-display data line with a higher weight has a higher priority than the sub-display data line with a lower weight; and the sub-display data line with a lower weight has a higher priority than the sub-display data line with a higher weight.

[0126] In some embodiments of this disclosure, for each row of pixel units, scanning the row selection line corresponding to that row of pixel units when the sub-display data row corresponding to that row of pixel units is provided to the corresponding data line to provide the sub-display data row to that row of pixel units includes: within a frame period, when the predetermined time for the sub-display data row of the current image frame to be provided to the data line does not overlap with the predetermined time for the sub-display data row of other image frames to be provided to the data line, for each sub-display data row with different weights in the first image row, scanning N row selection lines sequentially at a first preset time interval starting from when the sub-display data row is provided to the corresponding data line; and within a frame period, when the predetermined time for the i-th sub-display data row of the j-th image row of the current image frame to be provided to the data line overlaps with the predetermined time for the sub-display data row of other image frames to be provided to the data line, scanning the j-th row selection line when the i-th sub-display data row is provided to the corresponding data line; wherein, the display data has K gray levels, K is a natural number greater than 1, i is a natural number greater than or equal to 1 and less than or equal to K, and j is a natural number greater than or equal to 1 and less than or equal to N.

[0127] In some embodiments of this disclosure, the driving method further includes: setting a reservation time period before each sub-display data line of each image row of each image frame is provided to the data line; in response to an update of display parameters for an image frame within a specified time period, storing the updated display parameters, and updating the display parameters of the bit plane corresponding to the sub-display data line with the stored display parameters within a reservation time period corresponding to each sub-display data line of the first image row of the image frame; and in response to an update of display parameters for an image frame within a non-specified time period, storing the updated display parameters, and updating the display parameters of the bit plane corresponding to the sub-display data line with the stored display parameters within a reservation time period corresponding to each sub-display data line of the first image row of the next image frame. The specified time period is the time period before the first sub-display data line of the first image row of an image frame is provided to the data line within each frame period. Display parameters for odd-numbered frames and display parameters for even-numbered frames are stored separately.

[0128] In some embodiments of the present disclosure, within the display time of an image frame, for each sub-display data row with different weights, starting from the time when the sub-display data row is provided to the corresponding data line, N row selection lines are sequentially scanned at intervals of a first preset time.

[0129] In some embodiments of the present disclosure, for each row of pixel units, the sub-display data rows corresponding to the pixel units of that row are sequentially provided to the corresponding data lines in the same bit order. The bit order includes: ascending order by bit, descending order by bit, or disordered order by bit.

[0130] In some embodiments of the present disclosure, starting from the time when the last bit of the display data in the first image row of each image frame reaches the product of the weight of the bit multiplied by the unit display time plus the sum of k clock cycles, N row selection lines are sequentially scanned at intervals of a first preset time, so that blanking data can be provided to the pixel units of the corresponding row.

[0131] Hereinafter, an example will be given where the display data has K-bit gray scale and each image frame has N image rows. N and K are natural numbers greater than 1.

[0132] In some embodiments of the present disclosure, the driving method further includes: when 2 K <N, after a first preset time fst from the time when the first sub-display data row in the last image row of the current image frame is provided to the corresponding pixel unit, the first sub-display data row in the first image row of the next image frame is provided to the corresponding pixel unit.

[0133] In some embodiments of the present disclosure, the driving method further includes: when 2 K <N, the binary value of each display data is shifted left by S bits so that 2 (K+S) ≥N. Where S is a natural number greater than 1.

[0134] In some embodiments of the present disclosure, the driving method further includes: when 2 K <N, for each row of pixel units, the time difference between two adjacent sub-display data rows in the same image row being provided to the corresponding data lines is magnified by P times. Where P≥N / 2 K .

[0135] In some embodiments of the present disclosure, the driving method further includes: when 2 KWhen N is greater than or equal to N, after the blanking time has elapsed from the time when the last sub-display data line in the first image line of the current image frame is displayed (the product of the weight of the last sub-display data line multiplied by the unit display time and k clock cycles), the first sub-display data line in the first image line of the next image frame is provided to the corresponding pixel unit.

[0136] In summary, the timing control and row / column driving circuits according to embodiments of this disclosure simultaneously achieve high grayscale, low operating clock frequency, and high refresh rate by using a multi-row parallel scanning method. In the multi-row parallel scanning mode, the timing control and row / column driving circuits according to embodiments of this disclosure, by setting counters for odd-numbered and even-numbered frame periods respectively, can better implement signal control logic during the overlapping time periods of odd-numbered and even-numbered frame periods, improving computational efficiency in practice. The timing control and row / column driving circuits according to embodiments of this disclosure also solve the conflict problem that may be caused by the field synchronization signal and the local clock signal being from different sources in certain operating modes, ensuring the normal display of image frames. When the display parameters of an image frame are updated, the timing control and row / column driving circuits according to embodiments of this disclosure can alleviate image flickering by latching the updated display parameters and updating them according to the bit plane.

[0137] The timing control and row / column driving circuits according to embodiments of the present disclosure simplify the operating logic by providing a dedicated row scanning circuit and a dedicated sub-buffer circuit for each bit of the display data, thereby simplifying the structure of the timing control and row / column driving circuits. The timing control and row / column driving circuits according to embodiments of the present disclosure only need to buffer at least half a frame of image, thus reducing the buffer area and consequently the area of ​​the timing control and row / column driving circuits. The frame buffer circuit in the timing control and row / column driving circuits according to embodiments of the present disclosure supports parallel reading and addressing operations, thus enabling faster reading speeds to match the parallel scanning method. The timing control and row / column driving circuits according to embodiments of the present disclosure can also maintain overall display brightness by extending the grayscale or prolonging the display time of each sub-display data row. Similarly, the display device and driving method according to embodiments of the present disclosure also have the above advantages.

[0138] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatuses and methods according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0139] Unless otherwise expressly indicated by the context, the singular form of words used herein and in the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the terms “comprising” and “including” shall be interpreted as including rather than exclusively. Likewise, the terms “including” and “or” shall be interpreted as including unless such interpretation is expressly prohibited herein. Where the term “example” is used herein, particularly when it follows a set of terms, the “example” is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0140] Further aspects and scope of adaptation become apparent from the description provided herein. It should be understood that various aspects of this application may be implemented individually or in combination with one or more other aspects. It should also be understood that the descriptions and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of this application.

[0141] Several embodiments of this disclosure have been described in detail above. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of this disclosure without departing from the spirit and scope of this disclosure. The scope of protection of this disclosure is defined by the appended claims.

Claims

1. A timing control and row / column driving circuit, the timing control and row / column driving circuit being used to drive an active matrix, the active matrix comprising pixel units defined by the intersection of N row selection lines and M data lines, the row selection lines extending along the row direction and the data lines extending along the column direction, the timing control and row / column driving circuit comprising: Odd / even frame determination circuit, odd frame counting circuit, even frame counting circuit, column data control circuit, row selection circuit. The odd / even frame determination circuit is configured to generate an odd frame indication signal and an even frame indication signal based on the field synchronization signal, wherein the odd frame indication signal is at an active level during the odd frame period and the even frame indication signal is at an active level during the even frame period. The odd-frame counting circuit is configured to: during the period when the odd-frame indication signal is at the active level, use a first counter to count the number of clock cycles per unit display time and use a second counter to count the number of unit display times within a single odd-frame; The even-numbered frame counting circuit is configured to: during the period when the even-numbered frame indication signal is at the active level, use a third counter to count the number of clock cycles per unit display time and use a fourth counter to count the number of unit display times within a single even-numbered frame; The column data control circuit is configured to: in the odd-numbered frames, for each row of pixel units, provide the display data corresponding to that row of pixel units bit by bit to the corresponding data line by means of the first counter and the second counter; in the even-numbered frames, for each row of pixel units, provide the display data corresponding to that row of pixel units bit by bit to the corresponding data line by means of the third counter and the fourth counter, wherein the time difference between two adjacent bits of the display data being provided to the corresponding data line is equal to the sum of the weight of the first bit of the two bits multiplied by the unit display time and k clock cycles, and the time difference between the same bits of the display data corresponding to two adjacent rows of pixel units being provided to the corresponding data line is equal to a first preset time, the first preset time being less than or equal to the unit display time and greater than or equal to one clock cycle; The row selection circuit is configured to scan the row selection line corresponding to each row of pixel units when the display data corresponding to that row of pixel units is provided to the corresponding data line so that the display data is provided to the corresponding pixel unit. Where N and M are natural numbers greater than 1, and k is an integer greater than or equal to 0.

2. The timing control and row / column driving circuit according to claim 1, wherein, The odd-numbered frame periods partially overlap with the even-numbered frame periods.

3. The timing control and row / column drive circuit according to claim 1, wherein, The field synchronization signal comes from an external circuit. There is a blanking time between the same image lines of two adjacent image frames, and the blanking time is the same for different image lines of the same image frame. The timing control and row / column drive circuit further includes a collision detection circuit, which is configured to: determine, by means of the first counter and the third counter, whether the predetermined times for the provision of display data bits of two adjacent image frames to the data line overlap, and, if the predetermined times for the provision of two bits to the data line overlap, determine the priority of the provision of the two bits to the data line. The column data control circuit is further configured to: provide the data line with the higher priority bit of the two bits at the predetermined time, and provide the data line with the lower priority bit of the two bits after one or more clock cycles of the predetermined time.

4. The timing control and row / column drive circuit according to claim 3, wherein, The priority of the two bits provided to the data line is set according to one of the following criteria: Bits belonging to even-numbered frames have a higher priority than bits belonging to odd-numbered frames. Bits belonging to odd-numbered frames have a higher priority than bits belonging to even-numbered frames. Bits with higher weights have higher priority than bits with lower weights. Bits with lower weights have higher priority than bits with higher weights.

5. The timing control and row / column drive circuit according to any one of claims 1 to 4, wherein, A retention period is set before each bit of the display data for each image row in each image frame is provided to the data line; The timing control and row / column driving circuit further includes a parameter latch circuit, which is configured to: in response to an update of the display parameters for an image frame within a specified time period, store the updated display parameters, and update the display parameters of the bit plane corresponding to that bit with the stored display parameters within a retention time period corresponding to each bit of the display data of the first image row of the image frame; and in response to an update of the display parameters for an image frame within a non-specified time period, store the updated display parameters, and update the display parameters of the bit plane corresponding to that bit with the stored display parameters within a retention time period corresponding to each bit of the display data of the first image row of the next image frame; wherein the specified time period is the time period before the first bit of the display data of the first image row of the image frame is provided to the data line in each frame period, and the parameter latch circuit includes an odd-frame parameter latch sub-circuit and an even-frame parameter latch sub-circuit, wherein the display parameters for odd-numbered frames are stored in the odd-frame parameter latch sub-circuit and the display parameters for even-numbered frames are stored in the even-frame parameter latch sub-circuit.

6. The timing control and row / column drive circuit according to any one of claims 1 to 4, wherein, The displayed data has K gray levels, the column data control circuit includes K sub-buffer circuits, and the row selection circuit includes K row scanning circuits, where K is a natural number greater than 1. The i-th sub-cached circuit in the K sub-cached circuits is configured to store the i-th bit of the display data to be provided to the M data lines; The i-th row scanning circuit in the K row scanning circuits is configured to: scan the N row selection lines sequentially at the first preset time interval within the display time of an image frame, so that the i-th bit of the display data stored in the i-th sub-buffer circuit can be provided to the pixel unit of the corresponding row. Where i is a natural number greater than or equal to 1 and less than or equal to K.

7. The timing control and row / column driving circuit according to claim 6, wherein the row selection circuit further includes a blanking scan circuit, the blanking scan circuit being configured to: starting from the time when the last bit of the display data in the first image row of each image frame is displayed reaches the sum of the product of the weight of that bit and the unit display time and k clock cycles, sequentially scan the N row selection lines at a first preset time interval, so that blanking data can be provided to the pixel units of the corresponding row.

8. The timing control and row / column drive circuit according to any one of claims 1 to 4, further comprising: Frame buffer circuit, The frame buffer circuit is configured to store display data of at least half a frame of image and provide display data to be displayed to the column data control circuit. The display data of each image row in the at least half frame of image is divided into multiple sub-display data rows by bit, and each sub-display data row corresponds to the same bit of the display data of the same image row. The display data has K gray levels, and the frame buffer circuit includes K frame buffer sub-circuits. The i-th frame buffer sub-circuit is used to store the i-th sub-display data line in each image line, where K is a natural number greater than 1, and i is a natural number greater than or equal to 1 and less than or equal to K.

9. The timing control and row / column drive circuit according to any one of claims 1 to 4, wherein, The display data has K bits of gray scale, where K is a natural number greater than 1. When 2 K <N, the binary value of each display data is shifted left by S bits so that 2 (K+S) ≥N, where S is a natural number greater than 1.

10. The timing control and row / column drive circuit according to any one of claims 1 to 4, wherein, The display data has K bits of gray scale, where K is a natural number greater than 1. When it is in 2 K <N, for each row of pixel units, the time difference between two adjacent bits in the display data corresponding to the pixel units in that row provided to the corresponding data line is amplified by P times, where P ≥ N / 2 K .

11. A display device comprising timing control and row / column driving circuits according to any one of claims 1 to 10.

12. A driving method for driving an active matrix, the active matrix comprising pixel units defined by the intersection of N row selection lines and M data lines, the row selection lines extending along a row direction and the data lines extending along a column direction, wherein... N and M are natural numbers greater than 1, and the driving method includes: An odd-numbered frame indication signal and an even-numbered frame indication signal are generated based on the field synchronization signal, wherein the odd-numbered frame indication signal is at an active level during the odd-numbered frame period and the even-numbered frame indication signal is at an active level during the even-numbered frame period. During the period when the odd-numbered frame indication signal is at the active level, a first counter is used to count the number of clock cycles per unit display time and a second counter is used to count the number of unit display times within a single odd-numbered frame; During the period when the even-numbered frame indicator signal is at the active level, a third counter is used to count the number of clock cycles per unit display time and a fourth counter is used to count the number of unit display times within a single even-numbered frame; The display data of each image row of the image frame is divided into multiple sub-display data rows by bit, and each sub-display data row corresponds to the same bit of the display data of the same image row; In the odd-numbered frames, for each row of pixel units, multiple sub-display data rows corresponding to that row of pixel units are sequentially provided to the corresponding data lines using the first counter and the second counter. In the even-numbered frames, for each row of pixel units, multiple sub-display data rows corresponding to that row of pixel units are sequentially provided to the corresponding data lines using the third counter and the fourth counter. The time difference between providing two adjacent sub-display data rows to the corresponding data lines in the same image row is equal to the sum of the weight of the former of the two sub-display data rows multiplied by the unit display time and k clock cycles. Furthermore, the time difference between providing sub-display data rows with the same weight corresponding to two adjacent rows of pixel units to the corresponding data lines is equal to a first preset time. The first preset time is less than or equal to the unit display time and greater than or equal to one clock cycle, where k is an integer greater than or equal to 0. For each row of pixel units, when the sub-display data row corresponding to that row of pixel units is provided to the corresponding data line, the row selection line corresponding to that row of pixel units is scanned so that the sub-display data row is provided to that row of pixel units.

13. The driving method according to claim 12, wherein, The odd-numbered frame periods partially overlap with the even-numbered frame periods.

14. The driving method according to claim 12, wherein, The field synchronization signal comes from an external circuit, and the driving method further includes: Set the blanking time between the same image rows of two adjacent image frames, wherein the blanking time is the same for different image rows of the same image frame; The system uses the first counter and the third counter to determine whether the predetermined times for providing sub-display data lines of two adjacent image frames to the data line overlap, and, if the predetermined times for providing two sub-display data lines to the data line overlap, determines the priority of providing the two sub-display data lines to the data line; and The higher-priority sub-display data line of the two sub-display data lines is provided to the data line at the predetermined time, and the lower-priority sub-display data line of the two sub-display data lines is provided to the data line after one or more clock cycles of the predetermined time.

15. The driving method according to claim 14, wherein, The priority of the two sub-display data rows provided to the data line is set according to one of the following criteria: The sub-display data rows belonging to the even-numbered frames have a higher priority than the sub-display data rows belonging to the odd-numbered frames; The priority of the sub-display data line belonging to the odd-numbered frame is higher than the priority of the sub-display data line belonging to the even-numbered frame; The higher-weight sub-row of data has a higher priority than the lower-weight sub-row of data. The child data rows with lower weights have higher priority than the child data rows with higher weights.

16. The driving method according to claim 14, wherein, For each row of pixel units, scanning the row selection line corresponding to that row of pixel units so that the sub-display data line is provided to the corresponding data line includes: Within a frame period, if the predetermined time when the sub-display data line of the current image frame is provided to the data line does not overlap with the predetermined time when the sub-display data lines of other image frames are provided to the data line, for each sub-display data line with different weights in the first image line, the N line selection lines are scanned sequentially at the first preset time interval, starting from when the sub-display data line is provided to the corresponding data line; and Within a frame period, if the predetermined time when the i-th sub-display data line of the j-th image row of the current image frame is provided to the data line overlaps with the predetermined time when the sub-display data lines of other image frames are provided to the data line, the j-th row selection line is scanned when the i-th sub-display data line is provided to the corresponding data line. The displayed data has K gray levels, where K is a natural number greater than 1, i is a natural number greater than or equal to 1 and less than or equal to K, and j is a natural number greater than or equal to 1 and less than or equal to N.

17. The driving method according to any one of claims 12 to 16, further comprising: A retention period is set before each sub-display data line of each image row in each image frame is provided to the data line; In response to the update of the display parameters for an image frame within a specified time period, the updated display parameters are stored, and the stored display parameters are used to update the display parameters of the bit plane corresponding to each sub-display data line of the first image line of the image frame within a retention time period. as well as In response to an update of the display parameters for an image frame during an unspecified time period, the updated display parameters are stored, and the stored display parameters are used to update the display parameters of the bit plane corresponding to each sub-display data line during a reserved time period corresponding to the first image line of the next image frame. The specified time period is the period before the first sub-display data line of the first image line of the image frame is provided to the data line within each frame period, and the display parameters of odd-numbered frames and even-numbered frames are stored separately.

18. The driving method according to any one of claims 12 to 16, further comprising: Starting from the time when the last sub-display data line in the first image line of each image frame is displayed reaches the sum of the product of the weight of the sub-display data line and the unit display time and k clock cycles, the N line selection lines are scanned sequentially at the first preset time interval so that blanking data can be provided to the pixel units of the corresponding line.

19. The driving method according to any one of claims 12 to 16, wherein, The display data has K bits of gray scale, where K is a natural number greater than 1, and the driving method further includes: when 2 K <N, shifting the binary value of each display data to the left by S bits so that 2 (K+S) ≥N, where S is a natural number greater than 1.

20. The driving method according to any one of claims 12 to 16, wherein, The display data has K-bit gray scale, where K is a natural number greater than 1, and the driving method further includes: when 2 K <is less than N, for each row of pixel units, the time difference between two sub-display data rows in adjacent bits in the same image row provided to the corresponding data line is amplified by P times, where P ≥ N / 2 K .

Images