Memory multi-value programming method, memory, and electronic device

Abstract

The present disclosure relates to a memory multi-value programming method, a memory, and an electronic device. The memory multi-value programming method includes: reading the storage value of a storage unit; judging whether the storage value of the storage unit is within a reference range, if not, applying a first adjustment signal to the storage unit to adjust the storage value of the storage unit to the reference range; judging whether the storage value of the storage unit is within a target range, if not, applying a second adjustment signal to the storage unit to adjust the storage value of the storage unit to the target range; wherein the minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range. The single adjustment amplitude of the second adjustment signal is smaller than the single adjustment amplitude of the first adjustment signal. The present disclosure is used to improve the efficiency of multi-value programming.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a memory multi-value programming method, a memory, and an electronic device. Background Art

[0002] With the development of communication technology and digital technology, in order to efficiently store, access and calculate massive amounts of data, new types of memory such as resistive random access memory (RRAM), phase change memory (PRAM), magnetoresistive random access memory (MRAM) and ferroelectric random access memory (FeRAM) have received widespread attention and research.

[0003] However, the multi-value programming methods currently used by various memories are mostly incremental step programming pulse (ISPP) methods, which have the problems of a large number of programming pulses and low programming efficiency, and are difficult to keep up with the rapid growth of data storage capacity. Summary of the invention

[0004] Based on this, the embodiments of the present disclosure provide a memory multi-value programming method, a memory, and an electronic device, which are used to improve the efficiency of multi-value programming.

[0005] In order to achieve the above objectives, in a first aspect, some embodiments of the present disclosure provide a memory multi-value programming method. The memory includes a plurality of memory cells arranged in an array, and the memory multi-value programming method includes the following steps.

[0006] Read the stored value of a memory cell.

[0007] It is determined whether the storage value of the storage unit is within a reference range; if not, a first adjustment signal is applied to the storage unit to adjust the storage value of the storage unit to the reference range.

[0008] It is determined whether the storage value of the storage unit is within the target range; if not, a second adjustment signal is applied to the storage unit to adjust the storage value of the storage unit to the target range.

[0009] In the above embodiment, the minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range. The single adjustment amplitude of the second adjustment signal is smaller than the single adjustment amplitude of the first adjustment signal.

[0010] In some embodiments of the present disclosure, the method for determining whether the stored value is located before the reference range further comprises: presetting the target range and the reference range; and presetting the control parameters of the first adjustment signal. The storage unit is connected to the bit line, the word line, and the source line correspondingly. The control parameters of the first adjustment signal include: the bit line coarse adjustment voltage, the word line coarse adjustment voltage, and the maximum number of coarse adjustment times.

[0011] In some embodiments of the present disclosure, the first adjustment signal includes a set pulse control signal having a fixed pulse width and a fixed amplitude.

[0012] In some embodiments of the present disclosure, the memory multi-value programming method further includes the following steps.

[0013] The number of times the storage value of the storage unit is adjusted according to the first adjustment signal is obtained.

[0014] If the adjustment times reach the maximum coarse adjustment times and the storage value of the storage unit cannot be adjusted to the reference range, the steps of switching the storage unit and reading the storage value of the switched storage unit are performed.

[0015] If the adjustment times do not reach the maximum coarse adjustment times and the storage value of the storage unit has been adjusted to the reference range, a step of determining whether the storage value of the storage unit is within the target range is performed.

[0016] In some embodiments of the present disclosure, the method for determining whether the storage value of the storage unit is located before the target range, and the memory multi-value programming method further includes: presetting the control parameters of the second adjustment signal. The storage unit is connected to the bit line, the word line, and the source line correspondingly. The control parameters of the second adjustment signal include: the bit line start adjustment voltage, the bit line end adjustment voltage, the bit line voltage increment step, the word line start adjustment voltage, the word line end adjustment voltage, the word line voltage increment step, the source line start adjustment voltage, the source line end adjustment voltage, the source line voltage increment step, and the maximum number of fine adjustments.

[0017] In some embodiments of the present disclosure, the second adjustment signal includes a set pulse control signal and a reset pulse control signal with adjustable pulse width and amplitude; wherein the set pulse control signal is used for the first adjustment mode, and the reset pulse control signal is used for the second adjustment mode. The start condition of the first adjustment mode includes that the storage value of the storage unit is less than or equal to the first preset value, and the start condition of the second adjustment mode includes that the storage value of the storage unit is greater than the first preset value; the end conditions of the first adjustment mode and the second adjustment mode include: the storage value of the storage unit is within the target range, and / or the number of adjustment times of adjusting the storage value of the storage unit according to the second adjustment signal reaches the maximum number of fine adjustments. wherein the first preset value is between the minimum value of the target range and the minimum value of the reference range.

[0018] In some embodiments of the present disclosure, the memory multi-value programming method further includes the following steps.

[0019] In the first adjustment mode, when the storage value of the storage unit is outside the target range, it is determined whether the storage value of the storage unit is less than the minimum value of the target range; if so, the set pulse control signal is updated, and the storage value of the storage unit is adjusted again according to the updated set pulse control signal.

[0020] Correspondingly, the updating of the set pulse control signal and re-adjusting the storage value of the storage unit according to the updated set pulse control signal includes the following steps.

[0021] It is determined whether a voltage of a bit line connected to a memory cell is less than or equal to a maximum preset voltage of the bit line.

[0022] If so, the bit line voltage increment step is determined according to the adjustment amount of the storage value of the storage cell by the previous set pulse control signal, so as to adjust the storage value of the storage cell again according to the bit line voltage increment step.

[0023] If not, the bit line voltage is set as the bit line starting adjustment voltage, and the word line voltage increment step is determined according to the adjustment amount of the storage value of the storage cell by the previous set pulse control signal, so as to adjust the storage value of the storage cell again according to the word line voltage increment step.

[0024] In some embodiments of the present disclosure, the memory multi-value programming method further includes the following steps.

[0025] In the second adjustment mode, when the storage value of the storage unit is outside the target range, it is determined whether the storage value of the storage unit is greater than the maximum value of the target range; if so, the reset pulse control signal is updated and the storage value of the storage unit is adjusted again according to the updated reset pulse control signal.

[0026] Correspondingly, the updating of the reset pulse control signal and re-adjusting the storage value of the storage unit according to the updated reset pulse control signal includes the following steps.

[0027] It is determined whether the voltage of the source line connected to the memory cell is less than or equal to the maximum preset voltage of the source line.

[0028] If yes, the source line voltage increment step is determined according to the adjustment amount of the storage value of the storage unit by the previous reset pulse control signal, so as to adjust the storage value of the storage unit again according to the source line voltage increment step.

[0029] If not, the source line voltage is set as the source line starting adjustment voltage, and the word line voltage increment step is determined according to the adjustment amount of the storage value of the storage unit by the previous reset pulse control signal, so as to adjust the storage value of the storage unit again according to the word line voltage increment step.

[0030] In a second aspect, some embodiments of the present disclosure further provide a memory, comprising: a memory cell and a bit line, a word line and a source line connected to the memory cell accordingly. The memory further comprises a reading circuit and a control circuit respectively connected to the bit line, the word line and the source line; wherein the control circuit is also connected to the reading circuit. The reading circuit is configured to: read the storage value of the memory cell. The control circuit is configured to: determine whether the storage value of the memory cell is within a reference range, and when the storage value of the memory cell is outside the reference range, apply a first adjustment signal to the memory cell to adjust the storage value of the memory cell to the reference range; and, when the storage value of the memory cell is within the reference range, determine whether the storage value of the memory cell is within a target range, and when the storage value of the memory cell is outside the target range, apply a second adjustment signal to the memory cell to adjust the storage value of the memory cell to the target range.

[0031] Furthermore, the minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range. The single adjustment amplitude of the second adjustment signal is smaller than the single adjustment amplitude of the first adjustment signal.

[0032] In a third aspect, some embodiments of the present disclosure further provide an electronic device, comprising: a memory as described in some of the above embodiments.

[0033] The embodiments of the present disclosure may or at least have the following advantages:

[0034] In the embodiment of the present disclosure, by reading the storage value of the storage unit in real time, when it is judged that the storage value of the storage unit is outside the reference range, a first adjustment signal can be applied to the storage unit to adjust the storage value of the storage unit to the reference range, and when the storage value of the storage unit is within the reference range and it is judged that the storage value of the storage unit is outside the target range, a second adjustment signal can be applied to the storage unit to adjust the storage value of the storage unit to the target range. In other words, the embodiment of the present disclosure can make a single large-amplitude rough adjustment to the storage value of the storage unit in response to the first adjustment signal, and can make a single small-amplitude fine adjustment in response to the second adjustment after the storage value of the storage unit is within the reference range, so as to dynamically adjust the storage value of the storage unit to within the target range. Therefore, the memory multi-value programming method provided by the embodiment of the present disclosure can dynamically control the single adjustment amplitude of the storage value of the storage unit in real time, so as to significantly shorten the multi-value programming time of the memory, thereby effectively improving the multi-value programming efficiency.

[0035] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic flow chart of a memory multi-value programming method provided in some embodiments;

[0038] Figure 2 A schematic flow chart of another memory multi-value programming method provided in some embodiments;

[0039] Figure 3 A schematic diagram of executing a first adjustment mode and a second adjustment mode provided in some embodiments;

[0040] Figure 4 A flow chart of a method for updating a set pulse control signal and re-adjusting a storage value of a storage unit according to the updated set pulse control signal provided in some embodiments;

[0041] Figure 5 A flow chart of a method for updating a reset pulse control signal and re-adjusting a storage value of a storage unit according to the updated reset pulse control signal provided in some embodiments;

[0042] Figure 6 A schematic diagram of the structure of a memory provided in some embodiments;

[0043] Figure 7 An operation diagram of a memory multi-value programming method provided in some embodiments;

[0044] Figure 8 A programming efficiency comparison diagram of the memory multi-value programming method and the ISPP method provided in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0046] While some exemplary embodiments of the present invention have been described for the purpose of illustration, it should be understood that the present invention may be implemented in other ways not specifically shown in the drawings.

[0047] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0049] It should be understood that when an element or layer is referred to as being "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0050] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0051] As one of the research directions that has attracted much attention in non-volatile memory, multi-value storage has a significant effect on improving storage density. Taking resistive random access memory as an example, one method of implementing multi-value storage is to introduce an intermediate resistance state between the high resistance state and the low resistance state, so that each storage unit of the resistive random access memory can store more than two states; among them, the basic storage principle of resistive random access memory is that the resistance reflected by the storage unit can be reversibly converted between the high resistance state ("0" state) and the low resistance state ("1" state) under the stimulation of an external voltage or current, thereby realizing data storage.

[0052] However, the multi-value programming methods currently used by various memories are mostly incremental step pulse programming methods, which have the problems of a large number of programming pulses and low programming efficiency, and are difficult to keep up with the rapid growth of data storage capacity.

[0053] Based on this, the embodiments of the present disclosure provide a memory multi-value programming method, a memory, and an electronic device, which are used to improve the efficiency of multi-value programming.

[0054] See also Figure 1 The embodiment of the present disclosure provides a memory multi-value programming method. The memory includes a plurality of memory cells arranged in an array, and the memory multi-value programming method includes the following steps S100 to S300.

[0055] S100, reading the storage value of the storage unit.

[0056] S200, determining whether the storage value of the storage unit is within a reference range.

[0057] If not, a first adjustment signal is applied to the storage unit to adjust the storage value of the storage unit to a reference range.

[0058] Correspondingly, if yes, execute step S300.

[0059] S300, determining whether the storage value of the storage unit is within a target range.

[0060] If not, a second adjustment signal is applied to the storage unit to adjust the storage value of the storage unit to a target range.

[0061] Correspondingly, if yes, the storage value adjustment of the storage unit is terminated.

[0062] In the above embodiment, the minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range. The single adjustment amplitude of the second adjustment signal is smaller than the single adjustment amplitude of the first adjustment signal.

[0063] In the embodiment of the present disclosure, by reading the storage value of the storage unit in real time, when it is judged that the storage value of the storage unit is outside the reference range, a first adjustment signal can be applied to the storage unit to adjust the storage value of the storage unit to the reference range, and when the storage value of the storage unit is within the reference range and it is judged that the storage value of the storage unit is outside the target range, a second adjustment signal can be applied to the storage unit to adjust the storage value of the storage unit to the target range. In other words, the embodiment of the present disclosure can make a single large-amplitude rough adjustment to the storage value of the storage unit in response to the first adjustment signal, and can make a single small-amplitude fine adjustment in response to the second adjustment after the storage value of the storage unit is within the reference range, so as to dynamically adjust the storage value of the storage unit to within the target range. Therefore, the memory multi-value programming method provided by the embodiment of the present disclosure can dynamically control the single adjustment amplitude of the storage value of the storage unit in real time, so as to significantly shorten the multi-value programming time of the memory, thereby effectively improving the multi-value programming efficiency.

[0064] In some embodiments of the present disclosure, before executing step S100, the memory multi-value programming method further includes: initializing each storage unit of the memory.

[0065] In some embodiments of the present disclosure, step S200 determines whether the storage value is located before the reference range, and the memory multi-value programming method further includes: presetting the target range and the reference range; and presetting the control parameters of the first adjustment signal. The storage unit is connected to the bit line, the word line, and the source line correspondingly. The control parameters of the first adjustment signal include: the bit line coarse adjustment voltage, the word line coarse adjustment voltage, and the maximum number of coarse adjustment times.

[0066] Illustratively, the first adjustment signal includes a set pulse control signal (SET) having a fixed pulse width and a fixed amplitude.

[0067] For example, reading the storage value of the storage cell in step S100 includes, but is not limited to, reading the output current of the source line connected to the storage cell.

[0068] See also Figure 2 In some embodiments of the present disclosure, the memory multi-value programming method also includes the following steps S400~S600.

[0069] S400, obtaining the number of times of adjusting the storage value of the storage unit according to the first adjustment signal.

[0070] S500, determining whether the number of times of adjusting the storage value of the storage unit according to the first adjustment signal reaches a maximum number of coarse adjustment times.

[0071] Accordingly, if the adjustment times reach the maximum coarse adjustment times and the storage value of the storage unit cannot be adjusted to the reference range, step S600 is executed to switch the storage unit and read the storage value of the switched storage unit.

[0072] If the adjustment times do not reach the maximum coarse adjustment times and the storage value of the storage unit has been adjusted to the reference range, step S300 is executed to determine whether the storage value of the storage unit is within the target range.

[0073] In some embodiments of the present disclosure, step S300 determines whether the storage value of the storage unit is located before the target range, and the memory multi-value programming method further includes: presetting the control parameters of the second adjustment signal. The storage unit is connected to the bit line, the word line, and the source line accordingly. The control parameters of the second adjustment signal include: the bit line start adjustment voltage, the bit line end adjustment voltage, the bit line voltage increment step, the word line start adjustment voltage, the word line end adjustment voltage, the word line voltage increment step, the source line start adjustment voltage, the source line end adjustment voltage, the source line voltage increment step, and the maximum number of fine adjustments.

[0074] For example, the second adjustment signal includes a set pulse control signal (SET) and a reset pulse control signal (RESET) with adjustable pulse width and amplitude; wherein the set pulse control signal (SET) is used for the first adjustment mode, and the reset pulse control signal (RESET) is used for the second adjustment mode. The start condition of the first adjustment mode includes that the storage value of the storage unit is less than or equal to the first preset value, and the start condition of the second adjustment mode includes that the storage value of the storage unit is greater than the first preset value; the end conditions of the first adjustment mode and the second adjustment mode include: the storage value of the storage unit is within the target range, and / or, the number of adjustment times of adjusting the storage value of the storage unit according to the second adjustment signal reaches the maximum number of fine adjustment times. wherein the first preset value is between the minimum value of the target range and the minimum value of the reference range, that is, an open interval formed by the minimum value of the target range and the minimum value of the reference range.

[0075] See also Figure 3 In some embodiments of the present disclosure, the memory multi-value programming method further includes: in the first adjustment mode, when the storage value of the storage unit is outside the target range, executing steps S10 and S20.

[0076] S10, determining whether the storage value of the storage unit is less than the minimum value of the target range.

[0077] S20: If yes, then update the set pulse control signal, and readjust the storage value of the storage unit according to the updated set pulse control signal.

[0078] For some examples, see Figure 3 If it is determined that the storage value of the storage unit is greater than or equal to the minimum value of the target range, the second adjustment mode can be executed accordingly, that is, a reset pulse control signal is applied to the storage unit.

[0079] For example, see Figure 4 Step S20 updates the set pulse control signal and readjusts the storage value of the storage unit according to the updated set pulse control signal, which may include the following steps S21 to S23.

[0080] S21, determining whether the voltage of the bit line connected to the memory cell is less than or equal to a maximum preset voltage of the bit line.

[0081] S22, if yes, determine the bit line voltage increment step length according to the adjustment amount of the storage value of the storage cell by the previous set pulse control signal, so as to adjust the storage value of the storage cell again according to the bit line voltage increment step length.

[0082] For example, the adjustment amount of the storage value of the memory cell may be represented by the relative change amount of the read current.

[0083] For example, different adjustment amounts of the storage value of the memory cell may correspond to different bit line voltage increment steps, respectively.

[0084] S23, if not, then set the voltage of the bit line as the starting adjustment voltage of the bit line, and determine the word line voltage increment step according to the adjustment amount of the storage value of the storage cell by the previous set pulse control signal, so as to adjust the storage value of the storage cell again according to the word line voltage increment step.

[0085] Please continue reading Figure 3 In some embodiments of the present disclosure, the memory multi-value programming method further includes: in the second adjustment mode, when the storage value of the storage unit is outside the target range, executing steps S30 and S40.

[0086] S30, determining whether the storage value of the storage unit is greater than the maximum value of the target range.

[0087] S40: If yes, then update the reset pulse control signal, and readjust the storage value of the storage unit according to the updated reset pulse control signal.

[0088] For some examples, see Figure 3If it is determined that the storage value of the storage unit is less than or equal to the maximum value of the target range, the first adjustment mode can be executed accordingly, that is, a set pulse control signal is applied to the storage unit.

[0089] For example, see Figure 5 Step S40 updates the reset pulse control signal and readjusts the storage value of the storage unit according to the updated reset pulse control signal, which may include the following steps S41-S43.

[0090] S41, determining whether the voltage of the source line connected to the memory cell is less than or equal to the maximum preset voltage of the source line.

[0091] S42, if yes, determine the source line voltage increment step size according to the adjustment amount of the storage value of the storage unit by the previous reset pulse control signal, so as to adjust the storage value of the storage unit again according to the source line voltage increment step size.

[0092] For example, the adjustment amount of the storage value of the memory cell may be represented by the relative change amount of the read current.

[0093] For example, different adjustment amounts of the storage value of the storage unit may correspond to different source line voltage increment steps, respectively.

[0094] S43, if not, then set the voltage of the source line as the source line starting adjustment voltage, and determine the word line voltage increment step according to the adjustment amount of the storage value of the storage cell by the previous reset pulse control signal, so as to adjust the storage value of the storage cell again according to the word line voltage increment step.

[0095] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0096] Based on the same inventive concept, please refer to Figure 6 The present disclosure also provides a memory, including: a memory unit U and a bit line BL, a word line WL and a source line SL connected to the memory unit U. The memory also includes a reading circuit and a control circuit ( Figure 6); wherein the control circuit is also connected to the reading circuit. The reading circuit is configured to: read the storage value of the storage unit U. The control circuit is configured to: determine whether the storage value of the storage unit U is within a reference range, and when the storage value of the storage unit U is outside the reference range, apply a first adjustment signal to the storage unit U to adjust the storage value of the storage unit U to the reference range; and, when the storage value of the storage unit U is within the reference range, determine whether the storage value of the storage unit U is within a target range, and when the storage value of the storage unit U is outside the target range, apply a second adjustment signal to the storage unit U to adjust the storage value of the storage unit U to the target range.

[0097] Furthermore, the minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range. The single adjustment amplitude of the second adjustment signal is smaller than the single adjustment amplitude of the first adjustment signal.

[0098] By way of example, the memory includes, but is not limited to, a resistive memory, a phase change memory, a magnetoresistive memory, a ferroelectric memory, or the like that can be used to implement multi-value storage.

[0099] For example, the reading circuit and the control circuit can be respectively formed by electronic components that can realize their functions. The embodiments of the present disclosure do not specifically limit the component composition of the reading circuit and the control circuit.

[0100] For example, the storage value of the memory cell U is obtained by reading the current of the source line connected to the memory cell U through the reading circuit.

[0101] The implementation solution provided by the above-mentioned memory to solve the problem is similar to the implementation solution recorded in the above-mentioned method. Therefore, the specific limitations in one or more memory embodiments provided below can refer to the relevant limitations on the memory multi-value programming method above, and will not be repeated here.

[0102] It should be noted that the process of adjusting the storage value of the storage unit U by the control circuit after applying the first adjustment signal and the second adjustment signal to the storage unit U can be implemented by referring to the relevant records in the aforementioned embodiments, which will not be elaborated here.

[0103] In order to more clearly illustrate the memory and memory multi-value programming method provided in some of the above embodiments, the following takes the memory as a resistive memory and the storage unit as a single transistor single resistor (1T1R) as an example to exemplarily describe the specific execution of the memory multi-value programming method. However, it can be understood that the memory multi-value programming method provided in the embodiments of the present disclosure is not only applicable to resistive memory, but also can be applied to phase change memory, magnetoresistive memory, ferroelectric memory and other memories that can be used to implement multi-value storage.

[0104] See also Figure 6 The memory includes: a memory unit U and a bit line BL, a word line WL and a source line SL connected to the memory unit U. By way of example, the memory unit U includes a transistor T and a resistor R, wherein a control electrode of the transistor T is connected to the word line WL, a first electrode of the transistor T is connected to the source line SL, a second electrode of the transistor T is connected to a first end of the resistor R, and a second end of the resistor R is connected to the bit line BL.

[0105] For example, in step S100 , reading the storage value of the memory cell U may be performed by reading the output current I_read of the source line SL to which the memory cell U is connected.

[0106] For example, the first adjustment signal uses a set pulse control signal SET with a fixed pulse width and a fixed amplitude. In response to the set pulse control signal SET in the first adjustment signal, the source line SL is grounded GND, the bit line BL connected to the selected storage unit U is applied with a SET voltage, the word line WL connected to the selected storage unit U is applied with an open voltage and controls the transistor T to be turned on, the bit line BL connected to the unselected storage unit U is floated, and the word line WL connected to the unselected storage unit U is grounded GND. The storage value of the storage unit is obtained by reading the current size of the source line SL.

[0107] By way of example, the second adjustment signal includes a set pulse control signal SET and a reset pulse control signal RESET, both of which have adjustable pulse width and amplitude. In response to the set pulse control signal SET of the second adjustment signal, the source line SL is grounded to GND, the bit line BL connected to the selected storage unit U is applied with a SET voltage, the word line WL connected to the selected storage unit U is applied with a start voltage and controls the transistor T to be turned on, the bit line BL connected to the unselected storage unit U is floated, and the word line WL connected to the unselected storage unit U is grounded to GND; the storage value of the storage unit is obtained by reading the current of the source line SL. In response to the reset pulse control signal RESET of the second adjustment signal, the source line SL connected to the selected storage unit U is applied with a RESET voltage, the bit line BL connected to the selected storage unit U is grounded to GND, the word line WL connected to the selected storage unit U is applied with a start voltage and controls the transistor T to be turned on, the bit line BL connected to the unselected storage unit U is floated, and the word line WL connected to the unselected storage unit U is grounded to GND; the storage value of the storage unit is obtained by reading the current of the source line SL.

[0108] For example, before executing step S100 in the memory multi-value programming method provided by the embodiment of the present disclosure, the memory multi-value programming method further includes: initializing each memory cell of the memory. For example, an initial reset pulse control signal RESET can be applied to each memory cell of the memory to put each memory cell U in a high impedance state HRS.

[0109] Please combine the following Figure 7 understand.

[0110] Before executing step S200 to determine whether the storage value is within the reference range, the memory multi-value programming method further includes: presetting a target range and a reference range; and presetting a control parameter of the first adjustment signal.

[0111] Here, the target range is, for example, [I_min, I_max]. The reference range is, for example, [Ic_min, Ic_max]. The control parameters of the first adjustment signal SET include: the bit line coarse adjustment voltage V BL_coarse , word line coarse adjustment voltage V WL_coarse And the maximum number of coarse adjustments N coarse .

[0112] Illustratively, Ic_min ≤ I_min and Ic_max ≥ I_max.

[0113] During the execution of step S200, a series of first adjustment signals (ie, set pulse control signals SET) are applied to the selected storage unit U in the high-resistance state HRS. coarse (ie: MAX loop = N coarse ), the reading current I_read of the storage value of the storage unit U has not fallen into the reference range [Ic_min, Ic_max], then it is determined that the coarse adjustment has failed, and the next storage unit U can be switched to perform the step of reading the storage value of the switched storage unit U. If the maximum number of coarse adjustments N coarse (ie: MAX loop = N coarse ), if the storage value of the storage unit U has been adjusted to the reference range, step S300 is executed to perform a more precise resistance adjustment on the storage unit U whose storage value has entered the reference range.

[0114] Similarly, before executing step S300 to determine whether the storage value of the storage unit is within the target range, the memory multi-value programming method further includes: presetting a control parameter of the second adjustment signal.

[0115] Here, the control parameters of the second adjustment signal include: the bit line starting voltage V BL_start , bit line termination adjustment voltage V BL_end , bit line voltage increment step size V BL _ step , word line start adjustment voltage V WL_start , word line termination adjustment voltage V WL_end , word line voltage increment step V WL_step , Source line start adjustment voltage V SL_start , Source line termination adjustment voltage V SL_end, Source line voltage increment step V SL _ step and the maximum number of fine-tuning times N fine .

[0116] For example, the bit line voltage is incremented by a step size V BL _ step The value range of includes 0.05V~0.2V, for example, it can be 0.05V, 0.1V, 0.2V. The source line voltage increment step size V SL _ step The value range includes 0.05V~0.2V, for example, it can be 0.05V, 0.1V, and 0.2V.

[0117] Based on this, the memory multi-value programming method can apply the set pulse control signal SET or the reset pulse control signal RESET in the second adjustment signal according to the storage value of the read memory cell U to correspondingly execute the first adjustment mode or the second adjustment mode.

[0118] See also Figure 7 When it is determined that the storage value of the storage unit U is outside the target range, by determining that the storage value of the storage unit U is less than or equal to the first preset value I_aim_min, the set pulse control signal SET in the second adjustment signal can be applied when I_read≤I_aim_min to start the first adjustment mode; or, the reset pulse control signal RESET in the second adjustment signal can be applied when I_read>I_aim_min to start the second adjustment mode.

[0119] For example, the first preset value I_aim_min is between the minimum value I_min of the target range and the minimum value Ic_min of the reference range, that is, an open interval (Ic_min, I_min) formed by the minimum value I_min of the target range and the minimum value Ic_min of the reference range. Here, Ic_min<I_min.

[0120] It should be supplemented that the first adjustment mode and the second adjustment mode may end when it is determined that the storage value of the storage unit U is within the target range (i.e., I_read∈[I_min, I_max]); and / or when it is determined that the number of times the storage value of the storage unit U is adjusted according to the second adjustment signal reaches the maximum number of fine adjustments (i.e., MAX loop=N fine ) ends.

[0121] In some embodiments, please refer to Figure 7When executing steps S10 and S20 of the first adjustment mode, by determining whether the storage value of the storage unit U is less than the minimum value I_min of the target range, the set pulse control signal SET can be updated when I_read<I_min, and the storage value of the storage unit U can be adjusted again according to the updated set pulse control signal SET. In addition, the reset pulse control signal RESET can be applied to the storage unit U when I_read≥I_min.

[0122] It can be understood that the set pulse control signal SET is applied to the memory cell U, and the bit line starting voltage V is applied to the bit line BL. BL_start And apply word line starting voltage V to word line WL WL_start Start. A reset pulse control signal RESET is applied to the memory cell U, and a source line start voltage V is applied to the source line SL. SL_start And apply word line starting voltage V to word line WL WL_start start.

[0123] For example, executing step S20 to update the set pulse control signal SET, and re-adjusting the storage value of the storage unit U according to the updated set pulse control signal SET may include the following steps S21 - S23 .

[0124] In step S21, the voltage V of the bit line BL connected to the memory cell U is determined. BL Is it less than or equal to the maximum preset voltage V of the bit line? BL_MAX .

[0125] Optionally, the bit line maximum preset voltage V BL_MAX Less than or equal to the bit line termination adjustment voltage V BL_end .

[0126] In step S22, if (ie: V BL ≤V BL_MAX ), the bit line voltage increment step length V is determined according to the adjustment amount of the storage value of the storage unit U by the previous set pulse control signal BL _ step , to increase the step size V according to the bit line voltage BL _ step The storage value of the storage unit U is readjusted.

[0127] Optionally, the single adjustment amount of the storage value of the storage unit U can be characterized by the relative change amount ΔI of the read current. For example, different current increment gears can be set to respectively execute different bit line voltage increment steps V BL _ step .

[0128] For example, when the set pulse control signal SET is applied, the formula for obtaining the relative change △I of the read current corresponding to the single adjustment amount of the storage value of the storage unit U can be: △I=(Iread-Iread_old) / (Imin-Iread_old); wherein, Iread is the read current corresponding to the current storage value of the storage unit U, Iread_old is the read current corresponding to the storage value of the storage unit U under the previous reset pulse control signal, and Imin is the minimum value of the target range.

[0129] For example, the current increment level is set to three levels. In the first level, △I<l1, the bit line voltage increment step length V BL _ step Take the first step V BL _ step1 In the second gear, l1≤△I<l2, the bit line voltage increment step size V BL _ step Use the second step length V BL _ step2 In the third gear, l2≤△I, the bit line voltage increment step is V BL _ step Using the third step length V BL _ step3 . And, optionally, the first step length V BL _ step1 , the second step length V BL _ step2 and the third step length V BL _ step3 The voltage increases sequentially between them are 0.05V, 0.1V or 0.2V.

[0130] In step S23, if no (ie: V BL >V BL__MAX ), then the voltage of the bit line BL is set to the bit line start adjustment voltage V BL_start , and determine the word line voltage increment step length V according to the adjustment amount of the storage value of the storage unit U by the previous set pulse control signal WL_step , to increase the step size V according to the word line voltage WL_step The storage value of the storage unit U is readjusted.

[0131] In some embodiments, please refer to Figure 7, when executing steps S30 and S40 of the second adjustment mode, by judging whether the storage value of the storage unit U is greater than the maximum value I_max of the target range, the reset pulse control signal RESET can be updated when I_read>I_max, and the storage value of the storage unit U can be adjusted again according to the updated reset pulse control signal RESET. Moreover, the set pulse control signal SET can be applied to the storage unit U when I_read≤I_max.

[0132] For example, executing step S40 to update the reset pulse control signal RESET, and re-adjusting the storage value of the storage unit U according to the updated reset pulse control signal RESET may include the following steps S41 to S43.

[0133] In step S41, the voltage V SL Is it less than or equal to the maximum preset voltage V of the source line? SL_MAX .

[0134] Optionally, the maximum preset voltage of the source line V SL_MAX Less than or equal to the source line termination adjustment voltage V SL_end .

[0135] In step S42, if (ie: V SL ≤V SL_MAX ), the source line voltage increment step length V is determined according to the adjustment amount of the storage value of the storage unit U by the previous reset pulse control signal SL _ step , to increase the step size V according to the source line voltage SL _ step The storage value of the storage unit U is readjusted.

[0136] Optionally, the single adjustment amount of the storage value of the storage unit U can be characterized by the relative change amount ΔI of the read current. For example, different current increment gears can be set to respectively execute different source line voltage increment steps V SL _ step .

[0137] For example, when the reset pulse control signal RESET is applied, the formula for obtaining the relative change △I of the read current corresponding to the single adjustment amount of the storage value of the storage unit U can be: △I=(Iread_old-Iread) / (Iread_old-Imax); wherein, Iread_old is the read current corresponding to the storage value of the storage unit U under the previous reset pulse control signal, Iread is the read current corresponding to the current storage value of the storage unit U, and Imax is the maximum value of the target range.

[0138] For example, the current increment level is set to three levels. In the first level, △I<l1, the source line voltage increment step length V SL _ step Take the first step V SL _ step1 In the second gear, l1≤△I<l2, the source line voltage increment step size V SL _ step Use the second step length V SL _ step2 In the third gear, l2≤△I, the source line voltage increment step V SL _ step Using the third step length V SL _ step3 . And, optionally, the first step length V SL _ step1 , the second step length V SL _ step2 and the third step length V SL _ step3 The voltage increases sequentially between them are 0.05V, 0.1V or 0.2V.

[0139] In step S43, if no (ie: V SL >V BL_MAX ), then the voltage of the source line SL is set to the source line start adjustment voltage V SL_start , and determine the word line voltage increment step length V according to the adjustment amount of the storage value of the storage unit U by the previous set pulse control signal WL_step , to increase the step size V according to the word line voltage WL_step The storage value of the storage unit U is readjusted.

[0140] It is worth mentioning that in some of the above embodiments, if the relative change ΔI of the read current increases, the word line voltage increases by a step length V WL _ step and the corresponding bit line voltage increment step V BL _ step Or source line voltage increment step size V SL _ step Conversely, if the relative change in the read current △I decreases, the word line voltage increases by a step size V WL _ step and the corresponding bit line voltage increment step V BL _ step Or source line voltage increment step size V SL _ step That is, each time the set pulse control signal SET or the reset pulse control signal RESET is updated, the word line voltage increases by a step size V WL _ step and the corresponding bit line voltage increment step VBL _ step Or source line voltage increment step size V SL _ step Each step size setting can be determined by the adjustment amount of the storage value of the storage unit U by the previous signal.

[0141] From the above, the above-mentioned memory and its multi-value programming method provided by the embodiments of the present disclosure, compared with the related incremental step pulse programming (ISPP) method, the embodiments of the present disclosure can dynamically control the single adjustment amplitude of the storage value of the storage unit in real time, so as to significantly shorten the multi-value programming time of the memory, thereby effectively improving the multi-value programming efficiency.

[0142] Figure 8 A programming efficiency comparison diagram of the memory multi-value programming method provided by the embodiment of the present disclosure and the ISPP method is shown. Figure 8 The horizontal axis is the storage state number, and the vertical axis is the number of pulses. It can be understood that a storage state can represent a storage value. Figure 8 The programming efficiency comparison between the disclosed method and the ISPP method shown in the figure shows that the disclosed method can improve the multi-value programming efficiency to nearly 10 times that of the traditional programming algorithm (ie, the ISPP method).

[0143] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include a housing, a circuit board disposed in the housing, and a memory integrated on the circuit board. The structure of the memory may refer to the relevant description in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0144] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0145] The above-mentioned embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure.

Claims

1. A memory multi-value programming method, characterized in that: The memory includes a plurality of storage cells arranged in an array, and the memory multi-value programming method includes: Read the storage value of the storage unit; determining whether the storage value of the storage unit is within a reference range; If not, applying a first adjustment signal to the storage unit to adjust the storage value of the storage unit to the reference range; Determining whether the storage value of the storage unit is within a target range; If not, applying a second adjustment signal to the storage unit to adjust the storage value of the storage unit to the target range; The minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range; the single adjustment amplitude of the second adjustment signal is less than the single adjustment amplitude of the first adjustment signal; the storage unit is connected to the bit line, the word line, and the source line correspondingly; the control parameters of the first adjustment signal include: a bit line coarse adjustment voltage, a word line coarse adjustment voltage, and a maximum number of coarse adjustments; The memory multi-value programming method further comprises: Acquire an adjustment number of times of adjusting a storage value of the storage unit according to the first adjustment signal; If the adjustment times reach the maximum coarse adjustment times and the storage value of the storage unit cannot be adjusted to the reference range, the steps of switching the storage unit and reading the storage value of the switched storage unit are executed; If the adjustment times do not reach the maximum coarse adjustment times and the storage value of the storage unit has been adjusted to the reference range, a step of determining whether the storage value of the storage unit is within a target range is performed.

2. The memory multi-value programming method according to claim 1, characterized in that: The determining whether the stored value is located before the reference range, the memory multi-value programming method further comprises: Presetting the target range and the reference range; A control parameter of the first adjustment signal is preset.

3. The memory multi-value programming method according to claim 2, characterized in that: The first adjustment signal includes a set pulse control signal with a fixed pulse width and a fixed amplitude.

4. The memory multi-value programming method according to claim 1, characterized in that: The determining whether the storage value of the storage unit is located before the target range, the memory multi-value programming method further comprises: Presetting a control parameter of the second adjustment signal; Among them, the storage unit is connected to the bit line, word line and source line correspondingly; the control parameters of the second adjustment signal include: bit line starting adjustment voltage, bit line ending adjustment voltage, bit line voltage incremental step, word line starting adjustment voltage, word line ending adjustment voltage, word line voltage incremental step, source line starting adjustment voltage, source line ending adjustment voltage, source line voltage incremental step and maximum fine adjustment times.

5. The memory multi-value programming method according to claim 4, characterized in that: The second adjustment signal includes a set pulse control signal and a reset pulse control signal with adjustable pulse width and amplitude; The set pulse control signal is used for the first adjustment mode, and the reset pulse control signal is used for the second adjustment mode; the start condition of the first adjustment mode includes that the storage value of the storage unit is less than or equal to the first preset value, and the start condition of the second adjustment mode includes that the storage value of the storage unit is greater than the first preset value; the end conditions of the first adjustment mode and the second adjustment mode include: the storage value of the storage unit is within the target range, and / or the number of adjustment times of adjusting the storage value of the storage unit according to the second adjustment signal reaches the maximum number of fine adjustment times; The first preset value is between the minimum value of the target range and the minimum value of the reference range.

6. The memory multi-value programming method according to claim 5, characterized in that: Also includes: In the first adjustment mode, when the storage value of the storage unit is outside the target range, determining whether the storage value of the storage unit is less than a minimum value of the target range; If yes, then updating the set pulse control signal, and re-adjusting the storage value of the storage unit according to the updated set pulse control signal; Wherein, the updating of the set pulse control signal and re-adjusting the storage value of the storage unit according to the updated set pulse control signal includes: Determining whether the voltage of the bit line connected to the memory cell is less than or equal to a maximum preset voltage of the bit line; If yes, determining the bit line voltage increment step size according to the adjustment amount of the storage value of the storage cell by the previous set pulse control signal, so as to adjust the storage value of the storage cell again according to the bit line voltage increment step size; If not, the voltage of the bit line is set as the starting adjustment voltage of the bit line, and the word line voltage increment step is determined according to the adjustment amount of the storage value of the storage cell by the previous set pulse control signal, so as to adjust the storage value of the storage cell again according to the word line voltage increment step.

7. The memory multi-value programming method according to claim 5, characterized in that: Also includes: In the second adjustment mode, when the storage value of the storage unit is outside the target range, determining whether the storage value of the storage unit is greater than a maximum value of the target range; If yes, then updating the reset pulse control signal, and re-adjusting the storage value of the storage unit according to the updated reset pulse control signal; Wherein, updating the reset pulse control signal and re-adjusting the storage value of the storage unit according to the updated reset pulse control signal includes: Determining whether the voltage of the source line connected to the storage unit is less than or equal to a maximum preset voltage of the source line; If yes, the source line voltage increment step is determined according to the adjustment amount of the storage value of the storage unit by the reset pulse control signal last time, so as to adjust the storage value of the storage unit again according to the source line voltage increment step; If not, the voltage of the source line is set as the starting adjustment voltage of the source line, and the word line voltage increment step is determined according to the adjustment amount of the storage value of the storage unit by the previous reset pulse control signal, so as to adjust the storage value of the storage unit again according to the word line voltage increment step.

8. A memory, characterized in that: include: A memory cell and a bit line, a word line and a source line connected to the memory cell; the memory further comprises a reading circuit and a control circuit connected to the bit line, the word line and the source line respectively; wherein, The read circuit is configured to: read the storage value of the storage unit; The control circuit is configured to: determine whether the storage value of the storage cell is within a reference range, and when the storage value of the storage cell is outside the reference range, apply a first adjustment signal to the storage cell to adjust the storage value of the storage cell to the reference range; and, when the storage value of the storage cell is within the reference range, determine whether the storage value of the storage cell is within a target range, and when the storage value of the storage cell is outside the target range, apply a second adjustment signal to the storage cell to adjust the storage value of the storage cell to the target range; The minimum value of the reference range is less than or equal to the minimum value of the target range, and the maximum value of the reference range is greater than or equal to the maximum value of the target range; the single adjustment amplitude of the second adjustment signal is less than the single adjustment amplitude of the first adjustment signal; the control parameters of the first adjustment signal include: a bit line coarse adjustment voltage, a word line coarse adjustment voltage and a maximum number of coarse adjustments; The control circuit is also configured to: obtain the number of adjustments of the storage value of the storage unit according to the first adjustment signal; in response to the adjustment number reaching the maximum coarse adjustment number and the storage value of the storage unit failing to be adjusted to the reference range, switch the storage unit and read the storage value of the switched storage unit; in response to the adjustment number not reaching the maximum coarse adjustment number and the storage value of the storage unit having been adjusted to the reference range, determine whether the storage value of the storage unit is within the target range.

9. An electronic device, characterized in that: include: A memory as claimed in claim 8.

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