A display panel and display device

Abstract

This invention provides a display panel and a display device. The display panel includes pixel circuits and signal lines. The pixel circuits include data writing transistors and reset transistors. The signal lines include data signal lines and reset signal lines. The data signal lines are electrically connected to the first electrode of the data writing transistors, and the reset signal lines are electrically connected to the first electrode of the reset transistors. Multiple data signal lines are arranged along a first direction and extend along a second direction, intersecting the first and second directions. The reset signal lines include first reset lines, and multiple first reset lines are arranged along the first direction and extend along the second direction. The first reset lines and data signal lines are disposed in the same layer. By using the technical method provided by this invention, the data signal lines and first reset lines with the same arrangement and extension directions are disposed in the same layer, which can reduce the number of film layers in the display panel, reduce the manufacturing cost and manufacturing difficulty of the display panel, and facilitate the realization of a thinner display panel design.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, display panels have been widely used in people's production and daily life. To better meet people's needs, adjustments can be made to the display panel, such as adjusting some of the wiring, thereby improving the overall effect of the display panel. Summary of the Invention

[0003] This invention provides a display panel and a display device. By arranging data signal lines with the same arrangement direction and extension direction and a first reset line in the same layer, the number of film layers in the display panel can be reduced, which is beneficial for achieving a thinner design of the display panel.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including pixel circuits and signal lines;

[0005] The pixel circuit includes a data writing transistor and a reset transistor; the signal line includes a data signal line and a reset signal line, the data signal line is electrically connected to the first terminal of the data writing transistor, and the reset signal line is electrically connected to the first terminal of the reset transistor;

[0006] The plurality of data signal lines are arranged along a first direction and extend along a second direction, the first direction and the second direction intersecting; the reset signal line includes a first reset line, and the plurality of the first reset lines are arranged along the first direction and extend along the second direction;

[0007] The first reset line is disposed on the same layer as the data signal line.

[0008] In a second aspect, embodiments of the present invention provide a display device including the display panel described in the first aspect.

[0009] This invention provides a display panel including a data writing transistor and a reset transistor. The data writing transistor is electrically connected to a data signal line, and the reset transistor is electrically connected to a reset signal line. The reset signal line includes a first reset line, and both the first reset line and the data signal line are arranged along a first direction and extend along a second direction. In this invention, signal lines with the same arrangement and extension directions are arranged in the same layer, thus reducing the number of film layers in the display panel. Therefore, while ensuring the display effect, arranging the first reset line and the data signal line in the same layer can reduce the number of film layers in the display panel, reduce the manufacturing cost and difficulty of the display panel, and facilitate the realization of a thinner display panel design. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of exemplary embodiments of the present invention, the accompanying drawings used in describing the embodiments are briefly introduced below. Obviously, the accompanying drawings described are only a portion of the drawings of the embodiments to be described in this invention, and not all of the drawings. For those skilled in the art, other drawings can be obtained from these drawings without any creative effort.

[0011] Figure 1 This is a schematic diagram of the structure of the first type of display panel provided in an embodiment of the present invention;

[0012] Figure 2A This is a schematic diagram of the structure of the first pixel circuit provided in the embodiment of the present invention;

[0013] Figure 2B This invention provides, within a driving cycle, the capability to... Figure 2A A timing diagram of the implementation of the signal of the pixel circuit shown;

[0014] Figure 3A This is a schematic diagram of the structure of the second pixel circuit provided in an embodiment of the present invention;

[0015] Figure 3B This invention provides, within a driving cycle, the capability to... Figure 3A A timing diagram of the implementation of the signal of the pixel circuit shown;

[0016] Figure 4 This is a schematic diagram of the film structure of the first pixel circuit provided in the embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram of the film layer structure of the first type of display panel provided in the embodiments of the present invention;

[0018] Figure 6 yes Figure 5 A schematic diagram of the first part of the structure;

[0019] Figure 7 yes Figure 5 A schematic diagram of the second part of the structure;

[0020] Figure 8 yes Figure 5 A schematic diagram of the third part of the structure;

[0021] Figure 9 yes Figure 5 A schematic diagram of the fourth part of the structure;

[0022] Figure 10 yes Figure 5 A schematic diagram of the fifth part of the structure;

[0023] Figure 11 yes Figure 5 A schematic diagram of the sixth part of the structure;

[0024] Figure 12 yes Figure 5 The first schematic diagram of the structure of the seventh part;

[0025] Figure 13 yes Figure 5 A schematic diagram of the eighth part of the structure;

[0026] Figure 14 This is a schematic diagram of the film layer structure of the second type of display panel provided in an embodiment of the present invention;

[0027] Figure 15 yes Figure 14 A schematic diagram of the first part of the structure;

[0028] Figure 16 yes Figure 14 A schematic diagram of the second part of the structure;

[0029] Figure 17 yes Figure 14 A schematic diagram of the third part of the structure;

[0030] Figure 18 yes Figure 14 A schematic diagram of the fourth part of the structure;

[0031] Figure 19 yes Figure 14 A schematic diagram of the fifth part of the structure;

[0032] Figure 20 yes Figure 14 A schematic diagram of the sixth part of the structure;

[0033] Figure 21 yes Figure 14 The first schematic diagram of the structure of the seventh part;

[0034] Figure 22 yes Figure 14 A schematic diagram of the eighth part of the structure;

[0035] Figure 23 This is a schematic diagram of the film layer structure of the third type of display panel provided in the embodiments of the present invention;

[0036] Figure 24 yes Figure 23 A schematic diagram of the first part of the structure;

[0037] Figure 25 yes Figure 23 A schematic diagram of the second part of the structure;

[0038] Figure 26 yes Figure 23 A schematic diagram of the third part of the structure;

[0039] Figure 27 yes Figure 23 A schematic diagram of the fourth part of the structure;

[0040] Figure 28 yes Figure 23 A schematic diagram of the fifth part of the structure;

[0041] Figure 29 yes Figure 23 A schematic diagram of the sixth part of the structure;

[0042] Figure 30 yes Figure 23 A schematic diagram of the seventh part of the structure;

[0043] Figure 31 yes Figure 23 A schematic diagram of the eighth part of the structure;

[0044] Figure 32 This is a schematic diagram of the structure of the second type of display panel provided in an embodiment of the present invention;

[0045] Figure 33 yes Figure 32 An enlarged schematic diagram of the pixel circuit group provided in the document;

[0046] Figure 34 This is a schematic diagram of the third pixel circuit provided in the embodiments of the present invention;

[0047] Figure 35 This is a schematic diagram of the film structure of the first pixel circuit provided in the embodiment of the present invention;

[0048] Figure 36 This is a schematic diagram of the structure of the third type of display panel provided in the embodiments of the present invention;

[0049] Figure 37 yes Figure 5 The second schematic diagram of the seventh part of the structure;

[0050] Figure 38 This is a schematic diagram of the structure of the fourth type of display panel provided in the embodiments of the present invention;

[0051] Figure 39 yes Figure 14 The second schematic diagram of the seventh part of the structure;

[0052] Figure 40 This is a schematic diagram of the structure of the fifth type of display panel provided in the embodiments of the present invention;

[0053] Figure 41 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0054] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0055] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a system, product, or device comprising a series of units is not necessarily limited to those steps or units explicitly listed, but may include other units not explicitly listed or inherent to such products or devices.

[0056] Figure 1 This is a schematic diagram of the structure of the first type of display panel provided in an embodiment of the present invention. Figure 2A This is a schematic diagram of the structure of the first pixel circuit provided in the embodiment of the present invention. Figure 2B This invention provides, within a driving cycle, the capability to... Figure 2A The timing diagram shows an implementation of the signal of the pixel circuit. Figure 3A This is a schematic diagram of the structure of the second pixel circuit provided in an embodiment of the present invention. Figure 3B This invention provides, within a driving cycle, the capability to... Figure 3A The timing diagram of the signal implementation of the pixel circuit shown is referenced. Figures 1 to 3B This invention provides a display panel 10, which includes a pixel circuit 100 and signal lines 200. The pixel circuit 100 includes a data writing transistor 110 and a reset transistor 120. The signal lines include a data signal line 210 and a reset signal line 220. The data signal line 210 is electrically connected to the first electrode of the data writing transistor 110, and the reset signal line 220 is electrically connected to the first electrode of the reset transistor 220. Multiple data signal lines 210 are arranged along a first direction X and extend along a second direction Y, and the first direction X and the second direction Y intersect. The reset signal line 220 includes a first reset line 221, and multiple first reset lines 221 are arranged along the first direction X and extend along the second direction Y. The first reset line 221 and the data signal lines 210 are disposed on the same layer.

[0057] For details, please refer to Figure 1The display panel 10 includes a pixel circuit 100, which is electrically connected to the light-emitting element 400 in the display panel 10 to drive the light-emitting element 400 and ensure its light emission display. Furthermore, the display panel 10 also includes a signal line 200, configured to provide voltage and / or current signals to the pixel circuit 100, thereby driving the light-emitting element 400. Further, the signal line 200 includes a data signal line 210 and a reset signal line 220. The data signal line 210 is electrically connected to the data writing transistor 110 in the pixel circuit 100, and the reset signal line 220 is electrically connected to the reset transistor 120 in the pixel circuit 100. Since the pixel circuit 100 can be configured in various ways... Figure 1 The specific structure of the pixel circuit 100 is not shown in the figure, and the specific electrical connection positions of the signal line 200 and the transistors in the pixel circuit 100 are not clearly shown. Therefore, the figure only shows the electrical connection relationship between the signal line 200 and the pixel circuit 100 by the fact that they overlap, but this is not intended to limit the position and area of ​​the overlap.

[0058] Furthermore, the pixel circuit 100 can be configured in various ways. Referring to Figure 2, the pixel circuit 100 is illustrated as "7T2C", and referring to Figure 3, the pixel circuit 100 is illustrated as "8T1C", where "T" represents a transistor and "C" represents a capacitor. Based on the configuration of the pixel circuit 100, those skilled in the art can make adaptive adjustments according to their needs.

[0059] For example, refer to Figure 2A As shown, the pixel circuit 100 may include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initial reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, a storage capacitor Cst, and a first capacitor C1. Specifically, for the operation of the pixel circuit 100, refer to... Figure 2AFor example, the scan signal line (shown as S1N in the figure) connected to the control terminal of the initial reset transistor T5 can control the turn-on and turn-off of the initial reset transistor T5. When the initial reset transistor T5 is turned on, the reset signal in the reset signal line 220 (shown as Vref1 in the figure) connected to the input terminal of the initial reset transistor T5 is written to the gate of the driving transistor T3 to reset the first node N1. The storage capacitor Cst and the first capacitor C1 can ensure the potential stability of the first node N1. The scan signal line (shown as S1 in the figure) connected to the control terminal of the data writing transistor T2 can control the turn-on and turn-off of the data writing transistor T2. When the data writing transistor T2 is turned on, the data signal on the data signal line 210 (shown as Vdata in the figure) is written to the first terminal of the driving transistor T3. The scan signal line (shown as S2N in the figure) connected to the control terminal of the threshold compensation transistor T4 can control the turn-on and turn-off of the threshold compensation transistor T4, and performs threshold voltage compensation on the driving transistor T3 when the threshold compensation transistor T4 is on. Simultaneously, the scan signal line (shown as S2 in the figure) connected to the control terminal of the anode reset transistor T7 can control the turn-on and turn-off of the anode reset transistor T7, and resets the anode of the light-emitting element 400 connected to the pixel circuit 100 when the anode reset transistor T7 is on, i.e., writing the reset signal on the reset signal line 220 (shown as Vref2 in the figure) to the anode of the light-emitting element 400. The light-emitting control signal line Emit, connected to the control terminal of the first light-emitting control transistor T1 and the control terminal of the second light-emitting control transistor T6, can control the turn-on and turn-off of the first light-emitting control transistor T1 and the second light-emitting control transistor T6, and writes the power signal transmitted by the power signal line PVDD to the light-emitting element 400 when the first light-emitting control transistor T1 and the second light-emitting control transistor T6 are on, thereby realizing the display and light emission of the light-emitting element 400. Specifically, refer to... Figure 2BAs shown, one frame of the display panel 10 includes at least an initialization writing phase T1, a data writing phase T2, and a light-emitting phase T3. In the initialization phase T1, the initial reset transistor T5 is turned on under the control of the scan signal S1N, writing the initialization signal Vref1 to the first node N1, which is electrically connected to the gate of the driving transistor T3, to initialize the gate of the driving transistor T3. Simultaneously, since the threshold compensation transistor T4 is turned on, the initialization signal Vref1 is also written to the second terminal of the driving transistor T3, i.e., node N3. In the data writing phase T2, the data writing transistor T2 is turned on under the control of the scan signal S1, and the threshold compensation transistor T4 is turned on under the control of the scan signal S2N, causing the data signal Vdata to be written sequentially to the gate of the driving transistor T3 through the data writing transistor T2, the driving transistor T3, and the threshold compensation transistor T4. Simultaneously, in the data writing phase T2, the anode reset transistor T7 is turned on under the control of the scan signal S2, writing the reset signal Vref2 to the anode of the light-emitting element 400, to initialize the anode of the light-emitting element 400. During the light-emitting stage T3, the first light-emitting transistor T1 and the second light-emitting control transistor T6 are turned on under the control of the light-emitting control signal Emit, so that the driving transistor T3 generates a driving current that can be transmitted to the anode of the light-emitting element 400, thereby driving the light-emitting element 400 to emit light.

[0060] Further reference Figure 3A As shown, the pixel circuit 100 may include a first light-emitting control transistor T1, a data writing transistor T2, a driving transistor T3, a threshold compensation transistor T4, an initial reset transistor T5, a second light-emitting control transistor T6, an anode reset transistor T7, a bias transistor T8, and a storage capacitor Cst. The operation of the pixel circuit 100 is similar to the process described above and will not be repeated here. Furthermore, in... Figure 3A In the pixel circuit 100, the scan signal line (shown as Sp in the figure) connected to the control terminal of the bias transistor T8 can control the conduction and turn-off of the bias transistor T8. When the bias transistor T8 is turned on, the bias signal transmitted by the reset signal line 220 (shown as DVH in the figure) is written to the bias transistor T8, and the bias adjustment of the second node N2 is performed.

[0061] For details, please refer to Figure 3B As shown, further, in one driving cycle Y of the pixel circuit 100, there are a data writing stage Y1, a light emission stage Y2, and a light emission holding stage Y3. The data writing stage Y1 includes a disabled level stage of the light emission control signal Emit; the light emission stage Y2 includes an enabled level stage of the light emission control signal Emit; and in the light emission holding stage Y3, the light emission control signal Emit includes multiple disabled level stages and at least one enabled level stage. Figure 3B(Taking an enable level stage as an example for illustration). Meanwhile, the magnitude of the bias voltage signal line DVH in the data writing stage Y1 and the light emission stage Y2 can be the same as or different from the magnitude of the bias voltage signal line DVH in the light emission holding stage Y3. Figure 3B (Illustration in the diagram). Further, the data writing stage Y1 includes a first bias adjustment stage Y11. In the first bias adjustment stage Y11, the signal transmitted by the scan signal line SP includes at least one low-level period, and during this period, the signal transmitted by the scan signal line S2N includes at least one high-level period. In other words, in the first bias adjustment stage Y11, at least the bias transistor T8 and the threshold compensation transistor T4 are turned on. The bias signal of the bias voltage signal line DVH is transmitted to the driving transistor T3 through the bias transistor T8, and then to the gate of the driving transistor T3 through the threshold compensation transistor T4. That is, in the first bias adjustment stage Y11, the bias signal can adjust the bias of the first node N1, the second node N2, and the third node N3. The data writing stage Y1 also includes an initialization and second bias adjustment stage Y12. In the initialization and second bias adjustment stage Y12, the signal transmitted through the scan signal line S2N includes at least one high-level period. In other words, in the initialization and second bias adjustment stage Y12, the initialization transistor T5 is turned on, and the subsequent threshold compensation transistor T4 is also turned on. The initialization signal line Vref1 can adjust the gate of the driving transistor T3 through the initialization transistor T5. The initialization signal line Vref1 can also adjust the third node N3 through the initialization transistor T5 and the threshold compensation transistor T4. The data writing stage Y1 also includes a data signal writing stage Y13. In the data signal writing stage Y13, the signal transmitted through the scan signal line S2N includes a high-level period, and the signal transmitted through the scan signal line SP* includes at least one low-level period. In other words, in the data signal writing stage Y13, the data writing transistor T2 and the threshold compensation transistor T4 are turned on, and the data signal Vdata can be transmitted to the gate of the driving transistor T3 through the data writing transistor T2 and the threshold compensation transistor T4. The data writing stage Y1 also includes a third bias adjustment stage Y14, in which the signal transmitted by the scan signal line SP includes at least one low-level period, during which the second stage N2 can be biased again by the bias transistor T8.

[0062] Optionally, the transistors in the pixel circuit 100 can be of various types. Transistors include indium gallium zinc oxide (IGZO) transistors and low-temperature polysilicon (LTPS) transistors. Oxide transistors have advantages such as low leakage current, while LTPS transistors have advantages such as high switching speed, high carrier mobility, and low power consumption. (Reference) Figure 2A and Figure 3A As shown, the pixel circuit 100 may include low-temperature polysilicon transistors, or may include both oxide transistors and low-temperature polysilicon transistors. The type of transistor in the pixel circuit 100 can be adapted to actual needs, and the embodiments of the present invention do not impose specific limitations on this.

[0063] Specifically, the display panel 10 is composed of multiple overlapping film layers. Figure 4 This is a schematic diagram of the film layer structure of the first pixel circuit provided in the embodiment of the present invention, for reference. Figure 4 As shown, the film layer structure of the pixel circuit 100, from the bottom to the light-emitting side of the display panel 10, can be sequentially: substrate 300, buffer layer 310, first active layer 320, first insulating layer 330, first metal layer 340, interlayer insulating layer 350, capacitor substrate layer 360, second insulating layer 370, second active layer 380, third insulating layer 390, top gate metal layer 311, inorganic insulating layer 321, second metal layer 331, first planarization layer 341, third metal layer 351, second planarization layer 361, and anode layer 371. For a specific pixel circuit 100, the film layer structure can be adaptively adjusted according to actual needs, such as adding or removing some film layers. Furthermore, any of the above film layers can contain at least one sublayer; this embodiment of the invention does not impose specific limitations on this.

[0064] Furthermore, Figure 5 This is a schematic diagram of the film layer structure of the first type of display panel provided in the embodiments of the present invention. Figure 6 yes Figure 5 A schematic diagram of the first part of the structure. Figure 7 yes Figure 5 A schematic diagram of the second part of the structure. Figure 8 yes Figure 5 A schematic diagram of the third part of the structure. Figure 9 yes Figure 5 A schematic diagram of the fourth part of the structure. Figure 10 yes Figure 5 A schematic diagram of the fifth part of the structure. Figure 11 yes Figure 5 A schematic diagram of the sixth part of the structure. Figure 12 yes Figure 5The first schematic diagram of the seventh part of the structure. Figure 13 yes Figure 5 The schematic diagram of the eighth part of the structure is shown in Figure 2. If the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in Figure 2, then the film layer structure relationship of the display panel 10 can be referred to... Figure 5 As shown, and Figures 6 to 13 Used to Figure 5 The different film layers are illustrated from bottom to top. Further, refer to 2. Figure 5 and Figure 12 As shown, the display panel 10 includes multiple reset signal lines 220, and each reset signal line 220 includes a first reset line 221 (shown as Vref2(a) in the figure). The first reset line 221 and the data signal line 210 (shown as Vdata in the figure) are arranged in the same layer. The first reset line 221, which has the same arrangement direction and extension direction as the data signal line 210, is placed in the same film layer as the data signal line 210. Since the two types of traces have the same setting trend, they are considered to be placed in the same film layer, eliminating the need for a separate film layer for the first reset line 221. This reduces the number of film layers in the display panel 10. Therefore, while ensuring the display effect of the display panel 10, the manufacturing cost and manufacturing difficulty of the display panel 10 are reduced, which is beneficial for achieving a thinner design of the display panel 10.

[0065] For example, Figure 14 This is a schematic diagram of the film layer structure of the second type of display panel provided in an embodiment of the present invention. Figure 15 yes Figure 14 A schematic diagram of the first part of the structure. Figure 16 yes Figure 14 A schematic diagram of the second part of the structure. Figure 17 yes Figure 14 A schematic diagram of the third part of the structure. Figure 18 yes Figure 14 A schematic diagram of the fourth part of the structure. Figure 19 yes Figure 14 A schematic diagram of the fifth part of the structure. Figure 20 yes Figure 14 A schematic diagram of the sixth part of the structure. Figure 21 yes Figure 14 A schematic diagram of the seventh part of the structure. Figure 22 yes Figure 14 The schematic diagram of the eighth part of the structure is shown in Figure 3. If the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in Figure 3, then the film layer structure relationship of the display panel 10 can be referred to... Figure 14 As shown, and Figures 15 to 22 Used to Figure 14 The different film layers are illustrated from bottom to top. Further, refer to 3. Figure 14 and Figure 21As shown, the display panel 10 includes multiple reset signal lines 220, and each reset signal line 220 includes a first reset line 221 (shown as Vref2(a) in the figure). The first reset line 221 and the data signal line 210 (shown as Vdata in the figure) are arranged in the same layer. The first reset line 221, which has the same arrangement direction and extension direction as the data signal line 210, is placed in the same film layer as the data signal line 210. Since the two types of traces have the same setting trend, they are considered to be placed in the same film layer, eliminating the need for a separate film layer for the first reset line 221. This reduces the number of film layers in the display panel 10. Therefore, while ensuring the display effect of the display panel 10, the manufacturing cost and manufacturing difficulty of the display panel 10 are reduced, which is beneficial for achieving a thinner design of the display panel 10.

[0066] For example, Figure 23 This is a schematic diagram of the film layer structure of the third type of display panel provided in the embodiments of the present invention. Figure 24 yes Figure 23 A schematic diagram of the first part of the structure. Figure 25 yes Figure 23 A schematic diagram of the second part of the structure. Figure 26 yes Figure 23 A schematic diagram of the third part of the structure. Figure 27 yes Figure 23 A schematic diagram of the fourth part of the structure. Figure 28 yes Figure 23 A schematic diagram of the fifth part of the structure. Figure 29 yes Figure 23 A schematic diagram of the sixth part of the structure. Figure 30 yes Figure 23 A schematic diagram of the seventh part of the structure. Figure 31 yes Figure 23 The schematic diagram of the eighth part of the structure is shown in Figure 3. If the pixel circuit 100 in the display panel 10 is the pixel circuit 100 shown in Figure 3, then the film layer structure relationship of the display panel 10 can be referred to... Figure 23 As shown, and Figures 24 to 31 Used to Figure 23 The different film layers are illustrated from bottom to top. Further, refer to 3. Figure 23 and Figure 30As shown, the display panel 10 includes multiple reset signal lines 220, and each reset signal line 220 includes a first reset line 221 (shown as Vref2(a) and DVH(a) in the figure). The first reset line 221 and the data signal line 210 (shown as Vdata in the figure) are arranged in the same layer. The first reset line 221, which has the same arrangement direction and extension direction as the data signal line 210, is placed in the same film layer as the data signal line 210. Since the two types of traces have the same setting trend, they are considered to be placed in the same film layer, eliminating the need for a separate film layer for the first reset line 221. This reduces the number of film layers in the display panel 10. Therefore, while ensuring the display effect of the display panel 10, the manufacturing cost and manufacturing difficulty of the display panel 10 are reduced, which is beneficial for achieving a thinner design of the display panel 10. Only a partial schematic diagram of the film layer structure of the display panel 10 is shown here. The display panel 10 has various different film layer settings, which are not shown here.

[0067] In general, the specific signal transmitted in the first reset line 221 can be adjusted according to the differences in the pixel circuit 100, but the arrangement of the first reset line 221 is the same as that of the data signal line 210. For example, it can be at least one of the following: an initial reset signal line, an anode reset signal line, and a bias reset signal line, arranged along the first direction and extending along the second direction. Adaptive adjustments can be made based on the specific type of the first reset line 221. Setting the first reset line 221 and the data signal line 210 on the same layer ensures the thin design of the display panel 10.

[0068] It should be noted that, Figures 5 to 31 In the diagram, the dashed lines are used to roughly divide the pixel circuits 100, facilitating the description of their structure. The division of the pixel circuits 100 can be adapted to the actual display panel 10; this embodiment of the invention does not impose specific limitations on this.

[0069] In summary, the display panel provided by the embodiments of the present invention includes data signal lines and reset signal lines in the display panel. The reset signal lines include a first reset line. Both the first reset line and the data signal lines are arranged along a first direction and extend along a second direction. Furthermore, the first reset line and the data signal lines are arranged in the same layer. Under the premise of ensuring the display effect of the display panel, the number of film layers of the display panel can be reduced, the manufacturing cost and manufacturing difficulty of the display panel can be reduced, and it is beneficial to realize the thin design of the display panel.

[0070] Figure 32 This is a schematic diagram of the structure of the second type of display panel provided in an embodiment of the present invention. Figure 33 yes Figure 32 An enlarged schematic diagram of the pixel circuit group provided in the document is shown below. Figure 5 , Figure 12 , Figure 14 , Figure 21 , Figure 23 , Figure 30 , Figure 32 and Figure 33 As shown, the display panel 10 also includes a plurality of pixel circuit groups 101, each pixel circuit group 101 including two pixel circuits 100 arranged adjacent to each other along the first direction X; along the first direction X, the first reset line 221 is located between two data signal lines 210 electrically connected to the two pixel circuits 100 in the same pixel circuit group 101.

[0071] For details, please refer to Figure 32 and Figure 33 As shown, the pixel circuit group 101 includes two pixel circuits 100 arranged adjacent to each other along the first direction X. This can be understood as dividing the multiple pixel circuits 100 in the display panel 10 through the pixel circuit group 101. (Refer to...) Figure 33 The pixel circuit 100 is electrically connected to the data signal line 210. The figure shows the electrical connection between the data signal line 210 and the pixel circuit 100 by showing their overlapping. The setting position of the data signal line 210 is adjusted based on the type of pixel circuit 100, and will not be specifically explained here.

[0072] Furthermore, along the first direction X, in the pixel circuit group 101, the first reset line 221 is located between two data signal lines 210 electrically connected to the same two pixel circuits 100. It can be understood that the first reset line 221, which is in the same direction as the data signal lines 210 and the same direction of routing, is located between the two data signal lines 210. The first reset line 221 can reduce the interference of electrical signal coupling between the two data signal lines 2210, thereby ensuring the reliability of the signal transmitted from the data signal lines 210 to the pixel circuit 100, and thus ensuring the display effect of the display panel 10.

[0073] For example, refer to Figure 5 and Figure 12 The display panel 10, under this film structure, references Figure 12 As shown in region A, the first reset line 221 is located between two data signal lines 210 along the first direction X. (Reference) Figure 14 and Figure 21 The display panel 10, under this film structure, references Figure 21 As shown in region B, the first reset line 221 is located between two data signal lines 210 along the first direction X. (Reference) Figure 23 and Figure 30 ,refer to Figure 30As shown in region C or region D, the first reset line 221 is located between two data signal lines 210 along the first direction X. The display panel 10 may also have other film layer arrangements, which are not shown in detail in this embodiment. The display panel 10 provided in this embodiment, while ensuring that the first reset line 221 and the data signal lines 210 are on the same layer, reducing the film layer structure of the display panel 10, adjusts the first reset line 221 to be located between two data signal lines 210. The first reset line 221 can reduce the interference of electrical signal coupling between the two data signal lines 2210, thereby ensuring the display effect of the display panel 10.

[0074] Optional, see reference Figure 19 and Figure 28 As shown, the display panel 10 also includes a shielding structure 700. The shielding structure 700 can be located between the signal line experiencing signal transitions and the first node N1. Furthermore, the shielding structure 700 is electrically connected to a fixed potential, thus preventing other signal transitions from affecting the potential of the first node N1, ensuring the stability of the first node N1's potential, and guaranteeing the normal operation of the pixel circuit. Further, the shielding structure 700 can be located in the film layer where the top gate of the oxide transistor is located, for example, in the top gate metal layer 311. Figure 19 and Figure 28 As shown; or, the shielding structure may also be located in the capacitor substrate layer (not shown in the figure). In this embodiment of the invention, the setting of the shielding structure film layer is not limited.

[0075] Referring again to Figure 2, the reset transistor 120 includes an initial reset transistor T5 and an anode reset transistor T7; the reset signal line 220 includes an initial reset signal line Vref1 and an anode reset signal line Vref2; the pixel circuit 100 also includes a driving transistor T3, and the display panel 10 also includes a light-emitting element 400; the initial reset transistor T5 is electrically connected between the initial reset signal line Vref1 and the gate of the driving transistor T3; the anode reset transistor T7 is electrically connected between the anode reset signal line Vref2 and the light-emitting element 400.

[0076] Specifically, referring to Figure 2, the reset transistor 120 in the pixel circuit 100 includes an initial reset transistor T5 and an anode reset transistor T7. The input terminal of the initial reset transistor T5 is electrically connected to the initial reset signal line Vref1, and the output terminal is connected to the gate of the driving transistor T3. When the initial reset transistor T5 is turned on, the initial reset signal in the initial reset signal line Vref1 can reset the gate of the driving transistor T3, which can also be understood as resetting the first node N1 in Figure 2.

[0077] Furthermore, the reset transistor 120 in the pixel circuit 100 also includes an anode reset transistor T7. The input terminal of the anode reset transistor T7 is electrically connected to the anode reset signal line Vref2, and the output terminal of the anode reset transistor T7 is electrically connected to the light-emitting element 400. When the anode reset transistor T7 is turned on, the anode reset signal in the anode reset signal line Vref2 can reset the anode of the light-emitting element 400. It should be noted that in some pixel circuits 100, the initial reset signal line Vref1 can also be multiplexed as the anode reset signal line Vref2, that is, the anode reset transistor T7 and the initialization reset transistor T5 are connected to the same reset signal line.

[0078] The first reset line 221 may include at least one of the initial reset signal line Vref1 and the anode reset signal line Vref2.

[0079] The specific settings for the first reset line 221 are as follows:

[0080] Optional, refer to Figure 2. Figures 5 to 12 As shown, the initial reset signal line Vref1 includes a first initial reset line, and multiple first initial reset lines are arranged along the first direction X and extend along the second direction Y. The first reset line 221 includes the first initial reset line; and / or, the anode reset signal line Vref2 includes a first anode reset line Vref2(a), and multiple first anode reset lines Vref2(a) are arranged along the first direction X and extend along the second direction Y. The first reset line 221 includes the first anode reset line Vref2(a).

[0081] Specifically, refer to Figure 2 and Figure 5 As shown, the reset signal line 220 includes an initial reset signal line Vref1 and an anode reset signal line Vref2, combined with... Figures 5 to 12 As shown, the anode reset signal line Vref2 includes a first anode reset line Vref2(a), wherein the first anode reset line Vref2(a) is arranged along the first direction X and extends along the second direction Y. That is, the arrangement direction and extension direction of the first anode reset line Vref2(a) are the same as those of the data signal line 210. Therefore, the first reset line 221 includes the first anode reset line Vref2(a).

[0082] It should be noted that, Figures 5 to 12 In this configuration, the anode reset signal line Vref2, which is electrically connected to the anode reset transistor T7, is arranged in the form of a mesh trace. That is, a portion of the anode reset signal line Vref2 is provided in the film layer where the capacitor substrate layer 360 is located, extending along the first direction X (see reference). Figure 8 As shown), part of the anode reset signal line Vref2 is provided in the film layer where the third metal layer 351 is located, extending along the second direction Y (see reference). Figure 12(As shown). The initial reset signal line Vref1, electrically connected to the initial reset transistor T5, is only provided on the film layer where the capacitor substrate layer 360 is located, extending along the first direction X. Therefore... Figures 5 to 12 The example shown here is only the first reset line 221, which includes the first anode reset line Vref2(a).

[0083] Furthermore, setting the anode reset signal line Vref2 as a mesh trace and simultaneously setting the initial reset signal line Vref1 as a trace extending along the second direction Y is just one possible routing configuration for the reset signal line 220 in the display panel 10. Another possibility is that the initial reset signal line Vref1 is set as a mesh trace and the anode reset signal line Vref2 is also set as a trace extending along the second direction Y. In this case, the initial reset signal line Vref1 contains a first initial reset line with the same arrangement and extension direction as the data signal line 210, and the first reset line 221 includes the first initial reset line. Yet another possibility is that the anode reset signal line Vref2 is set as a mesh trace and the initial reset signal line Vref1 is also set as a mesh trace, in which case the first reset line 221 includes both the first initial reset line and the first anode reset line. This demonstrates the flexibility in configuring the first reset line 221.

[0084] Optionally, the first reset line 221 includes a first initial reset line and a first anode reset line; along the first direction X, the first initial reset line and the first anode reset line are arranged alternately.

[0085] Furthermore, when the first reset line 221 includes a first initial reset line and a first anode reset line, that is, the initial reset signal line Vref1 contains a first initial reset line with the same arrangement and extension direction as the data signal line 210, and the anode reset signal line Vref2 contains a first anode reset line with the same arrangement and extension direction as the data signal line 210. This can be understood as the initial reset signal line Vref1 being set as a mesh trace, and the anode reset signal line Vref2 also being set as a mesh trace. In this case, the first initial reset line and the first anode reset line are arranged alternately along the first direction X, which ensures the balance of the reset signal line 220 arrangement. Simultaneously, the reset signal transmission effect in the initial reset signal line Vref1 and the anode reset signal line Vref2 is balanced, which is beneficial for ensuring the display effect of the display panel 10.

[0086] Furthermore, referring to Figure 3, the reset transistor 120 also includes a bias reset transistor T8; the reset signal line 220 also includes a bias reset signal line DVH; the bias reset transistor T8 is electrically connected between the bias reset signal line 220 and the first and / or second pole of the drive transistor T3.

[0087] Specifically, referring to Figure 3, the pixel circuit 100 may further include a bias reset transistor T8. The input terminal of the bias reset transistor T8 is electrically connected to the bias reset signal line DVH, and the output terminal is connected to the driving transistor T3, thereby adjusting the bias of the driving transistor T3 to ensure its stability, and thus ensuring the working stability of the display panel 10 and its display effect. Specifically, the bias reset transistor T8 can be connected at the first terminal of the driving transistor T3 (as shown in Figure 3), i.e., the second node N2; the bias reset transistor T8 can also be connected at the second terminal of the driving transistor T3 (not specifically shown in the figure), i.e., the third node N3; the bias reset transistor T8 can also be connected at both the first and second terminals of the driving transistor T3. Based on the specific location of the output terminal of the bias reset transistor T8, it can be adaptively adjusted according to the actual bias adjustment of the driving transistor T3. This embodiment of the invention does not impose specific limitations on this.

[0088] In addition to the initial reset signal line Vref1 and the anode reset signal line Vref2 being at least one of which can be the first reset line 221, the bias reset signal line DVH mentioned in this embodiment can also be the first reset line 221.

[0089] The specific settings for the first reset line 221 can also be as follows:

[0090] Optional, refer to Figure 3. Figures 23 to 31 As shown, the bias reset signal line DVH includes a first bias reset line DVH(a), and multiple first bias reset lines DVH(a) are arranged along the first direction X and extend along the second direction Y; the first reset line 221 includes the first bias reset line DVH(a).

[0091] Specifically, referring to Figure 3, the reset signal line 220 also biases the reset signal line DVH, combined with... Figures 23 to 31 As shown, please refer to the following for details. Figure 30 As shown, the bias reset signal line DVH includes a first bias reset line DVH(a), wherein the first bias reset line DVH(a) is arranged along the first direction X and extends along the second direction Y. That is, the arrangement direction and extension direction of the first bias reset line DVH(a) are the same as those of the data signal line 210. Therefore, the first reset line 221 includes the first bias reset line DVH(a).

[0092] It should be noted that, Figures 23 to 31 In this configuration, the bias reset signal line DVH is arranged as a mesh trace, meaning that a portion of the bias reset signal line DVH extends along the first direction X in the film layer where the capacitor substrate layer 360 is located (see reference). Figure 26As shown), a partial bias reset signal line DVH is provided in the film layer where the third metal layer 351 is located, extending along the second direction Y (see reference). Figure 30 (As shown).

[0093] Furthermore, the first reset line 221 can be a portion of the initial reset signal line Vref1 and / or the anode reset signal line Vref2, or a portion of the bias reset signal line DVH, thus better reflecting the diverse configuration options of the first reset line 221.

[0094] Furthermore, refer to Figure 3. Figures 23 to 31 As shown, the initial reset signal line Vref1 includes a first initial reset line, and multiple first initial reset lines are arranged along a first direction X and extend along a second direction Y; the first reset line 221 also includes a first initial reset line; along the first direction X, the first initial reset line and the first bias reset line are arranged alternately. Alternatively, the anode reset signal line Vref2 includes a first anode reset line Vref2(a), and multiple first anode reset lines Vref2(a) are arranged along a first direction X and extend along a second direction Y; the first reset line 221 also includes a first anode reset line Vref2(a); along the first direction X, the first anode reset line Vref2(a) and the first bias reset line DVH(a) are arranged alternately. Alternatively, the initial reset signal line Vref1 includes a first initial reset line, and multiple first initial reset lines are arranged along a first direction X and extend along a second direction Y; the anode reset signal line Vref2 includes a first anode reset line, and multiple first anode reset lines are arranged along a first direction X and extend along a second direction Y; the first reset line 221 also includes a first initial reset line and a first anode reset line; the first initial reset line, the first anode reset line, and the first bias reset line are arranged along the first direction X.

[0095] Specifically, referring to Figure 3, the reset signal line 220 includes an initial reset signal line Vref1, an anode reset signal line Vref2, and a bias reset signal line DVH, combined with... Figures 23 to 31 As shown, please refer to the following for details. Figure 30 As shown, the anode reset signal line Vref2 includes a first anode reset line Vref2(a), which is arranged along the first direction X and extends along the second direction Y. That is, the arrangement direction and extension direction of the first anode reset line Vref2(a) are the same as those of the data signal line 210. Similarly, the bias reset signal line DVH includes a first bias reset line DVH(a), which is also arranged along the first direction X and extends along the second direction Y. That is, the arrangement direction and extension direction of the first bias reset line DVH(a) are also the same as those of the data signal line 210. Therefore, the first reset line 221 can include the first anode reset line Vref2(a) and the first bias reset line DVH(a). Further, refer to... Figure 30 As shown, along the first direction X, the first anode reset line Vref2(a) and the first bias reset line DVH(a) can be set alternately, that is, a first bias reset line DVH(a) is set between two adjacent first anode reset lines Vref2(a), or a first anode reset line Vref2(a) is set between two adjacent first bias reset lines DVH(a). By setting them alternately, the balanced arrangement of the traces of the display panel 10 can be ensured, and the regularity of the display panel 10 can be guaranteed.

[0096] Furthermore, the reset signal line 220 includes an initial reset signal line Vref1, an anode reset signal line Vref2, and a bias reset signal line DVH. The initial reset signal line Vref1 may include a first initial reset line, meaning it includes traces arranged along the first direction X and extending along the second direction Y. Similarly, the bias reset signal line DVH includes a first bias reset line, which is also arranged along the first direction X and extending along the second direction Y. In other words, the arrangement and extension directions of the first bias reset line are the same as those of the data signal line 210. Therefore, the first reset line 221 includes both a first initial reset line and a first bias reset line. Furthermore, along the first direction X, the first initial reset line and the first bias reset line can be alternately set, meaning a first bias reset line can be set between two adjacent first initial reset lines, or vice versa. This alternating setting ensures a balanced arrangement of the traces on the display panel 10, guaranteeing the regularity of the display panel 10.

[0097] Furthermore, the reset signal line 220 includes an initial reset signal line Vref1, an anode reset signal line Vref2, and a bias reset signal line DVH. The initial reset signal line Vref1 may include a first initial reset line, that is, the initial reset signal line Vref1 includes traces arranged along the first direction X and extending along the second direction Y. At the same time, the anode reset signal line Vref2 includes a first anode reset line, which is arranged along the first direction X and extending along the second direction Y. That is, the arrangement direction and extension direction of the first anode reset line are the same as those of the data signal line 210. At the same time, the bias reset signal line DVH includes a first bias reset line, which is also arranged along the first direction X and extending along the second direction Y. That is, the arrangement direction and extension direction of the first bias reset line are also the same as those of the data signal line 210. Therefore, the first reset line 221 includes a first initial reset line, a first anode reset line, and a first bias reset line. Furthermore, along the first direction X, the first initial reset line, the first anode reset line, and the first bias reset line DVH(a) can be alternately set. This alternation ensures a balanced arrangement of the traces on the display panel 10, guaranteeing its regularity. Furthermore, when the first reset line 221 includes the first initial reset line, the first anode reset line, and the first bias reset line, the alternating routing method is diverse. For example, if the first initial reset line is represented by "a", the first anode reset line by "b", and the first bias reset line by "c", then the arrangement of the first reset line 221 can be "abcabc...", "abcacb...", or "abcbac...", etc. Based on the specific arrangement of the first initial reset line, the first anode reset line, and the first bias reset line along the first direction X, adaptive adjustments can be made according to the actual display panel 10. This embodiment of the invention does not impose specific limitations on this.

[0098] For details, please refer to Figures 1 to 31 As shown, the reset signal line 220 also includes a second reset line 222, which extends at least partially along the first direction X, and the second reset line 222 and the first reset line 221 are disposed on different layers.

[0099] Specifically, the reset signal line 220 includes a first reset line 221 and a second reset line 222. The first reset line 221 is arranged along a first direction X and extends along a second direction Y, while the second reset line 222 is arranged along the second direction Y and extends along the first direction X. Furthermore, the first reset line 221 and the second reset line 222 are arranged on different layers, reflecting the flexible arrangement of the reset signal line 220.

[0100] For example, refer to Figures 5 to 13 As shown, please refer to the following for details. Figure 8 and Figure 12In the pixel circuit 10, the anode reset signal line Vref2 connected to the anode reset transistor T7 contains a second reset line 222 located in the film layer where the capacitor substrate layer 360 is located, and a first reset line 221 located in the film layer where the third metal layer 351 is located. Figures 5 to 13 In this embodiment, the reset signal line 220, which includes the first reset line 221 and the second reset line 222, is exemplified by the anode reset signal line Vref2. In other embodiments, the reset signal line 220, which includes the first reset line 221 and the second reset line 222, can also be the initialization reset signal line Vref1 or the bias reset signal line DVH, etc., and this embodiment of the invention does not impose specific limitations on it.

[0101] Furthermore, the first reset line 221 and the second reset line 222 included in the reset signal line 220 can be signal lines that transmit the same signal, but are located in different film layers. For example, the first reset line 221 and the second reset line 222 are respectively the traces of the anode reset signal line Vref2 in different film layers. Furthermore, the first reset line 221 and the second reset line 222 included in the reset signal line 220 can also be signal lines that transmit different signals and are located in different film layers. For example, the first reset line 221 includes the first anode reset signal line Vref2(a), and the second reset line 222 includes the bias reset signal line DVH. This further demonstrates the flexibility of the reset signal line 220 configuration.

[0102] Further reference Figures 1 to 31 As shown, the second reset line 222 includes a first reset portion 223; the first reset portion 223 extends along the first direction X, and along the first direction X, the first reset portion 223 located on the same film layer continuously penetrates the display area of ​​the display panel 10.

[0103] Specifically, the second reset line 222 includes a first reset portion 223, wherein the first reset portion 223 is continuously disposed on the same film layer and penetrates the display area of ​​the display panel 10. This can be understood as the first reset portion 223 being unbroken at its location on the film layer, and its extension length along the first direction X is equivalent to the length of the display area of ​​the display panel 10. The display area is not shown in the figure; the display area can be understood as the area where the light-emitting element 400 emits light for display.

[0104] For example, refer to Figures 5 to 13 As shown, please refer to the following for details. Figure 8 In this embodiment, the second reset line 222 may include an initialization reset signal line Vref1 and an anode reset signal line Vref2, and... Figure 8In the film layer shown, the initialization reset signal line Vref1 and the anode reset signal line Vref2 both extend along the first direction X and continuously penetrate the display area of ​​the display panel 10. Therefore, the first reset section 223 can be the initialization reset signal line Vref1 and the anode reset signal line Vref2 under this film layer.

[0105] For example, refer to Figures 14 to 31 As shown, please refer to the following for details. Figure 17 and Figure 26 In this embodiment, the second reset line 222 may include an initialization reset signal line Vref1 and a bias reset signal line DVH, and... Figure 17 and Figure 26 In the film layer, both the initialization reset signal line Vref1 and the bias reset signal line DVH extend along the first direction X and continuously penetrate the display area of ​​the display panel 10. Therefore, the first reset section 223 can be the initialization reset signal line Vref1 and the bias reset signal line DVH under this film layer. Furthermore, the reset signal line 220 is flexible and can be configured in various ways.

[0106] Continue referring to Figure 2 to Figure 31 As shown, the pixel circuit 100 includes at least one first-type transistor and at least one second-type transistor. The first-type transistor includes a first active layer 320 and a first gate M1. The second-type transistor includes a second active layer 380, a second top gate MG, and a second bottom gate MC. The first active layer 320 includes a silicon semiconductor portion, and the second active layer 380 includes an oxide semiconductor portion. The first gate is located on the side of the first active layer 320 close to the second active layer 380 or on the side of the first active layer 320 away from the second active layer 380. The second top gate MG is located on the side of the second active layer 380 away from the first active layer 320, and the second bottom gate MC is located on the side of the second active layer 380 close to the first active layer 320. The first reset portion 223 is on the same layer as at least one of the first active layer 320, the first gate M1, the second active layer 380, the second top gate MG, or the second bottom gate MC.

[0107] Specifically, the pixel circuit 100 includes a first type of transistor and a second type of transistor. The first type of transistor includes a first active layer 320, which includes a silicon semiconductor portion; therefore, the first type of transistor can be understood as a low-temperature polycrystalline silicon transistor (LTPS). The second type of transistor includes a second active layer 380, which includes an oxide semiconductor portion; therefore, the second type of transistor can be understood as an oxide transistor. Thus, the pixel circuit 100 simultaneously includes both LPS transistors and oxide transistors. Therefore, the pixel circuit 100 possesses the advantages of oxide transistors, such as low leakage current, while also possessing the advantages of LPS transistors, such as high switching speed, high carrier mobility, and low power consumption.

[0108] Furthermore, the first type of transistor includes a first active layer 320 and a first gate M1, and the second type of transistor includes a second active layer 380, a second top gate MG, and a second bottom gate MC. The first gate is located on the side of the first active layer 320 closest to the second active layer 380, the second top gate MG is located on the side of the second active layer 380 furthest from the first active layer 320, and the second bottom gate MC is located on the side of the second active layer 380 closest to the first active layer 320. Further reference. Figure 4 As shown, the first gate M1 is located on the film layer of the first metal layer 340, the second bottom gate MC is located on the film layer of the capacitor substrate layer 360, and the second top gate MG is located on the film layer of the top gate metal layer 311. In this case, the first gate is located on the side of the first active layer away from the substrate, and this first type of transistor is a top-gate transistor. Alternatively, the first gate M1 can also be located on the side of the first active layer 320 away from the second active layer 380 (not shown in the figure). In this case, the first type of transistor is a bottom-gate transistor. This embodiment of the invention does not specifically limit the specific positional relationship between the first gate and the first active layer.

[0109] Further reference Figures 5 to 31 In the pixel circuit 100 described above, the first reset portion 223 may be on the same layer as at least one of the first active layer 320, the first gate M1, the second active layer 380, the second top gate MG, or the second bottom gate MC. For example, refer to Figure 8 , Figure 17 and Figure 26 As shown, the first reset portion 223 is located in the film layer of the capacitor substrate layer 360, that is, the first reset portion 223 and the second bottom gate MC are disposed in the same layer. The film layer position of the first reset portion 223 can be adjusted according to the actual situation. The embodiments of the present invention do not impose specific limitations on this, thus demonstrating the flexibility of the setting of the first reset portion 223.

[0110] Optional, Figure 34 This is a schematic diagram of the third pixel circuit provided in an embodiment of the present invention. Figure 35 This is a schematic diagram of the film layer structure of the first pixel circuit provided in the embodiment of the present invention, for reference. Figures 5 to 31 , Figure 34 and Figure 35As shown, the pixel circuit 100 includes at least one transistor, the transistor including a silicon semiconductor layer poly; the pixel circuit 100 also includes a storage capacitor Cst, the storage capacitor Cst including a first electrode Cst1 and a second electrode Cst2 disposed opposite to each other, the second electrode Cst2 being located on the side of the first electrode Cst1 away from the silicon semiconductor layer poly; the first reset portion 223 is on the same layer as at least one of the silicon semiconductor layer poly, the first electrode Cst1 or the second electrode Cst2.

[0111] For details, please refer to Figure 34 As shown, the transistors in the pixel circuit 100 may include a silicon semiconductor layer, which can be understood as low-temperature polysilicon transistors in the pixel circuit 100. For details, refer to... Figure 35 As shown, along the direction away from the substrate, the film structure included in the pixel circuit 100 may be a substrate 600, a buffer layer 610, a silicon semiconductor layer 620, a first insulating layer 630, a first metal layer 640, an interlayer insulating layer 650, a capacitor substrate layer 660, a second insulating layer 670, a second metal layer 631, a first planarization layer 641, a third metal layer 651, a second planarization layer 661, and an anode layer 671. The pixel circuit 100 includes a storage capacitor Cst, which includes a corresponding first electrode Cst1 and a second electrode Cst2. The film layer containing the first electrode Cst1 is located within the film layer containing the first metal layer 640, and the film layer containing the second electrode Cst2 is located within the film layer containing the capacitor substrate layer 660.

[0112] Furthermore, in the pixel circuit 100 described above, the first reset portion 223 can be co-layered with at least one of the silicon semiconductor layer poly, the first electrode Cst1, or the second electrode Cst2. Thus, the first reset portion 223 can be co-layered with one of the aforementioned film layers, or with at least two of the aforementioned film layers, and can be flexibly adjusted based on the film layer position of the first reset portion 223. Moreover, when the first reset portion 223 is co-layered with at least two of the silicon semiconductor layer poly, the first electrode Cst1, or the second electrode Cst2, the first reset portion 223 disposed in each film layer can continuously penetrate the display area of ​​the display panel 10 along the first direction X. For example, the first reset portion 223 can be located in the film layer where the capacitor substrate layer 660 is located, that is, the first reset portion 223 is co-layered with the second electrode Cst2, as can be referred to... Figure 8 , Figure 17 and Figure 26 The layout shown. The position of the film layer based on the specific setting of the first reset section 223 can be adaptively adjusted according to the actual situation. This embodiment of the invention does not impose specific limitations on this, thus demonstrating the flexibility of the setting of the first reset section 223.

[0113] Continue to refer to Figure 11 As shown, the display panel 10 also includes a transition section 240, which is electrically connected to the first reset section 223 and to the reset transistor 120 and the first reset line 221, respectively; the film layer where the transition section 240 is located is located between the film layer where the first reset section 223 is located and the film layer where the first reset line 221 is located.

[0114] Specifically, the display panel 10 also includes a converter 240, which electrically connects the reset transistor 120, the first reset line 221, and the first reset section 223. This ensures the normal writing of the reset signal in the reset transistor 120 and the electrical connection of the reset signal line 220 transmitting the same signal, thereby ensuring the normal transmission of signals in the display panel 10 and thus guaranteeing the display effect of the display panel 10. The converter 240 can be understood as an "intermediate connection structure" that electrically connects the reset transistor 120, the first reset line 221, and the second reset line 222, which are located in different film layers and transmit the same signal. The anode reset signal line Vref2, the bias reset signal line DVH, or the initialization reset signal line Vref1 can all be located in two different film layers and electrically connected through the converter 240.

[0115] For example, refer to Figures 5 to 13 As shown, the anode reset signal line Vref2 includes a first reset line 221 and a second reset line 222, wherein the first reset line 221 (reference) Figure 12 ) and second reset line 222 (reference) Figure 8 The anode reset signal line Vref2 is a trace extending in different film layers, which can be routed through the adapter 240 (reference). Figure 11 This enables the anode reset transistor T7, the first reset line 221, and the second reset line 222 to be electrically connected.

[0116] For example, refer to Figures 23 to 31 As shown, the bias reset signal line DVH includes a first reset line 221 and a second reset line 222, wherein the first reset line 221 (reference) Figure 30 ) and second reset line 222 (reference) Figure 26 The bias reset signal line DVH is a trace extending in different film layers, and can be routed through the adapter 240 (reference). Figure 29 This enables the electrical connection between the first reset line 221 and the second reset line 222.

[0117] The flexibility in setting the reset signal line 220 also allows for flexibility in the signals transmitted in the first reset line 221 and the first reset section 223 connected to the adapter 240. The above examples only illustrate two cases.

[0118] Continue to refer to Figures 14 to 31 As shown, the second reset line 221 includes a second reset portion 224 and a third reset portion 225 that are disposed in different layers and electrically connected; the second reset portion 224 extends at least partially along the first direction X, the third reset portion 225 extends at least partially along the first direction X, and the second reset portion 224 and the third reset portion 225 are alternately disposed along the first direction X.

[0119] Specifically, the second reset line 222 includes a second reset section 224 and a third reset section 225. Both the second reset section 224 and the third reset section 225 extend at least partially along the first direction X. The two disparately layered trace sections extend in the same direction and are electrically connected to each other, ensuring that the second reset section 224 and the third reset section 225 transmit the same signal. Furthermore, along the first direction X, the second reset section 224 and the third reset section 225 are alternately arranged; that is, along the first direction X, the signal transmitted in the second reset line 221 is transmitted from the second reset section 224 to the third reset section 225, and then back to the second reset section 224, and so on. By implementing a layered design for the second reset line 221 through the second reset section 224 and the third reset section 225, the flexible arrangement of the second reset line 221 is further demonstrated.

[0120] For example, refer to Figures 14 to 22 As shown, please refer to the following for details. Figure 19 and Figure 20 In this embodiment, the second reset line 222 may be the anode reset signal line Vref2, which includes a second reset portion 224 (see reference). Figure 19 ) and the third reset section 225 (reference) Figure 20 The second reset portion 224 and the third reset portion 225, located in different film layers, are alternately electrically connected along the first direction X, thereby realizing the transmission of a reset signal to the anode along the first direction X. Figures 14 to 22 In this embodiment, the second reset portion 224 is placed on the film layer where the top gate metal layer 311 is located, and the third reset portion 225 is placed on the film layer where the second metal layer 331 is located. The positions of the second reset portion 224 and the third reset portion 225 can be adaptively adjusted or interchanged, and this embodiment of the invention does not impose specific limitations on this.

[0121] For example, refer to Figures 23 to 31 As shown, please refer to the following for details. Figure 28 and Figure 29 In this embodiment, the second reset line 222 is also the anode reset signal line Vref2, and the anode reset signal line Vref2 includes a second reset portion 224 (see reference). Figure 28 ) and the third reset section 225 (reference) Figure 29The second reset portion 224 and the third reset portion 225, located in different film layers, are alternately electrically connected along the first direction X, thereby realizing the signal transmission for resetting the anode along the first direction X. Figures 14 to 22 In this embodiment, the second reset portion 224 is placed on the film layer where the top gate metal layer 311 is located, and the third reset portion 225 is placed on the film layer where the second metal layer 331 is located. The positions of the second reset portion 224 and the third reset portion 225 can be adaptively adjusted or interchanged, and this embodiment of the invention does not impose specific limitations on this.

[0122] Furthermore, the above embodiment uses the anode reset signal line Vref2 as an example. The second reset line 222 is not limited to the anode reset signal line Vref2. The specific type of the second reset line 222 can be adapted to the adjustment of the film structure according to the display panel 10.

[0123] Continue referring to Figure 2 to Figure 31 As shown, the pixel circuit 100 includes at least one first-type transistor and at least one second-type transistor. The first-type transistor includes a first active layer 320 and a first gate M1. The second-type transistor includes a second active layer 380, a second top gate MG, and a second bottom gate MC. The first active layer 320 includes a silicon semiconductor portion, and the second active layer 380 includes an oxide semiconductor portion. The first gate M1 is located on the side of the first active layer 320 near the second active layer 380 or on the side of the first active layer 320 away from the second active layer 380. The second top gate MG is located on the side of the second active layer 380 away from the first active layer 320, and the second bottom gate MC is located on the side of the second active layer MG near the first active layer 320. Figures 14 to 31 As shown, the display panel 10 also includes a transition layer, which is located on the side of the second top gate MG away from the first active layer 320; the second reset portion 224 and the third reset portion 225 are on the same layer as any two of the first active layer 320, the first gate M1, the second active layer 380, the second top gate MG, the second bottom gate MC and the transition layer.

[0124] Specifically, the pixel circuit 100 includes a first type of transistor and a second type of transistor. The first type of transistor includes a first active layer 320, which includes a silicon semiconductor portion; therefore, the first type of transistor can be understood as a low-temperature polycrystalline silicon transistor (LTPS). The second type of transistor includes a second active layer 380, which includes an oxide semiconductor portion; therefore, the second type of transistor can be understood as an oxide transistor. Thus, the pixel circuit 100 simultaneously includes both LPS transistors and oxide transistors. Therefore, the pixel circuit 100 possesses the advantages of oxide transistors, such as low leakage current, while also possessing the advantages of LPS transistors, such as high switching speed, high carrier mobility, and low power consumption.

[0125] Furthermore, the first type of transistor includes a first active layer 320 and a first gate M1, and the second type of transistor includes a second active layer 380, a second top gate MG, and a second bottom gate MC. The first gate is located on the side of the first active layer 320 closest to the second active layer 380, the second top gate MG is located on the side of the second active layer 380 furthest from the first active layer 320, and the second bottom gate MC is located on the side of the second active layer 380 closest to the first active layer 320. Figure 4 As shown, the first gate M1 is located on the film layer of the first metal layer 340, the second bottom gate MC is located on the film layer of the capacitor substrate layer 360, and the second top gate MG is located on the film layer of the top gate metal layer 311. In this case, the first gate is located on the side of the first active layer away from the substrate, and this first type of transistor is a top-gate structure transistor. Alternatively, the first gate M1 can also be located on the side of the first active layer 320 away from the second active layer 380 (not specifically shown in the figure). In this case, the first type of transistor is a bottom-gate structure transistor. This embodiment of the invention does not specifically limit the specific positional relationship between the first gate and the first active layer. A transition layer is used to electrically connect the second reset section 224 and the third reset section 225. Figures 14 to 31 In this context, it can be understood that the membrane layer where the second reset portion 224 and the third reset portion 225 are electrically connected, i.e., the transition layer can be the second metal layer 331.

[0126] Furthermore, in the pixel circuit 100 described above, the second reset portion 224 and the third reset portion 225 can be co-layered with at least two of the following: the first active layer 320, the first gate M1, the second active layer 380, the second top gate MG, the second bottom gate MC, or the transition layer, i.e., the second metal layer 331. For example, the second reset portion 224 can be co-layered with one of the aforementioned film layers, and the third reset portion 225 can be co-layered with one of the aforementioned film layers; or, the second reset portion 224 can be co-layered with two or more of the aforementioned film layers, and the third reset portion 225 can be co-layered with two or more of the aforementioned film layers. Based on the specific film layer positions of the second reset portion 224 and the third reset portion 225, adaptive adjustments can be made according to actual conditions. This embodiment of the invention does not impose specific limitations on this, thus demonstrating the flexibility in the arrangement of the second reset portion 224 and the third reset portion 225.

[0127] Optional, continue to refer to Figures 5 to 31 , Figure 34 and Figure 35As shown, the pixel circuit 100 includes at least one transistor, the transistor including a silicon semiconductor layer poly; the pixel circuit 100 also includes a storage capacitor Cst, the storage capacitor Cst including a first electrode Cst1 and a second electrode Cst2 disposed opposite to each other, the second electrode Cst2 being located on the side of the first electrode Cst1 away from the silicon semiconductor layer poly; the display panel 10 also includes a transition layer, the transition layer being located on the side of the second electrode Cst2 away from the first electrode Cst1; the second reset portion 224 and the third reset portion 225 are on the same layer as any two of the silicon semiconductor layer poly, the first electrode Cst1, the second electrode Cst2 and the transition layer 241.

[0128] For details, please refer to Figure 34 As shown, the transistors in the pixel circuit 100 may include a silicon semiconductor layer, which can be understood as low-temperature polysilicon transistors in the pixel circuit 100. For details, refer to... Figure 35 As shown, along the direction away from the substrate, the film structure included in the pixel circuit 100 may be a substrate 600, a buffer layer 610, a silicon semiconductor layer 620, a first insulating layer 630, a first metal layer 640, an interlayer insulating layer 650, a capacitor substrate layer 660, a second insulating layer 670, a second metal layer 631, a first planarization layer 641, a third metal layer 651, a second planarization layer 661, and an anode layer 671. The pixel circuit 100 includes a storage capacitor Cst, which includes a corresponding first electrode Cst1 and a second electrode Cst2. The film layer containing the first electrode Cst1 is located within the film layer containing the first metal layer 640, and the film layer containing the second electrode Cst2 is located within the film layer containing the capacitor substrate layer 660. The adapter layer used to electrically connect the second reset portion 224 and the third reset portion 225 can be disposed in the film layer where the second metal layer 631 is located. The second reset portion 224 and the third reset portion 225 can be electrically connected to the second metal layer 631, i.e. the adapter layer, by drilling holes, thereby realizing the electrical connection between the second reset portion 224 and the third reset portion 225.

[0129] Furthermore, in the pixel circuit 100 described above, the second reset portion 224 and the third reset portion 225 can be on the same layer as at least two of the silicon semiconductor layer poly, the first electrode Cst1, the second electrode Cst2, and the transition layer, as can be seen from the corresponding reference. Figure 19 and Figure 20 or refer to the corresponding reference. Figure 28 and Figure 29 The film positions based on the specific configuration of the second reset portion 224 and the third reset portion 225 can be adaptively adjusted according to the actual situation. This embodiment of the invention does not impose specific limitations on this, thus demonstrating the flexibility of the configuration of the second reset portion 224 and the third reset portion 225.

[0130] Continue to refer to Figures 5 to 13 , Figures 23 to 31 As shown, the second reset line 222 is electrically connected to the first reset line 221 through a via.

[0131] Specifically, when the second reset line 222 and the first reset line 221 transmit the same signal, they can be electrically connected across different layers via vias. For example, see reference... Figures 5 to 13 As shown, the anode reset signal line Vref2 in the reset signal line 220 includes the second reset line 222 (reference). Figure 8 The middle anode reset signal line Vref2) and the first reset line 221 (reference) Figure 12 The first anode reset line 221 (Vref2(a)) and the second reset line 222 are electrically connected to the first reset line 221 via vias. For example, refer to... Figures 23 to 31 As shown, the bias reset signal line DVH in the reset signal line 220 includes the second reset line 222 (reference). Figure 26 The middle bias reset signal line DVH and the first reset line 221 (reference) Figure 30 The first bias reset line 221 (DVH(a)) and the second reset line 222 are electrically connected to the first reset line 221 through vias. The above are just two examples.

[0132] Continue to refer to Figures 14 to 31 As shown, the second reset line 222 is insulated from the first reset line 221.

[0133] Specifically, when a portion of the second reset line 222 and a portion of the first reset line 221 transmit different signals, they are insulated from each other. This ensures stable signal transmission in the display panel 10 and guarantees the display effect of the display panel 10.

[0134] For example, refer to Figures 14 to 22 As shown, in this embodiment, there is a first reset line 221, namely the first anode reset line Vref2(a), which can be referenced. Figure 21 Further, see reference Figures 17 to 21 As shown, in Figure 17 There are bias reset signal lines DVH and Vref1, which are equivalent to two different second reset lines 222. Figure 19 and Figure 20The display panel 10 contains alternating anode reset signal lines Vref2 along the first direction X, which also serve as the second reset line 222. The first reset line 221 is electrically connected only to the alternating anode reset signal lines Vref2 along the first direction X, while the first reset line 221 is insulated from the bias reset signal line DVH and the initial reset signal line Vref1. Therefore, the second reset line 222 is insulated from the first reset line 221, ensuring stable signal transmission in the display panel 10.

[0135] For example, refer to Figures 23 to 31 As shown, please refer to the following for details. Figure 30 There are two types of first reset lines 221, namely the first anode reset line Vref2(a) and the first bias reset line DVH(a), and a second reset line 222. In this embodiment, there are two types of first reset lines 221, namely the first anode reset line Vref2(a) and the first bias reset line DVH(a), which can be referred to... Figure 29 Further, see reference. Figures 26 to 29 As shown, in Figure 26 There are bias reset signal lines DVH and Vref1, which are equivalent to two different second reset lines 222. Figure 28 and Figure 29 The display panel 10 contains alternating anode reset signal lines Vref2 along the first direction X, which also serve as the second reset line 222. A portion of the first reset line 221 (transmitting the anode reset signal) is electrically connected to the alternating anode reset signal lines Vref2 along the first direction X, and a portion of the first reset line 221 (transmitting the bias reset signal) is electrically connected to the bias reset signal line DVH extending along the first direction X. Since the first reset line 221 is insulated from the initial reset signal line Vref1, the second reset line 222 is insulated from the first reset line 221, ensuring stable signal transmission in the display panel 10.

[0136] Figure 36 This is a schematic diagram of the structure of the third type of display panel provided in the embodiment of the present invention, for reference. Figures 4 to 31 and Figure 26As shown, the display panel 10 includes a display area AA and a non-display area NA that at least partially surrounds the display area AA; the non-display area NA includes a fan-out area A1 located on one side of the display area AA along the second direction Y; the display area AA includes a first display area AA1 and a second display area AA2, the second display area AA2 being located on at least one side of the first display area AA1 along the first direction X; the fan-out area A1 includes multiple fan-out traces S0, and both the first display area AA1 and the second display area AA2 have multiple data signal lines 210; the data signal lines 210 are connected to the fan-out traces S0; wherein, the data signal lines 210 of the second display area AA2 are connected to the fan-out traces S0 through connecting traces L0; the connecting traces L0 are located in the display area AA and include a first connecting segment L2 and a second connecting segment L1 that are electrically connected, the first connecting segment L2 extending along the first direction X, and the second connecting segment L1 extending along the second direction Y; the second connecting segment L1 is disposed on the same layer as the data signal lines 210.

[0137] Specifically, the display panel 10 includes a display area AA and a non-display area NA. The display area AA includes a light-emitting element (not specifically shown in the figure) and a data signal line 210 connected to the light-emitting element, etc., for realizing the display function of the display panel 10. The non-display area NA includes a display controller, such as a driver chip (not specifically shown in the figure), connected to the data signal line 210. The display controller provides display signals to the data signal line 210, thereby driving the display panel 10 to realize the display function. The non-display area NA surrounds at least a portion of the display area AA. Based on the specific locations of the display area AA and the non-display area NA, the embodiments of the present invention do not impose specific limitations.

[0138] Further reference Figure 36 As shown, the non-display area NA also includes a fan-out area A1, which includes multiple fan-out traces S0. The fan-out traces S0 are electrically connected to multiple data signal lines 210 to ensure stable transmission of data signals.

[0139] Specifically, the display area AA includes a first display area AA1 and a second display area AA2. Along the first direction X, the second display area AA2 is located on both sides of the first display area AA1, and the second display area AA2 is closer to the boundary of the display area AA than the first display area AA1. The data signal lines 210 in the first display area AA1 can be directly electrically connected to the fan-out trace S0, and the data signal lines 210 in the second display area AA2 can be electrically connected to the fan-out trace S0 through the connecting trace L0. This reduces the space occupied by the fan-out trace S0, thereby reducing the area of ​​the fan-out area A1, effectively reducing the proportion of the non-display area NA, increasing the proportion of the display area AA of the display panel 10, and improving the display effect of the display panel 10.

[0140] Specifically, the connecting trace L0 includes a first connecting segment L2 and a second connecting segment L1. The first connecting segment L2 extends along the first direction X, and the second connecting segment L1 extends along the second direction Y. The first connecting segment L2 is electrically connected to the second connecting segment L1 and the data signal line 210 in the second display area AA2, thus ensuring that the data signal line 210 in the second display area AA2 and the fan-out trace S0 are electrically connected through the connecting trace L0.

[0141] Furthermore, since the first connection segment L2 and the second connection segment L1 extend in different directions, they can be placed in different film layers and electrically connected via vias. Specifically, the second connection segment L1 can be located on the side of the first connection segment L2 away from the substrate. For example, refer to... Figure 4 As shown, the first connecting segment L2 can be located in the second metal layer 331, and the second connecting segment L1 can be located in the third metal layer 351.

[0142] In this configuration, the second connecting segment L1 is arranged along the first direction X and extends along the second direction Y. Therefore, the second connecting segment L1 and the data signal line 210 have the same arrangement and extension directions. Since the two routing methods share the same trend, they are considered to be placed in the same film layer. This eliminates the need for the original film layer containing the second connecting segment L1, allowing it to be placed on the same film layer as the data signal line 210. This reduces the number of film layers in the display panel 10. Therefore, while maintaining the display effect of the display panel 10, this reduces the manufacturing cost and difficulty of the display panel 10, simplifies the film layer structure of the display panel 10, and facilitates the thinning design of the display panel 10. For example, refer to... Figures 5 to 31 As shown, please refer to the following for details. Figure 12 , Figure 21 and Figure 30 As shown, the second connecting line segment L1 is set on the same layer as the data signal line 210.

[0143] Figure 37 yes Figure 5 The second schematic diagram of the seventh part of the structure. Figure 38 This is a schematic diagram of the structure of the fourth type of display panel provided in the embodiments of the present invention, for reference. Figures 36 to 38As shown, along the first direction X, both the first display area AA1 and the second display area AA2 include multiple pixel circuit groups 101 and multiple data signal line groups 211, with the multiple data signal line groups 211 arranged along the third direction Z. Each pixel circuit group 101 includes two adjacent pixel circuits 100 arranged along the first direction X, and each data signal line group 211 includes a first data signal line 211a and a second data signal line 211b arranged along the first direction X. Furthermore, two data signal lines 210 in the same data signal line group 211 are respectively connected to two data signal lines 210a and 211b in the same pixel circuit group 101. The pixel circuit 100 is electrically connected; the first display area AA1 also includes multiple sets of second connection segment groups L10, which are arranged along the first direction X; the second connection segment group L10 includes a second A connection segment L1a and a second B connection segment L1b arranged along the first direction X, the second A connection segment L1a is located on the side of the first data signal line 211a away from the reset signal line 220, and the second B connection segment L1b is located on the side of the second data signal line 211b away from the reset signal line 220; within a second display area AA2, along the second display... The second display area AA2 points in the direction of the first display area AA1. The second display area AA2 includes M groups of data signal lines 211. Along the direction of the display area AA2 pointing towards the fan-out area A1, 2*M first connecting segments L2 are arranged sequentially. Along the direction of the second display area AA2 pointing towards the first display area AA1, the first display area AA1 includes M groups of second connecting segments L10; M≥1 and is an integer. The first data signal line 211a in the i-th group of data signal lines 211(i) of the second display area AA2 is electrically connected to the j-th first connecting segment L2(j). A connecting line segment L2(j) is electrically connected to the second connecting line segment L1a in the kth group of the second connecting line segment group L10(k) of the first display area AA1; where i, j and k are all positive integers; the second data signal line 211b in the ith group of the data signal line group 211(i) of the second display area AA2 is electrically connected to the (j+1)th first connecting line segment L2(j+1), and the (j+1)th first connecting line segment L2(j+1) is electrically connected to the second connecting line segment L1b in the kth group of the second connecting line segment group L10(k) of the first display area AA1.

[0144] Specifically, the display panel 10 includes multiple pixel circuit groups 101 and multiple data signal line groups 211. Each pixel circuit group 101 includes two pixel circuits 100 arranged adjacent to each other along the first direction X. This can be understood as the pixel circuit groups 101 dividing the multiple pixel circuits 100 in the display panel 10. Similarly, each data signal line group 211 includes data signal lines 210 arranged along the first direction X. (Refer to...) Figure 37 and Figure 38As shown, the data signal line group 211 includes a first data signal line 211a and a second data signal line 211b arranged along the first direction X. Furthermore, two data signal lines 210 in the same data signal line group 211 are electrically connected to two pixel circuits 100 in the same pixel circuit group 101, respectively. Figure 37 As shown, the first data signal line 211a is electrically connected to the pixel circuit 100a, and the second data signal line 211b is electrically connected to the pixel circuit 100b. The first data signal line 211a and the second data signal line 211b are the same data signal line group 211, and the pixel circuit 100a and the pixel circuit 100b are the same pixel circuit group 101.

[0145] Furthermore, the display panel 10 also includes multiple groups of second connection segments L10, and the multiple second connection segments L1 are also grouped and represented. By grouping the pixel circuit 100, data signal line 210, and connection traces L, the electrical connection relationships of the traces are easier to understand. Specifically, the second connection segment group L10 includes a second A connection segment L1a and a second B connection segment L1b arranged along the first direction X, wherein reference... Figure 37 and Figure 38 As shown, the second connecting segment L1a is located on the side of the first data signal line 211a away from the reset signal line 220, and the second connecting segment L1b is located on the side of the second data signal line 211b away from the reset signal line 220. Furthermore, the arrangement of the second connecting segment L1 and the data signal line 210 can also be referenced from [the previous text]. Figure 30 As shown. Among them, Figure 37 The reset signal line 220 in the figure is the anode reset signal line Vref2. Figure 30 The reset signal line 220 consists of alternating anode reset signal line Vref2 and bias reset signal line DVH.

[0146] Furthermore, as can be seen from the accompanying drawings, for the first display area AA1, the number of data signal lines 210 and the number of second connection segments L1 are the same, that is, one data signal line 210 corresponds to one second connection segment L1, and a group of data signal lines located in the second display area AA2 transmits data signals through a group of second connection segments L1 located in the first display area AA1.

[0147] Further reference Figure 38As shown, for a single second display area AA2, M groups of data signal line groups 211 can be provided. Each M group of data signal line groups 211 includes 2*M data signal lines. These 2*M data signal lines require 2*M first connecting segments L2 to connect to 2*M second connecting segments L1 located in the first display area AA1. The aforementioned M groups of second connecting segments L10 include these 2*M second connecting segments L1. If the display area includes two second display areas AA2, and each second display area AA2 includes M groups of data signal line groups 211, then 4*M second connecting segments L1 need to be provided in the first display area AA1 to electrically connect to the 4*M data signal lines in the 2*M groups of data signal line groups 211 of the two second display areas AA2. Furthermore, the first connecting line segment L2 electrically connected to the data signal line in the second display area AA1 to the left of the first display area AA1 can be located in the same sub-pixel row as the first connecting line segment L2 electrically connected to the data signal line in the second display area AA1 to the right of the first display area AA1.

[0148] The data signal line 210 in the i-th group of data signal lines 211(i) of the second display area AA2 shown in the figure and the second connection line segment L1 in the k-th group of second connection line segments L10(k) of the first display area AA1 are electrically connected through different first connection line segments L2. Specifically, the first data signal line 211a in the i-th group of data signal lines 211(i) of the second display area AA2 is electrically connected to the j-th first connection segment L2(j), and the j-th first connection segment L2(j) is electrically connected to the second A connection segment L1a in the k-th group of second connection segments L10(k) of the first display area AA1; the second data signal line 211b in the i-th group of data signal lines 211(i) of the second display area AA2 is electrically connected to the (j+1)-th first connection segment L2(j+1), and the (j+1)-th first connection segment L2(j+1) is electrically connected to the second B connection segment L1b in the k-th group of second connection segments L10(k) of the first display area AA1. Two data signal lines in the data signal line group 211 in the second display area AA2 are electrically connected to the fan-out routing lines through the second connection segment group L10 in the first display area AA1. Here, i and k can be the same number. For example, two data signal lines in the first group of data signal lines 211 in the second display area AA2 are electrically connected to the fan-out routing line through the first group of second connecting line segments L10 in the first display area AA1. Alternatively, two data signal lines in the fifth group of data signal lines 211 in the second display area AA2 are electrically connected to the fan-out routing line through the fifth group of second connecting line segments L10 in the first display area AA1. Or, i and k can be different numbers. For example, two data signal lines in the first group of data signal lines 211 in the second display area AA2 are electrically connected to the fan-out routing line through the second group of second connecting line segments L10 in the first display area AA1. Similarly, two data signal lines in the fifth group of data signal lines 211 in the second display area AA2 are electrically connected to the fan-out routing line through the sixth group of second connecting line segments L10 in the first display area AA1. This embodiment of the invention is not entirely limited in this respect.

[0149] It should be noted that, Figure 38 Only the second display area AA2, located to one side of the first display area AA1, is shown. (See reference) Figure 37As shown, the display panel may include second display areas AA2 located on both sides of the first display area AA1. Correspondingly, the first display area AA1 includes second connecting line segment groups that are respectively connected to the data signal line groups in the second display areas AA2 on both sides. The second connecting line segment groups connecting the data signal line groups in different second display areas AA2 can be symmetrically arranged about the central axis of the first display area AA1, or about the central axis of the display panel. Here, the central axis can be understood as a central axis that passes through the center of the second display area or the display panel and extends along the second direction Y.

[0150] Figure 39 yes Figure 14 The second schematic diagram of the seventh part of the structure. Figure 40 This is a structural schematic diagram of the fifth type of display panel provided in the embodiments of the present invention, for reference. Figure 36 , Figure 39 and Figure 40 As shown, along the first direction X, both the first display area AA1 and the second display area AA2 include multiple pixel circuit groups 101 and multiple data signal line groups 211, with the multiple data signal line groups 211 arranged along the first direction X. Each pixel circuit group 101 includes two adjacent pixel circuits 100 arranged along the first direction X. Each data signal line group 211 includes a third data signal line 211c and a fourth data signal line 211d arranged along the first direction X, and two data signal lines 210 in the same data signal line group 211 are electrically connected to two pixel circuits 100 in the same pixel circuit group 101. Along the first direction X, a second connecting line segment L1 located in the first display area AA1 is located between two data signal lines 210 in the same data signal line group 211. In a second display area AA2, along the direction from the second display area AA2 to the first display area AA1, the second display area AA2 includes N groups of data signal line groups 211. A points in the direction of the fan-out area A1, and 2*N first connecting segments L2 are arranged sequentially; along the direction from the second display area AA2 to the first display area AA1, the first display area AA1 includes 2*N second connecting segments L1; N≥1 and is an integer; the third data signal line 211c in the m-th group of data signal lines 211(m) of the second display area AA2 is electrically connected to the p-th first connecting segment L2(p), and the p-th first connecting segment L2(p) is electrically connected to the (2*q-1)-th second connecting segment L1(2*q-1) of the first display area AA1; where m, p, and q are all positive integers; the fourth data signal line 211d in the m-th group of data signal lines 211(m) of the second display area AA2 is electrically connected to the (p+1)-th first connecting segment L2(p+1), and the (p+1)-th first connecting segment is electrically connected to the (2*q)-th second connecting segment L1(2*q) of the first display area AA1.

[0151] Specifically, the display panel 10 includes multiple pixel circuit groups 101 and multiple data signal line groups 211. Each pixel circuit group 101 includes two pixel circuits 100 arranged adjacent to each other along the first direction X. This can be understood as the pixel circuit groups 101 dividing the multiple pixel circuits 100 in the display panel 10. Similarly, each data signal line group 211 includes data signal lines 210 arranged along the first direction X. (Refer to...) Figure 39 and Figure 40 As shown, the data signal line group 211 includes a third data signal line 211c and a fourth data signal line 211d arranged along the first direction X. Furthermore, two data signal lines 210 in the same data signal line group 211 are electrically connected to two pixel circuits 100 in the same pixel circuit group 101, respectively. Figure 39 As shown, the third data signal line 211c is electrically connected to the pixel circuit 100c, the fourth data signal line 211d is electrically connected to the pixel circuit 100d, the first data signal line 211a and the second data signal line 211b are the same data signal line group 211, and the pixel circuit 100a and the pixel circuit 100b are the same pixel circuit group 101.

[0152] For details, please refer to Figure 39 and Figure 40 As shown, along the third direction Z, the second connecting line segment L1 located in the first display area AA1 is situated between two data signal lines 210 in the same data signal line group 211. Furthermore, referring to the accompanying drawings, it can be seen that for the first display area AA1, the number of data signal lines 210 and the number of second connecting line segments L1 are different, such as 39 and... Figure 40 The example illustrates this by setting the ratio of data signal line 210 to the number of second connecting line segment L1 to 2:1.

[0153] Further reference Figure 40As shown, for a single second display area AA2, N groups of data signal line groups 211 can be provided. Each group of N data signal line groups 211 includes 2*N data signal lines. These 2*N data signal lines require 2*N first connecting segments L2 to connect to 2*N second connecting segments L1 located in the first display area AA1. If the display area includes two second display areas AA2, and each second display area AA2 includes N groups of data signal line groups 211, then 4*N second connecting segments L1 need to be provided in the first display area AA1 to electrically connect to the 4*N data signal lines in the 2*N groups of data signal line groups 211 in the two second display areas AA2 respectively. Furthermore, the first connecting segment L2 electrically connected to the data signal lines in the second display area AA1 to the left of the first display area AA1 can be located in the same sub-pixel row as the first connecting segment L2 electrically connected to the data signal lines in the second display area AA1 to the right of the first display area AA1.

[0154] In the diagram, two data signal lines 210 in the m-th data signal line group 211(m) of the second display area AA2, namely the third data signal line 211c and the fourth data signal line 211d, are electrically connected to different second connection segments L1. Specifically, the third data signal line 211c in the m-th data signal line group 211(m) of the second display area AA2 is electrically connected to the (2*q-1)-th second connection segment L1(2*q-1) through the first connection segment L2, and the fourth data signal line 211d in the m-th data signal line group 211(m) of the second display area AA2 is electrically connected to the (2*q)-th second connection segment L1(2*q) through the first connection segment L2. Two data signal lines in the data signal line group 211 in the second display area AA2 are electrically connected to the fan-out traces through two second connection segments L1 in the first display area AA1, and these two second connection segments L1 are located between different pixel circuit groups. Here, m and q can be the same number. For example, two data signal lines in the first group of data signal lines 211 in the second display area AA2 are electrically connected to the fan-out routing line through the first second connecting line segment L1 and the second second connecting line segment L1 in the first display area AA1, respectively. Or, for example, two data signal lines in the fifth group of data signal lines 211 in the second display area AA2 are electrically connected to the fan-out routing line through the ninth second connecting line segment L1 and the tenth second connecting line segment L1 in the first display area AA1. Alternatively, m and q can be different numbers. For example, two data signal lines in the first group of data signal lines 211 in the second display area AA2 can be electrically connected to the fan-out routing line through the third and fourth second connecting segments L1 in the first display area AA1, respectively. Or, for example, two data signal lines in the fifth group of data signal lines 211 in the second display area AA2 can be electrically connected to the fan-out routing line through the eleventh and twelfth second connecting segments L1 in the first display area AA1. This embodiment of the invention is not entirely limited in this respect.

[0155] It should be noted that, Figure 40 Only the second display area AA2, located to one side of the first display area AA1, is shown. (See reference) Figure 37 As shown, the display panel may include second display areas AA2 located on both sides of the first display area AA1. Correspondingly, the first display area AA1 includes second connecting segments that are respectively connected to the data signal line groups in the second display areas AA2 on both sides. The second connecting segments connecting the data signal line groups in different second display areas AA2 may be symmetrically arranged about the central axis of the first display area AA1, or about the central axis of the display panel. Here, the central axis can be understood as a central axis that passes through the center of the second display area or the display panel and extends along the second direction Y.

[0156] Continue to refer to Figure 36 As shown, the display panel 10 also includes an auxiliary line segment L3; the auxiliary line segment L3 includes a first auxiliary line segment L31 extending along a first direction X and / or a second auxiliary line segment L32 extending along a second direction Y; the first auxiliary line segment L31 is disposed on the same layer as the first connecting line segment L2 and is insulated from the first connecting line segment L2 and the second connecting line segment L1; the second auxiliary line segment L32 is disposed on the same layer as the second connecting line segment L1 and is insulated from the first connecting line segment L2 and the second connecting line segment L1.

[0157] Furthermore, the display area AA also includes an auxiliary line segment L3, which includes a first auxiliary line segment L31 and / or a second auxiliary line segment L32 extending along the second direction Y. That is, the auxiliary line segment L3 may include only the first auxiliary line segment L31, or the auxiliary line segment L3 may include only the second auxiliary line segment L32, or the auxiliary line segment L3 may include both the first auxiliary line segment L31 and the second auxiliary line segment L32.

[0158] refer to Figure 36 As shown, both the first auxiliary segment L31 and the second auxiliary segment L32 are insulated from the connecting trace L0. By setting the auxiliary segment L3, the overall wiring arrangement can be ensured to be balanced without affecting the normal signal transmission in the connecting trace L0. For example, the first auxiliary segment L31 can be set in an area not reached by the first connecting segment L2, and the second auxiliary segment L32 can be set in an area not reached by the second connecting segment L1. That is, by setting the auxiliary segment L3, the wiring of the connecting trace L0 is balanced overall, ensuring a uniform density of wiring in different areas. This avoids uneven light reflectivity in different areas of the display panel 10 due to uneven wiring, thus preventing uneven display effects.

[0159] Optionally, the non-display area NA also includes a power bus, which includes a positive power bus and / or a negative power bus; the auxiliary line segment L3 is electrically connected to the power bus.

[0160] Furthermore, the auxiliary line segment L3 can be electrically connected to the fixed potential terminal. On the one hand, this can prevent interference to the display caused by other signals being coupled to the floating potential of the auxiliary line segment L3. On the other hand, connecting it in parallel with the fixed potential terminal can reduce the resistance on the fixed signal terminal or the fixed potential signal line, ensuring that the fixed potential signal has less loss during transmission.

[0161] Furthermore, the non-display area NA includes a power bus (not specifically shown in the figure), which includes a positive power bus (PVDD) and / or a negative power bus (PVEE). The positive power bus (PVDD) and / or the negative power bus (PVEE) are fixed signals. Both the positive power bus (PVDD) and / or the negative power bus (PVEE) can be electrically connected to the auxiliary line segment L3 to provide a fixed potential signal to the auxiliary line segment L3.

[0162] Continue referring to Figure 2 to Figure 31 As shown, the signal line 200 also includes a positive power signal line PVDD, which extends along the second direction Y, and multiple positive power signal lines PVDD are arranged along the first direction X; along the first direction X, the data signal line 210 and the first reset line 221 are located between two adjacent positive power signal lines PVDD.

[0163] Specifically, referring to Figures 2 and 3, the pixel circuit 100 is electrically connected to the positive power signal line PVDD. By transmitting the positive power signal line PVDD to the pixel circuit 100, the driving transistor T3 generates the corresponding driving current, thereby ensuring the normal display of the light-emitting element 400 in the display panel 10. For the positive power signal line PVDD in the display panel 10, refer to... Figures 5 to 31 As shown, please refer to the following for details. Figure 12 , Figure 21 and Figure 30 The positive power signal line PVDD is arranged along the first direction X and extends along the second direction Y. That is, the routing direction and arrangement direction of the positive power signal line PVDD and the data signal line 210 are the same. Optionally, in some display panels 10, the positive power signal line PVDD may also extend along the first direction X and be arranged along the second direction Y. Further details can be found by referring to... Figure 12 , Figure 21 and Figure 30 The data signal line 210 and the first reset line 221 are located between two adjacent positive power supply signal lines PVDD. Figure 12 and Figure 21 The first reset line 221 includes the anode reset signal line Vref2. The data signal line 210 and the anode reset signal line Vref2 are positioned along the first direction X between two adjacent positive power supply signal lines PVDD. (Reference) Figure 30In the circuit, the first reset line 221 includes an anode reset signal line Vref2 and a bias reset signal line DVH, and the anode reset signal line Vref2 and the bias reset signal line DVH are arranged alternately. Therefore, between two adjacent positive power supply signal lines PVDD, there is either a data signal line 210 and an anode reset signal line Vref2, or a bias reset signal line DVH and a data signal line 210. Based on the specific routing arrangement, adjustments can be made according to the actual situation.

[0164] Continue to refer to Figures 5 to 31 As shown, the positive power signal line PVDD and the data signal line 210 are arranged on the same layer.

[0165] In this configuration, the positive power signal line PVDD is arranged along the first direction X and extends along the second direction Y. The routing and arrangement directions of the positive power signal line PVDD and the data signal line 210 are also the same. Since the routing trends of the two types of lines are the same, they can be placed in the same film layer, thus reducing the number of film layers in the display panel 10. Therefore, while ensuring the display effect of the display panel 10, reducing the manufacturing cost and difficulty of the display panel 10 is beneficial for achieving a thinner design of the display panel 10.

[0166] For details, please refer to Figures 5 to 31 As shown, please refer to the following for details. Figure 13 As shown, the display panel 10 also includes a light-emitting element 400, which is electrically connected to the pixel circuit 100. The light-emitting element 400 includes a first-color light-emitting element 400a, a second-color light-emitting element 400b, and a third-color light-emitting element 400c. The first-color light-emitting element 400a, the second-color light-emitting element 400b, and the third-color light-emitting element 400c are all different from red, blue, and green light-emitting elements. Multiple first-color light-emitting elements 400a and second-color light-emitting elements 400b form a first virtual quadrilateral 21. Element 400a is located at the first vertex of the first virtual quadrilateral 21, the center of the second color light-emitting element 400b is located at the second vertex of the first virtual quadrilateral 21, the first vertex and the second vertex alternate and are spaced apart, and the third color light-emitting element 400c is located inside the first virtual quadrilateral 21; multiple third color light-emitting elements 400c form a second virtual quadrilateral 22, the centers of multiple third color light-emitting elements 400c are respectively located at the vertices of the second virtual quadrilateral, and the first color light-emitting element 400a or the second color light-emitting element 400b is located inside the second virtual quadrilateral 22.

[0167] For details, see Figure 13Multiple first-color light-emitting elements 400a and second-color light-emitting elements 400b form a first virtual quadrilateral 21. Two first-color light-emitting elements 400a are located at opposite corners of the first virtual quadrilateral 21, and two second-color light-emitting elements 400b are located at the other two opposite corners of the first virtual quadrilateral 21. A third-color light-emitting element 400c is placed at the center of the first virtual quadrilateral 21.

[0168] Furthermore, multiple third-color light-emitting elements 400c can also form a second virtual quadrilateral 22, in which either the first-color light-emitting element 400a or the second-color light-emitting element 400b is located at the center. The overall arrangement is similar to a "diamond" pixel arrangement.

[0169] Furthermore, the first color, the second color, and the third color correspond to one of red, blue, and green, respectively. Through the arrangement of the light-emitting elements 400 described above, the rendering effect of the light-emitting elements 400 can be better, further ensuring the color display effect of the display panel 10.

[0170] Continue to refer to Figure 5 , Figure 14 and Figure 23 As shown, along the thickness direction of the display panel 10, the anodes of the first color light-emitting element 400a and the second color light-emitting element 400b overlap with the data signal line 210 and the reset signal line 220.

[0171] Specifically, by adjusting the positions of the data signal line 210 and the reset signal line 220 along the thickness direction of the display panel 10, it is ensured that the anodes of the first color light-emitting element 400a and the second color light-emitting element 400b overlap with the signal line 200. This increases the coverage area of ​​the anodes on a portion of the data signal line 210 and the reset signal line 220, meaning that more areas of the data signal line 210 and the reset signal line 220 are placed within the coverage area of ​​the anode. This ensures that the degree to which the entire area of ​​the anode is supported by the metal traces is similar, thereby preventing color shift or dispersion in the display panel and ensuring the display effect. Furthermore, the overlap between the anode and the signal line 200 reduces the obstruction of light transmission by the signal line 200, which helps improve the transmittance of the display panel 10 and ensures the display effect.

[0172] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 41 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention, such as... Figure 41As shown, the display device 1 includes the display panel 10 described in any of the above embodiments. Therefore, the display device 1 provided in this embodiment of the invention possesses the corresponding beneficial effects described in the above embodiments, which will not be repeated here. For example, the display device 1 can be an electronic device such as a mobile phone, computer, smart wearable device (e.g., smartwatch), and in-vehicle display device, and this embodiment of the invention does not limit it.

[0173] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that, Includes pixel circuitry and signal lines; The pixel circuit includes a data writing transistor and a reset transistor; the signal line includes a data signal line and a reset signal line, the data signal line is electrically connected to the first terminal of the data writing transistor, and the reset signal line is electrically connected to the first terminal of the reset transistor. The plurality of data signal lines are arranged along a first direction and extend along a second direction, the first direction and the second direction intersecting; the reset signal line includes a first reset line, and the plurality of the first reset lines are arranged along the first direction and extend along the second direction; The first reset line is disposed on the same layer as the data signal line; The reset signal line further includes a second reset line, which extends at least partially along the first direction, and the second reset line is disposed in a different layer from the first reset line. The second reset line includes a second reset section and a third reset section that are disposed in different layers and electrically connected; The second reset portion extends at least partially along the first direction, and the third reset portion extends at least partially along the first direction, and the second reset portion and the third reset portion are alternately arranged along the first direction; The pixel circuit includes at least one transistor, the transistor including a silicon semiconductor layer; The pixel circuit also includes a storage capacitor, which includes a first electrode plate and a second electrode plate disposed opposite to each other, with the second electrode plate located on the side of the first electrode plate away from the silicon semiconductor layer. The display panel further includes a transition layer, which is located on the side of the second electrode plate away from the first electrode plate; The second reset portion and the third reset portion are on the same layer as any two of the silicon semiconductor layer, the first electrode plate, the second electrode plate, and the transition layer; or, The pixel circuit includes at least one first-type transistor and at least one second-type transistor. The first-type transistor includes a first active layer and a first gate. The second-type transistor includes a second active layer, a second top gate, and a second bottom gate. The first active layer includes a silicon semiconductor portion, and the second active layer includes an oxide semiconductor portion. The first gate is located on the side of the first active layer close to the second active layer or on the side of the first active layer away from the second active layer. The second top gate is located on the side of the second active layer away from the first active layer, and the second bottom gate is located on the side of the second active layer close to the first active layer. The display panel further includes a transition layer, which is located on the side of the second top gate away from the first active layer; The second reset portion and the third reset portion are on the same layer as any two of the first active layer, the first gate, the second active layer, the second top gate, the second bottom gate, and the transition layer.

2. The display panel according to claim 1, characterized in that, The display panel further includes a plurality of pixel circuit groups, and the pixel circuit group includes two pixel circuits arranged adjacent to each other along the first direction; Along the first direction, the first reset line is located between the two data signal lines electrically connected to two pixel circuits in the same pixel circuit group.

3. The display panel according to claim 1, characterized in that, The reset transistor includes an initial reset transistor and an anode reset transistor; The reset signal line includes an initial reset signal line and an anode reset signal line; The pixel circuit further includes a driving transistor, and the display panel further includes a light-emitting element; The initial reset transistor is electrically connected between the initial reset signal line and the gate of the driving transistor; the anode reset transistor is electrically connected between the anode reset signal line and the light-emitting element.

4. The display panel according to claim 3, characterized in that, The initial reset signal line includes a first initial reset line, and a plurality of the first initial reset lines are arranged along the first direction and extend along the second direction, wherein the first reset line includes the first initial reset line; And / or, The anode reset signal line includes a first anode reset line, and multiple first anode reset lines are arranged along the first direction and extend along the second direction. The first reset line includes the first anode reset line.

5. The display panel according to claim 4, characterized in that, The first reset line includes the first initial reset line and the first anode reset line; Along the first direction, the first initial reset line and the first anode reset line are arranged alternately.

6. The display panel according to claim 3, characterized in that, The reset transistor also includes a bias reset transistor; The reset signal line also includes a bias reset signal line; The bias reset transistor is electrically connected between the bias reset signal line and the first and / or second pole of the drive transistor.

7. The display panel according to claim 6, characterized in that, The bias reset signal line includes a first bias reset line, and multiple first bias reset lines are arranged along the first direction and extend along the second direction; The first reset line includes the first bias reset line.

8. The display panel according to claim 7, characterized in that, The initial reset signal line includes a first initial reset line, and a plurality of the first initial reset lines are arranged along the first direction and extend along the second direction; the first reset line further includes the first initial reset line; along the first direction, the first initial reset line and the first bias reset line are arranged alternately. or, The anode reset signal line includes a first anode reset line, and multiple first anode reset lines are arranged along the first direction and extend along the second direction. The first reset line also includes the first anode reset line. Along the first direction, the first anode reset line and the first bias reset line are arranged alternately. or, The initial reset signal line includes a first initial reset line, and multiple first initial reset lines are arranged along the first direction and extend along the second direction; the anode reset signal line includes a first anode reset line, and multiple first anode reset lines are arranged along the first direction and extend along the second direction; the first reset line further includes the first initial reset line and the first anode reset line; the first initial reset line, the first anode reset line, and the first bias reset line are arranged along the first direction.

9. The display panel according to claim 1, characterized in that, The second reset line includes a first reset portion; The first reset portion extends along the first direction, and along the first direction, the first reset portion located on the same film layer continuously penetrates the display area of ​​the display panel.

10. The display panel according to claim 9, characterized in that, The pixel circuit includes at least one transistor, the transistor including a silicon semiconductor layer; The pixel circuit also includes a storage capacitor, which includes a first electrode plate and a second electrode plate disposed opposite to each other, with the second electrode plate located on the side of the first electrode plate away from the silicon semiconductor layer. The first reset portion is on the same layer as at least one of the silicon semiconductor layer, the first electrode, or the second electrode.

11. The display panel according to claim 9, characterized in that, The pixel circuit includes at least one first-type transistor and at least one second-type transistor. The first-type transistor includes a first active layer and a first gate. The second-type transistor includes a second active layer, a second top gate, and a second bottom gate. The first active layer includes a silicon semiconductor portion, and the second active layer includes an oxide semiconductor portion. The first gate is located on the side of the first active layer close to the second active layer or on the side of the first active layer away from the second active layer. The second top gate is located on the side of the second active layer away from the first active layer, and the second bottom gate is located on the side of the second active layer close to the first active layer. The first reset portion is on the same layer as at least one of the first active layer, the first gate, the second active layer, the second top gate, or the second bottom gate.

12. The display panel according to claim 9, characterized in that, The display panel further includes an adapter, which is electrically connected to the first reset section and electrically connected to the reset transistor and the first reset line, respectively. The membrane layer where the adapter is located is situated between the membrane layer where the first reset section is located and the membrane layer where the first reset line is located.

13. The display panel according to claim 1, characterized in that, The second reset line is electrically connected to the first reset line via a via.

14. The display panel according to claim 1, characterized in that, The second reset line is insulated from the first reset line.

15. The display panel according to claim 1, characterized in that, The display panel includes a display area and a non-display area that at least partially surrounds the display area; The non-display area includes a fan-out area located on one side of the display area along the second direction; the display area includes a first display area and a second display area, wherein the second display area is located on at least one side of the first display area along the first direction. The fan-out area includes multiple fan-out traces, and both the first display area and the second display area include multiple data signal lines; The data signal line is connected to the fan-out trace; wherein, the data signal line of the second display area is connected to the fan-out trace via a connecting trace; The connection trace is located in the display area and includes a first connection segment and a second connection segment that are electrically connected. The first connection segment extends along the first direction, and the second connection segment extends along the second direction. The second connecting line segment is arranged on the same layer as the data signal line.

16. The display panel according to claim 15, characterized in that, Along the first direction, both the first display area and the second display area include multiple pixel circuit groups and multiple data signal line groups, with the multiple data signal line groups arranged along the first direction; each pixel circuit group includes two pixel circuits arranged adjacent to each other along the first direction, and each data signal line group includes a first data signal line and a second data signal line arranged along the first direction, with two data signal lines in the same data signal line group being electrically connected to two pixel circuits in the same pixel circuit group respectively; The first display area further includes multiple sets of second connection segment groups, which are arranged along the first direction; the second connection segment group includes a second A connection segment and a second B connection segment arranged along the first direction, the second A connection segment is located on the side of the first data signal line away from the reset signal line, and the second B connection segment is located on the side of the second data signal line away from the reset signal line. Within a second display area, along the direction from the second display area to the first display area, the second display area includes M groups of data signal lines; along the direction from the display area to the fan-out area, 2*M first connection segments are arranged sequentially; along the direction from the second display area to the first display area, the first display area includes M groups of second connection segments; M≥1 and is an integer; The first data signal line in the i-th group of data signal lines in the second display area is electrically connected to the j-th first connection line segment, and the j-th first connection line segment is electrically connected to the second A connection line segment in the k-th group of second connection line segments in the first display area; wherein i, j, and k are all positive integers; The second data signal line in the i-th group of data signal lines in the second display area is electrically connected to the (j+1)-th first connection line segment, and the (j+1)-th first connection line segment is electrically connected to the second B connection line segment in the k-th group of the second connection line segments in the first display area.

17. The display panel according to claim 15, characterized in that, Along the first direction, both the first display area and the second display area include multiple pixel circuit groups and multiple data signal line groups, with the multiple data signal line groups arranged along the first direction; each pixel circuit group includes two pixel circuits arranged adjacent to each other along the first direction, and each data signal line group includes a third data signal line and a fourth data signal line arranged along the first direction, with two data signal lines in the same data signal line group being electrically connected to two pixel circuits in the same pixel circuit group respectively; Along the first direction, the second connecting line segment located in the first display area is located between two data signal lines in the same data signal line group; Within a second display area, along the direction from the second display area to the first display area, the second display area includes N groups of data signal lines; along the direction from the display area to the fan-out area, 2*N first connecting segments are arranged sequentially; along the direction from the second display area to the first display area, the first display area includes 2N second connecting segments; N≥1 and is an integer; The third data signal line in the m-th group of data signal lines in the second display area is electrically connected to the p-th first connection line segment, and the p-th first connection line segment is electrically connected to the (2*q-1)-th second connection line segment in the first display area; where m, p, and q are all positive integers; The fourth data signal line in the m-th group of data signal lines in the second display area is electrically connected to the (p+1)-th first connection line segment, and the (p+1)-th first connection line segment is electrically connected to the (2*q)-th second connection line segment in the first display area.

18. The display panel according to claim 15, characterized in that, The display panel also includes auxiliary line segments; The auxiliary line segment includes a first auxiliary line segment extending along the first direction and / or a second auxiliary line segment extending along the second direction; The first auxiliary line segment is disposed on the same layer as the first connecting line segment and is insulated from the first connecting line segment and the second connecting line segment; the second auxiliary line segment is disposed on the same layer as the second connecting line segment and is insulated from the first connecting line segment and the second connecting line segment.

19. The display panel according to claim 18, characterized in that, The non-display area also includes a power bus, which includes a positive power bus and / or a negative power bus. The auxiliary line segment is electrically connected to the power bus.

20. The display panel according to claim 1, characterized in that, The signal line also includes a positive power signal line, which extends along the second direction, and a plurality of the positive power signal lines are arranged along the first direction; Along the first direction, the data signal line and the first reset line are located between two adjacent positive power signal lines.

21. The display panel according to claim 20, characterized in that, The positive power signal line is arranged on the same layer as the data signal line.

22. The display panel according to claim 1, characterized in that, The display panel further includes a light-emitting element, which is electrically connected to the pixel circuit. The light-emitting element includes a first color light-emitting element, a second color light-emitting element, and a third color light-emitting element, wherein the first color light-emitting element, the second color light-emitting element, and the third color light-emitting element are one of red light-emitting element, blue light-emitting element, and green light-emitting element, and each is different; Multiple first-color light-emitting elements and second-color light-emitting elements constitute a first virtual quadrilateral. The first-color light-emitting elements are located at the first vertex of the first virtual quadrilateral, and the center of the second-color light-emitting elements is located at the second vertex of the first virtual quadrilateral. The first vertex and the second vertex alternate and are spaced apart, and the third-color light-emitting element is located inside the first virtual quadrilateral. The plurality of third-color light-emitting elements form a second virtual quadrilateral, with the centers of the plurality of third-color light-emitting elements respectively located at the vertices of the second virtual quadrilateral, and the first-color light-emitting element or the second-color light-emitting element located inside the second virtual quadrilateral.

23. The display panel according to claim 22, characterized in that, Along the thickness direction of the display panel, the anodes of the first color light-emitting element and the second color light-emitting element overlap with the data signal line and the reset signal line.

24. A display device, characterized in that, Includes the display panel as described in any one of claims 1-23.

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