Chip fault location method and system

Abstract

The present invention provides a method and system for locating a core fault, the method comprising: constructing a fault detection model based on the core historical operation data, and pre-training the model; when a chip fails, obtaining all core operation data; defining a queue, arbitrarily selecting a core, and placing the core into the queue; taking a core out of the queue, obtaining its data, marking it as accessed, and making a judgment based on a pre-trained fault detection model; registering if a fault occurs; obtaining the adjacent core of the core in the access queue, and placing it into the queue; judging whether the current queue is empty; and obtaining the marked fault core. The present invention solves the technical problems of low fault location accuracy, low location efficiency, high fault detection cost, and few applicable scenarios.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testing, and in particular to a method and system for locating a core fault. Background Art

[0002] As the size of semiconductor processes gradually approaches the physical limit, the performance and area of ​​chips are getting smaller and smaller with the progress of process technology, and semiconductor technology has entered the "post-Moore era". Chiplet technology came into being. Chiplets refer to pre-manufactured chips (die) with specific functions that can be combined and integrated. Integrated chips are chiplets manufactured with specific functions that are integrated into chips through semiconductor integration technology according to application requirements. The emergence of chiplets has brought greater flexibility and customization possibilities to integrated circuit design.

[0003] However, as the development of chiplet technology increases, its complexity continues to increase, and chiplet technology also brings new challenges. After packaging, one or more chiplets may fail due to interconnection problems or long-term operation loss. Existing technologies often obtain the interconnection relationship of chiplets based on the working mode to determine the detection point for detection; or group the chiplets of integrated chips and make judgments based on the fault index.

[0004] How to quickly and accurately locate the faulty core particle is our current urgent and in-depth research direction.

[0005] In current chip fault diagnosis, it is often difficult to determine the root cause of the problem due to the complex interconnection and communication of multiple chiplets. Traditional fault diagnosis methods may take a lot of time to determine the exact location of the fault and require expensive equipment or expertise, thereby increasing the cost of system maintenance and repair.

[0006] The existing technology obtains the correlation relationship of the core particles based on the working mode, determines the detection points to judge and locate the faulty core particles, and the operation is relatively complicated and takes a lot of time. Judgment based on the fault index may involve subjective judgment and setting thresholds, which will cause different users to obtain inconsistent fault indices in different situations, lack objectivity, and may not cover all fault types, resulting in inaccurate judgment.

[0007] The existing invention patent application document "Digital Microfluidic Chip Fault Detection Method and System Based on Improved Particle Swarm Algorithm" with publication number CN106886843A, the existing method includes: obtaining the starting position and end position of the test droplet; constructing a taboo table; constructing at least one particle swarm, and constructing a position matrix corresponding to each particle swarm; determining the velocity vector of each particle in the particle swarm algorithm until all adjacent electrodes are traversed; updating the particle position sequence according to the formula; calculating the fitness of the position vector of each particle, and determining the current shortest path of each population and the global shortest path respectively; repeating the above steps until a predetermined number of iterations is reached, and outputting the global shortest path to perform fault detection on the digital microfluidic chip. However, the above-mentioned prior art is mainly aimed at the fault detection of digital microfluidic chips, and uses the improved particle swarm algorithm to optimize the droplet movement path in the chip so as to quickly and accurately locate the fault. It focuses on the technology of updating the particle position sequence through PSO, which is suitable for operating droplet microfluidic chips, and mainly involves the motion control and path optimization of droplets on the electrode array.

[0008] The existing invention patent application document "A method and device for fault detection of a multi-chip chip" with publication number CN116340072A, the existing method includes: obtaining the operating data of the target multi-chip chip; parsing the operating data to determine the association relationship between the core particles in the target multi-chip chip; wherein the association relationship is used to characterize the communication connection relationship between the core particles; according to each association relationship, determining the site to be detected located on the core particle; based on a pre-trained fault detection model, performing fault detection on each site to be detected according to the operating data to obtain a fault detection result. Among them, S1: determine the scale, dimension, preset number of iterations, position and speed of the particle swarm, initialize the position and speed of the particle swarm; S2: construct a deep belief network, initialize the weights and network hidden node values ​​of the deep belief network according to the particle swarm, obtain the initialized deep belief network, and use the initialized deep belief network as the current deep belief network to execute step S3; S3: according to the current deep belief network, iterate using the particle swarm optimization algorithm to obtain the current optimal solution; S4: use the current optimal solution as the initial point to obtain the position and speed of the current optimal solution; S5: according to the position and speed of the current optimal solution, use the conjugate gradient to update the speed of the current optimal solution to obtain the global optimal solution; S6: according to the global optimal solution, update the position, speed of the particle swarm, the weights and network hidden node values ​​of the deep belief network to obtain a new deep belief network; judge whether the current number of iterations is less than the preset number of iterations; if so, return the new deep belief network as the current deep belief network to step S3; otherwise, output the new deep belief network as the optimized deep belief network. From the above specific implementation scheme of the prior art, it can be seen that the concept of association relationship is introduced to characterize the communication connection between core particles, and these relationships are used to determine the detection site. The deep belief network DBN is optimized using the particle swarm optimization algorithm, and the conjugate gradient method is used to further optimize the search effect of the particle swarm to establish an optimized fault detection model.

[0009] Since the failure mode of a chip can be very complex and involve multiple physical and logical factors, traditional PSO or BFS algorithms require a lot of customization for specific failure types and chip architectures. At the same time, combining these two algorithms requires a deep understanding of the inherent mechanisms of chip failures and how to effectively map these mechanisms through algorithms. In the traditional PSO algorithm, the position and velocity of each particle are updated based on its own experience and group experience.

[0010] In summary, the above-mentioned existing technologies have technical problems such as low fault location accuracy, low location efficiency, high fault detection cost and few applicable scenarios. Summary of the invention

[0011] The technical problem to be solved by the present invention is: how to solve the technical problems in the prior art of low fault location accuracy, low location efficiency, high fault detection cost and few applicable scenarios.

[0012] The present invention adopts the following technical solutions to solve the above technical problems: the chip fault location method includes:

[0013] S1. Obtain and build a fault detection model based on the historical operation data of the chip, and pre-train the fault detection model to obtain an applicable fault detection model;

[0014] S2. When it is determined that a chip fails, obtain the operation data of all chips;

[0015] S3. Define a queue, select a core particle at random, and put the core particle into the queue;

[0016] S4, taking out a chip from the queue, obtaining the operation data of the chip, marking the current chip as a selected chip, and performing fault determination based on an applicable fault detection model; when a chip fails, performing a fault marking operation;

[0017] S5, access the adjacent core particles of the selected core particle, and put the adjacent core particles into the queue;

[0018] S6, loop through steps S4 to S5 until the queue is empty;

[0019] S7. Acquire the selected core particles to obtain the faulty core particles.

[0020] The present invention performs core particle fault detection based on the graph breadth first search algorithm (BFS) and particle swarm optimization (PSO). All interconnected core particles in the integrated chip are quickly traversed by BFS, and fault diagnosis is performed by a fault diagnosis model based on PSO to quickly and accurately locate the faulty core particles. PSO can dynamically adjust parameters according to feedback information from the search process to adapt to different fault diagnosis scenarios, and can be applied to diagnostic problems of different types and scales.

[0021] Specifically, the present invention utilizes breadth-first search BFS to quickly traverse all cores in the integrated circuit. This method has low time complexity, is simple to implement, and helps to quickly locate the area where the fault occurs.

[0022] In a more specific technical solution, S1 includes:

[0023] S11, extracting data features from the core particle historical operation data and performing normalization processing;

[0024] S12, establish a BP neural network model, determine the topological structure of the BP neural network model, and define a fitness function suitable for PSO;

[0025] S13, randomly generate a group of particles, set the maximum number of iterations, and update the position and velocity of each particle in each iteration;

[0026] S14. Based on the historical operation data, pre-training operation is performed on the BP neural network model to obtain a suitable fault detection model.

[0027] The present invention uses historical data to pre-train the fault detection model through model pre-training, thereby improving the prediction accuracy and response speed of the model, reducing the demand for real-time calculation, and thus reducing the detection cost.

[0028] In a more specific technical solution, in S11, the historical operation data of the core particles are used to construct a historical operation data set of multiple core particles.

[0029] In a more specific technical solution, in S13, the particle update operation includes: PSO particle swarm optimization algorithm.

[0030] Specifically, during the initialization process, the position of each particle corresponds to a specific set of neural network weights and biases, and the velocity of each particle is initialized to a small random vector representing the rate of change of each parameter;

[0031] In a more specific technical solution, the update rules involved in the particle update operation include but are not limited to:

[0032] Velocity Update: The velocity of each particle is updated according to the following formula:

[0033] v i (t+1)=w·v i (t)+c1·r1·(P best,i -x i (t))+c2·r2·(g best -x i (t))

[0034] Among them, v i is the particle's velocity in time, x i is the current position, P best,i is the optimal individual position of the particle, g best is the global optimal position, w is the inertia weight, c1 and c2 are learning factors, and r1 and r2 are random numbers in the interval [0,1].

[0035] Location Updates:

[0036] x i (t+1)=x i (t)+vi (t+1)

[0037] Specifically, the setting of the inertia weight w enables the algorithm to effectively balance the global and progressive search. By adjusting the learning factors c1 and c2, the particle swarm algorithm can better find a balance between individual experience and group experience, which helps to effectively find the optimal solution in the solution space.

[0038] The present invention utilizes particle swarm optimization (PSO) combined with deep belief network (DBN), and uses PSO optimization algorithm to adjust network parameters to adapt to different fault detection scenarios. It can dynamically adjust the detection strategy according to the operation data, thus increasing the accuracy and adaptability of fault detection.

[0039] In a more specific technical solution, in S3, interconnection operations are performed with core particles as vertices to obtain an undirected graph.

[0040] In a more specific technical solution, the edges between vertices are used to represent the interconnection relationship between the core particles.

[0041] In a more specific technical solution, in S3, a queue is defined to store the core particles to be accessed.

[0042] In a more specific technical solution, S5 includes:

[0043] S51, using the selected core particle as the starting point, performing a breadth-first traversal on the undirected graph, visiting the adjacent vertices corresponding to the adjacent core particles, and marking the adjacent vertices as visited vertices;

[0044] S52. Add the visited vertices to the queue.

[0045] The present invention aims at locating core particle faults, introduces BFS and PSO to quickly locate faulty core particles, and the detection involves updating of particle position and velocity, and also includes a model based on a deep belief network DBN.

[0046] The time complexity of the BFS used in the present invention is O(|V|+|E|), which is fast and easy to implement. In short, compared with traditional detection, the test efficiency can be improved and the test cost can be reduced.

[0047] In a more specific technical solution, the chip fault location system includes:

[0048] A pre-training module is used to acquire and construct a fault detection model based on the historical operation data of the core particle, and to pre-train the fault detection model to obtain an applicable fault detection model;

[0049] A faulty chip operation data acquisition module is used to acquire all chip operation data when determining that a chip fails. The faulty chip operation data acquisition module is connected to the pre-training module.

[0050] The chip queue module is used to define a queue, select a chip at random, and put the chip into the queue. The chip queue module is connected to the fault chip operation data acquisition module;

[0051] The chip traversal marking module is used to take out a chip from the queue, obtain the operation data of the chip, mark the current chip as a selected chip, and perform fault determination based on the applicable fault detection model; when a chip fails, a fault marking operation is performed, and the chip traversal marking module is connected to the chip entry queue module;

[0052] The adjacent core grain queue module is used to access the adjacent core grains of the selected core grain and put the adjacent core grains into the queue. The adjacent core grain queue module is connected to the core grain traversal marking module;

[0053] A loop module, used for looping step S4 to step S5 until the queue is empty, the loop module is connected to the adjacent core particle queue module;

[0054] The faulty core particle acquisition module is used to acquire the selected core particles to obtain the faulty core particles. The faulty core particle acquisition module is connected to the circulation module.

[0055] Compared with the prior art, the present invention has the following advantages:

[0056] The present invention performs core fault detection based on the breadth-first search algorithm (BFS) and particle swarm optimization (PSO) of the graph. All interconnected cores in the integrated chip are quickly traversed by BFS, and fault diagnosis is performed by a fault diagnosis model based on PSO to quickly and accurately locate the faulty core. PSO can dynamically adjust parameters according to feedback information from the search process, adapt to different fault diagnosis scenarios, and can be applied to diagnostic problems of different types and scales.

[0057] The time complexity of the BFS used in the present invention is O(|V|+|E|), which is fast and easy to implement. In short, compared with traditional detection, the test efficiency can be improved and the test cost can be reduced.

[0058] The present invention improves the particle update strategy to adapt to the characteristics of the core particle fault model, such as introducing the parameters of the deep belief network (DBN) as a part of the PSO. Such integration can help to more accurately adjust and optimize the network weights and the values ​​of hidden nodes.

[0059] The specific formula used in the present invention involves the adjustment of the speed and position update formula in the PSO to adapt to the characteristics of the complex interconnection between core particles.

[0060] In the present invention, BFS is used to quickly traverse the core particle network structure, identify and mark the faulty core particles. This method can quickly locate and isolate the fault area, reduce the fault diagnosis time, and can also give priority to traversing those fault areas or core particles that have high probability of being traversed according to historical data, or dynamically adjust the traversal priority during the traversal process.

[0061] The present invention solves the technical problems existing in the prior art of low fault location accuracy, low location efficiency, high fault detection cost and few applicable scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1 This is a schematic diagram of the basic steps of the method for locating a core fault according to Embodiment 1 of the present invention;

[0063] Figure 2 This is a schematic diagram of specific steps for constructing and training a fault detection model in Example 1 of the present invention;

[0064] Figure 3 This is a schematic diagram of the core particle interconnection principle of Example 1 of the present invention;

[0065] Figure 4 This is a schematic diagram of vertices joining a queue in Embodiment 1 of the present invention;

[0066] Figure 5 This is a schematic diagram of vertex selection in Example 1 of the present invention;

[0067] Figure 6a and Figure 6b This is a screenshot of the experimental result data of Example 1 of the present invention. DETAILED DESCRIPTION

[0068] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in combination with the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0069] Example 1

[0070] like Figure 1 As shown, the chip fault location method provided by the present invention also includes the following basic steps:

[0071] S1. Build a fault detection model based on the historical operation data of the chiplet and perform model pre-training;

[0072] like Figure 2 As shown, in this embodiment, step S1 of constructing and training the fault detection model also includes the following specific steps:

[0073] S11, obtaining a historical operation data set of a multi-core chip, extracting data features, and performing normalization processing;

[0074] S12, establish a BP neural network model, determine its topological structure, and define a fitness function suitable for PSO;

[0075] S13, randomly generate a group of particles, set the maximum number of iterations, and update the position and velocity of each particle through PSO in each iteration;

[0076] S14, using BP neural network to train based on historical data;

[0077] S2. When a chip fails, obtain all chip operation data;

[0078] S3. Define a queue, select a core particle at random, and put the core particle into the queue;

[0079] like Figure 3 As shown, in this embodiment, the interconnection of the core particles is regarded as an undirected graph, the circles in the undirected graph represent the vertices of the graph, which represent the core particles in the present invention, and the edges between the vertices represent the interconnection relationship of the core particles; a queue is defined for storing the accessed core particles, wherein the queue has a first-in-first-out characteristic;

[0080] S4. Take a chip from the queue, obtain its data, mark it as accessed, and make a judgment based on the pre-trained fault detection model; if it is a fault, register it;

[0081] In this embodiment, a vertex is taken out from the queue, its current running data is obtained, and a determination is made based on the fault detection model whether the core particle is faulty, and if so, a mark is made;

[0082] S5, access the adjacent coreparticles of the coreparticle in the queue and put them into the queue;

[0083] like Figure 4 As shown, in this embodiment, a core particle is randomly selected as the starting point of the breadth-first traversal of the graph, the vertex is visited, marked as visited, and added to the queue;

[0084] In this embodiment, all unvisited adjacent vertices of the retrieved vertex are visited, these adjacent vertices are marked as visited, and are added to the queue.

[0085] like Figure 5 As shown, in this embodiment, the first vertex 1 is taken out, and its adjacent vertices, namely the second vertex 2, the third vertex 3, the fourth vertex 4 and the fifth vertex 5, are visited.

[0086] S6, determine whether the current queue is empty;

[0087] In this embodiment, the aforementioned steps S4 to S5 are repeatedly executed until the queue is empty.

[0088] S7. Obtain the marked faulty core particle.

[0089] like Figure 6a and Figure 6b As shown, the experimental result data obtained by the experiment in this embodiment.

[0090] In the actual scenario of this embodiment, the present invention can improve the speed and accuracy of fault location.

[0091] Specifically, the present invention extracts key performance indicators and operating parameters from the core particle historical operating data, performs normalization processing, and ensures the consistency and accuracy of the data input model.

[0092] When a chip fails, the operating data of all related cores are collected in real time as input to the fault detection model. The data flow is managed through a queue system to ensure fast data processing and real-time fault determination.

[0093] In this embodiment, the BFS algorithm is used to quickly traverse all interconnected core particles in the chip, and the fault detection model optimized by PSO is combined to determine the fault of each core particle. According to the feedback results of the model, the search and diagnosis strategy is dynamically adjusted to accurately locate the faulty core particle.

[0094] In summary, the present invention performs core fault detection based on the breadth-first search algorithm (BFS) and particle swarm optimization (PSO) of the graph. All interconnected cores in the integrated chip are quickly traversed by BFS, and fault diagnosis is performed by the fault diagnosis model based on PSO to quickly and accurately locate the faulty core. PSO can dynamically adjust parameters according to the feedback information of the search process, adapt to different fault diagnosis scenarios, and can be applied to diagnosis problems of different types and scales.

[0095] The time complexity of the BFS used in the present invention is O(|V|+|E|), which is fast and easy to implement. In short, compared with traditional detection, the test efficiency can be improved and the test cost can be reduced.

[0096] In terms of improving the speed and accuracy of fault location, the present invention quickly locates possible fault areas through BFS and optimizes the fault diagnosis model through PSO to quickly and accurately locate and diagnose specific fault points.

[0097] In terms of optimizing adaptability and flexibility, the PSO adopted in the present invention allows the parameters of the fault judgment model to be dynamically adjusted according to actual operation data, which improves the adaptability and flexibility of the algorithm to different fault situations.

[0098] In terms of improving cost and efficiency, the present invention combines BFS and PSO to reduce the required fault diagnosis time and resources and lower the cost of fault detection, especially when it is necessary to process a large amount of core data and complex interconnections.

[0099] The present invention solves the technical problems existing in the prior art of low fault location accuracy, low location efficiency, high fault detection cost and few applicable scenarios.

[0100] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for locating a core fault, characterized in that: The method comprises: S1. Acquire and construct a fault detection model based on the historical operation data of the chip, and pre-train the fault detection model to obtain an applicable fault detection model; S2. When it is determined that a chip fails, obtain the operation data of all chips; S3, define a queue, select a core particle at random, and put the core particle into the queue; S4, taking out a core particle from the queue, obtaining the operation data of the core particle, marking the current core particle as a selected core particle, and performing a fault determination based on the applicable fault detection model; when a fault occurs in the core particle, performing a fault marking operation; S5, accessing the adjacent coregrains of the selected coregrain, and placing the adjacent coregrains into the queue; S6, looping through steps S4 to S5 until the queue is empty; S7. Obtain the marked selected core particle to obtain the faulty core particle.

2. The method for locating a chip fault according to claim 1, characterized in that: The S1 includes: S11, extracting data features from the core particle historical operation data and performing normalization processing; S12, establishing a BP neural network model, determining the topological structure of the BP neural network model, and defining a fitness function suitable for PSO; S13, randomly generate a group of particles, set the maximum number of iterations, and update the position and velocity of each particle in each iteration; S14. Based on the historical operation data, the pre-training operation is performed on the BP neural network model to obtain the applicable fault detection model.

3. The method for locating a chip fault according to claim 2, characterized in that: In S11, the historical operation data of the core particles are used to construct a historical operation data set of multiple core particles.

4. The method for locating a chip fault according to claim 2, characterized in that: In S13, the particle updating operation includes: PSO particle swarm optimization algorithm.

5. The method for locating a chip fault according to claim 4, characterized in that: The PSO particle swarm optimization algorithm includes: S131. Update the speed of each particle using the following logic: v i (t+1)=w·v i (t)+c1·r1·(P best,i -x i (t))+c2·r2·(g best -x i (t)) where v i is the velocity of the particle at the current moment, x i is the current position, P best,i is the optimal individual position of the particle, g best is the global optimal position, w is the inertia weight, c1 and c2 are learning factors, r1 and r2 are random numbers in the interval [0,1]; S132, using the following logic, update the position of each particle: x i (t+1)=x i (t)+v i (t+1)。 6. The method for locating a chip fault according to claim 1, characterized in that: In S3, an interconnection operation is performed with the core particles as vertices to obtain an undirected graph.

7. The chip fault location method according to claim 6, characterized in that: The edges between the vertices of the undirected graph represent the interconnection relationship between the core particles.

8. The method for locating a chip fault according to claim 1, characterized in that: In the step S3, the queue is defined to store the core particles to be accessed.

9. The method for locating a chip fault according to claim 6, characterized in that: The step S5 comprises: S51, using the selected core particle as a starting point, performing a breadth-first traversal on the undirected graph, visiting the adjacent vertices corresponding to the adjacent core particles, and marking the adjacent vertices as visited vertices; S52: Add the visited vertices to the queue.

10. A chip fault location system, characterized in that: The system comprises: A pre-training module, used to acquire and construct a fault detection model based on the historical operation data of the core particle, and perform model pre-training on the fault detection model to obtain a suitable fault detection model; A faulty chip operation data acquisition module, used to acquire all chip operation data when determining that a chip fails, wherein the faulty chip operation data acquisition module is connected to the pre-training module; A chiplet queue entry module is used to define a queue, select a chiplet at random, and put the chiplet into the queue. The chiplet queue entry module is connected to the fault chiplet operation data acquisition module; A core particle traversal marking module is used to take out a core particle from the queue, obtain the operation data of the core particle, mark the current core particle as a selected core particle, and perform fault determination based on the applicable fault detection model; when a fault occurs in the core particle, a fault marking operation is performed, and the core particle traversal marking module is connected to the core particle entry queue module; An adjacent coregrain queue entry module is used to access adjacent coregrains of the selected coregrain and put the adjacent coregrain into the queue, and the adjacent coregrain queue entry module is connected to the coregrain traversal marking module; A loop module, used for looping the steps performed by the core grain traversal marking module and the adjacent core grain queue entry module until the queue is empty, the loop module being connected to the adjacent core grain queue entry module; The faulty core particle acquisition module is used to acquire the marked core particles to obtain the faulty core particles. The faulty core particle acquisition module is connected to the circulation module.

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