Method and apparatus for reducing electromagnetic interference in a switching power supply

Abstract

The present disclosure relates to methods and apparatus for reducing electromagnetic interference in a switching power supply. An apparatus of the present technology includes a circuit consisting of an inductor and a switch that allows current to flow through the inductor and charges a capacitor of the circuit. A first circuit is coupled to the circuit and is for an analog event. A second circuit sets a threshold for triggering the event while partially compensating for propagation delay.

Description

Technical Field

[0001] This description generally relates to electronic circuits, including, for example, methods and apparatus for reducing electromagnetic interference in switching power supplies. Background Technology

[0002] A Switching Mode Power Supply (SMPS) turns on the power stage to charge the inductor during the duty cycle time set by the pulse width modulator. The stored energy in the inductor is then transferred to the output by turning off the power stage for the remainder of this switching cycle. This switching behavior causes the SMPS's startup current to be triangular rather than the direct current (DC) of a linear regulator, indicating that the SMPS's input current will have a high crest factor.

[0003] SMPS operates in pulse-width modulation (PWM) mode with a fixed switching frequency. Depending on the load level, SMPS operates in either continuous conduction mode (CCM) or discontinuous conduction mode (DCM). In CCM, the inductor current is continuous throughout the time period in a steady state. In DCM, the inductor current will be zero for a portion of the switching period. An inductor current zero-crossing detector circuit detects when the inductor current crosses zero and becomes negative. At this time, the high-side (HS) switch turns off to prevent the inductor current from flowing in the reverse (n) direction, which would otherwise cause the output capacitor to discharge, resulting in efficiency loss. Furthermore, once the HS switch is off, the reverse or negative inductor current can pull the voltage of the switching node below ground and inject minority carriers into the substrate, causing potential latch-up problems.

[0004] If the zero-crossing detector circuit triggers with a delay—for example, when the HS switch is off, the inductor current has already passed the zero-crossing point and become negative—the residual energy in the inductor will form an inductor-capacitor (LC) tank with the switching node capacitance, causing ringing at the switching node. Again, there will be a moment when the switching node is pulled below ground, causing a latch-up problem. Furthermore, this high-frequency ringing may potentially cause electromagnetic interference (EMI) problems in adjacent circuit systems. Ring suppression circuitry is needed to suppress this high-frequency ringing.

[0005] Existing methods use a zero-crossing detector circuit along with DC trimming using an automated test equipment (ATE). An ATE can be any device used to automate testing of a device (called a device under test (DUT), equipment under test (EUT), or unit under test (UUT)) to quickly perform measurements and evaluate test results. To simulate a zero crossover, a digital-to-analog (DAC) code sweeps from high to low until the zero-current comparator output switches from high to low by shorting the switching node to the boost converter output node using a zero-current comparator. The corresponding DAC code is then used as the zero-current threshold code. This trimming scheme fails to capture the propagation delay of the comparator and the effects of input and output voltage dependencies. Therefore, a conservative positive zero-current threshold code is used. This causes an earlier zero-crossing trigger, which causes the HS switch to turn off, while a positive current still exists in the inductor that must discharge to the output via the much less efficient body diode through the HS switch, resulting in less charge reaching the output. Summary of the Invention

[0006] In one aspect, this disclosure relates to an apparatus comprising: a circuit including an inductor and a switch configured to allow current to flow through the inductor and charge a capacitor of the circuit; a first circuit coupled to the circuit, wherein the first circuit is configured to simulate an event; and a second circuit configured to set a threshold for triggering the event when partially compensating for propagation delay.

[0007] On the other hand, this disclosure relates to an integrated circuit comprising: a circuit including: a first circuit comprising an inductor and a switch and coupled to a capacitor; a second circuit comprising a comparator; and a third circuit configured to set a threshold for triggering an event while compensating for propagation delay of the comparator, wherein the switch is configured to at least partially block the discharge of the capacitor at the threshold via a reverse current through the inductor.

[0008] On the other hand, this disclosure relates to a communication device comprising: a circuit including: a first circuit coupled to a capacitor; and a second circuit coupled to the first circuit, the second circuit including a comparator, wherein: the first circuit includes an inductor and a switch, the switch being operable to allow current to charge the capacitor through the inductor prior to a current zero-crossing event, the switch being operable to discharge the capacitor via a reverse current through the inductor at a threshold of the current zero-crossing event, and setting a threshold for triggering the current zero-crossing event when compensating for the propagation delay of the comparator. Attached Figure Description

[0009] Specific features of the present technology are set forth in the appended claims. However, for illustrative purposes, several aspects of the present technology are depicted in the following figures:

[0010] Figure 1A , 1B Figure 1C is a high-level diagram and corresponding diagram illustrating an example of a regulator circuit in which some aspects of the present technology are implemented.

[0011] Figure 2 This is a block diagram illustrating an example of an integrated circuit that implements the first step of an adaptive zero-current threshold scheme according to aspects of this technology.

[0012] Figure 3A and 3B This is a block diagram and corresponding diagram illustrating an example of an integrated circuit that implements the first step of an adaptive zero-current threshold scheme according to aspects of this technology.

[0013] Figure 4 This is a block diagram illustrating an example of an integrated circuit implementing the second step of an adaptive zero-current threshold scheme according to aspects of this technology.

[0014] Figure 5A and 5B This is a schematic diagram illustrating an exemplary embodiment of an integrated circuit according to aspects of the present technology.

[0015] Figure 6A and 6B This is a schematic diagram and corresponding block diagram illustrating an example of an integrated circuit implementing an anti-ringing scheme according to aspects of this technology.

[0016] Figure 7A , 7B Figures 7C and 7D are exemplary verification measurement results illustrating aspects of this technology.

[0017] Figure 8 This is a flowchart illustrating the process of implementing an adaptive zero-current threshold scheme according to aspects of this technology.

[0018] Figure 9 Examples of wireless communication devices that implement some aspects of this technology are described. Detailed Implementation

[0019] The detailed description set forth below is intended to describe various configurations of the present technology and is not intended to merely represent configurations in which the present technology can be practiced. The accompanying drawings are incorporated herein and form part of the detailed description. The detailed description contains specific details for the purpose of providing a thorough understanding of the present technology. However, the present technology is not limited to the specific details set forth herein and can be practiced using one or more embodiments. In one or more examples, structures and components are shown in block diagram form to avoid obscuring the concept of the present technology.

[0020] According to some aspects, this technology relates to a method and apparatus for reducing EMI in the switching power supply of an electronic device. In some embodiments, examples of the electronic device include (but are not limited to) health modules and wearable devices, such as smartwatches or any other similar electronic devices. Examples of health modules include (but are not limited to) blood glucose meters, pulse oximeters, muscle stimulators, and similar devices. The disclosed technology modifies existing methods by using zero current with DC trimming technology to account for efficiency losses in the methods and suppress the resulting EMI, as explained herein.

[0021] In some embodiments, the regulator circuitry of this technology includes a circuit (e.g., a boost converter circuit) comprising an inductor and a switch operable to allow current to flow through the inductor and charge an output capacitor. A first circuitry is coupled to the boost converter and includes a DAC circuitry and a comparator to mimic a current zero-crossing event. A second circuitry is programmed to set a threshold for triggering the current zero-crossing event, taking into account the propagation delay effect embedded in the comparator. In some embodiments, the zero-crossing event occurs when the inductor current passes through zero and becomes negative (e.g., when the HS switch is off).

[0022] In some embodiments, the integrated circuit of this technology includes a regulator circuit comprising a boost converter, a first circuit, and a second circuit. The boost converter includes an inductor and a switch and is coupled to an output capacitor. The first circuit includes a DAC circuit and a comparator circuit, and the second circuit is programmed to set a threshold for triggering a current-related zero-crossing event when the propagation delay of the embedded comparator is present. The switch is operable to block the discharge of the output capacitor via a reverse current through the inductor at the threshold of the zero-crossing event.

[0023] In some embodiments, the communication device of this technology includes a regulator circuit comprising a boost converter coupled to a capacitor and a first circuit coupled to the boost converter. The boost converter includes an inductor and a switch operable to allow current to charge the capacitor through the inductor prior to a current zero-crossing event associated with the current. The first circuit includes a comparator and sets a threshold for triggering the current zero-crossing event when the propagation delay effect of the comparator is embedded.

[0024] Figure 1A , 1B Figure 100A and Figure 100C are high-level diagrams illustrating examples of regulator circuit 100A in which some aspects of the present technology are implemented, corresponding to architecture 100B and diagram 100C. Figure 1AAn integrated circuit implementing a regulator circuit 100A (which is a switching regulator) is shown. The regulator circuit 100A includes a boost converter circuit 102 and a first circuit 120. The boost converter circuit 102 is a non-limiting example of a power circuit (e.g., a power stage circuit, a power supply circuit) and other power circuits can be used. The boost converter circuit 102 includes a driver circuit 110, an inductor 115, a first switch 116 (e.g., a high-side (HS) switch), and a second switch 118 (e.g., a low-side (LS) circuit). The boost converter circuit 102 is coupled to an output capacitor 117, which is the output capacitor of the boost converter. The driver circuit 110 can generate pulses at a switching frequency (fsw, e.g., 2.1 MHz) to control the operation of the first switch 116 and the second switch 118, which are complementary switches. That is, when the first switch 116 is on, the second switch 118 is off, and vice versa. The first switch 116 is operable to allow current IL to flow through inductor 115 and discharge through output capacitor 117. When the first switch 116 is off, the second switch 118 is on and provides a path for charging (e.g., ramping) inductor 115.

[0025] During discharge, the current IL is continuous until it reaches zero, and if the regulator is operating in DCM mode, the current remains zero for the remainder of the switching period (1 / fsw). (See Inductor Current Zero Crossover Detector) Figure 1B The system detects current crossover events (e.g., current zero-crossing events) associated with the current IL, which occur when the current IL crosses zero and is about to become negative. At this time, the first switch 116 must be turned off to prevent the current IL in inductor 115 from flowing in reverse; otherwise, it could cause the output capacitor 117 to discharge, resulting in efficiency loss. Furthermore, once the first switch 116 is turned off, the reverse or negative inductor current (IL) can pull the switching node 112 below ground and inject minority carriers into the substrate of the integrated circuit, potentially causing latch-up problems. The reverse or negative inductor current will flow along the... Figure 1A The arrows shown in the diagram indicate flow in the opposite direction. In other words, the reverse or negative inductor current will flow from... Figure 1A The switching node 112 flows to node 108. Latch-off is a failure mechanism of complementary metal-oxide-semiconductor (CMOS) integrated circuits, characterized by excessive current consumption, accompanied by functional failure, parameter failure and / or device damage.

[0026] The architecture 100B of the first circuit 120 is in Figure 1B As shown in the diagram. The first circuit 120 includes a DAC circuit 124 and a comparator circuit 122 and can implement a zero-current (IL) detector with DC trimming. In some embodiments, the comparator circuit 122 compares... Figure 1AThe nodes 112 and 114 of the first switch 116 shown are used to mimic a zero-current crossover event associated with the inductor current (IL). When the voltage (VSW) at node 112 becomes lower than the voltage (VBST_OUT) at node 114 plus the offset from the DAC circuit 124, the inductor current is considered negative and a zero-current crossover event is triggered. The DAC circuit 124 compensates for the voltage offset of the comparator circuit 122. To do this, at the input port of the DAC circuit 124, the DAC code VOS<6:0> sweeps from high to low until the output of the comparator circuit 122 switches from high (logic 1) to low (logic 0). The DAC code that causes the switching can be used as a current threshold code (e.g., a current threshold code). However, this DAC code may not capture the effects of the propagation delay of the comparator circuit 122 and the input and output voltage dependence of the offset of the comparator circuit 122.

[0027] Figure 100C shows a graph 134 of the inductor current (IL). During the discharge of inductor 115, a conservative positive zero-current threshold (e.g., IL1) must be used due to the drawbacks of the zero-current (IL) of the DC trimming scheme implemented by the first circuit 120. This causes premature zero-current triggering. That is, when the first switch 116 is turned off and there is still a positive current in inductor 115 that must be discharged to the output via the much less efficient power body diode 119 of the field-effect transistor (FET) (first switch 116). As illustrated in graph 134, the shaded area generally represents the lower charge to the output in the case of premature zero-current triggering.

[0028] This technology implements an adaptive zero-current threshold scheme to improve the zero-current (IL) of a DC trimming scheme. The adaptive zero-current threshold scheme addresses the problems caused by the shortcomings of the zero-current (IL) of the DC trimming scheme by adding a second circuit, as described in more detail below. The second circuit is programmed to set a threshold for triggering a current zero-crossing event when the propagation delay of the embedded comparator is at play. In some embodiments, the second circuit uses the zero-current threshold to determine the cutoff. Figure 1A The timing of the first switch 116. In some embodiments, the second circuit implements the procedure by determining a zero-current threshold based on a first code and a second code. Furthermore, the second circuit includes a digital circuitry system to determine the second code, which includes the comparator's dependence on the input and output voltages of the boost converter. Additionally, the integrated circuit of this technology includes anti-ringing circuitry to reduce (mitigate) EMI caused by oscillations in the inductor-capacitor (LC) slots within the boost converter circuit 102 (e.g., from inductor 115 and output capacitor 117), as described in more detail herein.

[0029] Figure 2This is a block diagram illustrating an example of an integrated circuit 200 implementing an adaptive zero-current threshold scheme (e.g., a zero-current threshold scheme) according to aspects of the present technology. Integrated circuit 200 is a first part of a second circuit that implements a program to set a threshold for triggering a current crossover event by determining an adaptive zero-current threshold based on a first code and a second code. In some embodiments, the adaptive zero-current threshold scheme of the present technology is an example of a program for setting a threshold for triggering a current zero crossover event and includes two steps. In the first step, the first code (base code) is obtained via ATE closed-loop automatic calibration (auto-cal) trimming to capture (consider) the event. Figure 1B The propagation delay of comparator 126. In some embodiments, trimming includes closed-loop automatic calibration trimming implemented via ATE. The term "trimming" is a term used in the field of fine-tuning. In the second step, a second code (offset code) is generated using a digital circuit system to account for the input and output voltage dependencies that take into account the inductor discharge rate, which will affect the used threshold used to accurately trigger a zero-crossing event at zero current.

[0030] Integrated circuit 200 includes register 210, offset calculator circuit 220, adder 230 (arithmetic adder), zero-current calibration circuit 240 (zeroICAL), multiplexer (MUX) 250, power stage (PS) block 260, one-time programmable (OTP) register 270, and MUX 280. Zero-current calibration circuit 240, MUX 250, and PS 260 form block 202, which is a closed-loop block that performs automatic calibration trimming to capture the propagation delay of comparator 126. When the select signal 242 (EN_ZCAL) is set high (logic 1), the output of zero-current calibration circuit 240 is transferred to PS block 260 via MUX 250, which provides feedback signal 262 to zero-current calibration circuit 240. The final output of MUX 250 is code 252, which represents the first code and is stored in OTP register 270. Code 252, representing the first code, can be retrieved from OTP register 270. It should be noted that the first code (e.g., Figure 2 Code 252) uses the range of operations VIN,min and VOUT,max to obtain the result. The following text is related to... Figure 3A Further details will be provided to describe the operation of the zero-current calibration circuit 240.

[0031] The second code (offset code) is determined by an offset calculator circuit 220 that receives input signals / data 212, 214, and 216 from register 210. Input signals / data 212, 214, and 216 represent the zero-current offset enable signal (i_EN_ZOS), the boost converter input voltage (VBST_IN), and the boost converter output voltage (VBST_OUT), respectively. The output 222 of the offset calculator circuit 220 is the second code, representing the zero-current threshold offset (zithOS). The output 222 (second code) is added by adder 230 to code 282 (first code) to generate signal 232, which represents the sum of the first code and the second code. In some embodiments, code 252 (first code) stored in OTP 270 is rewritten using multiplexer 280 with an external zero-current threshold (EXT_ZITH) 218 ​​stored in register 210. The following will refer to... Figure 4 Further details of the circuit system implementing the offset calculator circuit 220 will be described below.

[0032] Figure 3A and 3B This is a block diagram and corresponding diagram 300B illustrating an example of an integrated circuit 300A implementing the first step of an adaptive zero-current threshold scheme according to aspects of the present technology. Integrated circuit 300A is the second part of a second circuit and includes a comparator circuit 310, a DAC circuit 320, and a calibration circuit 330. The comparator circuit 310 and the DAC circuit 320 respectively correspond to... Figure 1B The comparator circuit 122 and DAC circuit 124 are responsible for considering the offset voltage and propagation delay of comparator 310. Comparator circuit 310 and DAC circuit 320 are... Figure 2 Part of PS block 260, and calibration circuit 330 is implemented. Figure 2 The zero-current calibration circuit 240.

[0033] In some embodiments, calibration circuit 330 includes (but is not limited to) three flip-flops (FFs) 332, 334, and 335, a digital counter 336, and a multiplexer 338. In some embodiments, calibration circuit 330 receives the output of comparator 310 and generates a control signal to turn off the first switch 116 of FIG. 1 and provide digital code 339 (which is the base code) to DAC circuit 320 to compensate for the propagation delay of comparator 310. The term "compensate" refers to offsetting a value, which may include eliminating or partially eliminating the value.

[0034] Chart 300B includes curves 301, 302, 303, 304, 305, 306, and 308, which respectively represent the switching nodes ( Figure 1AThe voltage (VSW) signal, zero current compensation (zeroI Comp) signal, control at node 112 Figure 1A The top gate (TG) signal of the first switch 116, the delayed version (TG-dly) of TG, calibration data (Cal_D), mode signal and control Figure 1A The delayed bottom gate (BG-dly) signal of the second switch 118. The signals are shown for (a) trigger advance, (b) trigger delay, and (c) CCM hold cases.

[0035] The operation of the calibration circuit 330 begins with operating a boost converter (e.g., the boost converter circuit 102) at a light load (e.g., a few milliamps (mA)) for DCM operation. Figure 1A When the first switch 116 is on and VSW < VBST_OUT + Vos, the zeroI comp signal (of graph 302) and the output 333 (zi_trig) of the FF 332 will switch high to turn off the first switch 116. When the first switch 116 is off, the zeroI comp signal (of graph 302) is checked to determine the polarity of the current IL through the inductor 115. If the current IL is greater than zero when the first switch 116 is off, then the switching node voltage (VSW) rises and the zeroI comp signal (of graph 302) switches low. This is the trigger advance case (a), where mode = 1 and the calibration data (CAL_D) of graph 305 = 1, which results in an increase in the digital code 339 and a decrease in the offset at the input of the comparator 310. Figure 1A However, if the current IL is less than zero, then the switching node voltage (VSW) remains low and the zeroI comp signal (of graph 302) remains high. This is the trigger delay case (b), where mode = 1 and the calibration data (CAL_D) of graph 305 = 0, which results in a decrease in the digital code 339 and an increase in the offset at the input of the comparator 310.

[0036]

[0037] Case (c) is the CCM mode, where when the first switch 116 is on, the zeroI comp signal does not switch high and the switching node voltage (VSW) remains greater than VBST_OUT + Vos. This results in mode = 0, the calibration data (CAL_D) of graph 305 = not concerned, resulting in the digital code 339 not being updated (remaining). Once the calibration circuit 330 stabilizes, the output of the MUX 338 will be the first code (base code) of the zero current threshold (zeroI_TH).

[0038] Figure 4 Figure 4This is a block diagram illustrating an example of an integrated circuit 400 implementing a second step of an adaptive zero-current threshold scheme according to aspects of the present technology. In some embodiments, the integrated circuit 400 is a third part of a second circuit and includes a digital circuit system that implements arithmetic blocks (e.g., Figure 2 The offset calculator circuit 220) is used to... Figure 1A The second code is determined by the lowest value of VIN (VIN,min) (e.g., minimum input voltage) and the highest value of VOUT (VOUT,max) (e.g., maximum output voltage) of the boost converter circuit 102. In some embodiments, the value of VIN,min is approximately 2.5V and the value of VOUT,max is approximately 5.6V.

[0039] Integrated circuit 400 includes an analog-to-digital converter (ADC) 410, a first subtractor 420, an adder 430, a second subtractor 440, a multiplier 460, a rounding block 470, and a MUX 480. ADC 410 converts the battery voltage 402 (VBAT) into a digital signal 412 (VBST_IN), which is subtracted by VIN,min by the first subtractor 420. The second subtractor 440 subtracts the boost converter output voltage 408 (VBST_OUT) from VOUT,max and sends the result to the adder 430 to be added to the result of the first subtractor 420. The output of adder 430 is multiplied by design dependency parameter 450 (Kv) via multiplier 460, and the result is rounded by rounding block 470 and sent to MUX 480, where the setting of select signal 482 (i_EN_ZOS) is transferred to the output of MUX 480 to form second code 484, which is shown as representing Figure 2 The zero current threshold offset (zithOS) of the output 222 of the offset calculator circuit 220. In some embodiments, the value of VIN can be in the range of about 2.5V to about 4.55V, and the value of VOUT can be in the range of about 4.7V to about 5.6V.

[0040] As mentioned above, the first code (e.g.) Figure 2 Code 252) is obtained using the operating range of VIN,min and VOUT,max. Using this first code, zero current will not be delayed for any other combination of VIN and VOUT values. For any other combination of VIN and VOUT values, the offset calculator circuit 220, implemented by integrated circuit 400, is used to find the second code (zithOS). The final zero current threshold for a given VIN / VOUT will be the first code (zithB) + the second code (zithOS). It should be noted that when i_EN_ZOS is set to zero, the value of the second code (zithOS) is calculated by the offset calculator circuit 220 (implemented by integrated circuit 400), which can be expressed as follows:

[0041] zithOS=Round{Kv*[(VBAT-VIN,min)+(Vout,max-VBST_OUT)]}

[0042] Where Kv is the design dependency parameter 450, which is usually equal to 1.

[0043] Figure 5A and 5B This is a schematic diagram illustrating an exemplary embodiment 500B of an integrated circuit 500A according to aspects of the present technology. The integrated circuit 500A includes... Figure 1A This is part of the boost converter circuit 102, namely, the HS switch 116 and the first circuit 120 consisting of a comparator 510, a DAC 520, and an adder 530. These correspond to... Figure 1B 122, 124, and 126 in the diagram. Implementation scheme 500B includes blocks 540, 550, 560, and buffer 570. Block 540, formed by N-type MOS (NMOS) and P-type MOS (PMOS) transistors, implements the pre-amplification stage of comparator 510. Block 550, formed by NMOS transistors and current sources, implements DAC 520. Block 560, formed by PMOS transistors, current sources, and an output stage, implements the differential gain stage of comparator 510. The output of block 560 is fed to buffer 570.

[0044] Figure 6A and 6B This is a schematic diagram and corresponding diagram 600B illustrating an example of an integrated circuit 600A implementing an anti-ringing scheme according to aspects of the present technology. Integrated circuit 600A includes anti-ringing logic 610 coupled to an NMOS transistor 630 and a pair of 640 NMOS transistors. A pair of PMOS transistors 650 are operable to short-circuit the terminals of an inductor LIN connected between an input node 602 and a switching node 604. When the pair of 640 NMOS transistors are turned on, the pair of PMOS transistors 650 conduct and thus short-circuit the input node 602 to the switching node 604. To turn off the pair of PMOS transistors 650, a turn-off assist circuit 620 is used to quickly turn off the pair of PMOS transistors 650. To cause this, the NMOS transistor 630 is turned on to cause the PMOS transistor 660 to conduct and to rapidly discharge the gate-source capacitance of the PMOS transistor 651.

[0045] Figure 600B shows graphs 612 and 614. Graphs 612 and 614 depict the time variation of the voltage at switching node 604 with and without the application of integrated circuit 600A. Graph 612 shows the undesired oscillation of the inductor-capacitor (LC) tank. This technique uses integrated circuit 600A to reduce (mitigate) the oscillation. As shown by graph 614, the voltage at switching node 604 stabilizes to the value indicated by the dashed line 616, which is the input voltage at input node 602.

[0046] Figure 7A , 7B Figures 700A, 700B, 700C, and 700D are exemplary verification measurement results according to aspects of this technology. Figure 700A displays curves 702, 704, 706, 708, 710, and 712. Curves 702, 704, and 706 illustrate the time variations of the LD, MD, and HD voltage waveforms, where LD, MD, and HD correspond to VIN = 4.5V and VOUT = 4.7V (LD), VIN = 3.85V and VOUT = 5.2V (MD), and VIN = 2.8V and VOUT = 5.6V (HD), respectively. Curves 708, 710, and 712 depict the inductor currents IL (e.g., LD, MD, and HD). Figure 1A The time variation of the IL waveform. The data in Figure 700A is based on a 40mA pulse frequency modulation (PFM) current threshold (IPFM_TH).

[0047] Charts 700B, 700C, and 700D respectively show Figure 7A The graph shows magnified versions of the MD, HD, and LD waveforms.

[0048] Figure 8 This describes the aspects of the present technology used for implementation by Figure 2 Integrated circuit 200, Figure 3A 300A and Figure 4 The flowchart below illustrates the process 800 of the adaptive zero-current threshold scheme implemented in 400. In some embodiments, process 800 is an example of a process for setting a threshold for triggering the zero-crossing event mentioned above. Process 800 begins at operation block 802, where ATE trimming is initiated using the minimum value of VBST_IN, the maximum value of VBST_OUT, and the initial DAC code. In operation block 804, it is checked whether the timer has expired. If the timer has expired, then in operation block 806, the DAC code (which is the first code 809 (base code, zithB)) is... Figure 2 The calculation of block 202 is written to the OTP register (e.g., Figure 2In the OTP register 270). In operation box 808, normal operation is initiated using real-time VBST_IN and real-time VBST_OUT. In operation box 810, (for example, via...) Figure 2 The offset calculator circuit 220 performs offset calculations to obtain the second code 811 (offset code, zithOS). In operation box 812, (via...) Figure 2 The adder 230) adds the first code 809 to the second code 811 to obtain the real-time zero current threshold (zeroI_TH) code 814.

[0049] If the timer has not expired, then in operation block 816, it is checked whether the zero-current comparator has been triggered. If the zero-current comparator has not yet been triggered, then control is passed to operation block 804. Otherwise, if the zero-current comparator has been triggered, then control is passed to operation block 818, where it is checked whether the zero-current comparator has been triggered prematurely. If the zero-current comparator has been triggered prematurely, then in operation block 820, the DAC code is incremented, and control is passed to operation block 804. Otherwise, if the zero-current compensation has not been triggered prematurely, then in operation block 822, the DAC code is decremented, and control is passed to operation block 804. The DAC code continues to increment or decrement until the timer in block 804 expires.

[0050] Figure 9 Examples of wireless communication devices 900 that implement some aspects of the present technology are illustrated herein. In one or more embodiments, the wireless communication device 900 may be a wearable device, such as a smartwatch or other electronic device, including one or more health sensing devices. The wireless communication device 900 may include an RF antenna 910, a duplexer 912, a receiver 920, a transmitter 930, a baseband processing module 940, a memory 950, a processor 960, and a local oscillator generator (LOGEN) 970. In various aspects of the present technology, Figure 9 The blocks represented herein may be integrated on one or more semiconductor substrates. For example, blocks 920 to 970 may be implemented in a single chip, a single system on a chip, or a multi-chip chipset.

[0051] Receiver 920 may include suitable logic circuitry and / or code operable to receive and process signals from RF antenna 910. For example, receiver 920 may be operable to amplify and / or down-convert received wireless signals. In various aspects of this technology, receiver 920 may be operable to eliminate noise in the received signal and be linear over a wide frequency range. In this way, receiver 920 may be suitable for receiving signals according to various wireless standards (e.g., Wi-Fi, WiMAX, BT, and various cellular standards). In various aspects of this technology, receiver 920 may not use any sawtooth acoustic filters and few or no off-chip discrete components, such as large capacitors and inductors.

[0052] Transmitter 930 may include suitable logic circuitry and / or code operable to process and transmit signals from RF antenna 910. For example, transmitter 930 may be operable to upconvert baseband signals into RF signals and amplify the RF signals. In various aspects of this technology, transmitter 930 may be operable to upconvert and amplify baseband signals processed according to various wireless standards. Examples of such standards may include Wi-Fi, WiMAX, BT, and various cellular standards. In various aspects of this technology, transmitter 930 may be operable to provide signals for further amplification by one or more power amplifiers.

[0053] The duplexer 912 provides isolation in the transmit frequency band to prevent saturation or damage to parts of the receiver 920 and relaxes one or more design requirements of the receiver 920. Furthermore, the duplexer 912 attenuates noise in the receiver band. The duplexer 912 can operate in multiple frequency bands across various wireless standards.

[0054] The baseband processing module 940 may include suitable logic, circuitry, interfaces, and / or code operable to perform baseband signal processing. For example, the baseband processing module 940 may analyze received signals, generate control and / or feedback signals for configuring various components of the wireless communication device 900, such as receiver 920. The baseband processing module 940 is operable to encode, decode, transcode, modulate, demodulate, encrypt, decrypt, scramble, descramble, and / or otherwise process data according to one or more wireless standards.

[0055] Processor 960 may include suitable logic, circuitry, and / or code that enables the processing of data and / or control of the operation of wireless communication device 900. In this regard, processor 960 may be able to provide control signals to various other parts of wireless communication device 900. Processor 960 may also control data transfer between various parts of wireless communication device 900. Additionally, processor 960 may implement an OS implementation or otherwise execute code to manage the operation of wireless communication device 900. In one or more implementations, processor 960 may interface with transducer module via existing host interface technologies such as Internal Integrated Circuit (I2C), Serial Interface Protocol (SPI), Peripheral Component Interconnect (PCIe), Universal Asynchronous Receiver-Transmitter (UART), and / or other interface technologies, depending on the data rate required for sampling and the pipeline from transducer module to processor 960.

[0056] The memory 950 may include logic, circuitry, and / or code suitable for storing various types of information, such as received data, generated data, code, and / or configuration information. The memory 950 may include, for example, RAM, ROM, flash memory, and / or magnetic storage devices. In various aspects of this technology, the information stored in the memory 950 can be used to configure the receiver 920 and / or the baseband processing module 940.

[0057] LOGEN 970 may include suitable logic, circuitry, interfaces, and / or code, operable to generate one or more oscillation signals at one or more frequencies. LOGEN 970 may also be operable to generate digital and / or analog signals. In this manner, LOGEN 970 may be operable to generate one or more clock signals and / or sinusoidal signals. The characteristics of the oscillation signals (e.g., frequency and / or duty cycle) may be determined based on one or more control signals from, for example, processor 960 and / or baseband processing module 940.

[0058] In operation, the processor 960 can configure various components of the wireless communication device 900 based on the wireless standard designed to receive signals. Wireless signals can be received via the RF antenna 910, amplified, and down-converted by the receiver 920. The baseband processing module 940 can perform noise estimation and / or noise cancellation, decoding, and / or demodulation of the baseband signals. In this way, information in the received signals can be recovered and appropriately utilized. For example, the information may be audio and / or video to be presented to the user of the wireless communication device 900, data to be stored in the memory 950, and / or information that affects and / or enables the operation of the wireless communication device 900. The baseband processing module 940 can modulate, encode, and perform other processing on audio, video, and / or control signals to be transmitted by the transmitter 930 according to various wireless standards.

[0059] In some implementations, all active components of the wireless communication device 900 (e.g., receiver 920, transmitter 930, baseband processing module 940, memory 950, processor 960, and LOGEN 970) can be powered from a source (including those incorporating the present technology). Figure 2 The integrated circuits 200 and 300 (SMPS) receive power and benefit from the improved efficiency and reduced EMI of the disclosed technology.

[0060] The predicates “configured to,” “operable to,” and “programmed to” do not imply any specific tangible or intangible modification of the subject, but are intended to be used interchangeably. For example, “processor configured to monitor and control operation” or “component” could also mean “processor programmed to monitor and control operation” or “processor operable to monitor and control operation.” Similarly, “processor configured to execute code” can be interpreted as “processor programmed to execute code” or “operable to execute code.”

[0061] When an element is referred to herein as "connected" or "coupled" to another element, it should be understood that the element may be directly connected to the other element or have an intermediary element present between the elements. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, it should be understood that there is no intermediary element in the "direct" connection between the elements. However, the presence of a direct connection does not preclude the existence of other connections in which intermediary elements may be present.

[0062] For example, the phrase "aspect" does not imply that this aspect is essential to the present technology or that this aspect applies to all configurations of the present technology. Disclosures relating to an aspect may apply to all configurations or one or more configurations. For example, the phrase "aspect" may refer to one or more aspects, and vice versa. For example, the phrase "configuration" does not imply that this configuration is essential to the present technology or that this configuration applies to all configurations of the present technology. Disclosures relating to configuration may apply to all configurations or one or more configurations. For example, the phrase "configuration" may refer to one or more configurations, and vice versa.

[0063] The word “example” is used in this document to mean “serving as an example or illustration.” Any aspect or design described as an “example” in this document is not necessarily to be construed as being better or superior to other aspects or designs.

[0064] All structural and functional equivalents of elements in the various aspects described throughout this disclosure that are known or will be known by one of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. Furthermore, nothing disclosed herein is intended to be offered to the public, whether or not such disclosure is expressly stated in the claims. No claim element should be construed in accordance with 35 U.S.SC §112(f) unless the element is expressly stated using the phrase “component for…” or, in the case of a method claim, the element is stated using the phrase “step for…”. Furthermore, with regard to the use of the terms “comprising,” “having,” or similar in the description or claims, such terms are intended to be inclusive in a manner similar to how the term “comprising” is interpreted when used as a transitional word in a claim.

[0065] Those skilled in the art will understand that the various illustrative blocks, modules, elements, components, methods, and algorithms described herein can be implemented as electronic hardware, computer software, or a combination of both. To illustrate this interchangeability between hardware and software, the various illustrative blocks, modules, elements, components, methods, and algorithms have been described above generally in terms of their functionality. Whether this functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in various ways for each specific application. Various components and blocks can be arranged in different ways (e.g., in different orders or in different ways), all without departing from the scope of this art.

Claims

1. An apparatus comprising: a circuit including an inductor and a switch configured to allow current to flow through the inductor and charge a capacitor of the circuit; a first circuit coupled to the circuit, wherein the first circuit is configured to simulate an event; and a second circuit including a multiplexer and configured to: set a threshold for triggering the event while partially compensating for a propagation delay, generate a control signal to turn off the switch based at least on the propagation delay, and provide a specific code to the first circuit to further compensate for the propagation delay.

2. The apparatus of claim 1, wherein the event includes a zero current crossing event, and wherein at the threshold of the zero current crossing event, the switch is configured to discharge the capacitor via a reverse current through the inductor.

3. The apparatus of claim 2, wherein the second circuit is configured to determine a threshold of the zero current crossing event based on a first code and a second code.

4. The apparatus of claim 3, wherein the second circuit is configured to determine a time to turn off the switch using the threshold of the zero current crossing event.

5. The apparatus of claim 3, wherein the first circuit includes a comparator with the propagation delay, and wherein the second circuit is configured to determine the first code by using trimming to capture the propagation delay of the comparator.

6. The apparatus of claim 5, wherein the trimming includes a closed loop auto-calibration trimming.

7. The apparatus of claim 5, wherein: the first circuit includes a digital-to-analog converter (DAC) circuit, and the multiplexer is configured to: receive an output of the comparator, generate the control signal to turn off the switch, and provide the specific code to the DAC circuit to further compensate for the propagation delay.

8. The apparatus of claim 5, wherein: the second circuit includes circuitry configured to determine the second code, and the second code is based on an input voltage and an output voltage of the circuit.

9. The apparatus of claim 8, wherein the circuitry is configured to determine the second code using a minimum input voltage and a maximum output voltage of the circuit.

10. The apparatus of claim 1, further comprising a third circuit configured to compensate for electromagnetic interference in the circuit.

11. An integrated circuit comprising: a circuit including: a first circuit including an inductor and a switch and coupled to a capacitor; a second circuit including a comparator; and a third circuit configured to set a threshold for triggering an event while compensating for a propagation delay of the comparator, wherein the switch is configured to at least partially block a discharge of the capacitor via a reverse current through the inductor at the threshold, wherein the third circuit includes a multiplexer and is configured to: generate a control signal to turn off the switch based at least on the propagation delay, and provide a specific code to the first circuit to further compensate for the propagation delay.

12. The integrated circuit of claim 11, wherein the switch is further configured to allow current to pass through the inductor to charge the capacitor.

13. The integrated circuit of claim 11, the event comprising a current zero-crossing event, and wherein the third circuit is configured to determine a threshold for the current zero-crossing event based on a first code and a second code.

14. The integrated circuit of claim 13, wherein the third circuit is configured to determine a time to turn off the switch using the threshold for the current zero-crossing event.

15. The integrated circuit of claim 13, wherein the third circuit is further configured to determine the first code by using a trim to capture the propagation delay.

16. The integrated circuit of claim 15, wherein the trim comprises a closed loop auto-calibration trim.

17. The integrated circuit of claim 15, wherein the third circuit is configured to: receive an output of the comparator, generate a control signal for turning off the switch based on the output, and provide a code to compensate for the propagation delay; and determine the second code based on an input voltage and an output voltage of the first circuit.

18. A communication device comprising: circuitry comprising: a first circuit coupled to a capacitor; a second circuit coupled to the first circuit, the second circuit comprising a comparator, and a third circuit comprising a multiplexer, wherein: the first circuit includes an inductor and a switch, the switch operable to allow current to pass through the inductor to charge the capacitor prior to a current zero-crossing event, the switch is operable to discharge the capacitor via a reverse current through the inductor at a threshold for the current zero-crossing event, and the third circuit is configured to: set a threshold for triggering the current zero-crossing event based on at least a propagation delay of the comparator, generate a control signal to turn off the switch when compensating for the propagation delay, and provide a specific code to the first circuit to further compensate for the propagation delay.

19. The communication device of claim 18, further comprising a third circuit configured to: implement a procedure to set the threshold for triggering the current zero-crossing event by determining a zero current threshold based on a first code and a second code; determine a time to turn off the switch using the zero current threshold; and determine the first code by using a trim to capture the propagation delay of the comparator.

20. The communication device of claim 19, wherein the third circuit is configured to determine the second code, the second code comprising a dependence of the comparator on an input voltage and an output voltage of the first circuit. ​

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