Database-based chip verification system

Abstract

The application relates to the chip technical field, in particular to a chip verification system based on a database, which comprises a first file database, a second file database, a verification IP and a first memory model arranged in the verification IP; the first file database is used for storing verification data; the verification IP reads the verification data in the first file database and stores the verification data into the first memory model through a structured query interface; the verification IP comprises a first data conversion interface and a second data conversion interface; the verification IP is also used for acquiring the verification data from the first memory model through the first data conversion interface, processing the verification data, generating result data, and storing the result data into the first memory model through the second data conversion interface; and the verification IP is also used for storing the result data in the first memory model into the second file database through the structured query interface. The application improves the chip verification efficiency.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a database-based chip verification system. Background Technology

[0002] With the development of chip technology, chips are becoming increasingly larger. During large-scale chip verification, the verification IP (Intellectual Property) needs to read massive amounts of source data from files and store them in memory, then read data from memory for processing, store the processed results back in memory, and finally store the massive results data from memory back in files. Due to the enormous size of the chips, the amount of data to be read from and written to files is also enormous, involving a large number of I / O operations, which significantly impacts the efficiency of chip verification. Therefore, improving chip verification efficiency has become a pressing technical problem. Summary of the Invention

[0003] The purpose of this invention is to provide a database-based chip verification system that improves chip verification efficiency.

[0004] This invention provides a database-based chip verification system, including a first file database, a second file database, a verification IP, and a first memory model set in the verification IP. The verification IP is generated based on the SystemVerilog language, and the first memory model is generated based on a preset high-level language. The first memory model is connected to the first file database and the second file database through a structured query interface.

[0005] The first file database is used to store verification data;

[0006] The verification IP reads the verification data from the first file database and stores it in the first memory model through a structured query interface;

[0007] The verification IP includes a first data conversion interface and a second data conversion interface. The first data conversion interface is used to convert data in a preset high-level language into data in SystemVerilog language, and the second data conversion interface is used to convert data in SystemVerilog language into data in a preset high-level language.

[0008] The verification IP is also used to obtain verification data from the first memory model through the first data conversion interface, process it, generate result data, and then store the result data into the first memory model through the second data conversion interface;

[0009] The verification IP is also used to store the result data in the first memory model into the second file database through a structured query interface.

[0010] Compared with existing technologies, this invention has significant advantages and beneficial effects. Through the above technical solution, the database-based chip verification system provided by this invention achieves considerable technological advancement and practicality, and has broad industrial application value, possessing at least the following beneficial effects:

[0011] This invention improves chip verification efficiency by setting a first memory model generated by a high-level language in the verification IP and communicating with an external first file database and a second file database through the first memory model. This enables data verification reading and result data storage, reduces large-scale file operations, and improves data processing efficiency in the chip verification process. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic diagram of a database-based chip verification system provided in an embodiment of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] This invention provides a database-based chip verification system, such as... Figure 1As shown, the system includes a first file database, a second file database, a verification IP, and a first storage model set within the verification IP. The verification IP is generated using SystemVerilog, and the first storage model is generated using a preset high-level language, specifically C++. The first storage model connects to the first and second file databases via a structured query interface. Specifically, each of the first and second file databases can be configured with a corresponding structured query interface, and the verification IP interacts with both databases through these interfaces. The structured query interface is generated using Structured Query Language (SQL), a database query and programming language used for accessing, querying, updating, and managing relational database systems.

[0016] As one embodiment, the first file database is used to store verification data. The system can write verification data to the first file database based on a preset first script through a structured query interface. The verification data includes data to be processed and data to be compared. The data to be processed can specifically be the stimulus data simulated in the verification process, and the data to be compared can specifically be preset target result data, used to compare with the actual output target result data. The verification data is very large; for example, when verifying a GPU chip, the verification data may be a large-scale image dataset. The first script can quickly store the verification data in the first file database, reducing large-scale opening and closing of files and greatly improving the storage efficiency of the verification data. The first script can specifically be a Python, JavaScript, Ruby, Perl, Shell, or other scripts.

[0017] The verification IP reads verification data from the first file database and stores it in the first memory model through a structured query interface. The verification IP cannot communicate directly with the first file database and the second file database, but the first memory model can communicate directly with both. All interactions between the verification IP and the first and second file databases must be performed through the first memory model.

[0018] Since the verification IP is generated based on the SystemVerilog language and the first memory model is generated based on a preset high-level language, the SystemVerilog language and the preset high-level language cannot communicate directly. Therefore, the verification IP includes a first data conversion interface and a second data conversion interface. The first data conversion interface is used to convert data from the preset high-level language to data from the SystemVerilog language, and the second data conversion interface is used to convert data from the SystemVerilog language to data from the preset high-level language. All existing implementations of converting data from the preset high-level language to SystemVerilog language and vice versa fall within the protection scope of this invention and will not be elaborated here.

[0019] The verification IP is also used to obtain verification data from the first memory model through the first data conversion interface, process it to generate result data, and then store the result data into the first memory model through the second data conversion interface.

[0020] The verification IP is also used to store the result data in the first memory model to the second file database through a structured query interface. The system can store the result data in the first memory model to the second file database in real time, resulting in higher real-time data storage performance. A preset data block size can also be set; when the result data in the first memory model reaches the size of the preset data block, the entire preset-size data block is then stored in the second file database, achieving block storage processing and further improving system performance.

[0021] This invention stores the result data directly in the database, eliminating the need for file storage. This reduces large-scale file operations and improves the efficiency of result data storage. Furthermore, when analysis is required, a pre-defined second script can be used to parse the second file database and generate the data to be analyzed, without requiring extensive file reading operations, thus improving the efficiency of data retrieval. The second script can be in languages ​​such as Python, JavaScript, Ruby, Perl, or Shell.

[0022] The result data can be divided into two types: one that requires further analysis and processing, and the other that can be released after the process is complete. Therefore, to further improve the processing efficiency of the result data, the result data can be processed in categories, without having to store it all in the second file database. As one embodiment, the system also includes a virtual memory module. The result data includes first result data and second result data. The first result data is the result data that needs to be compared, and the second result data is the result data that does not need to be compared. The verification IP is also used to store the first result data in the first memory model into the second file database through a structured query interface, and to store the second result data in the virtual memory module. When the verification is complete, the second result data in the virtual memory module is released.

[0023] As one embodiment, the system parses the second file database based on a preset second script to generate target result data, obtains comparison data from the first file database, compares the target result data with the comparison data, and if they match, the verification passes; otherwise, the verification fails. If the verification fails, the system can also present the user with specific information about the inconsistent target result data.

[0024] During chip verification, it is also necessary to obtain and analyze the interface data of the verification IP. Existing technologies require reading and writing raw files to obtain this data. This invention can also be implemented based on the interaction between a first memory model and a database. Specifically, the verification IP includes multiple verification interfaces. The verification IP is also used to read the performance data and bandwidth data corresponding to the interfaces, and to store the performance data and bandwidth data corresponding to the verification interfaces into the first memory model through a second data conversion interface. The verification IP is also used to store the performance data and bandwidth data corresponding to the verification interfaces stored in the first memory model into a second file database through a structured query interface. Subsequently, the performance data and bandwidth data corresponding to the interfaces can be obtained and analyzed through parsing using a second script.

[0025] To further improve data processing efficiency during chip verification, the system also includes a second memory model. This second memory model is generated using the SystemVerilog language. The first and second memory models are mirror images of each other, meaning they share the same memory address space and store the same data at the same addresses. Since both the verification IP and the second memory model are generated using SystemVerilog, the verification IP can communicate directly with the second memory model; that is, the verification IP can directly retrieve data from and store data in the second memory model.

[0026] As one embodiment, a third data conversion interface and a fourth data conversion interface are provided between the first memory model and the second memory model. The third data conversion interface is used to convert the data stored in the first memory model into SystemVerilog language data, and store the converted SystemVerilog language data in the address corresponding to the second memory model. The second data conversion interface is used to convert the data stored in the second memory model into data in a preset high-level language, and store the converted preset high-level language data in the address corresponding to the first memory model. Since the first memory model and the second memory model are mirror images of each other, the data conversion and storage between the first memory model and the second memory model is significantly faster than the data conversion and storage between the verification IP and the first memory model, further improving the data processing efficiency of chip verification. The verification IP is also used to obtain verification data from the second memory model, process it, generate result data, and then store the result data in the first memory model. The verification IP stores the result data in the first memory model into a second file database through a structured query interface.

[0027] The system described in this embodiment of the invention sets up a first memory model generated by a high-level language in the verification IP, and communicates with an external first file database and a second file database through the first memory model to realize data verification reading and result data storage, reduce large-scale file operations, improve data processing efficiency in the chip verification process, and thus improve chip verification efficiency.

[0028] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A database-based chip verification system, characterized in that, It includes a first file database, a second file database, a verification IP, and a first memory model set in the verification IP. The verification IP is generated based on the SystemVerilog language, and the first memory model is generated based on a preset high-level language. The first memory model is connected to the first file database and the second file database through a structured query interface. The first file database is used to store verification data; The verification IP reads the verification data from the first file database and stores it in the first memory model through a structured query interface; The verification IP includes a first data conversion interface and a second data conversion interface. The first data conversion interface is used to convert data in a preset high-level language into data in SystemVerilog language, and the second data conversion interface is used to convert data in SystemVerilog language into data in a preset high-level language. The verification IP is also used to obtain verification data from the first memory model through the first data conversion interface, process it, generate result data, and then store the result data into the first memory model through the second data conversion interface; The verification IP is also used to store the result data in the first memory model into the second file database through a structured query interface.

2. The system according to claim 1, characterized in that, The system writes verification data into the first file database based on a preset first script through a structured query interface. The verification data includes data to be processed and data to be compared.

3. The system according to claim 1, characterized in that, The system also includes a virtual memory module, and the result data includes first result data and second result data, wherein the first result data is result data that needs to be compared, and the second result data is result data that does not need to be compared. The verification IP is also used to store the first result data in the first memory model into the second file database through a structured query interface, store the second result data into the virtual memory module, and release the second result data in the virtual memory module when the verification ends.

4. The system according to claim 1, characterized in that, The system parses the second file database based on a preset second script, generates target result data, retrieves data to be compared from the first file database, and compares the target result data with the data to be compared. If they match, the verification passes; otherwise, the verification fails.

5. The system according to claim 1, characterized in that, The verification IP includes multiple verification interfaces. The verification IP is also used to read the performance data and bandwidth data corresponding to the interfaces, and to store the performance data and bandwidth data corresponding to the verification interfaces into the first memory model through the second data conversion interface. The verification IP is also used to store the performance data and bandwidth data corresponding to the verification interfaces stored in the first memory model into the second file database through the structured query interface.

6. The system according to claim 1, characterized in that, The system also includes a second memory model, which is generated based on the SystemVerilog language. The first memory model and the second memory model are mirror images of each other.

7. The system according to claim 6, characterized in that, A third data conversion interface and a fourth data conversion interface are provided between the first memory model and the second memory model. The third data conversion interface is used to convert the data stored in the first memory model into SystemVerilog language data, and store the converted SystemVerilog language data in the address corresponding to the second memory model. The second data conversion interface is used to convert the data stored in the second memory model into data in a preset high-level language, and to store the converted preset high-level language data in the address corresponding to the first memory model.

8. The system according to claim 7, characterized in that, The verification IP is used to obtain verification data from the second memory model, process it, generate result data, and then store the result data in the first memory model.

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