A charge release circuit and method, and a display device

Abstract

The present disclosure provides a charge release circuit, belonging to the technical field of display, which can solve the problem that the existing charge release circuit is not enough to completely open the oxide thin film transistor in the display panel, and cannot completely release the residual charge in the display panel when the display panel is abnormally powered off. The charge release circuit is applied to a display panel, which comprises a gate line connected with a plurality of pixel units and a gate driving circuit for providing a gate driving signal for the gate line; the gate driving circuit comprises a shift register with a signal output end connected with the gate line; the charge release circuit comprises: a working level supply module configured to convert the initial working level of the first signal end thereof into a target working level, and a second signal end connected with a first non-working level signal end of the shift register; a first control module configured to short the first signal end and the second signal end in response to a trigger signal to output the initial working level output by the working level supply module as the output of the signal output end.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a charge release circuit and method, and a display device. Background Technology

[0002] With the development of display technology, people are increasingly pursuing products with high refresh rates and low power consumption. Compared with hydrogenated amorphous silicon thin film transistors (TFTs), oxide TFTs are gradually being used in next-generation display panels due to their advantages such as high mobility, good large-area uniformity, and lower manufacturing process temperature. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. On one hand, it provides a charge release circuit applied to a display panel, the display panel including multiple pixel units, gate lines connected to the pixel units, and a gate driving circuit for providing gate driving signals to the gate lines; the gate driving circuit includes a shift register with a signal output terminal corresponding to the gate line; the charge release circuit includes: a working level supply module having a first signal terminal and a second signal terminal, configured to convert an initial working level received by its first signal terminal into a target working level, the second signal terminal being configured to be connected to a first non-working level signal terminal of the shift register; a first control module configured to short-circuit the first signal terminal and the second signal terminal in response to a trigger signal, so as to use the initial working level output by the working level supply module as the output of the signal output terminal of each shift register; the trigger signal is used to characterize an abnormal power-down of the display panel.

[0004] Optionally, the charge release circuit further includes a monitoring module and a trigger signal generation module; the monitoring module is configured to monitor the operating voltage output by the power management chip of the display panel and send the monitoring result to the trigger signal generation module; the trigger signal generation module is configured to compare the monitoring result with a preset voltage threshold and generate the trigger signal when the monitoring result is less than the preset voltage threshold.

[0005] Optionally, the trigger signal generation module includes a voltage comparator; the voltage comparator has a voltage input terminal, a first reference voltage terminal, and a trigger signal output terminal; the voltage input terminal is connected to the monitoring module; the first reference voltage terminal is connected to a voltage signal equal to the preset voltage threshold; the trigger signal output terminal is connected to the first control module and outputs the trigger signal.

[0006] Optionally, the first control module includes a first transistor; the first electrode of the first transistor is connected to a first signal terminal, the second electrode is connected to a second signal terminal, and the control electrode is connected to the trigger signal generation module.

[0007] Optionally, the charge release circuit further includes a first storage capacitor and a second storage capacitor; a first terminal of the first storage capacitor is connected to a first signal terminal of the working level supply module, and a second terminal of the first storage capacitor is connected to a second reference voltage terminal; a first terminal of the second storage capacitor is connected to a second signal terminal of the working level supply module, and a second terminal of the second storage capacitor is connected to a second reference voltage terminal.

[0008] Optionally, the operating level supply module includes a low-dropout linear regulator.

[0009] Secondly, the present invention provides a charge release method for a charge release circuit, wherein the charge release circuit is applied to a display panel, the display panel including a plurality of pixel units, gate lines connected to the pixel units, and a gate driving circuit for providing gate driving signals to the gate lines; the gate driving circuit includes a shift register whose signal output terminal is correspondingly connected to the gate line; the charge release circuit includes a first control module and a working level supply module; the charge release method includes: receiving an initial working level through a first signal terminal of the working level supply module, and using the working level supply module to convert the initial working level to a target working level; the first control module, in response to a received trigger signal, short-circuiting the first signal terminal and the second signal terminal of the working level supply module, so that an initial voltage is applied to the first low-level signal terminal of the shift register, and controlling the signal output terminal of each shift register to output the initial working level, wherein the trigger signal is used to characterize the abnormal power-down of the display panel.

[0010] Optionally, the above method further includes: monitoring the operating voltage output by the power management chip of the display panel in real time through a monitoring module, and sending the monitoring result to a trigger signal generation module; comparing the monitoring result with a preset voltage threshold through the trigger signal generation module, and generating the trigger signal when the monitoring result is less than the preset voltage threshold.

[0011] Optionally, the absolute value of the preset voltage threshold is greater than 3.65V.

[0012] Thirdly, the present invention provides a display device including the charge release circuit as described above. Attached Figure Description

[0013] Figure 1A This is a circuit diagram of an exemplary shift register.

[0014] Figure 1B To and Figure 1A The timing diagram corresponding to the shift register is shown.

[0015] Figure 1C This is an exemplary charge release circuit diagram in the related technology.

[0016] Figure 2 This is a charge release circuit structure according to an embodiment of the present disclosure.

[0017] Figure 3A for Figure 2 An example of a charge release circuit structure.

[0018] Figure 3B To adopt Figure 1C The curve showing the change of the target high-level voltage value over time during the charge release circuit is shown.

[0019] Figure 3C To adopt Figure 3A The curve showing the change of the target high-level voltage value over time during the charge release circuit is shown.

[0020] Figure 4 for Figure 2 Another example of a charge release circuit structure.

[0021] Figure 5 for Figure 2 Another example of a charge release circuit structure. Detailed Implementation

[0022] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0024] It should be noted that the transistors used in the embodiments of this invention can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between them. In the embodiments of this invention, to distinguish the source and drain of the transistor, one of them is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. Furthermore, transistors can be classified into N-type and P-type according to their characteristics. The following embodiments use N-type transistors for illustration. When using an N-type transistor, the first terminal is the source, the second terminal is the drain, and when the gate input is high, the source and drain are conducting; the opposite is true for P-type transistors. It is conceivable that using a P-type transistor is something that those skilled in the art can easily conceive of without creative effort, and therefore it is also within the scope of protection of the embodiments of this invention.

[0025] Taking an N-type transistor as an example, its working level signal is a high-level signal, and its non-working level signal is a low-level signal; the corresponding working level terminal is a high-level signal terminal, and the non-working level terminal is a low-level signal terminal.

[0026] The display panel includes multiple gate lines and multiple data lines. These gate lines and data lines intersect to define multiple pixel areas, each of which contains a thin-film transistor (TFT) and a pixel unit. The TFT includes a gate connected to the gate line, a source connected to the data line, and a drain connected to the pixel electrode of the pixel unit. The structure of the display panel is explained using the extension direction of the gate lines as the row direction and the extension direction of the data lines as the column direction as an example. When driving the display panel to display an image, gate scan signals are written to the gate lines row by row to apply voltage to the gate and turn on the TFT. Simultaneously, data voltage signals are written to each data line to apply pixel voltage to the pixel electrode of the pixel unit through the source and drain, thus lighting up the pixel units in the display panel row by row. In other words, the display panel is lit up to display an image by charging the pixels in the display panel.

[0027] The gate scan signal is provided by the gate driver circuit, and the data voltage signal is provided by the source driver circuit. In related technologies, the gate driver circuit can be integrated into the gate driver chip, and the source driver circuit can be integrated into the source driver chip. To reduce the number of chips in the display panel and to achieve narrow bezel or bezel-less displays, the mainstream design integrates the gate driver circuit on the array substrate (Gate On Array; GOA). The gate driver circuit includes multiple cascaded shift register units integrated on the array substrate. Each shift register unit is connected to a gate line, providing the gate scan signal to the connected gate line.

[0028] To better understand how the shift register unit implements the output of the gate scan signal, the following explanation uses a specific example of the shift register unit.

[0029] Figure 1A Here is a circuit diagram of an exemplary shift register, such as... Figure 1A As shown, the shift register includes an input sub-circuit 1, an output sub-circuit 3, a cascaded sub-circuit 4, a first reset sub-circuit 21 and a second reset sub-circuit 22, two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', two third noise reduction sub-circuits 10 / 10', a first global reset sub-circuit 11, and a second global reset sub-circuit 12. The input sub-circuit 1 is configured to pre-charge the pull-up node PU in response to the input signal at the input terminal Input; the pull-up node PU is the connection node between the input sub-circuit 1, the output sub-circuit 3, and the two first pull-down sub-circuits 6 / 6'. The output sub-circuit 3 is configured to output the clock signal through the signal output terminal G_out in response to the potential of the pull-up node PU. The first reset sub-circuit 21 is configured to reset the pull-up node PU via a first low-level signal under the control of a reset signal. The second reset sub-circuit 22 is configured to reset the output of the signal output terminal G_out via a first low-level signal under the control of a reset signal. The cascade sub-circuit 4 is configured to output a clock signal through the cascade signal terminal OC in response to the potential of the pull-up node PU. The pull-down control sub-circuit is configured to control the potential of the pull-down node via the power supply voltage; one pull-down control sub-circuit is connected to one first pull-down sub-circuit, and the connection node between them is a pull-down node. The first pull-down sub-circuit is configured to pull down the potential of the electrically connected pull-down node via a second low-level signal in response to the potential of the pull-up node PU. The second pull-down sub-circuit is configured to pull down the potential of the electrically connected pull-down node via a second low-level signal in response to an input signal. The first noise reduction sub-circuit is configured to reduce the noise of the output of the pull-up node PU via a second low-level signal under the control of the pull-down node connected to it. The second noise reduction sub-circuit is configured to reduce the noise of the output of the signal output terminal G_out under the control of the connected pull-down node by a first low-level signal. The third noise reduction sub-circuit is configured to reduce the noise of the output of the cascaded signal terminal OC under the control of the connected pull-down node. The first global reset sub-circuit 11 is configured to discharge the pull-up node PU by a second low-level signal in response to the first global reset signal. The second global reset sub-circuit 12 is configured to discharge the output of the signal output terminal G_out by a first low-level signal in response to the second global reset signal.

[0030] The circuit consists of two pull-down control sub-circuits 5 / 5', two first pull-down sub-circuits 6 / 6', two second pull-down sub-circuits 7 / 7', two first noise reduction sub-circuits 8 / 8', two second noise reduction sub-circuits 9 / 9', and two third noise reduction sub-circuits 10 / 10'. Pull-down control sub-circuit 5' is connected to one first pull-down sub-circuit 6 and one second pull-down sub-circuit 7, with the connection node being the first pull-down node PD1. Pull-down control sub-circuit 5' is connected to one first pull-down sub-circuit 6' and one second pull-down sub-circuit 7', with the connection node being the first pull-down node PD1. The first pull-down node PD1 connects to one first noise reduction sub-circuit 8, one second noise reduction sub-circuit 9, and one third noise reduction sub-circuit 10. The second pull-down node PD2 connects to another first noise reduction sub-circuit 8', another second noise reduction sub-circuit 9', and another third noise reduction sub-circuit 10'. The two pull-down control subcircuits 5 / 5' in the shift register have the same structure and function, except that they operate in a time-sharing manner during shift register operation; that is, the timing sequence of the control signals used to control these two pull-down control subcircuits 5 / 5' is reversed. Similarly, the two first pull-down subcircuits 6 / 6' have the same structure and function and operate in a time-sharing manner; the two second pull-down subcircuits 7 / 7' have the same structure and function and operate in a time-sharing manner; the two first noise reduction subcircuits 8 / 8' have the same structure and function and operate in a time-sharing manner; the two second noise reduction subcircuits 9 / 9' have the same structure and function and operate in a time-sharing manner; and the two third noise reduction subcircuits 10 / 10' have the same structure and function and operate in a time-sharing manner. The first global reset signal can be a pre-frame enable signal, which discharges the pull-up node PU before the current frame scan.

[0031] Specifically, input sub-circuit 1 includes a first transistor M1. First reset sub-circuit 21 includes a second transistor M2. Second reset sub-circuit 11 includes a fourth transistor M4. Output sub-circuit 3 includes a third transistor M3 and a storage capacitor C1. Cascade sub-circuit 4 includes an eleventh transistor M11. First global reset sub-circuit 11 includes a fifteenth transistor M15. Second global reset sub-circuit 12 includes a fourteenth transistor M14. Each pull-down control sub-circuit includes a fifth transistor; the fifth transistors in the two pull-down control sub-circuits 5 / 5' are denoted as M5 and M5', respectively. Each first pull-down sub-circuit includes a sixth transistor; the sixth transistors in the two first pull-down sub-circuits 6 / 6' are denoted as M6 and M6', respectively. Each second pull-down sub-circuit includes a sixth transistor; the seventh transistors in the two second pull-down sub-circuits 7 / 7' are denoted as M7 and M7', respectively. Each first noise reduction sub-circuit includes a tenth transistor; the tenth transistors in the two first noise reduction sub-circuits 8 / 8' are denoted as M10 and M10', respectively. Each second noise reduction subcircuit includes a thirteenth transistor, and the thirteenth transistors in the two second noise reduction subcircuits 9 / 9' are denoted as M13 and M13', respectively. Each third noise reduction subcircuit includes a tenth transistor, and the twelfth transistors in the two third noise reduction subcircuits 10 / 10' are denoted as M12 and M12', respectively.

[0032] Furthermore, the gate and source of M1 are connected to the signal input terminal Input, and the drain of M1 is connected to the pull-up node PU. The gate of M2 is connected to the reset signal terminal Reset, the source of M2 is connected to the pull-up node PU, and the drain of M2 is connected to the second low-level signal terminal LVGL. The gate of M4 is connected to the reset signal terminal Reset, the source of M4 is connected to the signal output terminal G_out, and the drain of M4 is connected to the first low-level signal terminal VGL. The gate of M3 is connected to the pull-up node PU, the source of M3 is connected to the clock signal terminal CLK, and the drain of M3 is connected to the signal output terminal G_out. The gate of M11 is connected to the pull-up node PU, the source of M11 is connected to the clock signal terminal CLK, and the drain of M11 is connected to the cascaded signal terminal OC. The first terminal of C1 is connected to the pull-up node PU, and the second terminal of C1 is connected to the signal output terminal G_out. The gate and source of M5 are both connected to the first power supply voltage terminal VDD1, and the drain of M5 is connected to the first pull-down node PD1. The gate and source of M5' are both connected to the second power supply voltage terminal VDD2, and the drain of M5 is connected to the second pull-down node PD2. The gate of M6 is connected to the pull-up node PU, the source of M6 is connected to the first pull-up node PU, and the drain of M6 is connected to the second low-level signal terminal LVGL. The gate of M6' is connected to the pull-up node PU, the source of M6' is connected to the second pull-up node PU, and the drain of M6' is connected to the second low-level signal terminal LVGL. The gate of M7 is connected to the signal input terminal Input, the source of M7 is connected to the first pull-up node PU, and the drain of M7 is connected to the second low-level signal terminal LVGL. The gate of M7' is connected to the signal input terminal Input, the source of M7' is connected to the second pull-up node PU, and the drain of M7' is connected to the second low-level signal terminal LVGL. The gate of M10 is connected to the first pull-down node PD1, the source of M10 is connected to the pull-up node PU, and the drain of M10 is connected to the second low-level signal terminal LVGL. M10''s gate is connected to the second pull-down node PD2, its source is connected to the pull-up node PU, and its drain is connected to the second low-level signal terminal LVGL. M12's gate is connected to the first pull-down node PD1, its source is connected to the cascade signal terminal OC, and its drain is connected to the second low-level signal terminal LVGL. M12's gate is connected to the second pull-down node PD2, its source is connected to the cascade signal terminal OC, and its drain is connected to the second low-level signal terminal LVGL. M13's gate is connected to the first pull-down node PD1, its source is connected to the signal output terminal G_out, and its drain is connected to the first low-level signal terminal VGL. M13's gate is connected to the second pull-down node PD2, its source is connected to the signal output terminal G_out, and its drain is connected to the second low-level signal terminal LVGL. The gate of M14 is connected to the second global reset signal terminal Total_RST, the source of M14 is connected to the signal output terminal G_out, and the drain of M14 is connected to the first low-level signal terminal VGL.The gate of M15 is connected to the first global reset signal terminal Total_RST1, the source of M15 is connected to the signal output terminal G_out, and the drain of M15 is connected to the second low-level signal terminal LVGL.

[0033] Figure 1B To and Figure 1A The timing diagram corresponding to the shift register shown is included; combined with... Figure 1B The operation of this shift register can specifically include the following stages:

[0034] During the discharge phase, before the frame is displayed, a high-level signal is input to the first global reset signal terminal Total_RST1 and the second global reset signal terminal Total_RST. The fourteenth and fifteenth transistors are turned on, and the second low-level signal input to the second low-level signal terminal LVGL discharges the pull-up node PU and the signal output terminal G_out to prevent residual charge in the pull-up node PU and the signal output terminal G_out from causing display abnormalities.

[0035] During the input phase, a high-level signal is input to the signal input terminal Input, M1 is turned on, and the pull-up node PU is pulled high through the high-level signal, charging C1. At the same time, M6 and M6', M7 and M7' are all turned on, pulling down the first pull-down node PD1 and the second pull-down node PD2 to avoid affecting the potential of the pull-up node PU.

[0036] During the output phase, since the pull-up node PU is pulled high during the input phase, M3 and M13 are enabled, and the high-level signal input from the clock signal terminal CLK is output to the connected gate line through the signal output terminal G_out. At the same time, the cascaded signal terminal OC outputs the same signal as the signal output terminal G_out, that is, it outputs a high-level signal to the pull-up reset signal terminal Reset of the previous stage shift register unit and the signal input terminal Input of the next stage shift register unit.

[0037] During the reset phase, a high-level signal is input to the Reset terminal, and M2 and M4 are enabled. The second low-level signal input to the second low-level signal terminal LVGL pulls down the potential of the pull-up node PU and the signal output terminal G_out to reset them. Simultaneously, the pull-down control node and the first pull-down node PD1 are both high-level signals, and M10, M13, and M12 are enabled. These signals reduce noise on the outputs of the pull-up node PU, the signal output terminal G_out, and the cascaded signal terminal OC, respectively, until the pull-up node PU is pulled high at the start of the next frame scan.

[0038] In the aforementioned 19T1C shift register, the two pull-down control sub-circuits operate in a time-sharing manner. Therefore, the VDD1 and VDD2 signals corresponding to the first power supply voltage terminal VDD1 and the second power supply voltage terminal VDD2, respectively connected to the two pull-down control sub-circuits, can switch during the blanking phase between two displayed frames, replacing single-channel VDD DC noise reduction. Correspondingly, the first pull-down node PD1 and the second pull-down node PD2 signals switch between high and low levels following the switching of VDD1 and VDD2 signals. The first pull-down node PD1 and the second pull-down node PD2 have two discharge paths: 1. When the current row signal input terminal Input is written with a high-level signal, it discharges through M7 and M7'; 2. When the current row pull-up node PU is at a high level, it discharges through M6 and M6'.

[0039] Abnormal power-downs caused by sudden shutdowns of the display device or firmware upgrades are unavoidable during user operation. At the moment of an abnormal power-down, residual charge within the display panel may remain due to prolonged operation. For LCD devices, there is no dedicated path for this residual charge to dissipate. Prolonged retention of this charge within the display panel can lead to DC bias, causing screen flickering when the panel is turned on again, or causing voltage drift on the common electrode within the display panel, resulting in uneven visual effects between adjacent pixels.

[0040] To release the aforementioned residual charge, some related technologies have been applied to charge release circuits in display panels. The following are examples... Figure 1A Taking the shift register shown as an example, we will introduce the circuit structure and working principle of related technologies. Figure 1A The shift register shown has a high level for operation and a low level for non-operation.

[0041] The charge release circuit in the related technology includes a working level supply module, which has a first signal terminal and a second signal terminal. This working level supply module is as follows: Figure 1C As shown, it includes a low-dropout linear regulator (LDO). The first signal terminal is connected to the initial operating level, i.e., the initial high level VGH. This initial high level VGH is converted to the target operating level, i.e., the target high level VGHO, by the LDO. The second signal terminal is connected to the first non-operating level signal terminal of the shift register, i.e., the first low level signal terminal VGL; simultaneously, the second signal terminal provides the target high level signal VGHO to the first power supply voltage terminal VDD1 and the second power supply voltage terminal VDD2. It is understood that the second signal terminal is not directly connected to the first low level signal terminal VGL; an OR gate is provided between them. This OR gate responds to the trigger signal Xon, which characterizes an abnormal power-down of the display panel, and is used to control the first low level signal terminal VGL to connect to the low level signal VGL during normal operation of the display panel, and to connect to the second signal terminal during abnormal power-down of the display panel.

[0042] The working principle of the aforementioned related technology is as follows: Since the first power supply voltage terminal VDD1 or the second power supply voltage terminal VDD2 is connected to the target high level VGHO, even if the display panel is abnormally powered down, the first pull-down node PD1 or the second pull-down node PD2 is still pulled high, causing the thirteenth transistor M13 / M13' to turn on. At this time, the aforementioned OR gate responds to the trigger signal Xon, connecting the first low-level signal terminal VGL to the second signal terminal. The target high level VGHO is input through the first low-level signal terminal VGL of the shift register, and through the thirteenth transistor M13 / M13', the signal output terminal G_out of the shift register outputs the target high level VGHO. The reason why the initial high level VGH is converted into the target high level VGHO by the low-dropout linear regulator LDO before being input to the shift register unit is that the initial high level VGH is formed by multiplying the analog voltage signal AVDD. The voltage value of the initial high level VGH cannot be adjusted. Therefore, it needs to be converted into an adjustable voltage signal—the target high level VGHO—before being transmitted to the display panel. Clearly, the voltage value of the target high level VGHO is less than that of the initial high level VGH.

[0043] With increasing demands for higher power consumption and refresh rates in displays, oxide-based thin-film transistors (TFTs) are increasingly being used in display panels due to their advantages such as high mobility and good large-area uniformity. A significant characteristic of oxide TFTs is their high on-state current (Ion) and low off-state current (Ioff). Therefore, compared to hydrogenated amorphous silicon thin-film transistors (HSi) or low-temperature polycrystalline silicon (LTPS) thin-film transistors (LTPS), displays based on oxide TFTs are less likely to release residual charge within the pixel units at the moment of power-off. This inherent characteristic of oxide TFTs makes them more prone to residual charge at the moment of abnormal power-off. Furthermore, after conducting the "8585" reliability test (exposing the product to an environment of 85 degrees Celsius and 85% humidity), the oxide TFTs experience characteristic drift, resulting in a smaller on-state current. This reduces the output signal of the GOA (Gate of Action), which is insufficient to turn on the switching transistors in the pixel units of the display panel, thus failing to fully release the residual charge.

[0044] In summary, due to the inherent properties of oxide thin-film transistors and the relatively small voltage value of the target high-level VGHO in existing technologies, the output signal of the shift register signal output terminal G_out is insufficient to fully turn on the switching transistors of the pixel unit during abnormal power-down, thus failing to fully release residual charge. Therefore, how to fully turn on the switching transistors of the pixel units in the display panel and completely release the residual charge in the panel is a problem that needs to be solved in related technologies.

[0045] To address the aforementioned technical problems, this disclosure provides a charge release circuit applied to a display panel. The display panel includes multiple pixel units, gate lines connected to the pixel units, and a gate drive circuit for providing gate drive signals to the gate lines. The gate drive circuit includes a shift register with a signal output terminal G_out corresponding to the gate line. Figure 2 As shown, the charge release circuit includes a working level supply module and a first control module. The working level supply module has a first signal terminal and a second signal terminal, configured to convert the initial working level received at its first signal terminal into a target working level. The second signal terminal is configured to connect to the first non-working level signal terminal of the shift register. The first control module is configured to short-circuit the first and second signal terminals in response to a trigger signal Xon, so that the initial working level output by the working level supply module is used as the output of the signal output terminal G_out of each shift register. The trigger signal Xon is used to characterize an abnormal power-down of the display panel. Those skilled in the art will understand that the second signal terminal is not directly connected to the first low-level signal terminal VGL; an OR gate is provided between them. This OR gate, in response to the trigger signal Xon characterizing an abnormal power-down of the display panel, controls the first low-level signal terminal VGL to connect to a low-level signal VGL during normal operation of the display panel and to connect to the second signal terminal during abnormal power-down.

[0046] The following is Figure 1A Taking the shift register shown as an example, the working principle of the embodiments of this disclosure is introduced. Figure 1A Taking the shift register shown as an example, the initial working level mentioned in this embodiment is the initial high level VGH, the target working level is the target high level VGHO, and the first non-working level signal terminal is the first low level signal terminal VGL.

[0047] The working principle of this embodiment is as follows: Since the first power supply voltage terminal VDD1 or the second power supply voltage terminal VDD2 is connected to the target high level VGHO, even if the display panel is abnormally powered down, the first pull-down node PD1 or the second pull-down node PD2 is still pulled high, causing the thirteenth transistor M13 / M13' to turn on. At this time, the above-mentioned OR gate responds to the trigger signal Xon and connects the first low-level signal terminal VGL to the second signal terminal; at the same time, the first control module responds to the trigger signal Xon and short-circuits the first signal terminal and the second signal terminal, that is, short-circuits the target high level VGHO with the initial high level VGH. Therefore, the second signal terminal outputs the initial high level VGH, which is input through the first low-level signal terminal VGL of the shift register and, through the thirteenth transistor M13 / M13', causes the signal output terminal G_out of the shift register to output the initial high level VGH.

[0048] Because this embodiment adds a first control module to the charge release circuit, when it receives the trigger signal Xon indicating an abnormal power-down of the display panel, it short-circuits the second signal terminal of the operating level supply module to the first signal terminal, making the target operating level output by the second signal terminal the initial operating level. This causes the signal output terminal G_out of the shift register to output the initial operating level. Since the voltage value of the initial operating level is greater than the target operating level, this increases the output signal of the shift register signal output terminal G_out, which helps to more fully open the switching transistors of the pixel units, thereby solving the problem that residual charge in the display panel cannot be completely released due to the decrease in Ion of the oxide thin-film transistors.

[0049] The charge release circuit of this disclosure embodiment is described in detail below with reference to specific examples.

[0050] like Figure 3A As shown, in some examples, the operating level supply module includes a low-dropout linear regulator (LDO), whose first signal terminal receives an initial operating level of initial high level VGH, and whose second signal terminal outputs a target operating level of target high level VGHO. Clearly, the voltage value of the target high level VGHO obtained by the LDO is less than the initial high level VGH. The first control module includes a first transistor, whose first electrode is connected to the first signal terminal of the operating level supply module, its second electrode is connected to the second signal terminal, and its control electrode is connected to a trigger signal Xon. When the display panel is abnormally powered down, the control electrode of the first transistor receives the trigger signal Xon and conducts, shorting the first and second signal terminals of the LDO. At this time, the second signal terminal outputs the initial high level VGH, meaning that the signal output terminal G_out of the shift register outputs the initial high level VGH to the switching transistor of the pixel unit. Relative to... Figure 1C The related technology shown in this example effectively increases the voltage value of the signal received by the switching transistor of the pixel unit, allowing the switching transistor of the pixel unit to be fully turned on, thereby fully releasing the charge remaining in the display panel when it is abnormally powered down. In addition, compared with other types of switching elements, the first transistor is smaller in size and easier to integrate into the driver chip of the display panel, thus increasing the original size and cost of the chip by almost nothing.

[0051] Figure 3B To adopt Figure 1C When the relevant technology is shown, the target high level VGHO output by the signal output terminal G_out of the shift register, Figure 3C To adopt Figure 3A In the charge release circuit shown, the target high level VGHO (actually the initial high level VGH) output by the shift register signal output terminal G_out is used. Figure 3BCurve L1 in the figure represents the change in the voltage value of the target high level VGHO over time. Figure 3B As can be seen, at the instant the display panel abnormally lost power, the voltage value of the target high level VGHO reached 7.90V; Figure 3C Curve L1' in the figure represents the change in the target high-level voltage VGHO over time after shorting the second signal terminal of the low-dropout linear regulator (LDO) to the first signal terminal. As can be seen from the figure, at the instant the display panel abnormally powers down, the target high-level voltage VGHO can reach 17.7V. This indicates the use of... Figure 3A When the charge release circuit shown is used, the voltage value of the signal output by the shift register signal output terminal G_out can be effectively increased. In other words, the signal voltage value received by the gate of the switching transistor of the pixel unit becomes larger, so it can be opened more fully, and the charge remaining in the display panel can be released more fully.

[0052] Further as Figure 4 As shown, in some examples, the charge release circuit further includes a monitoring module and a trigger signal Xon generation module. The monitoring module is configured to monitor the operating voltage output by the power management chip (PMIC) of the display panel and send the monitoring result to the trigger signal Xon generation module. Optionally, the monitoring module may include a voltage sampling circuit. The trigger signal Xon generation module is configured to compare the monitoring result with a preset voltage threshold and generate a trigger signal Xon when the monitoring result is less than the preset voltage threshold. Optionally, the trigger signal Xon generation module may include a voltage comparator. The voltage comparator has a voltage input terminal, a first reference voltage terminal, and a trigger signal Xon output terminal. The voltage input terminal is connected to the monitoring module to receive the monitoring result. The first reference voltage terminal is connected to a voltage signal equal to the preset voltage threshold, referred to as the first reference voltage Vref_1. The trigger signal Xon output terminal is connected to the first control module and outputs the trigger signal Xon; specifically, in the example of Figure 3, the trigger signal Xon output terminal of the voltage comparator is connected to the control electrode of the first transistor.

[0053] For example, the first reference voltage Vref_1 can be set to ±3.65V. That is, when the absolute value of the monitoring result output by the monitoring module decreases to 3.65V, the trigger signal Xon generation module outputs a trigger signal Xon to the first control module, causing the second signal terminal of the working level supply module to short-circuit with the first signal terminal, thus raising its target high level VGHO to the initial high level VGH. Preferably, the first reference voltage Vref_1 can be set to ±4.55V. That is, when the absolute value of the monitoring result output by the monitoring module decreases to 4.65V, the trigger signal Xon generation module outputs a trigger signal Xon to the first control module, causing the second signal terminal of the working level supply module to short-circuit with the first signal terminal, thus raising its target high level VGHO to the initial high level VGH. Compared to the example where the first reference voltage Vref_1 is set to ±3.65V, increasing the first reference voltage Vref_1 to ±4.45V has the effect of enabling the trigger signal Xon generation module to "detect" the abnormal power-down of the display panel earlier, thereby issuing the trigger signal Xon earlier. This extends the time for the shift register G_out to output a high-level signal, which in turn extends the time for the TFTs in the display panel to receive the high-level G_out signal, helping the TFTs to open more fully.

[0054] Or further as Figure 5 As shown, in some examples, the charge release circuit further includes a first storage capacitor C1 and a second storage capacitor C2. The first terminal of the first storage capacitor C1 is connected to the first signal terminal of the operating level supply module, and the second terminal is connected to the second reference voltage terminal. The first terminal of the second storage capacitor C2 is connected to the second signal terminal of the operating level supply module, and the second terminal is connected to the second reference voltage terminal. Optionally, the second reference voltage terminal is grounded.

[0055] For example, the capacitance of the first storage capacitor C1 is 1μF, and the capacitance of the second storage capacitor C2 can also be 1μF. Preferably, the capacitance of the second storage capacitor C2 can be increased to 2.2μF or 4.7μF. Compared with the 1μF second storage capacitor C2, it has a stronger storage capacity, that is, it stores a larger amount of charge. To a certain extent, it can slow down the power-down speed of the high-level output at the shift register signal output terminal G_out, which is equivalent to extending the output time of the high level, thereby extending the turn-on time of the TFT in the display panel, which is conducive to its full opening.

[0056] Secondly, embodiments of this disclosure provide a charge release method for a charge release circuit. The charge release circuit, as described above, includes a first control module and a working level supply module. The charge release method includes:

[0057] Step S1: Connect the initial working level to the first signal terminal of the working level supply module, and use the working level supply module to convert the initial working level to the target working level. For example, the initial working level is an initial high level VGH, the working level supply module includes a low dropout linear regulator LDO, and the target working level is a target high level VGHO.

[0058] Step S2: In response to the received trigger signal Xon, the first control module short-circuits the first and second signal terminals of the operating level supply module, so that the first low-level signal terminal of the shift register is loaded with an initial voltage, and controls the signal output terminal G_out of each shift register to output the initial operating level. The trigger signal Xon is used to characterize the abnormal power-down of the display panel. For example, the first control module can be a first transistor.

[0059] Specifically, the charge release circuit, such as Figure 3A As shown, it also includes a monitoring module and a trigger signal Xon generation module. The charge release method also includes:

[0060] Step SS1: Monitor the operating voltage output by the power management chip PMIC of the display panel in real time through the monitoring module, and send the monitoring results to the trigger signal Xon generation module.

[0061] Step SS2: The trigger signal Xon generation module compares the monitoring result with the preset voltage threshold, and generates the trigger signal Xon when the monitoring result is less than the preset voltage threshold.

[0062] Thirdly, embodiments of this disclosure provide a display device including the charge release circuit described above.

[0063] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A charge release circuit applied to a display panel, the display panel comprising a plurality of pixel units, gate lines connected to the pixel units, and a gate drive circuit for providing gate drive signals to the gate lines; the gate drive circuit comprising shift registers with signal output ends connected to the gate lines correspondingly; characterized in that the charge release circuit comprising: a working level supply module having a first signal end and a second signal end, configured to convert an initial working level received by the first signal end thereof into a target working level, the second signal end being configured to be connected to a first non-working level signal end of the shift registers; a first control module configured to short the first signal end and the second signal end in response to a trigger signal, so as to output the initial working level output by the working level supply module as the output of the signal output end of each of the shift registers; the trigger signal being used to represent an abnormal power-off of the display panel.

2. The charge release circuit according to claim 1, characterized by, Further comprising a monitoring module and a trigger signal generation module; the monitoring module being configured to monitor a working voltage output by a power management chip of the display panel, and send a monitoring result to the trigger signal generation module; the trigger signal generation module being configured to compare the monitoring result with a preset voltage threshold, and generate the trigger signal when the monitoring result is less than the preset voltage threshold.

3. The charge release circuit according to claim 2, characterized by, the trigger signal generation module comprising a voltage comparator; the voltage comparator having a voltage input end, a first reference voltage end, and a trigger signal output end; the voltage input end being connected to the monitoring module; the first reference voltage end being connected to a voltage signal equal to the preset voltage threshold; the trigger signal output end being connected to the first control module and outputting the trigger signal.

4. The charge release circuit of claim 1, wherein, the first control module comprising a first transistor; a first pole of the first transistor being connected to the first signal end, a second pole thereof being connected to the second signal end, and a control pole thereof being connected to the trigger signal generation module.

5. The charge release circuit of claim 1, wherein, the charge release circuit further comprising a first storage capacitor and a second storage capacitor; a first end of the first storage capacitor being connected to the first signal end of the working level supply module, and a second end thereof being connected to a second reference voltage end; a first end of the second storage capacitor being connected to the second signal end of the working level supply module, and a second end thereof being connected to the second reference voltage end.

6. The charge release circuit of claim 1, wherein, the working level supply module comprising a low-dropout linear regulator.

7. A charge release method of a charge release circuit, wherein, the charge release circuit applied to a display panel, the display panel comprising a plurality of pixel units, gate lines connected to the pixel units, and a gate drive circuit for providing gate drive signals to the gate lines; the gate drive circuit comprising shift registers with signal output ends connected to the gate lines correspondingly; the charge release circuit comprising a first control module and a working level supply module; characterized in that the charge release method comprises: connecting an initial working level to a first signal end of the working level supply module, and converting the initial working level into a target working level by the working level supply module. The first control module short-circuits the first signal end and the second signal end of the working level supply module in response to the received trigger signal, so that the first low-level signal end of the shift register is loaded with an initial voltage, and the signal output ends of the shift registers are controlled to output an initial working level, and the trigger signal is used to represent abnormal power-off of the display panel.

8. The charge release method according to claim 7, wherein, Further comprising: The monitoring module monitors the working voltage output by the power management chip of the display panel in real time, and sends the monitoring result to the trigger signal generation module; The trigger signal generation module compares the monitoring result with a preset voltage threshold, and generates the trigger signal when the monitoring result is less than the preset voltage threshold.

9. The charge release method according to claim 8, wherein, The absolute value of the preset voltage threshold is greater than 3.65V.

10. A display device comprising the charge release circuit according to any one of claims 1-6.

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