Method and system for cooperatively suppressing common-mode voltage and current harmonics of coupled three-level inverter

Abstract

The invention belongs to the field of power electronic power conversion, and provides a method and system for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter. The method comprises the following steps: judging the sector and region where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector; selecting four basic voltage vectors with low common-mode voltage amplitudes to synthesize the reference voltage vector; writing a volt-second balance equation according to the selected basic voltage vectors, and calculating the duty cycle thereof; updating the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, a given value of a DC side capacitor voltage deviation, and an actual value of the DC side capacitor voltage deviation, so as to realize independent control of the capacitor voltage; designing a switch sequence according to the sector and region where the reference voltage vector is located, a given value of a DC side capacitor voltage deviation, and an actual value of the DC side capacitor voltage deviation, converting the switch sequence into a PWM drive signal of a power switch tube, and controlling the operation of the coupled three-level inverter.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and in particular relates to a method and system for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] Three-level inverters are widely used in photovoltaic power generation, composite energy storage, and motor drive due to their advantages such as low voltage stress of power switch tubes and good system output waveform quality. Neutral-Point Clamped (NPC) and T-Type three-level inverters are the two most commonly used circuit topologies, but they still have the limitation of a large number of power switch tubes. Coupled three-level inverters use fewer power switch tubes to reduce system costs and maintain multi-level output functions, and have broad application prospects.

[0004] Common-mode voltage (CMV) is generated by the high-frequency switching action of the power switch tube. In photovoltaic power generation systems, it causes leakage current, resulting in inverter output current distortion and power loss, and even threatening personal safety. In high-power power transmission systems, the common-mode leakage current generated by it continuously flows through the motor insulation, causing serious damage to the motor. At the same time, it generates bearing current, damages the motor bearings, and increases the system electromagnetic interference.

[0005] The inventors found that the existing common-mode voltage suppression method is mainly aimed at the working condition where the two capacitor voltages on the DC side of the coupled three-level inverter are equal. When the coupled three-level inverter operates under the working condition where the capacitor voltages on the DC side are unequal, the output current harmonic content of the coupled three-level inverter will increase. In addition, the output state of this topology is limited and the neutral vector cannot be generated. Therefore, the existing control method cannot be directly applied. Therefore, the method for simultaneously suppressing the common-mode voltage and current harmonics suitable for the unbalanced DC side midpoint voltage needs to be studied urgently. Summary of the invention

[0006] In order to solve the above problems, the present invention proposes a method and system for coordinated suppression of common-mode voltage and current harmonics of a coupled three-level inverter. The present invention can achieve common-mode voltage suppression of a coupled three-level inverter under the condition of unbalanced DC side capacitor voltage while maintaining good output current waveform quality, and is suitable for the case of balanced DC side capacitor voltage.

[0007] According to some embodiments, a first solution of the present invention provides a method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter, using the following technical solution:

[0008] A method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter includes:

[0009] According to the amplitude and phase angle of the reference voltage vector, determine the sector and region where the reference voltage vector is located;

[0010] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, four basic voltage vectors with low common mode voltage amplitudes are selected to synthesize the reference voltage vector;

[0011] According to the selected basic voltage vector, write the volt-second balance equation and use the indirect calculation method to calculate its duty cycle;

[0012] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, the duty cycle of the basic voltage vector is updated to achieve independent control of the capacitor voltage;

[0013] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation, the switching sequence is designed and converted into a PWM drive signal of the power switch tube to control the operation of the coupled three-level inverter.

[0014] According to some embodiments, a second solution of the present invention provides a common-mode voltage and current harmonic cooperative suppression system for a coupled three-level inverter, which adopts the following technical solution:

[0015] The common mode voltage and current harmonic cooperative suppression system of coupled three-level inverter includes:

[0016] A sector determination module is configured to determine the sector and region where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector;

[0017] The basic voltage vector selection module is configured to select four basic voltage vectors with low common mode voltage amplitudes to synthesize a reference voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation, and the actual value of the DC side capacitor voltage deviation;

[0018] The basic voltage vector duty cycle calculation module is configured to list a volt-second balance equation according to the selected basic voltage vector and calculate its duty cycle using an indirect calculation method;

[0019] The capacitor voltage independent control module is configured to update the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation to achieve independent control of the capacitor voltage;

[0020] The drive signal generation module is configured to design a switch sequence according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation, convert the switch sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0021] According to some embodiments, a third aspect of the present invention provides a computer-readable storage medium.

[0022] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps in the method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter as described in the first aspect above.

[0023] According to some embodiments, a fourth aspect of the present invention provides a computer device.

[0024] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in the method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter as described in the first aspect above are implemented.

[0025] Compared with the prior art, the present invention has the following beneficial effects:

[0026] Compared with the traditional common-mode voltage suppression method, the method of the present invention eliminates the even harmonics caused by the unbalanced capacitor voltage on the DC side of the coupled three-level inverter, and reduces the total harmonic distortion rate of the three-phase output current. Under the conditions of balanced and unbalanced capacitor voltage on the DC side, the method of the present invention can effectively suppress the common-mode voltage of the coupled three-level inverter and maintain high-quality output current. Compared with the traditional virtual vector modulation method and the traditional space vector modulation method, the method of the present invention effectively suppresses the common-mode voltage of the coupled three-level inverter; the present invention suppresses the common-mode voltage of the coupled three-level inverter according to different sectors, regions and capacitor voltage given values ​​(V * diff ) and the difference between the two capacitor voltages on the DC side (V diff ), by modifying the duty cycle of the basic voltage vector, the DC side capacitor voltage can be independently controlled.

[0027] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0029] Figure 1 It is the circuit topology diagram of the coupled three-level inverter;

[0030] Figure 2 It is the space vector diagram of the coupled three-level inverter when the DC side unbalance factor is greater than 0;

[0031] Figure 3 It is the space vector diagram of the coupled three-level inverter when the DC side unbalance factor is less than 0;

[0032] Figure 4 This is a block diagram of a method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to Embodiment 1 of the present invention;

[0033] Figure 5 Schematic diagram of the switching sequence when the reference voltage vector is located in sector 1, region A;

[0034] Figure 6 When the reference voltage vector is located in sector 1, region B and V * diff –V diff Schematic diagram of the shutdown sequence when ≤0;

[0035] Figure 7 When the reference voltage vector is located in sector 1, region B and V * diff –V diff >0 when the switching sequence diagram;

[0036] FIG8(a) is an experimental waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0.2, and the modulation index is 0.8;

[0037] FIG8( b ) is an experimental waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is -0.2, and the modulation index is 0.8;

[0038] FIG8(c) is an experimental waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0, and the modulation index is 0.8;

[0039] FIG9( a ) is an experimental waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC side unbalance factor is 0.2, and the modulation index is 0.8;

[0040] FIG9( b ) is an experimental waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC side unbalance factor is -0.2, and the modulation index is 0.8;

[0041] FIG9( c ) is an experimental waveform diagram when the system adopts the control method of the first embodiment of the present invention, the DC side unbalance factor is 0, and the modulation index is 0.8;

[0042] FIG10( a ) is an experimental waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0.2, and the modulation index is 0.4;

[0043] FIG10( b ) is an experimental waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is -0.2, and the modulation index is 0.4;

[0044] FIG10( c ) is an experimental waveform diagram when the system adopts the traditional space vector modulation method, the DC side unbalance factor is 0, and the modulation index is 0.4;

[0045] FIG11( a ) is an experimental waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC side unbalance factor is 0.2, and the modulation index is 0.4;

[0046] FIG11( b ) is an experimental waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC side unbalance factor is -0.2, and the modulation index is 0.4;

[0047] FIG11( c ) is an experimental waveform diagram when the system adopts the control method of Embodiment 1 of the present invention, the DC side unbalance factor is 0, and the modulation index is 0.4;

[0048] FIG. 12( a ) shows a system using the control method of Embodiment 1 of the present invention, with the modulation index set to 0.8 and the capacitor voltage set value (V * diff ) Experimental waveform when switching from 20V to 0V;

[0049] FIG12(b) shows a system using the control method of Embodiment 1 of the present invention, with the modulation index set to 0.8 and the capacitor voltage set value (V * diff ) Experimental waveform when switching from -20V to 0V;

[0050] FIG. 12( c ) shows a system using the control method of Embodiment 1 of the present invention, with the modulation index set to 0.4 and the capacitor voltage set value (V * diff ) Experimental waveform when switching from 20V to 0V;

[0051] FIG. 12( d ) shows a system using the control method of Embodiment 1 of the present invention, with the modulation index set to 0.4 and the capacitor voltage set value (V * diff ) Experimental waveform when switching from -20V to 0V. DETAILED DESCRIPTION

[0052] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0053] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0054] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0055] In the absence of conflict, the embodiments of the present invention and the features of the embodiments may be combined with each other.

[0056] Embodiment 1

[0057] This embodiment provides a method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter. In this embodiment, the method includes the following steps:

[0058] According to the amplitude and phase angle of the reference voltage vector, determine the sector and region where the reference voltage vector is located;

[0059] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, four basic voltage vectors with low common mode voltage amplitudes are selected to synthesize the reference voltage vector;

[0060] According to the selected basic voltage vector, write the volt-second balance equation and use the indirect calculation method to calculate its duty cycle;

[0061] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, the duty cycle of the basic voltage vector is updated to achieve independent control of the capacitor voltage;

[0062] According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation, the switching sequence is designed and converted into a PWM drive signal of the power switch tube to control the operation of the coupled three-level inverter.

[0063] According to the selected basic voltage vector, the volt-second balance equation is listed, and the duty cycle is calculated using an indirect calculation method, specifically:

[0064] When the reference voltage vector is located in region A of each sector, the four closest basic voltage vectors are selected to construct the volt-second balance equation;

[0065] When the reference voltage vector is located in area A of each sector, the duty cycle of one of the small vectors is used as the solution value, and the duty cycles of the other three basic voltage vectors are determined by the indirect method;

[0066] When the reference voltage vector is located in region B of each sector, a large vector, two small vectors and a zero vector are selected to construct the volt-second balance equation;

[0067] When the reference voltage vector is located in region B of each sector, the volt-second balance equation is simplified, and the duty cycle of the large vector is used as the solution value, and the duty cycles of the other three vectors are determined using an indirect method.

[0068] The method of updating the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation to realize independent control of the capacitor voltage includes:

[0069] The difference between the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation is sent to the PI controller, and the absolute value of its output is calculated to obtain the correction value of the basic voltage vector duty cycle allocation factor;

[0070] The duty cycle of the basic voltage vector is updated according to the sector and region where the reference voltage vector is located, and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation.

[0071] The system structure of the coupled three-level inverter is as follows: Figure 1 As shown in the figure, the system consists of two groups of photovoltaic arrays, DC side capacitors (C1 and C2), coupled three-level inverters and loads. By connecting a group of photovoltaic arrays at both ends of each DC side capacitor, the system control strategy is further designed to realize the independent maximum power point tracking (MPPT) function of the two groups of photovoltaic arrays, effectively overcoming the efficiency reduction caused by component power mismatch and local shadow, thereby improving system efficiency and power generation.

[0072] The power switch tube refers to an insulated-gate bipolar transistor (IGBT); the power switch tube may also be implemented by transistors in other forms, which may be selected according to the actual needs of technicians in this field.

[0073] Like the traditional three-level inverter, the coupled three-level inverter has three switching states: P, O and N. Select the DC side neutral point O (see Figure 1 ) as a reference, when the switch state is P, the bridge arm output voltage is +V C1; When the switch state is O, the bridge arm output voltage is 0; when the switch state is N, the bridge arm output voltage is -V C2 .

[0074] To facilitate analysis, the DC side unbalance factor is defined as for:

[0075]

[0076] Among them, V C1 and V C2 are the voltages across the upper and lower capacitors, V diff is the difference between the two capacitor voltages on the DC side (i.e. V diff =V C1 -V C2 ), V dc It is the sum of the voltages of the two capacitors on the DC side.

[0077] Based on formula (1), the expressions of the upper and lower capacitor voltages on the DC side are:

[0078]

[0079] The common mode voltage is defined as the average value of the three-phase output phase voltage, that is:

[0080]

[0081] Among them, v cm is the common mode voltage, v ao 、v bo and v co is the three-phase output phase voltage of the coupled three-level inverter.

[0082] Table 1 shows the basic voltage vectors and common-mode voltage amplitudes of the coupled three-level inverter. Obviously, the basic voltage vectors with high common-mode voltage amplitudes in the small vectors and zero vectors are [PPO], [OPP], [POP], [ONN], [NON], [NNO], [PPP], and [NNN]. Therefore, when designing the modulation method, the system common-mode voltage can be suppressed by abandoning the basic voltage vectors with high common-mode voltage amplitudes.

[0083] Table 1 Basic voltage vectors and common-mode voltage of coupled three-level inverter

[0084]

[0085] Figure 2 and Figure 3They are the space vector diagrams of the coupled three-level inverter when the unbalance factor on the DC side is greater than and less than 0, respectively. The entire space vector diagram is divided into 6 sectors (i.e., sector 1-sector 6), and each sector is further divided into 2 small areas (i.e., area A and area B). It can be seen that under the condition of unbalanced midpoint voltage on the DC side, the positions of the large vector and the zero vector remain unchanged, that is, the same as when the midpoint voltage is balanced; the position of the small vector is offset, and the small vector no longer maintains the redundant characteristics, which makes the implementation process of the space vector modulation method extremely complicated.

[0086] Figure 4 The control block diagram of the method of the present invention is shown in FIG. In order to achieve the goals of common mode voltage suppression, independent control of DC side capacitor voltage, and low harmonic control of output current, a control method is designed, which specifically includes the following steps:

[0087] 1. Determine the sector where the reference voltage vector is located

[0088] The sector and region where the reference voltage vector is located are determined based on its amplitude and phase angle.

[0089] 2. Basic voltage vector selection

[0090] The basic voltage vector in sector 1 includes the small vector V S1 [POO], small vector V S2 [OON], Large Vector V L1 [PNN], large vector V L2 [PPN] and zero vector V Z [OOO], the expressions of each basic voltage vector are:

[0091]

[0092] When the reference voltage vector is located in region A of each sector, the reference voltage vector is synthesized using the four nearest basic voltage vectors. When the reference voltage vector is located in region B of each sector, the basic voltage vector selected using the nearest three vector principle cannot achieve independent control of the DC side capacitor voltage. To this end, the method of the present invention adds a large vector to synthesize the reference voltage vector, thereby generating a new control degree of freedom for achieving independent control of the DC side capacitor voltage. Table 2 shows the basic voltage vectors selected in different sectors and regions.

[0093] Table 2 Basic voltage vectors selected in different areas of each sector

[0094] Sector Region A Region B 1 [PNN], [PPN], [POO], [OON] [PNN], [PPN], [POO], [OON], [OOO] 2 [PPN], [NPN], [OON], [OPO] [PPN], [NPN], [OON], [OPO], [OOO] 3 [NPN], [NPP], [OPO], [NOO] [NPN], [NPP], [OPO], [NOO], [OOO] 4 [NPP], [NNP], [NOO], [OOP] [NPP], [NNP], [NOO], [OOP], [OOO] 5 [NNP], [PNP], [OOP], [ONO] [PNP], [PNN], [ONO], [POO], [OOO] 6 [PNP], [PNN], [ONO], [POO] [PNP], [PNN], [ONO], [POO], [OOO]

[0095] 3. Duty cycle calculation

[0096] In order to simplify the calculation, a non-orthogonal gh coordinate system is established. g and vh are the g-axis and h-axis components of the reference voltage vector, respectively, expressed as:

[0097]

[0098] where v α and v β are the α-axis and β-axis components of the reference voltage vector, respectively.

[0099] Taking sector 1 as an example, the calculation method of the duty ratio of the basic voltage vector is given in detail as follows:

[0100] When the reference voltage vector is in region A of sector 1 (i.e., the outer region of the space vector diagram), select the four basic voltage vectors closest in distance, including two small vectors and two large vectors (V S1 , V S2 , V L1 and V L2 ), synthesize the reference voltage vector, and the volt-second balance equation is:

[0101]

[0102] where d S1 , d S2 , d L1 and d L2 are the duty ratios of V S1 , V S2 , V L1 and V L2 respectively, and V ref is the reference voltage vector.

[0103] The following uses an indirect method to solve the above duty ratio.

[0104] Substitute the basic voltage vector expression into the volt-second balance equation, and the simplified volt-second balance equation is simplified to:

[0105]

[0106] It can be seen that: Equation (7) contains three equalities but four unknowns, and the above duty ratio cannot be directly solved. Therefore, an indirect solution method is designed as follows. Let the value of d S1 be y. Obviously, 0 < y < 1, then d S2 , d L1 and d L2 can be expressed as:

[0107]

[0108] Considering the constraint conditions of the duty ratios d S2 , d L1 and d L2 : 0 < dS2 <1,0 <d L1 <1 and 0 <d L2 <1, we can get that y needs to satisfy the constraints:

[0109]

[0110] Therefore, the maximum value of y (y max ) and minimum value (y min ) can be expressed as:

[0111]

[0112]

[0113] Take the initial value y0 of the duty cycle y as its maximum value (y max ) and minimum value (y min ), that is:

[0114]

[0115] When the reference voltage vector is in region B in sector 1 (i.e., the inner region of the space vector diagram), the basic voltage vector selected based on the nearest three vector principle cannot realize independent control of the DC side capacitor voltage. Therefore, the method of the present invention adds a large vector to generate a new control degree of freedom for realizing independent control of the DC side capacitor voltage. The specific introduction is as follows:

[0116] When the DC side capacitor voltage deviation is given by (V * diff ) is less than or equal to the actual value of the DC side capacitor voltage deviation (V diff ), select the large vector V L2 , small vector V S1 and V S2 , zero vector V Z , synthesized reference voltage vector, volt-second balance equation is:

[0117]

[0118] Among them, d Z is the duty cycle of the zero vector [OOO].

[0119] Substituting the basic voltage vector expression in equation (4) into equation (13), the volt-second balance equation can be further simplified to:

[0120]

[0121] Using the large vector duty cycle d L2 , the duty cycle of the other three basic voltage vectors can be expressed as:

[0122]

[0123] It can be seen that d S1 With d L2 Not relevant, but S2 Will follow d L2 As we all know, in the inverter mode, the P-type small vector reduces the voltage across capacitor C1 and increases the voltage across capacitor C2; the N-type small vector has the opposite effect on the DC side capacitor voltage. Therefore, increasing the duty cycle d of the large vector L2 This will reduce the voltage across capacitor C1.

[0124] Assuming the duty cycle of the large vector is y, and considering the constraints of the basic voltage vector duty cycle, the range of y is:

[0125]

[0126] Therefore, the maximum value of y (y max ) and minimum value (y min ) can be expressed as:

[0127]

[0128]

[0129] Design a proportional-integral (PI) controller to obtain the duty cycle y. The steps are given below. Substituting the value of y into equation (15), the duty cycle of each basic vector can be obtained. * diff Greater than V diff When the large vector [PPN] is replaced by the large vector [PNN], the duty cycle of each basic voltage vector can be obtained by following the same calculation steps, which will not be repeated here.

[0130] 4. Independent control of capacitor voltage

[0131] As mentioned above, in a large-capacity centralized photovoltaic power generation system, by connecting a group of photovoltaic arrays at both ends of each DC side capacitor, the voltages at both ends of the two DC side capacitors C1 and C2 are controlled separately to achieve independent MPPT function and improve system efficiency. * diff With V diff The difference between them is sent to the PI regulator, and its output is calculated by absolute value to obtain the basic voltage vector duty cycle allocation factor correction value ynp, that is:

[0132]

[0133] Among them, kp and k i are the parameters of the PI regulator.

[0134] When the reference voltage vector is located in region A of each sector, and V * diff –V diff ≤0, update the duty cycle of the P-type small vector to

[0135] y=y0+y np (20);

[0136] When the reference voltage vector is located in region A of each sector, and V * diff –V diff >0, update the P-type vector small duty cycle to

[0137] y=y0-y np (twenty one);

[0138] When the reference voltage vector is located in region B of each sector, for ease of calculation, let the duty cycle of the large vector be y np :

[0139] y=y np (twenty two);

[0140] To ensure accurate generation of the designed switching sequence, the correction value of the basic voltage vector duty cycle should be limited, that is:

[0141] y min <y<y max (twenty three).

[0142] 5. Switch sequence design

[0143] The switching sequence is designed by considering factors such as reducing the harmonic content of the output current and lowering the switching losses of the power devices.

[0144] When the reference voltage vector is located in region A within sector 1, the designed switching sequence is: [OON]-[PPN]-[PNN]-[POO]-[PNN]-[PPN]-[OON] (e.g. Figure 5 shown).

[0145] When the reference voltage vector is located in region B within sector 1 and V * diff -V diff ≤0, the designed switching sequence is: [OON]-[PPN]-[POO]-[OOO]-[POO]-[PPN]-[OON] (e.g. Figure 6 shown).

[0146] When the reference voltage vector is located in region B within sector 1 and V * diff –V diff >0, the designed switching sequence is: [OON]-[OOO]-[POO]-[PNN]-[POO]-[OOO]-[OON] (e.g. Figure 7 shown).

[0147] When the reference voltage vector is located in region A within sector 2, the designed switching sequence is: [OON]-[PPN]-[NPN]-[POO]-[NPN]-[PPN]-[OON].

[0148] When the reference voltage vector is located in region B within sector 2 and V * diff –V diff When ≤0, the designed switching sequence is: [OON]-[PPN]-[OPO]-[OOO]-[OPO]-[PPN]-[OON].

[0149] When the reference voltage vector is located in region B within sector 2 and V * diff –V diff When >0, the designed switching sequence is: [OON]-[OOO]-[OPO]-[NPN]-[OPO]-[OOO]-[OON].

[0150] When the reference voltage vector is located in region A within sector 3, the designed switching sequence is: [NOO]-[NPP]-[NPN]-[OPO]-[NPN]-[NPP]-[NOO].

[0151] When the reference voltage vector is located in region B within sector 3 and V * diff –V diff When ≤0, the designed switching sequence is: [NOO]-[NPP]-[OPO]-[OOO]-[OPO]-[NPP]-[NOO].

[0152] When the reference voltage vector is located in region B within sector 3 and V * diff –V diff When >0, the designed switching sequence is: [NOO]-[OOO]-[OPO]-[NNP]-[OPO]-[OOO]-[NOO].

[0153] When the reference voltage vector is located in region A within sector 4, the designed switching sequence is: [NOO]-[NPP]-[NNP]-[OOP]-[NNP]-[NPP]-[NOO].

[0154] When the reference voltage vector is located in region B within sector 4 and V * diff –V diff When ≤0, the designed switching sequence is: [NOO]-[NPP]-[OOP]-[OOO]-[OOP]-[NPP]-[NOO].

[0155] When the reference voltage vector is located in region B within sector 4 and V * diff –V diff When 0, the designed switching sequence is: [NOO]-[OOO]-[OOP]-[NNP]-[OOP]-[OOO]-[NOO].

[0156] When the reference voltage vector is located in region A within sector 5, the designed switching sequence is: [ONO]-[PNP]-[NNP]-[OOP]-[NNP]-[PNP]-[ONO].

[0157] When the reference voltage vector is located in region B within sector 5 and V * diff –V diff When ≤0, the designed switching sequence is: [ONO]-[PNP]-[OOP]-[OOO]-[OOP]-[PNP]-[ONO].

[0158] When the reference voltage vector is located in region B within sector 5 and V * diff –V diff When >0, the designed switching sequence is: [ONO]-[OOO]-[OOP]-[OOP]-[OPO]-[OOO]-[ONO].

[0159] When the reference voltage vector is located in region A within sector 6, the designed switching sequence is: [ONO]-[PNP]-[PNN]-[POO]-[PNN]-[PNP]-[ONO].

[0160] When the reference voltage vector is located in region B within sector 6 and V * diff –V diff When ≤0, the designed switching sequence is: [ONO]-[PNP]-[POO]-[OOO]-[POO]-[PNP]-[ONO].

[0161] When the reference voltage vector is located in region B within sector 6 and V * diff –V diffWhen >0, the designed switching sequence is: [ONO]-[OOO]-[POO]-[PNN]-[POO]-[OOO]-[ONO].

[0162] The switching sequence is converted into a driving signal of the power switch tube, thereby controlling the operation of the coupled three-level inverter system.

[0163] Figure 8 shows the experimental waveform when the system adopts the traditional space vector modulation method and the modulation index is 0.8, including the DC side capacitor voltage (V C1 、V C2 )、Line voltage(v ab )、A phase output voltage (i a ), common mode voltage (v cm ). Among them, the unbalance coefficient of Figure 8(a) is 0.2, the unbalance coefficient of Figure 8(b) is -0.2, and the unbalance coefficient of Figure 8(c) is 0. At this time, the DC side input voltage is set to 100V. It can be seen that the common mode voltage amplitude of the system is very high, and its common mode voltage effective values ​​are as high as 22.85V, 22.96V and 21.41V respectively.

[0164] FIG9 is an experimental waveform diagram when the system adopts the control method of the first embodiment of the present invention and the modulation index is 0.8, including the DC side capacitor voltage (V C1 、V C2 )、Line voltage(v ab )、A phase output voltage (i a ), common mode voltage (v cm ). Among them, the unbalance coefficient of Figure 10(a) is set to 0.2, the unbalance coefficient of Figure 9(b) is set to -0.2, and the unbalance coefficient of Figure 9(c) is set to 0. At this time, the DC side input voltage is set to 100V. The line voltage is a five-level waveform, and the output current is a sine waveform. It can be seen that the common-mode voltage amplitude of the system is reduced by 50% compared with the traditional space vector modulation method, and the output current quality is maintained. The effective value of the common-mode voltage is reduced to 18.49V, 18.27V and 16.00V respectively, which has obvious advantages.

[0165] Figure 10 shows the experimental waveforms when the system uses the traditional space vector modulation method and the modulation index is 0.4, including the DC side capacitor voltage (V C1 、V C2 )、Line voltage(v ab )、A phase output voltage (i a ), common mode voltage (v cm ). Among them, the unbalance coefficient of Figure 10(a) is 0.2, the unbalance coefficient of Figure 10(b) is -0.2, and the unbalance coefficient of Figure 10(c) is 0. At this time, the DC side input voltage is set to 100V. It can be seen that the line voltage (vab ) is reduced to a three-level waveform, the quality of the system's output current has declined, and its output current total harmonic distortion (THDi) is 4.20%, 4.46% and 4.46% respectively. The system's common-mode voltage amplitude is very high, and its common-mode voltage effective value is as high as 23.29V, 23.06V and 22.58V respectively.

[0166] FIG11 is an experimental waveform diagram of the system using the control method of the first embodiment of the present invention and the modulation index is 0.4, including the DC side capacitor voltage (V C1 、V C2 )、Line voltage(v ab )、A phase output voltage (i a ), common mode voltage (v cm ). Among them, the unbalance coefficient of Figure 11(a) is set to 0.2, the unbalance coefficient of Figure 11(b) is set to -0.2, and the unbalance coefficient of Figure 11(c) is set to 0. At this time, the DC side input voltage is set to 100V. The line voltage is a five-level waveform, and the output current is a sine waveform. It can be seen that under the low-profile system, the waveform quality of the output current is significantly improved compared with the traditional space vector modulation method, and the common-mode voltage of the system is reduced by 50% compared with the traditional space vector modulation method. The effective values ​​of the common-mode voltage are reduced to 18.49V, 18.27V and 16.00V, respectively, which are 29.29%, 41.11% and 44.46% lower than the traditional space vector modulation method, respectively, with obvious advantages.

[0167] FIG12 is an experimental waveform diagram of the system using the control method of the first embodiment of the present invention when the capacitor voltage deviation given value undergoes a step change. It can be seen that the control method of the first embodiment of the present invention can independently control the two capacitor voltages on the DC side. In addition, the control method of the first embodiment of the present invention achieves common mode voltage suppression under dynamic conditions while maintaining good output current waveform quality.

[0168] Embodiment 2

[0169] This embodiment provides a common-mode voltage and current harmonic cooperative suppression system for a coupled three-level inverter, including:

[0170] A sector determination module is configured to determine the sector and region where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector;

[0171] The basic voltage vector selection module is configured to select four basic voltage vectors with low common mode voltage amplitudes to synthesize a reference voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation, and the actual value of the DC side capacitor voltage deviation;

[0172] The basic voltage vector duty cycle calculation module is configured to list a volt-second balance equation according to the selected basic voltage vector and calculate its duty cycle using an indirect calculation method;

[0173] The capacitor voltage independent control module is configured to update the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation to achieve independent control of the capacitor voltage;

[0174] The drive signal generation module is configured to design a switch sequence according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation, convert the switch sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

[0175] The examples and application scenarios implemented by the above modules and corresponding steps are the same, but are not limited to the contents disclosed in the above embodiment 1. It should be noted that the above modules as part of the system can be executed in a computer system such as a set of computer executable instructions.

[0176] The description of each embodiment in the above embodiments has different emphases. For parts not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0177] The proposed system can be implemented in other ways. For example, the system embodiment described above is only illustrative, and the division of the modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules can be combined or integrated into another system, or some features can be ignored or not executed.

[0178] Embodiment 3

[0179] This embodiment provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the steps in the method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter as described in the first embodiment above are implemented.

[0180] Embodiment 4

[0181] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps in the method for coordinated suppression of common-mode voltage and current harmonics of a coupled three-level inverter as described in the first embodiment are implemented.

[0182] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0183] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0184] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0185] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0186] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0187] Although the above describes the specific implementation mode of the present invention in conjunction with the accompanying drawings, it is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art on the basis of the technical solution of the present invention without creative work are still within the scope of protection of the present invention.

Claims

1. A method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter, characterized in that: include: The space vector map is divided into 6 sectors, sector 1 to sector 6, and each sector is further divided into 2 small areas, namely area A and area B; the boundary line between area A and area B is the connecting line of the two small vectors, and the inner side of the connecting line of the end points of the two small vectors represents area B, and the outer side represents area A; According to the amplitude and phase angle of the reference voltage vector, determine the sector and region where the reference voltage vector is located; According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, a basic voltage vector is selected to synthesize a reference voltage vector; The basic voltage vector in sector 1 includes the small vector V S1 POO, small vector V S2 OON, large vector V L1 PNN, large vector V L2 PPN and Zero Vector V Z OOO, the expressions of each basic voltage vector are: ； in Represents the sum of the voltages of the two capacitors on the DC side. When the reference voltage vector is located in region A of each sector, the four nearest basic voltage vectors are used, including two small vectors and two large vectors. V S1 , V S2 , V L1 and V L2 , synthesize the reference voltage vector; when the reference voltage vector is located in area B of each sector, the basic voltage vector selected by the nearest three vector principle cannot realize the independent control of the DC side capacitor voltage. The reference voltage vector is synthesized into a large vector to generate a new control degree of freedom for realizing the independent control of the DC side capacitor voltage. Specifically, when the DC side capacitor voltage deviation is given by V * diff Less than or equal to the actual value of the DC side capacitor voltage deviation V diff When selecting a large vector V L2 , small vector V S1 and V S2 , zero vector V Z , synthesized reference voltage vector; when V * diff Greater than V diff When the large vector PPN is replaced by the large vector PNN, the reference voltage vector can be obtained by following the same calculation steps; when the reference voltage vector is located in other sectors, the basic voltage vector can be selected according to the above steps; According to the selected basic voltage vector, write the volt-second balance equation and use the indirect calculation method to calculate its duty cycle; According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation, the duty cycle of the basic voltage vector is updated to achieve independent control of the capacitor voltage; According to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation, the switching sequence is designed and converted into a PWM drive signal of the power switch tube to control the operation of the coupled three-level inverter.

2. The method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to claim 1, characterized in that: According to the selected basic voltage vector, the volt-second balance equation is listed, and its duty cycle is calculated using an indirect calculation method, specifically: When the reference voltage vector is located in region A of each sector, the four closest basic voltage vectors are selected to construct the volt-second balance equation; When the reference voltage vector is located in area A of each sector, the duty cycle of one of the small vectors is used as the solution value, and the duty cycles of the other three basic voltage vectors are determined by the indirect method; When the reference voltage vector is located in region B of each sector, a large vector, two small vectors and a zero vector are selected to construct the volt-second balance equation; When the reference voltage vector is located in region B of each sector, the duty cycle of the large vector is used as the solution value, and the duty cycles of the other three vectors are determined using an indirect method.

3. The method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to claim 1, characterized in that: The method of updating the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation to realize independent control of the capacitor voltage includes: The difference between the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation is sent to the PI controller, and the absolute value of its output is calculated to obtain the correction value of the basic voltage vector duty cycle allocation factor; The duty cycle of the basic voltage vector is updated according to the sector and region where the reference voltage vector is located, and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation.

4. The method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to claim 3, characterized in that: The step of updating the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation comprises: When the reference voltage vector is located in region A of each sector and the difference between the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation is ≤ 0, the duty cycle of the P-type small vector is updated to the sum of the initial value and the correction value of the duty cycle allocation factor of the current voltage vector; When the reference voltage vector is located in region A of each sector and the difference between the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation is greater than 0, the duty cycle of the P-type small vector is updated to the difference between the initial value and the correction value of the duty cycle allocation factor of the current voltage vector; When the reference voltage vector is located in the inner area of ​​the space vector diagram of each sector, the basic voltage vector duty cycle allocation factor correction value is used as the duty cycle of the large vector, and the duty cycle of the large vector is within a limited range.

5. The method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to claim 4, characterized in that: After the duty ratio of the basic voltage vector is updated, the duty ratios of other basic voltage vectors are updated using the updated duty ratio of the basic voltage vector by an indirect method.

6. The method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to claim 1, characterized in that: The designing of the switch sequence according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation includes: When the reference voltage vector is located outside the space vector diagram in sector 1, the designed switching sequence is: [OON] - [PPN] - [PNN] - [POO] - [PNN] - [PPN] - [OON]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 1 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is ≤ 0, the designed switching sequence is: [OON] - [PPN] - [POO]- [OOO] - [POO] - [PPN] - [OON]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 1 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is greater than 0, the designed switching sequence is: [OON] - [OOO] - [POO]- [PNN] - [POO] - [OOO] - [OON]; When the reference voltage vector is located outside the space vector diagram in sector 2, the designed switching sequence is: [OON] - [PPN] - [NPN] - [POO] - [NPN] - [PPN] - [OON]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 2 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is ≤ 0, the designed switching sequence is: [OON] - [PPN] - [OPO]- [OOO] - [OPO] - [PPN] - [OON]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 2 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is greater than 0, the designed switching sequence is: [OON] - [OOO] - [OPO]- [NPN] - [OPO] - [OOO] - [OON]; When the reference voltage vector is located outside the space vector diagram in sector 3, the designed switching sequence is: [NOO] -[NPP] - [NPN] - [OPO] - [NPN] - [NPP] - [NOO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 3 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is ≤ 0, the designed switching sequence is: [NOO] - [NPP] - [OPO]- [OOO] - [OPO] - [NPP] - [NOO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 3 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is greater than 0, the designed switching sequence is: [NOO] - [OOO] - [OPO]- [NNP] - [OPO] - [OOO] - [NOO].

7. The method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to claim 6, characterized in that: The designing of the switch sequence according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation also includes: When the reference voltage vector is located outside the space vector diagram in sector 4, the designed switching sequence is: [NOO] - [NPP] - [NNP] - [OOP] - [NNP] - [NPP] - [NOO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 4 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is ≤ 0, the designed switching sequence is: [NOO] - [NPP] - [OOP]- [OOO] - [OOP] - [NPP] - [NOO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 4 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is greater than 0, the designed switching sequence is: [NOO] - [OOO] - [OOP]- [NNP] - [OOP] - [OOO] - [NOO]; When the reference voltage vector is located outside the space vector diagram in sector 5, the designed switching sequence is: [ONO] -[PNP] - [NNP] - [OOP] - [NNP] - [PNP] - [ONO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 5 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is ≤ 0, the designed switching sequence is: [ONO] - [PNP] - [OOP]- [OOO] - [OOP] - [PNP] - [ONO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 5 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is greater than 0, the designed switching sequence is: [ONO] - [OOO] - [OOP]- [OOP] - [OPO] - [OOO] - [ONO]; When the reference voltage vector is located outside the space vector diagram in sector 6, the designed switching sequence is: [ONO] -[PNP] - [PNN] - [POO] - [PNN] - [PNP] - [ONO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 6 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is ≤ 0, the designed switching sequence is: [ONO] - [PNP] - [POO]- [OOO] - [POO] - [PNP] - [ONO]; When the reference voltage vector is located in the inner area of ​​the space vector diagram in sector 6 and the difference between the given value of the DC link capacitor voltage deviation and the actual value of the DC link capacitor voltage deviation is greater than 0, the designed switching sequence is: [ONO] - [OOO] - [POO]- [PNN] - [POO] - [OOO] - [ONO].

8. A common-mode voltage and current harmonic cooperative suppression system for a coupled three-level inverter, characterized in that: include: The space vector map is divided into 6 sectors, sector 1 to sector 6, and each sector is further divided into 2 small areas, namely area A and area B; the boundary line between area A and area B is the connecting line of the two small vectors, and the inner side of the connecting line of the end points of the two small vectors represents area B, and the outer side represents area A; A sector determination module is configured to determine the sector and region where the reference voltage vector is located according to the amplitude and phase angle of the reference voltage vector; A basic voltage vector selection module is configured to select a basic voltage vector to synthesize a reference voltage vector according to a sector and a region where a reference voltage vector is located, a given value of a DC side capacitor voltage deviation, and an actual value of a DC side capacitor voltage deviation; The basic voltage vector in sector 1 includes the small vector V S1 POO, small vector V S2 OON, large vector V L1 PNN, large vector V L2 PPN and Zero Vector V Z OOO, the expressions of each basic voltage vector are: ； in Represents the sum of the voltages of the two capacitors on the DC side. When the reference voltage vector is located in region A of each sector, the four nearest basic voltage vectors are used, including two small vectors and two large vectors. V S1 , V S2 , V L1 and V L2 , synthesize the reference voltage vector; when the reference voltage vector is located in area B of each sector, the basic voltage vector selected by the nearest three vector principle cannot realize the independent control of the DC side capacitor voltage. The reference voltage vector is synthesized into a large vector to generate a new control degree of freedom for realizing the independent control of the DC side capacitor voltage. Specifically, when the DC side capacitor voltage deviation is given by V * diff Less than or equal to the actual value of the DC side capacitor voltage deviation V diff When selecting a large vector V L2 , small vector V S1 and V S2 , zero vector V Z , synthesized reference voltage vector; when V * diff Greater than V diff When the large vector PPN is replaced by the large vector PNN, the reference voltage vector can be obtained by following the same calculation steps; when the reference voltage vector is located in other sectors, the basic voltage vector can be selected according to the above steps; The basic voltage vector duty cycle calculation module is configured to list a volt-second balance equation according to the selected basic voltage vector and calculate its duty cycle using an indirect calculation method; The capacitor voltage independent control module is configured to update the duty cycle of the basic voltage vector according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor voltage deviation to achieve independent control of the capacitor voltage; The drive signal generation module is configured to design a switch sequence according to the sector and region where the reference voltage vector is located, the given value of the DC side capacitor voltage deviation and the actual value of the DC side capacitor deviation, convert the switch sequence into a PWM drive signal of the power switch tube, and control the operation of the coupled three-level inverter.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps in the method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to any one of claims 1 to 7 are implemented.

10. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the method for cooperatively suppressing common-mode voltage and current harmonics of a coupled three-level inverter according to any one of claims 1 to 7 are implemented.

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