A method and device for remote online updating of FPGA multi-version firmware

Abstract

The present invention discloses a method and device for remote online updating of FPGA multi-version firmware. Before upgrading, the control unit receives at least one FPGA upgrade firmware sent by a host computer and stores it in a first memory. During upgrading, after receiving a first upgrade command containing information of firmware to be upgraded, the control unit sends a second upgrade command according to the information of the firmware to be upgraded. After receiving the second upgrade command, the complex programmable logic unit stores the firmware to be upgraded in a corresponding spatial position in the second memory. Then the complex programmable logic unit receives a reload command issued by the control unit, triggering the FPGA unit to load the firmware to be upgraded. The control unit issues a command to read the FPGA unit firmware version to obtain the version information. If the version information is consistent with the firmware version to be upgraded, the upgrade is judged to be successful. The present invention does not require the FPGA chip to participate in the upgrade process, the upgrade process does not affect the normal operation of the entire device function, and the upgrade process is stable and reliable.

Description

Technical Field

[0001] The present application belongs to the technical field of FPGA remote online upgrade, and in particular, relates to a method and device for remote online update of FPGA multi-version firmware. Background Art

[0002] In the whole communication equipment, multiple FPGA signal processing modules are usually installed. One or more high-end FPGA chips are designed inside each FPGA signal processing module. In order to meet the diverse needs of equipment application scenarios, it is necessary to switch and load FPGA function firmware with different algorithm versions in actual work to realize different business processes.

[0003] When the FPGA signal processing module is applied to the whole machine communication equipment and put into use, the whole machine communication equipment is in a closed state. Except for the necessary network interface that can communicate with the outside world, other hardware debugging interfaces will become invisible. Under the current circumstances, if the FPGA needs to be bug-fixed or function-upgraded, the FPGA firmware needs to be upgraded through the remote network.

[0004] The existing method requires the FPGA chip to participate in the upgrade process, which has the following problems:

[0005] 1) FPGA is required to participate in the upgrade process and read and write the flash memory through FPGA;

[0006] 2) The upgrade process affects the normal operation of the entire device: It takes 5 to 6 minutes to upgrade a single program version. If there are multiple or dozens of FPGA chips in the entire device that need to be upgraded, it will take a lot of upgrade time, seriously affecting the normal operation of the entire device;

[0007] 3) When upgrading multiple FPGA programs on multiple FPGA signal processing boards of a complete device, the FPGA chips need to be upgraded one by one, and they cannot be upgraded in parallel, resulting in low upgrade efficiency;

[0008] 4) Slow FPGA startup speed: The FPGA firmware loading address must be determined after booting up before loading can be realized, which increases the time for booting and running to determine the firmware loading address, and does not meet the application requirements that require boot time;

[0009] 5) Poor reliability: If an abnormal power outage occurs during the upgrade process, the upgrade may fail, causing the FPGA to fail after reloading and become a brick. The device needs to be powered off and restarted. Summary of the invention

[0010] The purpose of this application is to provide a method and device for remote online updating of FPGA multi-version firmware, so as to avoid the FPGA chip from participating in the upgrade process. The FPGA chip only needs to load the firmware to be upgraded, thereby realizing online upgrading, and the operation of the original program is not affected during the upgrade process.

[0011] In order to achieve the above purpose, the technical solution of this application is as follows:

[0012] A method for remote online updating of FPGA multi-version firmware is applied to an FPGA signal processing module, wherein the FPGA signal processing module includes a control unit, a complex programmable logic unit, and an FPGA unit. The method for remote online updating of FPGA multi-version firmware includes:

[0013] The control unit receives at least one FPGA upgrade firmware sent by the host computer and stores it in the first memory;

[0014] After receiving the first upgrade command containing the information of the firmware to be upgraded, the control unit sends a second upgrade command containing the location information of the second memory space corresponding to the firmware to be upgraded to the complex programmable logic module according to the information of the firmware to be upgraded;

[0015] After receiving the second upgrade command, the complex programmable logic unit erases the corresponding space position in the second memory, receives the firmware to be upgraded sent by the control unit, and stores it in the corresponding space position in the second memory;

[0016] The complex programmable logic unit receives the reload command sent by the control unit, triggering the FPGA unit to load the firmware to be upgraded;

[0017] The control unit sends a command to read the FPGA unit firmware version to obtain version information. If the version is consistent with the firmware version to be upgraded, the upgrade is judged to be successful.

[0018] Furthermore, the control unit is connected to the host computer via the TCP / IP network protocol to receive the FPGA upgrade firmware transmitted by the host computer.

[0019] Furthermore, the FPGA signal processing module further includes a substrate management unit, and the FPGA multi-version firmware remote online update method further includes:

[0020] After the baseboard management unit is powered on, it sends a default loading command to the complex programmable logic unit according to the default configuration;

[0021] The complex programmable logic unit receives the default loading command sent by the baseboard management unit, and triggers the FPGA unit to load the firmware of the default configuration.

[0022] Furthermore, the complex programmable logic unit receives a reload command sent by the control unit, triggering the FPGA unit to load the firmware to be upgraded, including:

[0023] After receiving the reload command sent by the control unit, the complex programmable logic unit sets the high address bit to correspond to the spatial location where the firmware to be upgraded is stored;

[0024] Then the FPGA unit is triggered to load the firmware to be upgraded from the spatial location where the firmware to be upgraded is stored.

[0025] Further, the complex programmable logic unit receives a default loading command issued by the baseboard management unit, triggering the FPGA unit to load the firmware of the default configuration, including:

[0026] The default load command includes the high address bit state of the default configuration, and the complex programmable logic unit sets the high address bit to correspond to the spatial position of the default configuration, and then triggers the FPGA unit to load the default configuration firmware from the spatial position to be configured by default.

[0027] The present application also proposes a FPGA multi-version firmware remote online update device, the FPGA multi-version firmware remote online update device comprises a control unit, a complex programmable logic unit and an FPGA unit, wherein:

[0028] The control unit is used to receive at least one FPGA upgrade firmware sent by the host computer and store it in the first memory; after receiving the first upgrade command containing the information of the firmware to be upgraded, send a second upgrade command containing the spatial location information of the second memory corresponding to the firmware to be upgraded to the complex programmable logic module according to the information of the firmware to be upgraded;

[0029] The complex programmable logic unit is used to, after receiving the second upgrade command, erase the corresponding space position in the second memory, receive the firmware to be upgraded sent by the control unit, and store it in the corresponding space position in the second memory; receive the reload command sent by the control unit, and trigger the FPGA unit to load the firmware to be upgraded;

[0030] The control unit is also used to issue a command to read the FPGA unit firmware version to obtain version information. If the version is consistent with the firmware version to be upgraded, it is determined that the upgrade is successful.

[0031] Furthermore, the control unit is connected to the host computer via the TCP / IP network protocol to receive the FPGA upgrade firmware transmitted by the host computer.

[0032] Furthermore, the FPGA multi-version firmware remote online update device also includes a baseboard management unit, which sends a default loading command to the complex programmable logic unit according to a default configuration after being powered on;

[0033] The complex programmable logic unit receives the default loading command sent by the baseboard management unit, and triggers the FPGA unit to load the firmware of the default configuration.

[0034] Further, the complex programmable logic unit receives a reload command sent by the control unit, triggers the FPGA unit to load the firmware to be upgraded, and performs the following operations:

[0035] After receiving the reload command sent by the control unit, the complex programmable logic unit sets the high address bit to correspond to the spatial location where the firmware to be upgraded is stored;

[0036] Then the FPGA unit is triggered to load the firmware to be upgraded from the spatial location where the firmware to be upgraded is stored.

[0037] Furthermore, the complex programmable logic unit receives a default loading command issued by the baseboard management unit, triggers the FPGA unit to load the firmware of the default configuration, and performs the following operations:

[0038] The default load command includes the high address bit state of the default configuration, and the complex programmable logic unit sets the high address bit to correspond to the spatial position of the default configuration, and then triggers the FPGA unit to load the default configuration firmware from the spatial position to be configured by default.

[0039] The present application proposes a method and device for remote online updating of FPGA multi-version firmware. The upgrade process does not affect the normal operation of the original FPGA program function after power-on, does not require the participation of the FPGA chip, and the upgrade process does not affect the normal operation of the entire device function; the FPGA programs of multiple FPGA signal processing boards of the entire device can be upgraded in parallel, reducing the FPGA multi-version firmware upgrade time of the entire device; there is no time limit for the upgrade, and the upgrade command can be issued at any time after the system is started; the FPGA startup speed is fast, and the default version program is loaded upon power-on; the upgrade method is stable and reliable. If an abnormal situation occurs during the upgrade process, the upgrade process can be repeatedly initiated online to achieve 100% stable and reliable upgrades; the FPGA version program switching speed is fast, and the FPGA version program switching and operation can be completed within 3 to 4 seconds. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 This is a flow chart of the remote online update method for FPGA multi-version firmware in this application.

[0041] Figure 2 This is a schematic diagram of the FPGA multi-version firmware remote online update device of this application.

[0042] Figure 3 This is a schematic diagram of the entire equipment for this application. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0044] An embodiment of the present application, such as Figure 1 As shown, a method for remote online updating of FPGA multi-version firmware is provided, which is applied to an FPGA signal processing module. The FPGA signal processing module includes a control unit, a complex programmable logic unit and an FPGA unit. The method for remote online updating of FPGA multi-version firmware includes:

[0045] The control unit receives at least one FPGA upgrade firmware sent by the host computer and stores it in the first memory;

[0046] After receiving the first upgrade command containing the information of the firmware to be upgraded, the control unit sends a second upgrade command containing the location information of the second memory space corresponding to the firmware to be upgraded to the complex programmable logic module according to the information of the firmware to be upgraded;

[0047] After receiving the second upgrade command, the complex programmable logic unit erases the corresponding space position in the second memory, receives the firmware to be upgraded sent by the control unit, and stores it in the corresponding space position in the second memory;

[0048] The complex programmable logic unit receives the reload command sent by the control unit, triggering the FPGA unit to load the firmware to be upgraded;

[0049] The control unit sends a command to read the FPGA unit firmware version to obtain version information. If the version is consistent with the firmware version to be upgraded, the upgrade is judged to be successful.

[0050] Specifically, the FPGA signal processing module is as follows: Figure 2 As shown, it includes a network communication interface unit, a control unit, a complex programmable logic unit, a first memory, a second memory and an FPGA unit. The control unit is also a CPU processor, and the complex programmable logic unit is a CPLD unit.

[0051] Specifically, the control unit establishes a physical connection with the network communication interface unit through the RGMII interface, and receives the FPGA upgrade firmware transmitted by the remote terminal (host computer) through the TCP / IP network protocol. In this embodiment, the upgrade firmware is a computer program suitable for the FPGA chip. Communicate with the first memory interface through the PCIE interface, and store the FPGA upgrade firmware transmitted from the remote TCP / IP network in the first memory. The first memory is an electronic hard disk or other storage medium, which is connected to the control unit through the PCIE interface or other interfaces. Some central processing units CPU have their own memory, which is also applicable. This application is not limited to the specific form of the first memory. The first memory is used to store the upgrade firmware sent by the remote terminal, and there can be multiple upgrade firmware stored.

[0052] In this embodiment, the upgrade firmware is sent to the first memory under the control unit through the TCP / IP network protocol, which belongs to the preparation stage before the upgrade. Unlike the transmission of the upgrade firmware during the upgrade process, it can be performed at any time without affecting the normal operation of the FPGA signal processing module. The upgrade is performed after the upgrade firmware is transmitted to the first memory, which can reduce the time of the upgrade process and avoid the problems of long upgrade time and easy transmission failure caused by network reasons when the upgrade firmware is transmitted during the upgrade process.

[0053] The technician who performs the upgrade operation logs in to the control unit remotely through the network and issues the first upgrade command of the FPGA, and the first upgrade command contains the file name of the upgrade firmware. For example, the file name of each upgrade firmware has a suffix, which is a different number, corresponding to different spatial positions in the second memory, for example, 1 represents the first segment of the second memory space, 2 represents the second segment of the second memory space, 3 represents the third segment of the second memory space, and 4 represents the fourth segment of the second memory space. Thus, the control unit automatically issues the second upgrade command to the CPLD unit according to the suffix of the FPGA upgrade firmware file name, and the second upgrade name contains the spatial position information of the second memory corresponding to the upgrade firmware, that is, which spatial segment of the second memory is stored. The second memory of this embodiment is a flash memory (flash), which can be erased and rewritten. In a specific embodiment, the second memory can use the SM29GL01GBMP Nor flash chip of Shenzhen Guowei, with a capacity of 1Gb (128MB), which is controlled by the high address 2 bits to divide the 128MB space into 4 segments, and 32MB meets the firmware space requirements of the ultra-large FPGA (JFM7VX690T36-AS). The present application can also realize the storage of more segments of 32MB multi-version firmware in the second memory, such as using a 2Gb capacity Nor flash chip, which can realize 8 segments of 32MB program space.

[0054] The control unit exchanges data commands with the CPLD unit through the QSPI interface, and uses register commands to implement command and data communication interaction. QSPI (Quad SPI) stands for 6-wire SPI, which is an extension of the SPI interface launched by Motorola. It is more widely used than SPI and has a higher transmission rate. As the control logic module management chip, the CPLD unit is responsible for controlling the upgrade process and coordinating the various steps in the upgrade process, including file verification, upgrade execution and status feedback, as well as erasing, reading and writing operations on the flash chip of the second storage module, realizing the solidification of the flash version of the FPGA program, and the FPGA's BPI program loading interface.

[0055] After receiving the second upgrade command, the CPLD unit configures the high address bit level state of the flash memory according to the command parameters and responds to the second upgrade command of the control unit. After receiving the CPLD response command, the control unit splits the FPGA upgrade firmware into 4K packets and sends them to the CPLD through QSPI interface data exchange. After receiving the upgrade firmware packet, the CPLD first performs data verification. After the verification passes, the corresponding flash memory space is erased and the upgrade data is written to the corresponding space of the flash memory until all the upgrade firmware data is written to the flash memory.

[0056] It should be noted that the CPLD unit selects the spatial position of the second memory by configuring the high address bit level state to determine the corresponding spatial position of the second memory. When configuring the high address bit level state of the flash memory, for example, the second memory has four segments, each with 32MB, and two high address bits (such as Figure 2 A25, A24) in the second memory to select the corresponding space segment, such as 00 corresponds to the first segment, 01 corresponds to the second segment, 10 corresponds to the third segment, and 11 corresponds to the fourth segment. Thus, the firmware to be upgraded can be placed in the corresponding space in the second memory.

[0057] It should be noted that for more upgraded firmware, a large-capacity flash memory can be used. When the CPLD unit configures the high address bit level state of the flash memory according to the command parameters, three high address bits can be used, such as A26, A25 and A24, which will not be repeated here.

[0058] After the CPLD unit completes writing the upgraded firmware to the flash memory, it waits for the control unit to reload the FPGA command. The reload command issued by the control unit is to allow the FPGA unit to load the firmware to be upgraded. If the CPLD unit receives the FPGA reload command, it sets the high address bit state according to the spatial location where the firmware to be upgraded is stored, selects the corresponding spatial location, and pulls down the FPGA program pin for 5ms to trigger the FPGA to load the corresponding upgraded firmware.

[0059] In a specific embodiment, the complex programmable logic unit receives a reload command sent by the control unit, triggering the FPGA unit to load the firmware to be upgraded, including:

[0060] After receiving the reload command sent by the control unit, the complex programmable logic unit sets the high address bit to correspond to the spatial location where the firmware to be upgraded is stored;

[0061] Then the FPGA unit is triggered to load the firmware to be upgraded from the spatial location where the firmware to be upgraded is stored.

[0062] That is, when a reload command is received, if the firmware to be upgraded is stored in the second space location of the second memory, the level states of the high address bits A25 and A24 are set to 0 and 1, corresponding to the second segment of the second space location of the second memory, where the firmware to be upgraded is stored, and loaded.

[0063] Then, the control unit sends a command to read the FPGA unit firmware version to obtain the version information. If it is consistent with the firmware version to be upgraded, the upgrade is judged to be successful. The control unit communicates with the FPGA unit interconnection interface (serial port) to read the firmware version information after the FPGA is loaded and upgraded. If the version is correct, the firmware upgrade is successful. If the versions are inconsistent, the upgrade fails and the control unit needs to resend the upgrade command to upgrade.

[0064] In another embodiment of the present application, the FPGA signal processing module further includes a substrate management unit, and the FPGA multi-version firmware remote online update method further includes:

[0065] After the baseboard management unit is powered on, it sends a default loading command to the complex programmable logic unit according to the default configuration;

[0066] The complex programmable logic unit receives the default loading command sent by the baseboard management unit, and triggers the FPGA unit to load the firmware of the default configuration.

[0067] Specifically, the default load command includes the high address bit state of the default configuration, the complex programmable logic unit sets the high address bit to correspond to the spatial position of the default configuration, and then triggers the FPGA unit to load the default configuration firmware from the spatial position to be configured by default.

[0068] The baseboard management unit (BMC unit, Baseboard Management Controller) is responsible for configuring the default FPGA startup version control after power-on, and outputs the A25 and A24 level states after power-on according to the default startup version information. The CPLD controls the flash memory high address A25 and A24 level states according to the A25 and A24 level state information to achieve different loader program versions. The control unit interacts with the BMC unit command through the Uart interface, and can configure the default FPGA version to be started after the next power-on, and obtain the BMC end card status information.

[0069] After power-on, due to the slow startup speed of the control unit CPU, the default loading version of the FPGA is controlled by the BMC unit. After power-on, the BMC unit outputs the high address control pin level to the outside according to the last default configuration state. The CPLD controls the flash high address A25 and A24 pin levels according to the high address pin level state output by the BMC end, and then pulls down the program pin of the FPGA for a 5ms pulse operation to load the FPGA firmware.

[0070] It should be noted that the technical solution of the present application supports the host computer to connect at least two FPGA signal processing modules through a network to achieve parallel upgrade of at least two FPGA signal processing modules.

[0071] Figure 3 This is the application system block diagram of the present application in the whole machine. The whole machine system is equipped with a network switching module and several FPGA signal processing modules. Each FPGA signal processing module in the whole machine is designed with an SGMII network interface connected to the network switching module. At the same time, the network switching module outputs a 1000Base-T network interface as the network debugging interface of the whole machine. By connecting the network debugging interface of the whole machine, the network communication function of the modules in the whole machine can be realized.

[0072] Through the external network debugging interface of the whole machine, network communication of all FPGA signal processing modules in the whole machine can be realized, and online remote parallel upgrade operations of FPGA multi-version firmware of all FPGA signal processing modules in the whole machine can be realized, which greatly shortens the remote online update time of FPGA multi-version firmware of multiple FPGA signal processing modules in the whole machine, improves maintenance efficiency, reduces maintenance costs, and is of great significance.

[0073] This application adopts the CPU+CPLD architecture. Through the remote network interface, during the upgrade process, the FPGA can run the program functions after power-on normally without affecting the normal operation of the entire device. There is no need for the FPGA chip to participate in the upgrade work. It can achieve remote upgrades of multiple versions of FPGA with high efficiency and high reliability. It has the following characteristics:

[0074] The upgrade process does not affect the normal operation of the original FPGA program function after power-on, and does not require the participation of the FPGA chip. The upgrade process does not affect the normal operation of the entire device function; the FPGA programs of multiple FPGA signal processing boards of the entire device can be upgraded in parallel, reducing the FPGA multi-version firmware upgrade time of the entire device; there is no time limit for the upgrade, and the upgrade command can be issued at any time after the system is up; the FPGA startup speed is fast, and the default version program is loaded when powered on; the upgrade method is stable and reliable. If an abnormal situation occurs during the upgrade process, the upgrade process can be repeatedly initiated online to achieve 100% stable and reliable upgrades; the FPGA version program switching speed is fast, and the FPGA version program switching and operation can be completed within 3 to 4 seconds.

[0075] In another embodiment of the present application, the present application further provides an FPGA multi-version firmware remote online update device, the FPGA multi-version firmware remote online update device includes a control unit, a complex programmable logic unit and an FPGA unit, wherein:

[0076] The control unit is used to receive at least one FPGA upgrade firmware sent by the host computer and store it in the first memory; after receiving the first upgrade command containing the information of the firmware to be upgraded, send a second upgrade command containing the spatial location information of the second memory corresponding to the firmware to be upgraded to the complex programmable logic module according to the information of the firmware to be upgraded;

[0077] The complex programmable logic unit is used to, after receiving the second upgrade command, erase the corresponding space position in the second memory, receive the firmware to be upgraded sent by the control unit, and store it in the corresponding space position in the second memory; receive the reload command sent by the control unit, and trigger the FPGA unit to load the firmware to be upgraded;

[0078] The control unit is also used to issue a command to read the FPGA unit firmware version to obtain version information. If the version is consistent with the firmware version to be upgraded, it is determined that the upgrade is successful.

[0079] For the specific definition of the device, please refer to the definition of the method above, which will not be repeated here.

[0080] In a specific embodiment, the control unit is connected to the host computer via the TCP / IP network protocol to receive the FPGA upgrade firmware transmitted by the host computer.

[0081] In a specific embodiment, the FPGA multi-version firmware remote online update device further includes a baseboard management unit, which sends a default loading command to the complex programmable logic unit according to a default configuration after being powered on;

[0082] The complex programmable logic unit receives the default loading command sent by the baseboard management unit, and triggers the FPGA unit to load the firmware of the default configuration.

[0083] In a specific embodiment, the complex programmable logic unit receives a reload command issued by the control unit, triggers the FPGA unit to load the firmware to be upgraded, and performs the following operations:

[0084] After receiving the reload command sent by the control unit, the complex programmable logic unit sets the high address bit to correspond to the spatial location where the firmware to be upgraded is stored;

[0085] Then the FPGA unit is triggered to load the firmware to be upgraded from the spatial location where the firmware to be upgraded is stored.

[0086] In a specific embodiment, the complex programmable logic unit receives a default loading command issued by the baseboard management unit, triggers the FPGA unit to load the default configuration firmware, and performs the following operations:

[0087] The default load command includes the high address bit state of the default configuration, and the complex programmable logic unit sets the high address bit to correspond to the spatial position of the default configuration, and then triggers the FPGA unit to load the default configuration firmware from the spatial position to be configured by default.

[0088] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A remote online update method for FPGA multi-version firmware, applied to FPGA signal processing module, It is characterized in that The FPGA signal processing module includes a control unit, a complex programmable logic unit and an FPGA unit. The FPGA multi-version firmware remote online update method includes: The control unit receives at least one FPGA upgrade firmware sent by the host computer and stores it in a first memory, where the first memory is an electronic hard disk; After receiving the first upgrade command containing the firmware information to be upgraded, the control unit sends a second upgrade command containing the second memory space location information corresponding to the firmware to be upgraded to the complex programmable logic module according to different space locations in the second memory corresponding to the firmware information to be upgraded; After receiving the second upgrade command, the complex programmable logic unit erases the corresponding space position in the second memory, receives the firmware to be upgraded sent by the control unit, and stores it in the corresponding space position in the second memory; The complex programmable logic unit receives the reload command sent by the control unit, selects the corresponding spatial position according to the spatial position where the firmware to be upgraded is stored, and triggers the FPGA unit to load the firmware to be upgraded; The control unit sends a command to read the FPGA unit firmware version to obtain version information. If the version is consistent with the firmware version to be upgraded, the upgrade is judged to be successful.

2. The multi-version firmware remote online update method according to claim 1, It is characterized in that The control unit is connected to the host computer via the TCP / IP network protocol and receives the FPGA upgrade firmware transmitted by the host computer.

3. The multi-version firmware remote online update method according to claim 1, It is characterized in that The FPGA signal processing module further includes a substrate management unit, and the FPGA multi-version firmware remote online update method further includes: After the baseboard management unit is powered on, it sends a default loading command to the complex programmable logic unit according to the default configuration; The complex programmable logic unit receives the default loading command sent by the baseboard management unit, and triggers the FPGA unit to load the firmware of the default configuration.

4. The multi-version firmware remote online update method according to claim 1, It is characterized in that The complex programmable logic unit receives a reload command issued by the control unit, selects a corresponding spatial position according to the spatial position where the firmware to be upgraded is stored, and triggers the FPGA unit to load the firmware to be upgraded, including: After receiving the reload command sent by the control unit, the complex programmable logic unit sets the high address bit to correspond to the spatial location where the firmware to be upgraded is stored; Then the FPGA unit is triggered to load the firmware to be upgraded from the spatial location where the firmware to be upgraded is stored.

5. The multi-version firmware remote online update method according to claim 3, It is characterized in that The complex programmable logic unit receives a default loading command issued by the baseboard management unit, triggering the FPGA unit to load the firmware of the default configuration, including: The default load command includes the high address bit state of the default configuration, and the complex programmable logic unit sets the high address bit to correspond to the spatial position of the default configuration, and then triggers the FPGA unit to load the default configuration firmware from the spatial position to be configured by default.

6. A remote online update device for FPGA multi-version firmware, It is characterized in that The FPGA multi-version firmware remote online update device includes a control unit, a complex programmable logic unit and an FPGA unit, wherein: The control unit is used to receive at least one FPGA upgrade firmware sent by the host computer and store it in a first memory, where the first memory is an electronic hard disk; after receiving a first upgrade command containing information about the firmware to be upgraded, according to different spatial positions in the second memory corresponding to the firmware information to be upgraded, send a second upgrade command containing spatial position information of the second memory corresponding to the firmware to be upgraded to the complex programmable logic module; The complex programmable logic unit is used to, after receiving the second upgrade command, erase the corresponding spatial position in the second memory, receive the firmware to be upgraded issued by the control unit, and store it in the corresponding spatial position in the second memory; receive the reload command issued by the control unit, select the corresponding spatial position according to the spatial position where the firmware to be upgraded is stored, and trigger the FPGA unit to load the firmware to be upgraded; The control unit is also used to issue a command to read the FPGA unit firmware version to obtain version information. If the version is consistent with the firmware version to be upgraded, it is determined that the upgrade is successful.

7. The multi-version firmware remote online update device according to claim 6, It is characterized in that The control unit is connected to the host computer via the TCP / IP network protocol and receives the FPGA upgrade firmware transmitted by the host computer.

8. The multi-version firmware remote online update device according to claim 6, It is characterized in that The FPGA multi-version firmware remote online update device also includes a baseboard management unit, which sends a default loading command to the complex programmable logic unit according to a default configuration after being powered on; The complex programmable logic unit receives the default loading command sent by the baseboard management unit, and triggers the FPGA unit to load the firmware of the default configuration.

9. The multi-version firmware remote online update device according to claim 6, It is characterized in that The complex programmable logic unit receives the reload command issued by the control unit, selects the corresponding spatial position according to the spatial position where the firmware to be upgraded is stored, triggers the FPGA unit to load the firmware to be upgraded, and performs the following operations: After receiving the reload command sent by the control unit, the complex programmable logic unit sets the high address bit to correspond to the spatial location where the firmware to be upgraded is stored; Then the FPGA unit is triggered to load the firmware to be upgraded from the spatial location where the firmware to be upgraded is stored.

10. The multi-version firmware remote online update device according to claim 7, It is characterized in that The complex programmable logic unit receives the default loading command issued by the baseboard management unit, triggers the FPGA unit to load the default configuration firmware, and performs the following operations: The default load command includes the high address bit state of the default configuration, and the complex programmable logic unit sets the high address bit to correspond to the spatial position of the default configuration, and then triggers the FPGA unit to load the default configuration firmware from the spatial position to be configured by default.

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