An incremental packing method and device for automatically optimizing timing performance

Abstract

An incremental packing method and device for automatically optimizing timing performance, after the overall layout is completed, the position of the CLB of the BLE on the critical path is incrementally adjusted, and whether to accept the adjustment is determined according to whether the timing changes after the adjustment; the timing analysis is called to obtain the connection set C with the smallest establishment time margin, and for each connection in C, incremental packing is performed to move the BLE at the starting point of the connection to the CLB where the BLE at the end point of the connection is located, and the incremental packing moves the BLE at the end point of the connection to the CLB where the BLE at the starting point of the connection is located; if one of the two incremental packings is feasible and makes the minimum value of the establishment time margin worst_slack better or the minimum number of slack connections is reduced, the result is maintained, C is updated, and the next round is entered; otherwise, the result before incremental packing is restored, and the next connection in C is optimized, and the delay of the critical path is further reduced through such iterative optimization, and the timing performance of the circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of field programmable gate arrays (FPGAs) in digital integrated circuits, and in particular to an incremental packing method for automatically optimizing timing performance, and an incremental packing device for automatically optimizing timing performance. Background Art

[0002] FPGA (Field-Programmable Gate Array) is a general-purpose logic circuit, and is known as one of the three general-purpose signal processing devices along with CPU and DSP. It has the advantages of high flexibility, high parallelism, and low development risk. It has been widely used in industrial control, aerospace, communications, automotive electronics, data centers, intelligent processing and other fields, and occupies an increasing market share.

[0003] The design process of FPGA EDA (Electronic Design Automation) software mainly includes multiple steps such as design input, synthesis, mapping, boxing, layout, routing, timing analysis, bit stream generation, and downloading. The boxing stage is to divide the basic logic unit BLE (Basic Logic Element) in the synthesized netlist into multiple boxes, so that each box can be mapped to a programmable logic block CLB (Configurable LogicBlock) inside the FPGA chip, and at the same time, the resource constraints need to be met to ensure that the logic of this box can be implemented in this CLB unit. The layout stage is to correspond each CLB to the physical coordinate position inside the FPGA chip and meet the constraints and optimization goals, such as area or timing.

[0004] The traditional FPGA binning process is completed before the layout stage, which means that after the layout stage is completed, the binning results cannot be modified. If the delay on the critical path is still large after the layout stage is completed, it cannot meet the user's timing requirements; and at this time, since the binning results cannot be modified, the number of CLBs on the critical path cannot be reduced, so the delay of the critical path cannot be significantly reduced, which leads to failure to meet the user's timing requirements. Summary of the invention

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide an incremental packing method for automatically optimizing timing performance, which can further reduce the delay of the critical path and improve the timing performance of the circuit through such iterative optimization.

[0006] The technical solution of the present invention is: the incremental packing method for automatically optimizing timing performance comprises the following steps:

[0007] (1)Conduct a timing analysis to obtain the minimum setup time margin worst_slack and the set of connections C with the setup time margin equal to worst_slack, and mark each connection in C as optimizable;

[0008] (2)Determine whether there is an optimizable connection in C. If so, find the first optimizable connection c in C; otherwise, stop.

[0009] (3)Perform incremental packing by moving the BLE at the starting point of c to the CLB where the BLE at the ending point of c is located.

[0010] (4)Determine whether this packing is feasible. If so, execute step (5); otherwise, execute step (7).

[0011] (5)Conduct a timing analysis to obtain the latest minimum setup time margin worst_slack´ and the set of connections C´ with the setup time margin equal to worst_slack´.

[0012] (6)Determine whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute step (11); otherwise, execute step (7).

[0013] (7)Perform incremental packing by moving the BLE at the ending point of c to the CLB where the BLE at the starting point of c is located.

[0014] (8)Determine whether this packing is feasible. If so, execute step (9); otherwise, execute step (12).

[0015] (9)Conduct a timing analysis to obtain the latest minimum setup time margin worst_slack´ and the set of connections C´ with the setup time margin equal to worst_slack´.

[0016] (10)Determine whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute step (11); otherwise, execute step (12).

[0017] (11)Retain the incremental packing result and update the set of connections C with the minimum slack in the latest timing analysis result; go to step (3).

[0018] (12)Restore the packing result and mark c as non-optimizable; go to step (2).

[0019] After the overall layout of the present invention is completed, the BLEs on the critical path are incrementally adjusted in their respective CLBs, and whether to accept or reject this adjustment is determined based on whether the timing changes after the adjustment; through such iterative optimization, the delay of the critical path is further reduced, and the timing performance of the circuit is improved.

[0020] An incremental packing device for automatically optimizing timing performance is also provided, which includes:

[0021] A first running timing analysis unit configured to obtain the minimum setup time margin worst_slack and the connection set C with the setup time margin equal to worst_slack, and mark each connection in C as optimizable;

[0022] A first judgment unit configured to judge whether there is an optimizable connection in C. If so, find the first optimizable connection c in C; otherwise stop;

[0023] A first incremental packing unit configured to perform incremental packing, moving the BLE at the starting point of c to the CLB where the BLE at the ending point of c is located;

[0024] A second judgment unit configured to judge whether this packing is feasible. If so, execute the second running timing analysis unit; otherwise execute the second incremental packing unit;

[0025] A second running timing analysis unit configured to perform timing analysis and obtain the latest minimum setup time margin worst_slack´ and the connection set C´ with the setup time margin equal to worst_slack´;

[0026] A third judgment unit configured to judge whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute the retention unit; otherwise execute the second incremental packing unit;

[0027] A second incremental packing unit configured to perform incremental packing, moving the BLE at the ending point of c to the CLB where the BLE at the starting point of c is located;

[0028] A fourth judgment unit configured to judge whether this packing is feasible. If so, execute the third running timing analysis unit; otherwise execute the restoration unit;

[0029] A third running timing analysis unit configured to perform timing analysis and obtain the latest minimum setup time margin worst_slack´ and the connection set C´ with the setup time margin equal to worst_slack´;

[0030] A fifth judgment unit configured to judge whether worst_slack´ > worst_slack, or the number of connections of C´ < the number of connections of C. If so, execute the retention unit; otherwise, execute the restoration unit;

[0031] A retention unit configured to retain the incremental packing result and update the set C of connections with the smallest slack in the latest timing analysis result; transfer to the first incremental packing unit;

[0032] A restoration unit configured to restore the packing result and mark c as non-optimizable; transfer to the first judgment unit. Description of the Drawings

[0033] Figure 1 The flowchart of the incremental packing method for automatically optimizing the timing performance according to the present invention is shown.

[0034] Figure 2 It is a schematic flow diagram of obtaining the set C of connections with the smallest setup time margin for running timing analysis.

[0035] Figure 3 It is a schematic flow diagram of moving a basic logic unit BLE1 from the original programmable logic block CLB1 to CLB2 for incremental packing. Detailed Embodiments

[0036] As Figure 1 shown, this incremental packing method for automatically optimizing the timing performance includes the following steps:

[0037] (1) Run timing analysis to obtain the minimum setup time margin worst_slack and the set C of connections with the setup time margin equal to worst_slack, and mark each connection in C as optimizable;

[0038] (2) Judge whether there are optimizable connections in C. If so, find the first optimizable connection c in C; otherwise, stop;

[0039] (3) Perform incremental packing to move the BLE at the starting point of c to the CLB where the BLE at the ending point of c is located;

[0040] (4) Judge whether this packing is feasible. If so, execute step (5); otherwise, execute step (7);

[0041] (5) Run timing analysis to obtain the latest minimum setup time margin worst_slack´ and the set C´ of connections with the setup time margin equal to worst_slack´;

[0042] (6) Judge whether worst_slack´ >worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute step (11); otherwise, execute step (7);

[0043] (7) Perform incremental packing, and move the BLE at the end point of c to the CLB where the BLE at the start point of c is located;

[0044] (8) Determine whether this packing is feasible. If so, execute step (9); otherwise, execute step (12);

[0045] (9) Run timing analysis to obtain the minimum value of the latest setup time margin worst_slack´ and the set of connections C´ whose setup time margin is equal to worst_slack´;

[0046] (10) Determine whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute step (11); otherwise, execute step (12);

[0047] (11) Retain the incremental packing result, and update the set C of connections with the minimum slack in the latest timing analysis result; go to step (3);

[0048] (12) Restore the packing result, and mark c as non-optimizable; go to step (2).

[0049] After the overall layout of the present invention is completed, the BLEs on the critical path are incrementally adjusted in the CLBs where they are located, and whether to accept or reject this adjustment is determined according to whether the timing changes after the adjustment; through such iterative optimization, the delay of the critical path is further reduced, and the timing performance of the circuit is improved.

[0050] Preferably, in the step (1), the step of running timing analysis to obtain the set C of connections with the minimum setup time margin includes:

[0051] (1.1) Traverse the timing graph G from front to back, and calculate the arrival time Tarrival of each node;

[0052] (1.2) Traverse the timing graph G from back to front, and calculate the required arrival time Trequired of each node;

[0053] (1.3) Calculate the setup time margin slack of each connection;

[0054] (1.4) Sort each connection in ascending order of slack;

[0055] (1.5) Get the minimum slack value worst_slack, which is equal to the slack of the first connection after sorting;

[0056] (1.6) Get the first connection c after sorting;

[0057] (1.7) If the slack of c is equal to worst_slack, execute step (1.8); otherwise exit;

[0058] (1.8) Add c to the set C and move on to the next connection.

[0059] Preferably, in step (3), the step of incrementally packing a basic logic unit BLE1 from the original programmable logic block CLB1 to CLB2 comprises:

[0060] (3.1) Remove BLE1 from the subunit list of CLB1;

[0061] (3.2) Update the properties of CLB1;

[0062] (3.3) Add BLE1 from the subunit list of CLB2;

[0063] (3.4) Update the properties of CLB2;

[0064] (3.5) For the signal i of each input port in BLE1;

[0065] (3.6) Find the sink that reaches CLB1 in the terminal node sink list of signal i and change it to the sink that reaches CLB2;

[0066] (3.7) For each output signal o in BLE1;

[0067] (3.8) Change the starting point source information in signal o to CLB2.

[0068] Preferably, in step (4), the rule for determining whether the incremental packing from the c-starting point BLE1 to the box where the c-end point BLE2 is located is feasible is: the box of BLE1 is of CLB type; the box of BLE2 is of CLB type; BLE1 is not on a certain carry chain; BLE2 is not on a certain carry chain; the number of BLEs in CLB2 does not reach the maximum capacity; after BLE1 is added to CLB2, the maximum number limit of CLB data signals is met; after BLE1 is added to CLB2, the maximum number limit of CLB control signals is met.

[0069] Those of ordinary skill in the art can understand that all or part of the steps in implementing the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the methods of the above embodiments, and the storage medium can be: ROM / RAM, magnetic disk, optical disk, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also simultaneously includes an incremental bin packing device for automatically optimizing timing performance, and this device is usually represented in the form of functional modules corresponding to the steps of the method. This device includes:

[0070] There is also provided an incremental bin packing device for automatically optimizing timing performance, which includes:

[0071] A first running timing analysis unit configured to obtain the minimum setup time margin worst_slack and the connection set C with the setup time margin equal to worst_slack, and mark each connection in C as optimizable;

[0072] A first judgment unit configured to judge whether there is an optimizable connection in C. If so, find the first optimizable connection c in C; otherwise stop;

[0073] A first incremental bin packing unit configured to perform incremental bin packing, and move the BLE at the starting point of c to the CLB where the BLE at the ending point of c is located;

[0074] A second judgment unit configured to judge whether this bin packing is feasible. If so, execute the second running timing analysis unit; otherwise, execute the second incremental bin packing unit;

[0075] A second running timing analysis unit configured to perform timing analysis, and obtain the latest minimum setup time margin worst_slack´ and the connection set C´ with the setup time margin equal to worst_slack´;

[0076] A third judgment unit configured to judge whether worst_slack´>worst_slack, or the number of connections in C´<the number of connections in C. If so, execute the retention unit; otherwise, execute the second incremental bin packing unit;

[0077] A second incremental bin packing unit configured to perform incremental bin packing, and move the BLE at the ending point of c to the CLB where the BLE at the starting point of c is located;

[0078] A fourth judgment unit configured to judge whether this bin packing is feasible. If so, execute the third running timing analysis unit; otherwise, execute the restoration unit;

[0079] The third timing analysis unit is configured to perform timing analysis, obtain the latest minimum setup time margin worst_slack´ and the connection set C´ with the setup time margin equal to worst_slack´;

[0080] The fifth judgment unit is configured to judge whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute the retention unit; otherwise, execute the restoration unit;

[0081] The retention unit is configured to retain the incremental packing result and update the slack minimum connection set C of the latest timing analysis result; transfer to the first incremental packing unit;

[0082] The restoration unit is configured to restore the packing result and mark c as non-optimizable; transfer to the first judgment unit.

[0083] Preferably, in the first timing analysis unit, the steps of performing timing analysis to obtain the connection set C with the minimum setup time margin include:

[0084] (1.1) Traverse the timing diagram G from front to back and calculate the arrival time Tarrival of each node;

[0085] (1.2) Traverse the timing diagram G from back to front and calculate the required arrival time Trequired of each node;

[0086] (1.3) Calculate the setup time margin slack of each connection;

[0087] (1.4) Sort each connection in ascending order of slack;

[0088] (1.5) Obtain the minimum slack worst_slack, and worst_slack is equal to the slack of the first connection after sorting;

[0089] (1.6) Obtain the first connection c after sorting;

[0090] (1.7) Judge that if the slack of c is equal to worst_slack, execute step (1.8); otherwise, exit;

[0091] (1.8) Add c to C and transfer to the next connection.

[0092] Preferably, in the first incremental packing unit, the steps of incrementally packing a basic logic element BLE1 from the original programmable logic block CLB1 to CLB2 include:

[0093] (3.1) Remove BLE1 from the subunit list of CLB1;

[0094] (3.2) Update the properties of CLB1;

[0095] (3.3) Add BLE1 from the subunit list of CLB2;

[0096] (3.4) Update the properties of CLB2;

[0097] (3.5) For the signal i of each input port in BLE1;

[0098] (3.6) Find the sink that reaches CLB1 in the terminal node sink list of signal i and change it to the sink that reaches CLB2;

[0099] (3.7) For each output signal o in BLE1;

[0100] (3.8) Change the starting point source information in signal o to CLB2.

[0101] Preferably, in the second judgment unit, the rules for judging whether the incremental packing from the c-starting point BLE1 to the box where the c-end point BLE2 is located are feasible are: the box of BLE1 is of CLB type; the box of BLE2 is of CLB type; BLE1 is not on a certain carry chain; BLE2 is not on a certain carry chain; the number of BLEs in CLB2 has not reached the maximum capacity; after BLE1 is added to CLB2, the maximum number limit of CLB data signals is met; after BLE1 is added to CLB2, the maximum number limit of CLB control signals is met.

[0102] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. An incremental packing method for automatically optimizing timing performance, characterized by: It includes the following steps: (1) Run timing analysis to obtain the connection set C with the minimum setup time margin worst_slack and the connection set C with the setup time margin equal to worst_slack, and mark each connection in C as optimizable; (2) Determine whether there is an optimizable connection in C. If so, find the first optimizable connection c in C; otherwise, stop; (3) Perform incremental packing to move the basic logic unit BLE at the starting point c to the programmable logic block CLB where the BLE at the end point c is located; (4) Determine whether the packing is feasible. If so, execute step (5); otherwise, execute step (7); (5) Run timing analysis to obtain the latest minimum value of the setup time margin, worst_slack´, and the connection set C´ whose setup time margin is equal to worst_slack´; (6) Determine whether worst_slack´ > < worst_slack, or the number of connections of C´ < the number of connections of C. If so, execute step (11); otherwise, execute step (7). (7) Perform incremental packing to move the BLE at the end of c to the CLB where the BLE at the start of c is located; (8) Determine whether the packing is feasible. If so, execute step (9); otherwise, execute step (12); (9) Run timing analysis to obtain the latest minimum value of the setup time margin, worst_slack´, and the connection set C´ whose setup time margin is equal to worst_slack´; (10) Determine whether worst_slack´ > is less than worst_slack, or the number of connections of C´ is less than the number of connections of C. If so, execute step (11); otherwise, execute step (12). (11) Keep the incremental packing results and update the slack minimum connection set C of the latest timing analysis results; go to step (3); (12) Restore the packing result and mark c as non-optimizable; go to step (2).

2. The incremental packing method for automatically optimizing timing performance according to claim 1, characterized in that: In step (1), the step of performing timing analysis to obtain a connection set C with the minimum establishment time margin includes: (1.1) Traverse the time series graph G from front to back and calculate the arrival time Tarrival of each node; (1.2) Traverse the timing graph G from back to front and calculate the required arrival time Trequired of each node; (1.3) Calculate the establishment time margin slack of each connection; (1.4) Sort each connection in ascending order of slack; (1.5) Get the minimum slack value worst_slack, which is equal to the slack of the first connection after sorting; (1.6) Get the first connection c after sorting; (1.7) If the slack of c is equal to worst_slack, execute step (1.8); otherwise exit; (1.8) Add c to C and move on to the next connection.

3. The incremental packing method for automatically optimizing timing performance according to claim 1, characterized in that: In step (3), the step of incrementally packing a basic logic unit BLE1 from the original programmable logic block CLB1 to CLB2 includes: (3.1) Remove BLE1 from the subunit list of CLB1; (3.2) Update the properties of CLB1; (3.3) Add BLE1 from the subunit list of CLB2; (3.4) Update the properties of CLB2; (3.5) For the signal i of each input port in BLE1; (3.6) Find the sink in the sink list of signal i that reaches CLB1 and modify it to reach CLB2; (3.7) For each output signal o in BLE1; (3.8) Modify the source information of signal o to CLB2.

4. The incremental packing method for automatically optimizing timing performance according to claim 1, characterized in that: In step (4), the rules for determining that the incremental packing of moving the starting point BLE1 of c to the box where the ending point BLE2 of c is located are feasible are: the box of BLE1 is of CLB type; the box of BLE2 is of CLB type; BLE1 is not on a certain carry chain; BLE2 is not on a certain carry chain; the number of BLEs in CLB2 has not reached the maximum capacity; after adding BLE1 to CLB2, the maximum number limit of CLB data signals is satisfied; after adding BLE1 to CLB2, the maximum number limit of CLB control signals is satisfied.

5. An incremental packing device for automatically optimizing timing performance, characterized in that: It includes: The first running timing analysis unit, which is configured to obtain the minimum setup time margin worst_slack and the connection set C with the setup time margin equal to worst_slack, and mark each connection in C as optimizable; The first judgment unit, which is configured to judge whether there is an optimizable connection in C. If so, find the first optimizable connection c in C; otherwise stop; The first incremental packing unit, which is configured to perform incremental packing and move the basic logic element BLE at the starting point of c to the programmable logic block CLB where the ending point BLE of c is located; The second judgment unit, which is configured to judge whether this packing is feasible. If so, execute the second running timing analysis unit; otherwise execute the second incremental packing unit; The second running timing analysis unit, which is configured to perform timing analysis and obtain the latest minimum setup time margin worst_slack´ and the connection set C´ with the setup time margin equal to worst_slack´; The third judgment unit, which is configured to judge whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute the retention unit; otherwise execute the second incremental packing unit; The second incremental packing unit, which is configured to perform incremental packing and move the BLE at the ending point of c to the CLB where the BLE at the starting point of c is located; The fourth judgment unit, which is configured to judge whether this packing is feasible. If so, execute the third running timing analysis unit; otherwise execute the restoration unit; The third running timing analysis unit, which is configured to perform timing analysis and obtain the latest minimum setup time margin worst_slack´ and the connection set C´ with the setup time margin equal to worst_slack´; The fifth judgment unit, which is configured to judge whether worst_slack´ > worst_slack, or the number of connections in C´ < the number of connections in C. If so, execute the retention unit; otherwise execute the restoration unit; The retention unit, which is configured to retain the incremental packing result and update the connection set C with the minimum slack of the latest timing analysis result; transfer to the first incremental packing unit; A restoration unit is configured to restore the packing result and mark c as non-optimizable; and the process proceeds to the first judgment unit.

6. The incremental packing device for automatically optimizing timing performance according to claim 5, characterized in that: In the first running timing analysis unit, the step of running timing analysis to obtain a connection set C with the smallest establishment time margin includes: (1.1) Traverse the time series graph G from front to back and calculate the arrival time Tarrival of each node; (1.2) Traverse the timing graph G from back to front and calculate the required arrival time Trequired of each node; (1.3) Calculate the establishment time margin slack of each connection; (1.4) Sort each connection in ascending order of slack; (1.5) Get the minimum slack value worst_slack, which is equal to the slack of the first connection after sorting; (1.6) Get the first connection c after sorting; (1.7) If the slack of c is equal to worst_slack, execute step (1.8); otherwise exit; (1.8) Add c to C and move on to the next connection.

7. The incremental packing device for automatically optimizing timing performance according to claim 5, characterized in that: In the first incremental packing unit, the step of incremental packing to move a basic logic unit BLE1 from the original programmable logic block CLB1 to CLB2 includes: (3.1) Remove BLE1 from the subunit list of CLB1; (3.2) Update the properties of CLB1; (3.3) Add BLE1 from the subunit list of CLB2; (3.4) Update the properties of CLB2; (3.5) For the signal i of each input port in BLE1; (3.6) Find the sink that reaches CLB1 in the terminal node sink list of signal i and change it to the sink that reaches CLB2; (3.7) For each output signal o in BLE1; (3.8) Change the starting point source information in signal o to CLB2.

8. The incremental packing device for automatically optimizing timing performance according to claim 5, characterized in that: In the second judgment unit, the rule for judging whether the incremental packing connecting the c starting point BLE1 to the box where the c end point BLE2 is located is feasible is: the box of BLE1 is of CLB type; the box of BLE2 is of CLB type; BLE1 is not on a carry chain; BLE2 is not on a carry chain; the number of BLEs in CLB2 does not reach the maximum capacity; after BLE1 is added to CLB2, the maximum number limit of CLB data signals is met; after BLE1 is added to CLB2, the maximum number limit of CLB control signals is met.

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