Display panel and display device

Abstract

The embodiments of the present disclosure provide a display panel and a display device, which relate to the field of display technology and are used to improve the effect of pixel circuit threshold voltage compensation and reduce the preparation cost of the display panel. The display panel includes a pixel circuit and a test circuit. The control electrode of the driving transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the third node. The data processing subcircuit is configured to transmit a first voltage signal to a fourth node in the first stage; transmit a data signal to the fourth node in the second stage, and adjust the voltage of the first node according to the voltage change of the fourth node. The functional subcircuit is configured to electrically connect the first signal line to the target node. The first end of the test circuit is electrically connected to the first node, the second node, the third node or the first signal line; the second end is electrically connected to the data signal line, the first voltage signal line or the fourth node. The above-mentioned display panel is used to display an image.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, display panels have been widely used, and people's requirements for display panels are becoming increasingly higher. Among them, large size, high pixel density (PPI), and high refresh rate are the key development trends of display panels. When display panels are operating, the threshold voltage compensation time of the driver transistors in the pixel circuits is getting shorter and shorter. How to improve the threshold voltage compensation time of the driver transistors in the pixel circuits is a major technical issue in the current development of display panels. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a display panel and a display device for improving the effect of pixel circuit threshold voltage compensation and reducing the manufacturing cost of the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display panel is provided. The display panel includes a plurality of pixel circuits and at least one test circuit. The pixel circuits include a driving transistor, a data processing subcircuit, a compensation subcircuit, and at least one functional subcircuit. The driving transistor has a control electrode electrically connected to a first node, a first electrode electrically connected to a second node, and a second electrode electrically connected to a third node. The driving transistor is configured to electrically connect the second node to the third node under the voltage control of the first node. The data processing subcircuit is electrically connected to a first scan signal terminal, a second scan signal terminal, a data signal line, a first voltage signal line, and the first node. The data processing subcircuit has a fourth node. In a first phase, the data processing subcircuit is configured to transmit a first voltage signal from the first voltage signal line to the fourth node under the control of the first scan signal terminal, and in a second phase, transmit a data signal from the data signal line to the fourth node under the control of the second scan signal terminal, and adjust the voltage of the first node based on a voltage change at the fourth node. The compensation subcircuit is electrically connected to a third scan signal terminal, the first node, and the second node, and is configured to electrically connect the first node to the second node under the control of the third scan signal terminal. The functional subcircuit is electrically connected to a control signal terminal, a first signal line, and a target node; the target node is one of the first node, the second node, and the third node; and the functional subcircuit is configured to electrically connect the first signal line to the target node under the control of the control signal terminal. The test circuit includes a test control terminal, a first terminal, and a second terminal. The first terminal is electrically connected to one of the first node, the second node, the third node, and the first signal line; the second terminal is electrically connected to one of the data signal line, the first voltage signal line, and the fourth node; and the test circuit is configured to electrically connect the first terminal and the second terminal under the control of the test signal terminal.

[0006] Based on the above-mentioned display panel, in the process of the data processing subcircuit transmitting the data signal to the first node, the data signal may not pass through the compensation subcircuit, and the process of transmitting the threshold voltage of the driving transistor to the first node may not pass through the data processing subcircuit, that is, the pixel circuit is a pixel circuit in which data writing and threshold voltage compensation are separated from each other, and the data processing subcircuit and the compensation subcircuit of the pixel circuit are independent of each other and can work independently and without affecting each other. Based on this, the pixel circuit can be configured to perform threshold voltage compensation and data signal writing on the control electrode (first node) of the driving transistor respectively at different time periods within the same display cycle (one frame time), that is, the data writing process and the threshold voltage compensation process of the pixel circuit can be independent of each other and performed separately. In this way, the duration of the threshold voltage compensation process can be not limited to 1H, which is conducive to improving the time length of the threshold voltage compensation process, and then fully compensating the threshold voltage of the driving transistor to the control electrode of the driving transistor, which is conducive to improving the accuracy of the driving current generated by the pixel circuit, and then improving the display quality of the display panel. In addition, when the array substrate needs to be tested, the test circuit electrically connects the first end and the second end under the control of the test signal end, and then electrically connects the first node, the second node, the third node and one of the first signal lines (the one connected to the first end) to the data signal line, the first voltage signal line and one of the fourth nodes (the one connected to the second end), and by controlling the pixel circuit, the pixel circuit generates a detection current that flows through the driving transistor and can be transmitted to the first end, and then collects the above-mentioned detection current through the data signal line or the first voltage signal line, and then calculates an ideal current in combination with the voltage applied to each circuit node of the pixel circuit, and compares the above-mentioned detection current with the ideal current to determine whether the driving transistor meets the usage conditions. If the driving transistor meets the usage conditions, the array substrate is considered to meet the usage requirements, and the array substrate is continued to be prepared to form a display panel. If the driving transistor does not meet the usage conditions, the array substrate is considered to not meet the usage requirements, and the array substrate is subjected to other processing (including but not limited to repair, recycling or scrapping) to prevent unqualified array substrates from entering the back-end process, reduce the waste of materials and processes of unqualified array substrates in the back-end process, and reduce the preparation cost of the display panel.

[0007] In some embodiments, the first end is electrically connected to one of the first node, the second node, and the third node, and the second end is electrically connected to the fourth node or the data signal line.

[0008] In some embodiments, the display panel includes a display area and a peripheral area surrounding the display area, the pixel circuit is located in the display area, the display panel includes a plurality of the test circuits, one test circuit is connected to one pixel circuit, and the plurality of test circuits are all located in the display area.

[0009] In some embodiments, the first end is electrically connected to the first signal line, and the second end is electrically connected to the first voltage signal line or the data signal line.

[0010] In some embodiments, the display panel includes a display area and a peripheral area surrounding the display area, the pixel circuit is located in the display area, and the display panel includes a test circuit, which is located in the peripheral area.

[0011] In some embodiments, the functional subcircuit includes a light-emission control subcircuit and a first reset subcircuit. The light-emission control subcircuit is electrically connected to a light-emission control signal terminal, a second voltage signal line, and the second node, and is configured to electrically connect the second voltage signal line to the second node under control of the light-emission control signal terminal. The first reset subcircuit is electrically connected to a first reset signal terminal, a third voltage signal line, and the third node, and is configured to electrically connect the third voltage signal line to the third node under control of the first reset signal terminal. The first signal line includes the second voltage signal line and the third voltage signal line.

[0012] In some embodiments, the functional subcircuit further includes a second reset subcircuit. The second reset subcircuit is electrically connected to the second reset signal terminal, a fourth voltage signal line, and the first node, and is configured to electrically connect the fourth voltage signal line to the first node under control of the second reset signal terminal. The first signal line further includes the fourth voltage signal line.

[0013] In some embodiments, the first end is electrically connected to the third node, and the second end is electrically connected to the data signal line.

[0014] In some embodiments, the light-emission control subcircuit includes a first transistor. A control electrode of the first transistor is electrically connected to the light-emission control signal terminal, a first electrode is electrically connected to the second voltage signal line, and a second electrode is electrically connected to the second node. The first reset subcircuit includes a second transistor. A control electrode of the second transistor is electrically connected to the first reset signal terminal, a first electrode is electrically connected to the third voltage signal line, and a second electrode is electrically connected to the third node. The second reset subcircuit includes a third transistor. A control electrode of the third transistor is electrically connected to the second reset signal terminal, a first electrode is electrically connected to the fourth voltage signal line, and a second electrode is electrically connected to the first node.

[0015] In some embodiments, the test circuit includes a test transistor, a control electrode of the test transistor forms the test control terminal, one of the first electrode and the second electrode forms the first terminal, and the other forms the second terminal.

[0016] In some embodiments, the data processing subcircuit includes a fourth transistor, a fifth transistor, and a first capacitor. The fourth transistor has a control electrode electrically connected to the first scan signal terminal, a first electrode electrically connected to the first voltage signal line, and a second electrode electrically connected to the fourth node. The fifth transistor has a control electrode electrically connected to the second scan signal terminal, a first electrode electrically connected to the data signal line, and a second electrode electrically connected to the fourth node. One plate of the first capacitor is electrically connected to the fourth node, and the other plate is electrically connected to the first node. The compensation subcircuit includes a sixth transistor; the sixth transistor has a control electrode electrically connected to the third scan signal terminal, a first electrode electrically connected to the first node, and a second electrode electrically connected to the second node. The pixel circuit also includes a second capacitor; one plate of the second capacitor is electrically connected to the fourth node, and the other plate is electrically connected to the third node. The third node is configured to be electrically connected to the light-emitting element.

[0017] In another aspect, a display device is provided, comprising: a display panel as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0019] Figure 1 is a structural diagram of a display device according to some embodiments;

[0020] Figure 2 is a structural diagram of a display device according to some embodiments;

[0021] Figure 3 is a structural block diagram of a pixel circuit according to some embodiments;

[0022] Figure 4 is an equivalent circuit diagram of a pixel circuit according to some embodiments;

[0023] Figure 5 is another structural block diagram of a pixel circuit according to some embodiments;

[0024] Figure 6 is another structural block diagram of a pixel circuit according to some embodiments;

[0025] Figure 7 is another structural block diagram of a pixel circuit according to some embodiments;

[0026] Figure 8 is another equivalent circuit diagram of a pixel circuit according to some embodiments;

[0027] Figure 9 is a structural block diagram of a test circuit according to some embodiments;

[0028] Figure 10 is a structural block diagram of a pixel circuit and a test circuit according to some embodiments;

[0029] Figure 11 is another structural block diagram of a test circuit according to some embodiments;

[0030] Figure 12 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0031] Figure 13 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0032] Figure 14 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0033] Figure 15 is a timing control diagram of a detection method for a pixel circuit according to some embodiments;

[0034] Figure 16 is another structural block diagram of a test circuit according to some embodiments;

[0035] Figure 17 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0036] Figure 18 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments;

[0037] Figure 19 is an equivalent circuit diagram of a pixel circuit and a test circuit according to some embodiments. DETAILED DESCRIPTION

[0038] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0039] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0040] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0041] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0042] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0043] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0044] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0045] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0046] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0047] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0048] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0049] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0050] The transistors used in the pixel circuit provided in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics, wherein the transistors in the embodiments of the present disclosure are all described by taking thin film transistors as an example. The thin film transistor may be a P-type transistor or an N-type transistor. The P-type transistor is turned on under the action of a low level and is cut off under the action of a high level; the N-type transistor is turned on under the action of a high level and is cut off under the action of a low level. In the embodiments of the present disclosure, an exemplary description is given by taking the thin film transistors included in the pixel circuit as P-type transistors as an example. The "effective level" implements a level signal that can turn on the corresponding thin film transistor.

[0051] The control electrode of each thin-film transistor used in the pixel circuit is the gate of the thin-film transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally the same. In other words, the first electrode and the second electrode of the thin-film transistor in the embodiments of the present disclosure can be structurally the same. For example, the first electrode of the thin-film transistor is the source, and the second electrode is the drain.

[0052] The various circuit nodes in the pixel circuit, such as the first node, the second node, etc., do not represent actual components, but represent the confluence points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the confluence points of related electrical connections in the circuit diagram.

[0053] See Figure 1 Embodiments of the present disclosure provide a display device 1000, which is a product having an image display function. For example, the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images.

[0054] The display device 1000 can be applied to a variety of electronic devices, for example, the display device 1000 can be a mobile phone, a wireless device, a personal digital assistant (PDA), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a handheld or portable computer, a GPS receiver / navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat-panel display, a computer monitor, a car display (e.g., an odometer display), a cockpit controller and / or display, a camera view display (e.g., a rearview camera display in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a packaging and an aesthetic structure (e.g., a display of an image of a piece of jewelry), etc. For example, Figure 1 As shown, the display device 1000 may be a mobile phone.

[0055] From the perspective of the light-emitting type of the display device 1000, the display device 1000 can be a liquid crystal display (LCD), or an organic light-emitting diode (OLED), a quantum dot electroluminescent display (QLED), or a mini / micro light-emitting diode (MLED) display. From the perspective of the form of the display device 1000, the display device 1000 can be a flat display, a curved display, or a foldable display. From the perspective of the shape of the display device 1000, the display device 1000 can be rectangular, circular, or other shapes. The following uses a rectangular and flat organic light-emitting diode display as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto, and any other display device can also be considered as long as the same technical concept is applied.

[0056] In some embodiments, see Figure 2, the display device 1000 includes a display panel 1100 and a driving circuit board 1200. The driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC / DC, and an adjustable resistor voltage divider circuit (generating Vcom) and other driving circuits. The driving circuit board 1200 may also include other circuit structures, which are not listed here one by one. The driving circuit board 1200 is electrically connected to the display panel 1100, and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display. Of course, the structure of the display device 1000 is not limited to this. For example, the display device 1000 may also include at least one of a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording, or fingerprint recognition.

[0057] like Figure 2 As shown, the display panel 1100 may include a display area AA and a peripheral area BB disposed on at least one side of the display area AA. For example, the peripheral area BB may be disposed around the display area AA. The display area AA refers to the area of ​​the display panel 1100 used to display images, and the peripheral area BB may also be referred to as a non-display area, which refers to the area of ​​the display panel 1100 outside the display area AA.

[0058] The display panel 1100 includes a plurality of sub-pixels P disposed within the display area AA. The sub-pixel P refers to the smallest light-emitting unit in the display panel 1100. The plurality of sub-pixels P may include at least two sub-pixels emitting light of different colors. For example, the plurality of sub-pixels P include a red sub-pixel emitting red light, a green sub-pixel emitting green light, and a blue sub-pixel emitting blue light, so that the display panel can achieve color display.

[0059] The sub-pixel P includes a pixel circuit 100 and a light-emitting element EL. The pixel circuit 100 is electrically connected to the light-emitting element EL and is configured to transmit a driving current to the light-emitting element EL to drive the light-emitting element EL to emit light. The multiple pixel circuits 100 included in the multiple sub-pixels P can be arranged in multiple rows and columns. Each row of pixel circuits 100 includes multiple pixel circuits 100 arranged along a first direction X, and the multiple rows of pixel circuits 100 are arranged along a second direction Y. Each column of pixel circuits 100 includes multiple pixel circuits 100 arranged along the second direction Y, and the multiple columns of pixel circuits 100 are arranged along the first direction X. The first direction X and the second direction Y intersect, for example, the first direction X and the second direction Y are perpendicular to each other.

[0060] The display panel 1100 may further include a gate driver circuit (Gate Driver On Array; GOA) and a source driver chip (Source Driver IC) arranged in the peripheral area BB. The gate driver circuit may be connected to the pixel circuits 100 of a row of sub-pixels P via scan signal lines GL, and the source driver chip may be connected to the pixel circuits 100 of a column of sub-pixels P via data signal lines DL, and transmit data signals to the pixel circuits 100 of a column of sub-pixels P.

[0061] In some embodiments, when the display device is an OLED display device or a QLED display device, the display panel may include an array substrate, and a light-emitting element and a packaging structure (packaging layer) stacked on the array substrate. Of course, the structure of the display panel is not limited to this. For example, the display panel may also include other functional stacks arranged on the side of the packaging structure away from the array substrate. The functional stack may be one or more of a touch function layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can achieve the corresponding function. The embodiments of the present disclosure do not specifically limit the type and quantity of the above-mentioned functional stacks. The preparation process of the display panel may include a front-end process (Array process) and a back-end process. The above-mentioned array substrate can be prepared in the front-end process, and the light-emitting element and the packaging structure are formed on the array substrate in the back-end process. Wherein, the pixel circuit 100 is arranged in the above-mentioned array substrate.

[0062] In some embodiments, the pixel circuit 100 may include a plurality of thin film transistors (TFTs) and at least one capacitor Cst. For example, the pixel circuit 100 may be a "9T2C" circuit, a "7T1C" circuit, or an "8T1C" circuit, etc. The embodiments of the present disclosure are not limited thereto, and any other pixel circuits may also be considered as long as the same technical concept is applied. Wherein, "T" refers to TFT, and the number before "T" refers to the number of TFTs; "C" refers to capacitor Cst, and the number before "C" refers to the number of capacitors Cst.

[0063] The pixel circuit 100 typically includes at least one driving transistor DT, and the pixel circuit 100 typically includes at least a data writing process and a threshold voltage compensation process within a frame period. The threshold voltage compensation process is configured to compensate the threshold voltage Vth of the driving transistor to the control electrode of the driving transistor to eliminate the influence of the threshold voltage Vth of the driving transistor on the driving current generated by the pixel circuit. The data writing process is configured to couple the data signal to the control electrode of the driving transistor, thereby controlling the driving current of the driving transistor through the data signal and controlling the luminous brightness of the sub-pixel (the displayed grayscale size).

[0064] In general pixel circuits, the data writing process and the threshold voltage compensation process are designed to be performed in the same time period. That is, during the process of writing the data signal to the control electrode of the driving transistor, the threshold voltage of the driving transistor is simultaneously compensated to the control electrode of the driving transistor. However, as display panels gradually develop towards larger sizes, higher pixel densities (Pixels Per Inch; PPI for short), and higher refresh rates, the 1H scanning time of a row of pixel circuits is getting shorter and shorter, and the duration of the data writing process is generally 1H. This results in a shorter and shorter duration of the data writing process, that is, a shorter and shorter duration of the threshold voltage compensation process. This may result in insufficient compensation of the threshold voltage of the driving transistor, resulting in a poor compensation effect, affecting the driving current generated by the driving transistor, and thus the display quality of the display panel.

[0065] To solve the above technical problems, see Figure 3 and Figure 4 The display panel provided by the embodiment of the present disclosure includes a pixel circuit 100 , and the pixel circuit 100 includes a driving transistor DT, a data processing sub-circuit 10 and a compensation sub-circuit 20 .

[0066] The drive transistor DT has a control electrode electrically connected to a first node N1, a first electrode electrically connected to a second node N2, and a second electrode electrically connected to a third node N3. The drive transistor DT is configured to electrically connect the second node N2 and the third node N3 under the voltage control of the first node N1. Exemplarily, the drive transistor DT may be an N-type thin film transistor. One of the second node N2 and the third node N3 is configured to be coupled to the light-emitting element EL, and the other is configured to be coupled to a power supply voltage signal line (e.g., a second voltage signal line VDD).

[0067] The data processing sub-circuit 10 is electrically connected to the first scan signal terminal G1, the second scan signal terminal G2, the data signal line DL, the first voltage signal line Vinit1, and the first node N1. The data processing sub-circuit 10 includes a fourth node N4. The data processing sub-circuit 10 is configured to, in a first phase, transmit a first voltage signal (denoted as: V1) from the first voltage signal line Vinit1 to the fourth node N4 under the control of the first scan signal terminal G1, and in a second phase, transmit a data signal (denoted as: Vdata) from the data signal line DL to the fourth node N4 under the control of the second scan signal terminal G2, and adjust the voltage of the first node N1 according to the voltage change (Vdata-V1) of the fourth node N4. In the embodiments of the present disclosure, "Vdata" is used to represent the data signal itself, as well as the voltage value of the data signal.

[0068] The first voltage signal line Vinit1 is configured to be electrically connected to at least one column of pixel circuits 100 so as to transmit a first voltage signal to the at least one column of pixel circuits 100. For example, the first voltage signal line Vinit1 may be electrically connected to all pixel circuits, that is, all pixel circuits 100 included in the display panel are electrically connected to the same first signal line Vinit1. Of course, the first signal line Vinit1 is not necessarily a line segment. For example, the first signal line Vinit1 may include a cross-grid structure formed by at least two conductive layers.

[0069] The compensation sub-circuit 20 is electrically connected to the third scan signal terminal G3 , the first node N1 and the second node N2 , and is configured to electrically connect the first node N1 and the second node N2 under the control of the third scan signal terminal G3 .

[0070] Based on the above-mentioned pixel circuit 100, during the process of the data processing sub-circuit 10 transmitting the data signal Vdata to the first node N1, the data signal Vdata can be transmitted without passing through the compensation sub-circuit 20. The process of transmitting the threshold voltage Vth of the driving transistor DT to the first node N1 can also be transmitted without passing through the data processing sub-circuit 10. In other words, the pixel circuit 100 is a pixel circuit 100 in which data writing and threshold voltage compensation are separated from each other. The data processing sub-circuit 10 and the compensation sub-circuit 20 of the pixel circuit 100 are independent of each other and can operate independently and without affecting each other. Based on this, the pixel circuit 100 can be configured to perform threshold voltage compensation and data signal writing on the control electrode (first node N1) of the driving transistor DT at different time periods within the same display cycle (one frame time). In other words, the data writing process and the threshold voltage compensation process of the pixel circuit 100 can be performed independently and separately. In this way, the duration of the threshold voltage compensation process can be not limited to 1H, which is beneficial to increasing the time length of the threshold voltage compensation process, and then fully compensating the threshold voltage Vth of the driving transistor DT to the control electrode of the driving transistor DT, which is beneficial to improving the accuracy of the driving current generated by the pixel circuit 100, and thus improving the display quality of the display panel.

[0071] In some embodiments, see Figure 4 The data processing sub-circuit 10 includes a fourth transistor T4, a fifth transistor T5, and a first capacitor C1. The compensation sub-circuit 20 includes a sixth transistor T6. Exemplarily, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can all be N-type thin film transistors.

[0072] A control electrode of the fourth transistor T4 is electrically connected to the first scan signal terminal G1, a first electrode is electrically connected to the first voltage signal line Vinit1, and a second electrode is electrically connected to the fourth node N4. A control electrode of the fifth transistor T5 is electrically connected to the second scan signal terminal G2, a first electrode is electrically connected to the data signal line DL, and a second electrode is electrically connected to the fourth node N4. One plate of the first capacitor C1 is electrically connected to the fourth node N4, and the other plate is electrically connected to the first node N1. A control electrode of the sixth transistor T6 is electrically connected to the third scan signal terminal G3, a first electrode is electrically connected to the first node N1, and a second electrode is electrically connected to the second node N2.

[0073] Exemplarily, one display cycle of the pixel circuit 100 may include a first phase (eg, an initialization phase), a second phase (eg, a data writing phase), and a third phase (eg, a compensation phase).

[0074] In the first phase, the first scan signal terminal G1 transmits an operating level (a voltage capable of driving the fourth transistor T4 to conduct), and the fourth transistor T4 is turned on under the control of the operating level. The first voltage signal transmitted on the first voltage signal line Vinit1 is transmitted to the fourth node N4 through the fourth transistor T4. The voltage of the fourth node N4 is V1.

[0075] In the third phase, a voltage signal (labeled as VN1) can be transmitted to the first node N1, and the driving transistor DT is turned on under the voltage control of the first node N1. A voltage signal (labeled as VN3) is then transmitted to the third node N3. Furthermore, the third scan signal terminal G3 transmits an operating voltage level (a voltage signal capable of driving the sixth transistor T6 to turn on), and the sixth transistor T6 is turned on under the control of the operating voltage level. Thus, the voltage VN3 at the third node N3 is sequentially transmitted to the first node N1 through the driving transistor DT and the sixth transistor T6 until the voltage at the first node N1 changes from VN1 to VN3+Vth. The voltage difference between the gate (first node N1) and source (third node N3) of the driving transistor DT is (VN3+Vth)-VN3=Vth, at which point the driving transistor DT is turned off. In other words, the third phase achieves the purpose of coupling the threshold voltage Vth of the driving transistor DT to the control electrode (first node N1) of the driving transistor DT.

[0076] In the second phase, the first scan signal terminal G1 transmits a non-operating level (a voltage capable of driving the fourth transistor T4 to be turned off), and the fourth transistor T4 is turned off under the control of the non-operating level. The second scan signal terminal G2 transmits an operating level (a voltage capable of driving the fifth transistor T5 to be turned on), and the fifth transistor T5 is turned on under the control of the operating level, and the data signal Vdata transmitted on the data signal line DL is transmitted to the fourth node N4. The voltage of the fourth node N4 changes from V1 to Vdata, and the voltage change of the fourth node N4 is (Vdata-V1). Under the bootstrap effect of the first capacitor C1, the voltage of the first node N1 changes according to the voltage change of the fourth node N4 to couple the data signal to the first node N1. Exemplarily, the voltage change of the first node N1 and the voltage change of the fourth node N4 can be the same.

[0077] For example, based on the above control process of the pixel circuit, at the end of the third phase, the voltage of the first node N1 is VN3+Vth. In the second phase, the voltage of the fourth node N4 changes by Vdata-V1. Under the action of the first capacitor C1, the voltage of the first node N1 changes from VN3+Vth to VN3+Vth+(Vdata-V1).

[0078] Among them, the first stage and the third stage are both located before the second stage, and the first stage and the third stage can be completely staggered or partially overlapped, and the respective durations and relative order of the first stage and the second stage can be adjusted as needed. For example, the duration of the third stage can be greater than the duration of the first stage, and the first stage is completely located within the third stage. This is conducive to increasing the duration of the threshold voltage compensation process and improving the compensation effect of the driving transistor DT. Of course, the control timing of the pixel circuit is not limited to this, as long as the same pixel circuit structure is used.

[0079] In some embodiments, see Figure 5 , the pixel circuit 100 further includes at least one functional sub-circuit 30. The functional sub-circuit 30 is electrically connected to the control signal terminal GX, the first signal line LX and the target node. The target node is one of the first node N1, the second node N2 and the third node N3. For example, Figure 5 As shown, the target node is the third node N3 as an example. The functional sub-circuit 30 is configured to electrically connect the first signal line LX to the target node under the control of the control signal terminal GX.

[0080] In some embodiments, see Figure 6, the functional sub-circuit 30 includes a light-emitting control sub-circuit 31 and a first reset sub-circuit 32. The light-emitting control sub-circuit 31 is electrically connected to the light-emitting control signal terminal EM, the second voltage signal line VDD and the second node N2, and is configured to electrically connect the second voltage signal line VDD to the second node N2 under the control of the light-emitting control signal terminal EM. The first reset sub-circuit 32 is electrically connected to the first reset signal terminal G4, the third voltage signal line Vinit2 and the third node N3, and is configured to electrically connect the third voltage signal line Vinit2 to the third node N3 under the control of the first reset signal terminal G4. The first signal line LX includes the second voltage signal line VDD and the third voltage signal line Vinit2. For example, as Figure 6 As shown, the third node N3 is also configured to be electrically connected to the light emitting element EL.

[0081] The first signal line LX is configured to be electrically connected to at least one column of pixel circuits 100 so as to transmit a voltage signal to the at least one column of pixel circuits 100. For example, the first signal line LX may be electrically connected to all pixel circuits, that is, all pixel circuits 100 included in the display panel are electrically connected to the same first signal line LX. Of course, the first signal line LX is not necessarily a single line segment. For example, the first signal line LX may include a mesh structure formed by at least two conductive layers intersecting each other.

[0082] In some embodiments, during the third phase of a display cycle, a voltage signal may be transmitted to the third node N3 via the first reset sub-circuit 32. For example, during the third phase, under the control of the first reset signal terminal G4, the first reset sub-circuit 32 electrically connects the third voltage signal line Vinit2 to the third node N3. The voltage signal (labeled as V3) transmitted by the third voltage signal line Vinit2 is transmitted to the third node N3. At this time, the voltage of the third node N3 (labeled as VN3 above) is V3.

[0083] For example, a display cycle may also include a light-emitting phase and a non-light-emitting phase, and the first, second, and third phases described above may all be in the non-light-emitting phase. During the light-emitting phase, the light-emitting control subcircuit 31 electrically connects the second voltage signal line VDD to the second node N2 under the control of the light-emitting control signal terminal EM. The driving transistor DT is turned on and generates a driving current under the control of the voltage difference between the first node N1 and the second node N2. This driving current flows through the third node N3 and is transmitted to the light-emitting element EL, thereby driving the light-emitting element EL to emit light.

[0084] In some embodiments, see Figure 7The functional sub-circuit 30 may further include a second reset sub-circuit 33. The second reset sub-circuit 33 is electrically connected to the second reset signal terminal G5, the fourth voltage signal line Vref, and the first node N1, and is configured to electrically connect the fourth voltage signal line Vref to the first node N1 under the control of the second reset signal terminal G5.

[0085] For example, a display cycle may further include a fourth phase (initialization phase). During this fourth phase, the second reset sub-circuit 33, under the control of the second reset signal terminal G5, electrically connects the fourth voltage signal line Vref to the first node N1 to transmit a fourth voltage signal (labeled as V4) transmitted by the fourth voltage signal line Vref to the first node N1, thereby initializing the voltage of the first node N1. For example, during the aforementioned third phase, the fourth voltage signal may be transmitted to the first node N1 by the second reset sub-circuit 33 to control the conduction of the driving transistor DT.

[0086] In some embodiments, see Figure 8 The light emitting control subcircuit 31 includes a first transistor T1, the first reset subcircuit 32 includes a second transistor T2, and the second reset subcircuit 33 includes a third transistor T3. For example, the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type thin film transistors.

[0087] The first transistor T1 has a control electrode electrically connected to the light-emission control signal terminal EM, a first electrode electrically connected to the second voltage signal line VDD, and a second electrode electrically connected to the second node N2. The second transistor T2 has a control electrode electrically connected to the first reset signal terminal G4, a first electrode electrically connected to the third voltage signal line Vinit2, and a second electrode electrically connected to the third node N3. The third transistor T3 has a control electrode electrically connected to the second reset signal terminal G5, a first electrode electrically connected to the fourth voltage signal line Vref, and a second electrode electrically connected to the first node N1.

[0088] In some embodiments, continue to refer to Figure 8 The pixel circuit 100 further includes a second capacitor C2, one plate of the second capacitor C2 is electrically connected to the fourth node N4, and the other plate of the second capacitor C2 is electrically connected to the third node N3.

[0089] Based on the above pixel circuit 100 (such as Figures 3 to 8In the pixel circuit 100 shown in FIG. 1 , since its data processing sub-circuit 10 and compensation sub-circuit 20 are independent of each other, and the threshold voltage Vth of the driving transistor DT cannot be transmitted to the data signal line DL through the compensation sub-circuit 20 and the data processing sub-circuit 10, after the display panel is manufactured and the array substrate is formed (after the pixel circuit 100 is formed), the driving transistor DT cannot be tested (for example, to detect whether the threshold voltage Vth of the driving transistor is within a preset range) through the structure of the pixel circuit 100 itself. Therefore, array substrates that do not meet the requirements (defective) cannot be eliminated, and defective array substrates will still undergo subsequent back-end processes, resulting in waste of materials and processes used in the back-end processes, and increasing the production cost of the display panel.

[0090] To solve the above technical problems, see Figure 9 and Figure 10 The display panel of the embodiment of the present disclosure further includes a test circuit 200. The test circuit 200 includes a test control terminal AT, a first terminal 21, and a second terminal 22. The first terminal 21 is electrically connected to the first node N1, the second node N2, the third node N3, and one of the first signal line LX. The second terminal 22 is electrically connected to the data signal line DL, the first voltage signal line Vinit1, and one of the fourth node N4. The test circuit 200 is configured to electrically connect the first terminal 21 and the second terminal 22 under the control of the test signal terminal AT. Figure 10 It only shows a possible connection mode by way of example, which should be understood as an exemplary description of the present application, rather than a limitation of the present application.

[0091] In some embodiments, the test circuit 200 is further configured to test the driving transistor DT. For example, when the array substrate needs to be tested, the test circuit 200, under the control of the test signal terminal AT, electrically connects the first terminal 21 and the second terminal 22, and further electrically connects the first node N1, the second node N2, the third node N3, and one of the first signal line LX (the one connected to the first terminal 21) to the data signal line DL, the first voltage signal line Vinit1, and one of the fourth node N4 (the one connected to the second terminal 22). Furthermore, by controlling the pixel circuit 100, the pixel circuit 100 generates a test current that flows through the driving transistor DT and can be transmitted to the first terminal 21. The test current is then collected through the data signal line DL or the first voltage signal line Vinit1, and an ideal current is calculated based on the voltage applied to each circuit node of the pixel circuit 100. The test current is compared with the ideal current to determine whether the driving transistor DT meets the usage conditions. If the driving transistor DT meets the usage conditions, the array substrate is considered to meet the usage requirements, and the array substrate is further prepared to form a display panel. If the driving transistor DT does not meet the usage conditions, the array substrate is considered to not meet the usage requirements, and the array substrate is subjected to other processing (including but not limited to repair, recycling or scrapping) to prevent unqualified array substrates from entering the back-end process, reduce the waste of materials and processes of unqualified array substrates in the back-end process, and reduce the production cost of the display panel.

[0092] For example, Figure 10 The pixel circuit 100 and test circuit 200 shown are used as examples to illustrate embodiments of the present disclosure. When testing the array substrate, voltages can be transmitted to the first node N1 and the second node N2, respectively, to turn on the drive transistor DT and cause the drive transistor DT to generate a drive current transmitted to the third node N3. The magnitude of the drive current is related to the actual threshold voltage Vth of the drive transistor DT. Under the control of the test signal terminal AT, the test circuit 200 connects the data signal line DL to the third node N3. In this way, the drive current can be collected via the data signal line DL. Furthermore, based on the design conditions of the drive transistor DT (including but not limited to the material of the channel structure and the aspect ratio of the channel structure), the designed threshold voltage Vth' of the drive transistor DT can be obtained. Based on the voltage values ​​transmitted to the first node N1 and the second node N2, and the designed threshold voltage Vth', an ideal current can be obtained. The actual collected drive current is compared with the ideal current. If the drive current deviates from the ideal current by a certain preset range, the threshold voltage Vth of the drive transistor DT is considered to not meet the usage conditions. Otherwise, the threshold voltage of the drive transistor DT is considered to meet the usage conditions.

[0093] The above-mentioned display panel provided by the embodiment of the present disclosure includes a test circuit 200. Therefore, after preparing an array substrate including a pixel circuit 100 and a test circuit 200 in a front-end process (array process), the driving transistor DT of the pixel circuit 100 in the array substrate can be directly tested by the test circuit 200 to detect whether the driving transistor DT meets the design requirements. Then, array substrates that meet the conditions are screened out to further prepare the display panel 1100, and array substrates that do not meet the conditions are screened out for other processing (including but not limited to repair, recycling or scrapping), so as to prevent array substrates that do not meet the conditions from entering the back-end process, reduce the waste of materials and processes of array substrates that do not meet the conditions in the back-end process, and reduce the production cost of the display panel.

[0094] In some embodiments, see Figure 10 and Figure 11 The first terminal 21 of the test circuit 200 is electrically connected to one of the first node N1, the second node N2, and the third node N3; and the second terminal 22 of the test circuit 200 is electrically connected to the fourth node N4 or the data signal line DL. In this case, a test circuit 200 can be provided for each pixel circuit 100, which helps improve the structural uniformity of the array substrate. Furthermore, multiple test circuits 200 can be used to accurately detect whether the driving transistor DT of each pixel circuit 100 meets the requirements.

[0095] In some embodiments, see Figures 10 to 14 When the first end 21 of the test circuit 200 is electrically connected to one of the first node N1, the second node N2 and the third node N3, the display panel may include multiple test circuits 200, and the multiple test circuits 200 are all located in the display area, and one test circuit 200 is correspondingly connected to one pixel circuit 100. In this way, multiple test circuits 200 can be used to accurately detect whether the driving transistor DT of each pixel circuit 100 meets the conditions.

[0096] In some embodiments, see Figure 12 、 Figure 13 and Figure 14 The test circuit 200 includes a test transistor T20 , wherein the control electrode of the test transistor T20 forms a test control terminal AT, one of the first electrode and the second electrode forms a first terminal 21 , and the other forms a second terminal 22 .

[0097] Below, the pixel circuit 100 is used as an example. Figure 8 The structure shown is used as an example to exemplify some embodiments of the present application. Of course, the embodiments of the present disclosure are not limited thereto, and the pixel circuit 100 can consider any other suitable circuit as long as the same technical concept is adopted.

[0098] See Figure 12 In an example, the first terminal 21 of the test transistor T20 may be electrically connected to the third node N3 , and the second terminal 22 may be electrically connected to the fourth node N4 .

[0099] See Figure 13 In one example, the first terminal 21 of the test transistor T20 may be electrically connected to the first node N1 , and the second terminal 22 of the test transistor T20 may be electrically connected to the data signal line DL.

[0100] See Figure 14 In an example, the first terminal 21 of the test transistor T20 may be electrically connected to the second node N2 , and the second terminal 22 of the test transistor T20 may be electrically connected to the data signal line DL.

[0101] The embodiments of the present disclosure are not limited thereto, and the connection relationship of the test transistor T20 can be adjusted as needed. For example, when the first end 21 of the test transistor T20 is electrically connected to the third node N3, the second end 22 can also be electrically connected to the data signal line DL. When the first end 21 of the test transistor T20 is electrically connected to the first node N1 or the second node N2, the second end 22 can also be electrically connected to the fourth node N4.

[0102] In one example, Figure 12 Taking the pixel circuit 100 and the test circuit 200 shown in FIG. Figure 15 The detection process D of the pixel circuit 100 may include: the second reset signal terminal G5 transmits an operating level, turning on the third transistor T3; the third scan signal terminal G3 transmits an operating level, turning on the sixth transistor T6; the test signal terminal AT transmits an operating level, turning on the test transistor T20; and the second scan signal terminal G2 transmits an operating level, turning on the fifth transistor T5. Simultaneously, a fourth voltage signal V4 is transmitted to the first node N1 via the fourth voltage signal line Vref. The drive transistor DT is turned on under the control of the fourth voltage signal V4. The fourth voltage signal V4 is sequentially transmitted through the third transistor T3, the sixth transistor T6, the drive transistor DT, the test transistor T20, and the fifth transistor T5 to the data signal line DL, forming a detection current. In this way, the detection current can be collected via the data signal line DL.

[0103] In another example, the pixel circuit 100 and the test circuit 200 are Figure 13When the connection relationship is shown, unlike the above example, the detection process of the pixel circuit 100 may include: the light-emitting control signal terminal EM transmits the working level, and the first transistor T1 is turned on; the second reset signal terminal G5 transmits the non-working level, and the third transistor T3 is turned off. And the voltage signal is transmitted through the second voltage signal line VDD line second node N2. The control process of the sixth transistor T6, the test transistor T20 and the fifth transistor T5 during the detection process is the same as the above example and will not be repeated here. The second voltage signal is transmitted to the first node N1 through the first transistor T1 and the sixth transistor T6 in sequence to turn on the driving transistor DT. At the same time, the second voltage signal is also transmitted to the data signal line DL through the driving transistor DT, the test transistor T20 and the fifth transistor T5, and forms a detection current. In this way, the above detection current can be collected through the data signal line DL.

[0104] See Figure 13 When the first terminal 21 of the test transistor T20 is electrically connected to the first node N1 and the second terminal 22 is electrically connected to the data signal line DL, the detection process of the pixel circuit 100 may include: turning on the sixth transistor T6 to electrically connect the first node N1 to the second node N2. The first transistor T1 is turned on, and the second voltage signal line VDD transmits a second voltage signal to the first node N1 through the first transistor T1 and the sixth transistor T6 in sequence, thereby turning on the drive transistor DT. Alternatively, the third transistor T3 is turned on, and the fourth voltage signal line Vref transmits a fourth voltage signal to the first node N1, thereby turning on the drive transistor DT. The second transistor T2 is turned on, and the third voltage signal line Vinit2 transmits a third voltage signal to the third node N3 through the second transistor T2. The drive transistor DT generates a detection current under the control of the voltages of the first node N1 and the third node N3. The detection current is sequentially transmitted to the data signal line DL through the drive transistor DT, the sixth transistor T6, and the detection transistor T20. In this way, the detection current can be collected via the data signal line DL.

[0105] See Figure 14 When the first terminal 21 of the test transistor T20 is electrically connected to the second node N2 and the second terminal 22 is electrically connected to the data signal line DL, the detection process of the pixel circuit 100 may include: the third transistor T3 is turned on, the fourth voltage signal line Vref transmits a fourth voltage signal to the first node N1, thereby turning on the driving transistor DT. The second transistor T2 is turned on, the third voltage signal line Vinit2 transmits a third voltage signal to the third node N3 via the second transistor T2, and the driving transistor DT generates a detection current under the control of the voltages of the first node N1 and the third node N3. The detection current is sequentially transmitted to the data signal line DL through the driving transistor DT and the detection transistor T20. In this way, the detection current can be collected via the data signal line DL.

[0106] It is understandable that the detection method of the pixel circuit 100 in the embodiment of the present disclosure is not limited to the above-mentioned embodiments, and any other appropriate methods can also be considered as long as the same technical concept is adopted.

[0107] In some embodiments, see Figures 16 to 19 The first end 21 of the test circuit 200 can be electrically connected to the first signal line LX, and the second end 22 of the test circuit 200 can be electrically connected to the first voltage signal line Vinit1 or the data signal line DL. In this case, multiple pixel circuits 100 can share one test circuit 200, which helps reduce the number of test circuits 200, simplifies the structure of the test substrate 400, and further reduces the difficulty and cost of manufacturing the test substrate 400.

[0108] In one embodiment, when the first end 21 of the test circuit 200 can be electrically connected to the first signal line LX, the display panel can include a test circuit 200, and the test circuit 200 is arranged in the peripheral area of ​​the display panel. In this way, not only can the number of test circuits 200 be greatly reduced, the structure of the test substrate 400 can be simplified, and the difficulty and cost of preparing the test substrate 400 can be simplified, but the test circuit 200 can also be arranged in the peripheral area of ​​the display panel, which is beneficial to reducing the space of the display area occupied by the test circuit 200 and improving the pixel density of the display panel. Figures 17 to 19 In order to facilitate the display of the connection relationship between the pixel circuit 100 and the test circuit 200, the test circuit 200 is drawn at the position of the pixel circuit 100. However, it should be understood that the first signal line LX, the data signal line DL and the first voltage signal line Vinit1 can all extend to the peripheral area, and the test circuit 200 can actually be set in the peripheral area of ​​the display panel.

[0109] Below, the pixel circuit 100 is used as an example. Figure 8 The illustrated structure is used as an example to illustrate some embodiments of the present application. Of course, the embodiments of the present disclosure are not limited thereto, and the pixel circuit 100 may consider any other suitable circuit, as long as the same technical concept is adopted. The functional subcircuit 30 includes a light emitting control subcircuit 31, a first reset subcircuit 32, and a second reset subcircuit 33. The first signal line LX includes a second voltage signal line VDD, a third voltage signal line Vinit2, and a fourth voltage signal line Vref.

[0110] See Figure 17 In an example, the first terminal 21 of the test transistor T20 may be electrically connected to the second voltage signal line VDD, and the second terminal 22 may be electrically connected to the first voltage signal line Vinit1.

[0111] See Figure 18 In an example, the first terminal 21 of the test transistor T20 may be electrically connected to the third voltage signal line Vinit2 , and the second terminal 22 of the test transistor T20 may be electrically connected to the data signal line DL.

[0112] See Figure 19 In an example, the first terminal 21 of the test transistor T20 may be electrically connected to the fourth voltage signal line Vref, and the second terminal 22 may be electrically connected to the data signal line DL.

[0113] The embodiments of the present disclosure are not limited to Figures 17 to 19 In the three examples shown, the connection relationship of the test transistor T20 can be adjusted as needed. For example, when the first terminal 21 of the test transistor T20 is electrically connected to the second voltage signal line VDD, the second terminal 22 can also be electrically connected to the data signal line DL. When the first terminal 21 of the test transistor T20 is electrically connected to the third voltage signal line Vinit2 or the fourth voltage signal line Vref, the second terminal 22 can also be electrically connected to the first voltage signal line Vinit1.

[0114] In one example, Figure 17 Taking the pixel circuit 100 and test circuit 200 shown as an example, the detection process of the pixel circuit 100 may include: the second reset signal terminal G5 transmits an operating level, turning on the third transistor T3; the fourth voltage signal line Vref transmits a fourth voltage signal V4 to the first node N1 via the third transistor T3. The first reset signal terminal G4 transmits an operating level, turning on the second transistor T2; the third voltage signal line Vinit2 transmits a third voltage signal to the third node N3 via the second transistor T2; and the driving transistor DT generates a detection current under the voltage control of the first node N1 and the third node N3. The light-emitting control signal terminal EM transmits an operating level, turning on the first transistor T1. The test signal terminal AT transmits an operating level, turning on the test transistor T20. The detection current is sequentially transmitted to the first voltage signal line Vinit1 via the driving transistor DT, the first transistor T1, and the test transistor T20. In this way, the detection current can be collected via the first voltage signal line Vinit1.

[0115] In another example, the pixel circuit 100 and the test circuit 200 are connected to each other. Figure 18When connected in the manner shown, the detection process of the pixel circuit 100 may include: one of the first transistor T1 and the third transistor T3 is turned on, and the sixth transistor T6 is turned on, so that the second voltage signal line VDD or the fourth voltage signal line Vref can transmit a voltage signal to the first node N1, thereby turning on the driving transistor DT. In addition, the voltage signal can pass through the driving transistor DT and form a detection current that is transmitted to the third node N3. The second transistor T2 and the test transistor T20 are both turned on, and the above-mentioned detection current is transmitted to the data signal line DL through the second transistor T2 and the test transistor T20 in turn. In this way, the above-mentioned detection current can be collected through the data signal line DL. Among them, the data signal line DL is provided with a binding pin (Pin) in the peripheral area. Compared with collecting the detection current through the first voltage signal line Vinit1, collecting the detection current through the data signal line DL can simplify the structure of the display panel, that is, it can reduce the change to the structure of the display panel.

[0116] In another example, the pixel circuit 100 and the test circuit 200 are connected to each other. Figure 19 When connected in the manner shown, the detection process of the pixel circuit 100 may include: the third transistor T3 is turned on, the fourth voltage signal line Vref can transmit a voltage signal to the first node N1, and in this case, the fourth voltage signal line Vref can transmit a constant voltage signal. The sixth transistor T6 is turned on to connect the first node N1 and the second node N2. The second transistor T2 is turned on, the third voltage signal line Vinit2 transmits a third voltage signal to the third node N3 through the second transistor T2, and the driving transistor DT generates a detection current under the control of the voltages of the first node N1 and the third node N3. In addition, the test transistor T20 is also in the on state, and the detection current is transmitted to the data signal line DL through the driving transistor DT, the sixth transistor T6, the third transistor T3, and the test transistor T20 in sequence.

[0117] It should be noted that, see Figures 17 to 19 In the case where the first end 21 of the test circuit 200 can be electrically connected to the first signal line LX, since the display panel generally adopts a row scanning driving method, when the pixel circuit 100 is tested, a row of pixel circuits will simultaneously transmit a test current to the first signal line LX. At this time, whether the driving transistors of the pixel circuits in the row are abnormal can be synchronously detected. For example, when the difference between the detected test current and the ideal current is greater than a preset value, it can be considered that the driving transistor of at least one pixel circuit in the row of pixel circuits does not meet the conditions, and then the array substrate is subjected to other processing.

[0118] The scope of protection of the present application is not limited to the above-mentioned embodiments. The above-mentioned multiple embodiments may be implemented individually or in combination under reasonable circumstances. Alternatively, the present application may also include other embodiments. For example, the first terminal 21 of the test circuit 200 is electrically connected to one of the first node N1, the second node N2, and the third node N3, and the second terminal 22 is electrically connected to the first voltage signal line Vinit1. The embodiments of the present disclosure will not illustrate these one by one.

[0119] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel, characterized in that: comprising a plurality of pixel circuits and at least one test circuit; wherein, The pixel circuit comprises: a driving transistor, wherein the control electrode of the driving transistor is connected to the first node, the first electrode is connected to the second node, and the second electrode is connected to the third node; the driving transistor is configured to connect the second node and the third node under the control of the voltage of the first node; A data processing subcircuit comprising a fourth transistor, a fifth transistor, and a first capacitor; the fourth transistor having a control electrode connected to the first scan signal terminal, a first electrode connected to the first voltage signal line, and a second electrode connected to the fourth node; the fifth transistor having a control electrode connected to the second scan signal terminal, a first electrode connected to the data signal line, and a second electrode connected to the fourth node; one plate of the first capacitor being connected to the fourth node, and the other plate being connected to the first node; the data processing subcircuit being configured to, in a first phase, transmit a first voltage signal from the first voltage signal line to the fourth node under the control of the first scan signal terminal, and, in a second phase, transmit a data signal from the data signal line to the fourth node under the control of the second scan signal terminal, and adjust the voltage of the first node according to a voltage change at the fourth node; a compensation sub-circuit, comprising a sixth transistor, wherein a control electrode of the sixth transistor is connected to the third scan signal terminal, a first electrode of the sixth transistor is connected to the first node, and a second electrode of the sixth transistor is connected to the second node, and the sixth transistor is configured to connect the first node to the second node under control of the third scan signal terminal; at least one functional subcircuit, the functional subcircuit being connected to a control signal terminal, a first signal line, and a target node; the target node being one of the first node, the second node, and the third node; the functional subcircuit being configured to connect the first signal line to the target node under the control of the control signal terminal; wherein the functional subcircuit comprises a light-emitting control subcircuit, a first reset subcircuit, and a second reset subcircuit, the light-emitting control subcircuit comprising a first transistor, the control electrode of the first transistor being connected to the light-emitting control signal terminal, the first electrode being connected to the second voltage signal line, and the second electrode being connected to the second node; the first reset subcircuit comprising a second transistor, the control electrode of the second transistor being connected to the first reset signal terminal, the first electrode being connected to the third voltage signal line, and the second electrode being connected to the third node; the second reset subcircuit comprising a third transistor, the control electrode of the third transistor being connected to the second reset signal terminal, the first electrode being connected to the fourth voltage signal line, and the second electrode being connected to the first node; the first signal line comprising the second voltage signal line, the third voltage signal line, and the fourth voltage signal line; a second capacitor, one plate of the second capacitor being connected to the fourth node and the other plate of the second capacitor being connected to the third node; the third node being configured to be connected to the light emitting element; The test circuit includes a test control end, a first end, and a second end; the first end is connected to the first node, the second node, the third node, and one of the first signal lines; the second end is connected to the data signal line, the first voltage signal line, and one of the fourth node; the test circuit is configured to connect the first end and the second end under the control of the test control end.

2. The display panel according to claim 1, wherein: The first end is connected to one of the first node, the second node, and the third node; and the second end is connected to the fourth node or the data signal line.

3. The display panel according to claim 2, wherein: The display panel includes a display area and a peripheral area surrounding the display area, and the pixel circuit is located in the display area; The display panel includes a plurality of the test circuits, one test circuit is correspondingly connected to one pixel circuit, and the plurality of test circuits are all located in the display area.

4. The display panel according to claim 1, wherein: The first end is connected to the first signal line, and the second end is connected to the first voltage signal line or the data signal line.

5. The display panel according to claim 4, wherein: The display panel includes a display area and a peripheral area surrounding the display area, and the pixel circuit is located in the display area; The display panel includes a test circuit, and the test circuit is located in the peripheral area.

6. The display panel according to claim 1, wherein: The first end is connected to the third node, and the second end is connected to the data signal line.

7. The display panel according to claim 1, wherein: The test circuit includes a test transistor, a control electrode of the test transistor forms the test control terminal, one of the first electrode and the second electrode forms the first terminal, and the other forms the second terminal.

8. A display device, characterized in that: include: The display panel according to any one of claims 1 to 7; The driving circuit board is electrically connected to the display panel and is configured to transmit a control signal to the display panel.

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