A method, device and electronic device for controlling GC performance balance

Abstract

The present invention belongs to the technical field of solid-state hard disks, and provides a method, device and electronic device for controlling GC performance balance. The method comprises the following steps: 1. Real-time recording of the total number of cmds and the current number of unfinished cmds at the front end; 2. Recording the GC read and write task volume; calculating the initial performance and recovery performance according to the total number of cmds, the current number of unfinished cmds and the GC read and write task volume after a set period; performing processing to obtain the final performance; 3. When the final performance is not an invalid value, obtaining the delay value delay according to the unit and final performance calculation; updating the DPU delay value dpu delay to the delay value delay, and then setting it to the corresponding register of the DPU. The method for controlling GC performance balance delays the entry of the front-end command by setting the delay of the DPU module taking the host command, thereby balancing the host read and write and the GC read and write.

Description

Technical Field

[0001] The present invention relates to the technical field of solid state hard disks, and in particular to a method, device and electronic device for controlling GC performance balance. Background Art

[0002] Server manufacturers usually test the performance of the entire SSD. The read and write performance curves of existing SSDs are very stable when the disk is empty, but as users use it for a longer time, the SSD will gradually be filled up. At this time, because the unique algorithm needs to start garbage collection to free up more space to store new user data, when testing the read and write curves of the SSD at this time, it will be found that the curve jitters greatly, which will cause many users to think that such SSDs have poor performance stability.

[0003] Therefore, a method is needed to balance the ratio of host reads and writes and GC (garbage collection) reads and writes of user data when the disk is full, so that the performance curve is stable without a significant drop in speed. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a method, device and electronic device for controlling GC performance balance, so as to solve or partially solve the above problems.

[0005] In a first aspect, an embodiment of the present invention provides a method for controlling GC performance balance, comprising the following steps:

[0006] S1, real-time record of the total number of front-end cmds host data cnt and the number of currently unfinished cmds host remaincnt;

[0007] S2. Triggered by GC read and write, record the GC read and write task amount gc current remain cnt; calculate the initial performance performance1 and the recovery performance data gc performance according to the total cmd number host data cnt, the current unfinished cmd number host remain cnt and the GC read and write task amount gc current remain cnt after a set period;

[0008] When data gc performance is not an invalid value, smoothing is performed to obtain the final performance performance2;

[0009] S3. When the final performance performance2 is not an invalid value, the delay value delay is calculated based on unit and the final performance performance2;

[0010] If the calculated delay value delay is different from the current DPU delay value dpu delay, the DPU delay value dpu delay is updated to the delay value delay, and then the DPU delay value dpu delay is set to a corresponding register of the DPU.

[0011] According to a specific implementation of the embodiment of the present invention, the initial performance performance1 and the recovery performance data gc performance are calculated as follows:

[0012] performance1 = (host data cnt - host remain cnt) / queue depth;

[0013] data gc performance = (host data cnt - gc current remain cnt) / queuedepth;

[0014] Among them, queue depth is the corresponding queue depth.

[0015] According to a specific implementation of an embodiment of the present invention, the final performance performance2 calculation method is as follows:

[0016] performance2=performance1 *1 / 5 + data gc performance * 4 / 5.

[0017] According to a specific implementation of an embodiment of the present invention, the delay value delay is calculated as follows:

[0018] delay=unit / performance2;

[0019] The unit is a time unit, which is set according to different system clocks.

[0020] In a second aspect, an embodiment of the present invention provides a device for controlling GC performance balance, using the above method, including:

[0021] Information collection module, used to record the total number of front-end cmds host data cnt and the number of currently unfinished cmds host remain cnt in real time;

[0022] The performance calculation module is triggered by GC reading and writing, and is used to record the GC reading and writing task volume gc current remain cnt; after a set period, the initial performance performance1 and the recovery performance datagc performance are calculated according to the total cmd number host data cnt, the current unfinished cmd number host remaincnt and the GC reading and writing task volume gc current remain cnt; when data gc performance is not an invalid value, smoothing processing is performed to obtain the final performance performance2;

[0023] The delay setting module is used to calculate the delay value delay according to unit and the final performance performance2 when the final performance performance2 is not an invalid value; if the calculated delay value delay is different from the current DPU delay value dpudelay, the DPU delay value dpu delay is updated to the delay value delay, and then the DPU delay value dpu delay is set to the corresponding register of the DPU.

[0024] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the method for controlling GC performance balance in the aforementioned first aspect or any implementation of the first aspect are implemented.

[0025] The method, device and electronic device for controlling GC performance balance provided by the embodiments of the present invention have at least the following technical effects:

[0026] First, the method of controlling GC performance balance is used to balance the relationship between host read and write and GC read and write, that is, by setting the DPU module to take the delay of the host cmd (host command) to delay the entry of the front-end command, so that GC read and write have a certain amount of time to complete and achieve a certain balance.

[0027] Second, the method of controlling GC performance balance uses the accumulation of cycles to decide when to adjust the GC strategy, so as to ensure that adjustments will not be made at the beginning of GC running, which will affect the performance curve when there is no maximum pressure. The performance curve will not drop sharply through periodic accumulation. In some extreme or high-pressure situations of the SSD, the gcefficiency is adjusted to achieve a stable performance effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for the specific embodiments or the description of the prior art. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn according to the actual scale.

[0029] Figure 1 A flow chart of a method for controlling GC performance balance provided by an embodiment of the present invention is shown;

[0030] Figure 2 The intermediate steps of the method in the embodiment of the present invention are shown Figure 1 ;

[0031] Figure 3 The intermediate steps of the method in the embodiment of the present invention are shown Figure 2 ;

[0032] Figure 4 A structural block diagram of a device for controlling GC performance balance provided by an embodiment of the present invention is shown;

[0033] Figure 5 A schematic structural diagram of an electronic device for controlling GC performance balance provided by an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0034] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0035] It should be noted that, unless otherwise specified, the technical terms or scientific terms used in this application should have the common meanings understood by those skilled in the art to which the present invention belongs.

[0036] Figure 1 A flow chart of the steps of a method for controlling GC performance balance provided by an embodiment of the present invention, see Figure 1 , the method comprises the following steps:

[0037] S1, real-time record of the total number of front-end cmds host data cnt and the number of currently unfinished cmds host remaincnt;

[0038] It mainly records the total number of cmds in the front end and the remaining number of cmds that have not been completed, and records them in a struct for later performance calculation. Because before adjustment, you need to know how many hostcmds in the current queue have not been completed, because the proportion of host remain cnt (number of remaining cmds on the host) is needed when calculating performance in step 2.

[0039] Among them, the total number of cmds and the remaining number of cmds in the front end are obtained by the firmware by reading specially set registers, and then recorded in the structure variables. When the hw dpu obtains the cmd, cnt will be added by itself, so there is no need to attach a specific system to obtain it.

[0040] like Figure 2 As shown, in this method, when receiving commands, the front end will consider the maximum number of stored cmds in the current queue, and determine when to adjust the depth of the queue and the maximum number of redundant cmds that can be stored.

[0041] S2. Triggered by GC read and write, record the GC read and write task volume gc current remain cnt; calculate the initial performance performance1 and the recovery performance data gc performance after a set period. The calculation method of the initial performance performance1 and the recovery performance data gc performance is as follows:

[0042] performance1 = (host data cnt - host remain cnt) / queue depth;

[0043] data gc performance = (host data cnt - gc current remain cnt) / queuedepth;

[0044] Where queue depth is the corresponding queue depth (host queue depth is generally set to 10, gc queue depth is generally set to 15);

[0045] When data gc performance is not an invalid value (0xFFFFFFFF), smoothing processing is performed to obtain the final performance performance2. The calculation method of the final performance performance2 is as follows:

[0046] performance2=performance1 *1 / 5 + data gc performance * 4 / 5.

[0047] When performing GC reading and writing, performance will be calculated, but a period will be accumulated inside. After reaching a certain period, the current GC efficiency will be calculated. If the period is not reached, it will return directly. After the next max period is reached, performance1 and data GC performance will be calculated. Performance1 will be calculated using host data cnt, and data GC performance will be calculated using GC current remaincnt. When data GC performance is not equal to an invalid value, a smoothing process will be performed, and performance 1*1 / 5 + data GC performance * 4 / 5 will be used as our final performance2. Figure 3 The purpose of smoothing is to further smooth the current performance number and then calculate the subsequent DPU delay unit. The above smoothing formula can achieve better results under maximum pressure.

[0048] The accumulation of periods is used to decide when to adjust the GC strategy. This is to ensure that adjustments are not made right after the GC starts, which will affect the performance curve when there is no maximum pressure. The accumulation of periods is used to ensure that the performance curve does not drop sharply when the SSD is under certain extreme or high pressure conditions. At this time, gcefficiency is adjusted to achieve a stable performance effect.

[0049] S3. When the final performance performance2 is not an invalid value (0xFFFFFFFF), the delay value delay is obtained according to the unit calculation. The delay value delay is calculated as follows:

[0050] delay=unit / performance2;

[0051] Wherein, the unit is a time unit, which is set according to different system clocks;

[0052] If the calculated delay value delay is different from the current DPU delay value dpu delay, the DPU delay value dpu delay is updated to the delay value delay, and then the DPU delay value dpu delay is set to a corresponding register of the DPU.

[0053] The DPU module is a hardware register module that is used to specifically receive read and write commands from the host and pass them to the back-end module.

[0054] Unit is a variable defined by the firmware and is only used for formula calculation. System clock is the CPU system clock frequency. Unit will be adjusted according to different system clocks. Currently, 1us is defined as 10 units. For example, when the CPU frequency is 333MHZ, 1us = 10 units, and our delay = (1000000 * 10) / performance), where 1000000 is the time unit us, 1s = 1000000us.

[0055] The final calculated delay value will be set in the hardware's DPU register. This value will affect the speed at which the DPU receives the cmd from the front-end host. By delaying, the rate at which the DPU receives the cmd will be slowed down, allowing the back-end to have extra bandwidth time to process the gc commands, thereby meeting the curve performance requirements.

[0056] Figure 4 This is a structural block diagram of a device for controlling GC performance balance provided by an embodiment of the present invention, the device comprising:

[0057] Information collection module, used to record the total number of front-end cmds host data cnt and the number of currently unfinished cmds host remain cnt in real time;

[0058] The performance calculation module is triggered by GC reading and writing, and is used to record the GC reading and writing task volume gc current remain cnt; after a set period, the initial performance performance1 and the recovery performance datagc performance are calculated according to the total cmd number host data cnt, the current unfinished cmd number host remaincnt and the GC reading and writing task volume gc current remain cnt; when data gc performance is not an invalid value, smoothing processing is performed to obtain the final performance performance2;

[0059] The delay setting module is used to calculate the delay value delay according to unit and the final performance performance2 when the final performance performance2 is not an invalid value; if the calculated delay value delay is different from the current DPU delay value dpudelay, the DPU delay value dpu delay is updated to the delay value delay, and then the DPU delay value dpu delay is set to the corresponding register of the DPU.

[0060] Figure 4 The functions of each module in the embodiment correspond to the contents in the corresponding method embodiment and will not be repeated here.

[0061] Figure 5 The structural schematic diagram of the electronic device 50 provided in an embodiment of the present invention is shown, and the electronic device 50 includes at least one processor 501 (such as a CPU), at least one input and output interface 504, a memory 502, and at least one communication bus 503, which are used to realize the connection and communication between these components. At least one processor 501 is used to execute the computer instructions stored in the memory 502, so that the at least one processor 501 can execute any of the embodiments of the aforementioned method for controlling GC performance balance. The memory 502 is a non-transitory memory, which may include a volatile memory, such as a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection with at least one other device or unit is realized through at least one input and output interface 504 (which may be a wired or wireless communication interface).

[0062] In some implementations, the memory 502 stores a program 5021, and the processor 501 executes the program 5021 to execute the content of any of the aforementioned table partitioning method embodiments.

[0063] The electronic device may exist in a variety of forms, including but not limited to:

[0064] (1) Mobile communication equipment: This type of equipment is characterized by having mobile communication functions and its main purpose is to provide voice and data communications. This type of terminal includes: smart phones, multimedia phones, functional phones, and low-end phones.

[0065] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access features. These terminals include: PDA, MID, and UMPC devices.

[0066] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players, handheld game consoles, e-books, smart toys, and portable car navigation devices.

[0067] (4) Specific servers: devices that provide computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to the general computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, manageability, etc.

[0068] (5) Other electronic devices with data interaction functions.

[0069] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A method for controlling GC performance balance, characterized in that: The following steps are involved: S1, real-time record of the total number of front-end cmds host data cnt and the number of currently unfinished cmds host remaincnt; S2. Triggered by GC read and write, record the GC read and write task volume gc current remain cnt; calculate the initial performance performance1 and the recovery performance data gc performance according to the total cmd number host data cnt, the current unfinished cmd number host remain cnt and the GC read and write task volume gccurrent remain cnt after a set period; When data gc performance is not an invalid value, smoothing is performed to obtain the final performance performance2; S3. When the final performance performance2 is not an invalid value, the delay value delay is calculated based on unit and the final performance performance2; If the calculated delay value delay is different from the current DPU delay value dpu delay, updating the DPU delay value dpu delay to the delay value delay, and then setting the DPU delay value dpu delay to a corresponding register of the DPU; Wherein, cmd is a command, DPU is a hardware register, and the initial performance performance1 and the recovery performance data gcperformance are calculated as follows: performance1=(host data cnt-host remain cnt) / queue depth; data gc performance=(host data cnt-gc current remain cnt) / queue depth; Among them, queue depth is the corresponding queue depth.

2. The method for controlling GC performance balance according to claim 1, characterized in that: The final performance performance2 calculation method is as follows: performance2=performance1*1 / 5+data gc performance*4 / 5.

3. The method for controlling GC performance balance according to claim 1, characterized in that: The delay value delay is calculated as follows: delay=unit / performance2; The unit is a time unit, which is set according to different system clocks. The system clock is the CPU system clock frequency.

4. A device for controlling GC performance balance, using the method for controlling GC performance balance as claimed in any one of claims 1 to 3, characterized in that: include: Information collection module, used to record the total number of front-end cmds host data cnt and the number of currently unfinished cmds host remain cnt in real time; The performance calculation module is triggered by GC reading and writing, and is used to record the GC reading and writing task volume gc current remain cnt; after a set period, the initial performance performance1 and the recovery performance data gcperformance are calculated according to the total cmd number host data cnt, the current unfinished cmd number host remain cnt and the GC reading and writing task volume gc current remain cnt; when data gc performance is not an invalid value, smoothing processing is performed to obtain the final performance performance2; The delay setting module is used to calculate the delay value delay according to unit and the final performance performance2 when the final performance performance2 is not an invalid value; if the calculated delay value delay is different from the current DPU delay value dpudelay, the DPU delay value dpu delay is updated to the delay value delay, and then the DPU delay value dpu delay is set to the corresponding register of the DPU.

5. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the method for controlling GC performance balance according to any one of claims 1 to 3 are implemented.

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