AVC Joint-Adjustment Control Method and System Based on Dynamic Reactive Power Compensation Technology

Abstract

The present application provides an AVC joint debugging control method and system based on dynamic reactive power compensation technology. By combining the admittance matrix and the compensation matrix, the compensation matrix is used to lock the output compensation voltage. Then, in combination with a neural network, the compensation matrix and the current admittance matrix are jointly used as inputs, and the neural network model calculates the overall compensation voltage to obtain an updated admittance matrix. Finally, the updated admittance matrix is used as the admittance matrix of the current power system for dynamic compensation. In this way, the influence of large voltage fluctuations can be reduced during reactive power compensation, and the power grid loss can be reduced.

Description

Technical Field

[0001] This application belongs to the technical field of power equipment, and particularly relates to an AVC coordinated control method and system based on dynamic reactive power compensation technology. Background Art

[0002] The AVC system is based on accurate real-time information of the power grid and realizes automatic adjustment of the reactive power of the power grid through voltage reactive power adjustment means of the power grid. Existing AVC systems generally use on-load tap-changers and capacitors / reactors configured in the power grid as voltage reactive power compensation means. Currently, the defect of the AVC system in adjusting voltage reactive power is that the voltage fluctuation is relatively large, resulting in a large power grid loss. Summary of the Invention

[0003] The embodiments of this application provide an AVC coordinated control method and system based on dynamic reactive power compensation technology. By combining the admittance matrix and the compensation matrix, the compensation matrix is used to lock the output compensation voltage. Then, in combination with a neural network, the compensation matrix and the current admittance matrix are used as inputs together. The neural network model calculates the overall compensation voltage to obtain an updated admittance matrix. Finally, the updated admittance matrix is used as the admittance matrix of the current power system for dynamic compensation. In this way, the influence of large voltage fluctuation can be reduced during reactive power compensation, and the power grid loss can be reduced.

[0004] The first aspect embodiment of this application provides an AVC coordinated control method based on dynamic reactive power compensation technology. The AVC coordinated control method includes:

[0005] Obtain the current operating parameters and operating state data of the power system to be controlled;

[0006] Determine the current admittance matrix of the power system according to the current operating parameters and operating state data;

[0007] Use the compensation matrix and the current admittance matrix as inputs and input them into a preset neural network model to obtain an updated admittance matrix; the neural network model is trained based on the historical admittance matrix and the compensation matrix;

[0008] Perform AVC coordinated control on the power system according to the updated admittance matrix.

[0009] In an optional embodiment, the determining the current admittance matrix of the power system according to the current operating parameters and operating state data includes:

[0010] Establish a nodal admittance matrix of the system and map the parameters of each power equipment in the power system to the admittance elements between nodes;

[0011] Determine the voltage amplitude and phase angle of each node according to the current operating state, and calculate the injection power of each node;

[0012] Using the node voltage and injection power, solve the node voltage of the current system through power flow calculation;

[0013] Substitute the calculated node voltage into the admittance matrix equation to obtain the admittance matrix of the current system.

[0014] In an alternative embodiment, the neural network model is established based on a physical model and data-driven technology.

[0015] In an alternative embodiment, the neural network model is:

[0016] dV / dt = f(I, Y, B), dI / dt = g(V, Y, B);

[0017] where I_comp = B * V, I_comp is the compensation current vector, B is the compensation matrix, I = Y * V, I is the node current vector, V is the node voltage vector, Y is the admittance matrix, Y_new = Y + B, Y_new is the updated admittance matrix, f and g are functional relationships established based on the physical principles of the power system, f(I, Y, B) = -k1Y * V – k2B * V + k3I; g(V, Y, B) = C * (-k1Y * V – k2B * V + k3I) + k4G * V; f(I, Y, B) represents the change of the node voltage over time, determined by the admittance matrix Y, the compensation matrix B, and the node current I; g(V, Y, B) represents the change of the node current over time, determined by the capacitance matrix C, the conductance matrix G, and the node voltage V, and k1, k2, k3, and k4 are weight parameters to be learned and determined.

[0018] In an alternative embodiment, it further includes:

[0019] Obtain the node information and node numbers of the power equipment nodes of the power system;

[0020] Determine whether the power equipment node of the power system is a compensation central power equipment node; the compensation central power equipment node is directly electrically connected to more than a preset number of power equipment;

[0021] If the power equipment node of the power system is not the compensation central power equipment node, then perform the following steps:

[0022] Obtain the numbers and operating state data of the power equipment nodes directly connected to the power equipment node;

[0023] If the power equipment nodes directly connected to the current power equipment node are not directly connected to one of the compensation central power equipment nodes, continue to obtain the numbers and operating status data of the directly connected power equipment nodes until the power equipment nodes directly connected to the current power equipment node are directly connected to one of the compensation central power equipment nodes;

[0024] Determine the compensation matrix according to the current power equipment node, one of the compensation central power equipment nodes, and the operating status data of the power equipment nodes directly connected to the current power equipment node.

[0025] In an alternative embodiment, the determining the compensation matrix according to the current power equipment node, one of the compensation central power equipment nodes, and the operating status data of the power equipment nodes directly connected to the current power equipment node includes:

[0026] According to the current reactive power in the operating status data of the current power equipment node, one of the compensation central power equipment nodes, and the power equipment nodes directly connected to the current power equipment node, and combining the allocation weight coefficients of each power equipment node itself, calculate the current reactive power that can be output by each power equipment node; wherein the allocation weight coefficient of the compensation central power equipment node is greater than that of other power equipment nodes;

[0027] Determine the compensation matrix according to the current reactive power that can be output by each power equipment node and in combination with the current directional input divergence coefficient map of its own power equipment node, where the current directional input divergence coefficient map includes the input coefficients of each directly connected node and the secondary directly connected nodes.

[0028] In an alternative embodiment, performing AVC joint debugging control on the power system according to the updated admittance matrix includes:

[0029] Control the node voltages and output powers of each power equipment node in the power system according to the updated admittance matrix.

[0030] An embodiment of the second aspect of the present application provides an AVC joint debugging control system based on dynamic reactive power compensation technology. The AVC joint debugging control system includes:

[0031] An acquisition module that acquires the current operating parameters and operating status data of the power system to be controlled;

[0032] A determination module that determines the current admittance matrix of the power system according to the current operating parameters and operating status data;

[0033] An input module takes the compensation matrix and the current admittance matrix as inputs and feeds them into a preset neural network model to obtain an updated admittance matrix; the neural network model is trained based on the historical admittance matrix and the compensation matrix.

[0034] A control module performs AVC coordinated control on the power system according to the updated admittance matrix.

[0035] In an optional embodiment, the determination module includes:

[0036] A establishment unit establishes the nodal admittance matrix of the system and maps the parameters of each power device in the power system to the admittance elements between nodes.

[0037] A calculation unit determines the voltage amplitude and phase angle of each node according to the current operating state and calculates the injection power of each node.

[0038] A nodal voltage solving unit uses the nodal voltage and the injection power to solve the nodal voltage of the current system through power flow calculation.

[0039] An admittance matrix determination unit substitutes the calculated nodal voltage into the admittance matrix equation to obtain the admittance matrix of the current system.

[0040] An embodiment of the third aspect of the present application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, where when the processor executes the computer program, the above method is implemented.

[0041] An embodiment of the fourth aspect of the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the above method is implemented.

[0042] Advantages of the present application

[0043] The present application provides an AVC coordinated control method and system based on dynamic reactive power compensation technology. By combining the admittance matrix and the compensation matrix, the compensation matrix is used to lock the output compensation voltage. Then, in combination with a neural network, the compensation matrix and the current admittance matrix are used as inputs together. The neural network model calculates the overall compensation voltage to obtain an updated admittance matrix. Finally, the updated admittance matrix is used as the admittance matrix of the current power system for dynamic compensation. In this way, the impact of large voltage fluctuations during reactive power compensation can be reduced, and power grid losses can be minimized. Description of the drawings

[0044] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for use in the embodiments or the description of the prior art. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0045] Figure 1 is a schematic flow chart of the steps of an AVC joint debugging control method provided by an embodiment of the present application based on dynamic reactive power compensation technology;

[0046] Figure 2 is a schematic structural diagram of an AVC joint debugging control device provided by an embodiment of the present application based on dynamic reactive power compensation technology;

[0047] Figure 3 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. Detailed implementation manners

[0048] In the following description, for the purpose of illustration rather than limitation, specific details such as specific system structures and technologies are proposed to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0049] It should be understood that when used in the specification of the present application and the appended claims, the term "comprising" indicates the presence of the described features, wholes, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their combinations.

[0050] It should also be understood that the term "and / or" used in the specification of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0051] As used in the specification of the present application and the appended claims, the term "if" can be interpreted as "when...", "once", "in response to a determination", or "in response to a detection" according to the context. Similarly, the phrase "if a determination is made" or "if [the described condition or event] is detected" can be interpreted as meaning "once a determination is made", "in response to a determination", "once [the described condition or event] is detected", or "in response to a detection of [the described condition or event]" according to the context.

[0052] In addition, in the description of the specification and the appended claims of the present application, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0053] The reference to "one embodiment" or "some embodiments" etc. described in the specification of the present application means that a specific feature, structure or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, the statements "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments", etc. that appear in different places in this specification do not necessarily refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in other ways. The terms "comprising", "including", "having" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in other ways.

[0054] The embodiment of the present application provides an AVC joint debugging control method and system based on dynamic reactive power compensation technology. By combining the admittance matrix and the compensation matrix, the compensation matrix is used to lock the output compensation voltage. Then, in combination with a neural network, the compensation matrix and the current admittance matrix are jointly used as inputs, and the neural network model calculates the overall compensation voltage to obtain an updated admittance matrix. Finally, the updated admittance matrix is used as the admittance matrix of the current power system for dynamic compensation. In this way, the influence of large voltage fluctuations can be reduced during reactive power compensation, and the grid loss can be reduced.

[0055] The embodiment of the first aspect of the present application provides an AVC joint debugging control method based on dynamic reactive power compensation technology. The AVC joint debugging control method includes:

[0056] S1: Obtain the current operation parameters and operation state data of the power system to be controlled;

[0057] S2: Determine the current admittance matrix of the power system according to the current operation parameters and operation state data;

[0058] S3: Jointly use the compensation matrix and the current admittance matrix as inputs and input them into a preset neural network model to obtain an updated admittance matrix;

[0059] S4: Perform AVC joint debugging control on the power system according to the updated admittance matrix.

[0060] The present application provides an AVC joint debugging control method and system based on dynamic reactive power compensation technology. By combining the admittance matrix and the compensation matrix, the compensation matrix is used to lock the compensated voltage output. Then, in combination with a neural network, the compensation matrix and the current admittance matrix are jointly used as inputs, and the neural network model calculates the overall compensated voltage to obtain an updated admittance matrix. Finally, the updated admittance matrix is used as the admittance matrix of the current power system for dynamic compensation. In this way, the influence of large voltage fluctuations during reactive power compensation can be reduced, and power grid losses can be minimized.

[0061] The following details the embodiments of the present application. In the embodiments of the present application, determining the current admittance matrix of the power system according to the current operating parameters and operating state data includes:

[0062] S21: Establish a nodal admittance matrix of the system, and map the parameters of each power device in the power system to the admittance elements between nodes;

[0063] S22: According to the current operating state, determine the voltage amplitude and phase angle of each node, and calculate the injection power of each node;

[0064] S23: Use the nodal voltage and injection power to solve the nodal voltage of the current system through power flow calculation;

[0065] S24: Substitute the calculated nodal voltage into the admittance matrix equation to obtain the admittance matrix of the current system.

[0066] Specifically, in the embodiments of the present application, the specific process of forming the admittance matrix can be formed in the following manner:

[0067] Step 1: Using a spatial distribution representation method of power system nodes based on electrical distance, first form a power system nodal admittance matrix, invert the nodal admittance matrix to obtain a power system nodal impedance matrix; use the power system nodal impedance matrix to solve the electrical distance between any two nodes in the power system to characterize the distribution of nodes in space. The modulus of the connection impedance between any two power system nodes is the electrical distance between the nodes. The relationship between the electrical distance and the power system nodal impedance matrix is: Xij = |(Zii - Zij) - (Zij - Zjj)|. In the formula, Xij is the electrical distance between any two nodes i and j in the power system. For a power system with n nodes, Xij is an n-order square matrix with all main diagonal elements being 0. The n-dimensional vector of each row represents the electrical distance from the node corresponding to that row to other nodes, constituting the distribution of a node in the n-dimensional space; Zij is the element in the i-th row and j-th column of the power system nodal impedance matrix, that is, the mutual impedance between nodes i and j, and Zii and Zjj are the diagonal elements of the nodal impedance matrix, which are the self-impedances of nodes i and j respectively;

[0068] Step 2: Using the power system node spatial distribution dimensionality reduction method, reduce the high-dimensional spatial distribution Xij of nodes represented by the electrical distances between power system nodes to two-dimensional spatial coordinates Yij. Define the coordinates of the power system nodes on the two-dimensional plane as (yi1, yi2), and plot the reduced power system nodes on the two-dimensional plane coordinates.

[0069] Furthermore, it should be noted that this application can number the power equipment nodes and define the vector parameters of the admittance matrix. Specifically, it includes the following steps:

[0070] S1. Obtain the node information of the power equipment nodes and the branch information of the network branches. The node information includes the names and types of all power equipment nodes in the power network, and the branch information includes: the starting node name, the ending node name, and the branch reactance of all network branches in the power network.

[0071] Step A2. Obtain the node numbers of each of the power equipment nodes. If any power equipment node already has a number and does not need to be adjusted, directly execute Step A3.

[0072] Step A3. Define the column vectors of the node admittance matrix in the compressed storage form (CSR). The column vectors include three columns, namely the numerical column vector, the column index column vector, and the row offset column vector. Define the numerical column vector as value, the column index column vector as colindex, and the row offset column vector as rowptr.

[0073] Step A4. Define and construct the node number column vector of the power equipment nodes of the power system and the admittance column vector of the target network branches. Among them, the power equipment nodes of the power system are any power equipment nodes in the power network, and the target network branches are all network branches connected to the power equipment nodes of the power system.

[0074] Step A5. Based on the column vectors of the node admittance matrix, splice and write the node number column vector and the admittance column vector to obtain the direct writing result of the node admittance matrix.

[0075] Furthermore, the node number of any power equipment node is less than the number of the compensation center in the power network. The compensation center is given in advance and will be indicated in the data file.

[0076] It should be noted that the compensation center node of this application is the core node of the compensation, which includes sufficient reactive power compensation devices and their combinations, such as multiple capacitors, etc. This application does not limit this.

[0077] Specifically, the neural network model is established based on the physical model and data-driven technology.

[0078] The neural network model is as follows:

[0079] dV / dt = f(I, Y, B), dI / dt = g(V, Y, B);

[0080] where I_comp = B * V, I_comp is the compensation current vector, B is the compensation matrix, I = Y * V, I is the node current vector, V is the node voltage vector, Y is the admittance matrix, Y_new = Y + B, Y_new is the updated admittance matrix, and f and g are functional relationships established based on the physical principles of the power system. f(I, Y, B) = -k1Y * V – k2B * V + k3I; g(V, Y, B) = C * (-k1Y * V – k2B * V + k3I) + k4G * V; f(I, Y, B) represents the change in node voltage over time, which is determined by the admittance matrix Y, the compensation matrix B, and the node current I; g(V, Y, B) represents the change in node current over time, which is determined by the capacitance matrix C, the conductance matrix G, and the node voltage V. k1, k2, k3, and k4 are weight parameters to be learned and determined.

[0081] In this way, the values of k1 - k4 can be obtained through deep learning, so as to obtain the corresponding relationships between the admittance matrix and the compensation matrix and f(I, Y, B) and g(V, Y, B), and thus the current and voltage of each node can be calculated to dynamically compensate the current and voltage of the power node to the current f(I, Y, B) and g(V, Y, B). This application will not elaborate on this.

[0082] In an alternative embodiment, it further includes:

[0083] Obtain the node information and node numbers of the power equipment nodes of the power system;

[0084] Determine whether the power equipment node of the power system is a compensation central power equipment node; the compensation central power equipment node is directly electrically connected to more than a preset number of power equipment;

[0085] If the power equipment node of the power system is not the compensation central power equipment node, then perform the following steps:

[0086] Obtain the numbers and operating status data of the power equipment nodes directly connected to the power equipment node;

[0087] If the power equipment nodes directly connected to the power equipment node are not directly connected to one of the compensation central power equipment nodes, continue to obtain the numbers and operating status data of the directly connected power equipment nodes until the power equipment nodes directly connected to the current power equipment node are directly connected to one of the compensation central power equipment nodes;

[0088] Determine the compensation matrix according to the operating status data of the current power equipment node, one of the compensation central power equipment nodes, and the power equipment nodes directly connected to the current power equipment node.

[0089] In this embodiment, the compensation matrix forms a high-compensation output node by configuring the compensation central power equipment node, and the remaining nodes directly connected to the compensation central power equipment node are used as low-compensation output nodes. Then, first, according to the direct connection relationship, find the compensation central power equipment node after one or more direct connections, and the direct connection nodes of all the direct connection nodes passed through during the search process together form a "compensation local graph". This graph includes a node graph formed by multiple direct connection topologies. In the node graph, with this power equipment node as the center, after multiple direct connection topologies, stop the topology until the compensation central power equipment node is found. Then, the compensation local graph includes one compensation central power equipment node, or if multiple compensation central power equipment nodes are found through a single direct connection topology, the compensation local graph includes multiple compensation central power equipment nodes.

[0090] The compensation central power equipment node and the directly connected nodes jointly compensate this power equipment node. Thus, on the one hand, the impact on other power equipment nodes is reduced, and on the other hand, the compensation power can always be transmitted along the optimal path through this method, thereby reducing the loss. That is, the compensation matrix formed by this method can simultaneously reduce the impact of the compensation itself on other power equipment nodes and the impact of transmission loss.

[0091] After that, each compensation output node has a corresponding output weight. The weight of the compensation central power equipment node is relatively high and can be used as the main compensation output, while the weights of other directly connected power equipment nodes are relatively low and can be used as secondary compensation outputs. In an alternative embodiment, the determining of the compensation matrix according to the operating status data of the current power equipment node, one of the compensation central power equipment nodes, and the power equipment nodes directly connected to the current power equipment node includes:

[0092] According to the current reactive power in the operating status data of the current power equipment node, one of the compensation central power equipment nodes, and the power equipment nodes directly connected to the current power equipment node, and combining the allocated weight coefficients of each power equipment node itself, calculate the current outputtable reactive power of each power equipment node; wherein the allocated weight coefficient of the compensation central power equipment node is greater than that of other power equipment nodes.

[0093] According to the current outputtable reactive power of each power equipment node, and combining the current directional input divergence coefficient graph of its own power equipment node, determine the compensation matrix, wherein the current directional input divergence coefficient graph includes the input coefficients of each directly connected node and the secondary directly connected nodes.

[0094] In this way, each node can perform compensation output for multiple directly connected nodes by combining the assigned weight coefficients. When there are multiple nodes that need compensation in the power system, the compensation can be spread out by combining the assigned weight coefficients. At the same time, a node to be compensated is compensated by multiple nodes, so that the entire compensation network will not have the phenomenon of overcurrent or overvoltage in one direction or at a single point.

[0095] Moreover, the self-node has input coefficients corresponding to each compensation node. Thus, by combining the input coefficients again, the compensation amount that each compensation node directionally compensates to the node to be compensated is limited within a controllable range, so that overall dynamic compensation within the entire domain can be carried out.

[0096] In this way, when a certain node fails, a new compensation network can be instantly updated. The failure of a certain node has almost no impact on the entire compensation process. And even if the faulty node is the compensation central power equipment node, other compensation central power equipment nodes can be found for replacement compensation. With the cooperation of the distribution coefficient and the input coefficient, the influence of each node with compensation output is further reduced, so that the entire dynamic compensation process will not be affected by any faults.

[0097] In an alternative embodiment, according to the updated admittance matrix, AVC coordinated control is performed on the power system, including:

[0098] Controlling the node voltages and output powers of each power equipment node in the power system according to the updated admittance matrix.

[0099] An embodiment of the second aspect of the present application provides an AVC coordinated control system based on dynamic reactive power compensation technology. The AVC coordinated control system includes:

[0100] An acquisition module that acquires the current operation parameters and operation status data of the power system to be controlled;

[0101] A determination module that determines the current admittance matrix of the power system according to the current operation parameters and operation status data;

[0102] An input module that takes the compensation matrix and the current admittance matrix as inputs and inputs them into a preset neural network model to obtain an updated admittance matrix; the neural network model is trained based on the historical admittance matrix and the compensation matrix;

[0103] A control module that performs AVC coordinated control on the power system according to the updated admittance matrix.

[0104] In an alternative embodiment, the determination module includes:

[0105] An establishment unit that establishes the node admittance matrix of the system and maps the parameters of each power equipment in the power system to the admittance elements between the nodes;

[0106] A calculation unit, which determines the voltage amplitude and phase angle of each node according to the current operating state and calculates the injection power of each node.

[0107] A node voltage solving unit, which uses the node voltage and injection power to solve the node voltage of the current system through power flow calculation.

[0108] An admittance matrix determining unit, which substitutes the calculated node voltage into the admittance matrix equation to obtain the admittance matrix of the current system.

[0109] It can be seen that the present application provides an AVC joint debugging control method and system based on dynamic reactive power compensation technology. By combining the admittance matrix and the compensation matrix, the compensation matrix is used to lock the compensated voltage output. Then, in combination with a neural network, the compensation matrix and the current admittance matrix are used as inputs together. The neural network model calculates the overall compensated voltage to obtain an updated admittance matrix. Finally, the updated admittance matrix is used as the admittance matrix of the current power system for dynamic compensation. In this way, the influence of large voltage fluctuations during reactive power compensation can be reduced and the power grid loss can be decreased.

[0110] Figure 3 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The electronic device 400 includes: at least one processor 401 ( Figure 3 only one processor is shown), a memory 402, and a computer program 403 stored in the memory 402 and executable on the at least one processor 401. When the processor 401 executes the computer program 403, the steps in the above method embodiment are implemented.

[0111] The electronic device 400 may be a computing device such as a desktop computer, a notebook, a palm computer, and a cloud server. The electronic device may include, but is not limited to, a processor 401 and a memory 402. Those skilled in the art can understand that Figure 3 merely examples of the electronic device 400, which do not constitute a limitation on the electronic device 400. It may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, it may also include input / output devices, network access devices, etc.

[0112] The so-called processor 401 may be a Central Processing Unit (CPU), and this processor 401 may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or this processor may also be any conventional processor, etc.

[0113] In some embodiments, the memory 402 may be an internal storage unit of the electronic device 400, such as the hard disk or memory of the electronic device 400. In other embodiments, the memory 402 may also be an external storage device of the electronic device 400, such as a plug-in hard disk equipped on the electronic device 400, a Smart Media Card (SMC), a Secure Digital (SD) card, a Flash Card, etc. Further, the memory 402 may also include both the internal storage unit of the electronic device 400 and the external storage device. The memory 402 is used to store an operating system, application programs, a Boot Loader, data, and other programs, such as the program code of the computer program, etc. The memory 402 may also be used to temporarily store data that has been output or will be output.

[0114] Those skilled in the art can clearly understand that, for the convenience and brevity of description, only the above division of each functional unit and module is used as an example. In actual applications, the above functions can be allocated to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment can be integrated in one processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above integrated unit can be implemented in the form of hardware or in the form of a software functional unit. In addition, the specific names of each functional unit and module are only for the convenience of mutual distinction and do not limit the protection scope of this application. The specific working processes of the units and modules in the above system can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated here.

[0115] The embodiments of the present application also provide a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in the above method embodiments can be implemented.

[0116] The embodiments of the present application provide a computer program product. When the computer program product runs on a mobile terminal, the mobile terminal can implement the steps in the above method embodiments when executed.

[0117] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the above method embodiments of the present application can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium. When the computer program is executed by a processor, the steps in the above method embodiments can be implemented. Among them, the computer program includes computer program code, and the computer program code can be in the form of source code, object code, executable file or some intermediate form. The computer-readable medium can at least include: any entity or device that can carry the computer program code to the photographing device / electronic device, recording medium, computer memory, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), electrical carrier signal, telecommunication signal, and software distribution medium. For example, a USB flash drive, a mobile hard disk, a magnetic disk or an optical disc, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium may not be an electrical carrier signal and a telecommunication signal.

[0118] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0119] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. A professional technician can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of the present application.

[0120] In the embodiments provided in the present application, it should be understood that the disclosed device / network device and method can be implemented in other ways. For example, the device / network device embodiments described above are merely illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces. The indirect coupling or communication connection of the device or unit can be in an electrical, mechanical or other form.

[0121] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. An AVC joint control method based on dynamic reactive power compensation technology, characterized in that: The AVC joint control method comprises: Obtaining current operating parameters and operating status data of the power system to be controlled; Determining a current admittance matrix of the power system according to the current operating parameters and operating status data; The compensation matrix and the current admittance matrix are inputted into a preset neural network model to obtain an updated admittance matrix; the neural network model is formed based on the training of the historical admittance matrix and the compensation matrix; Performing AVC joint control on the power system according to the updated admittance matrix; The neural network model is: dV / dt=f(I,Y,B), dI / dt=g(V,Y,B); Among them, I_comp=B*V, I_comp is the compensation current vector, B is the compensation matrix, I=Y*V, I is the node current vector, V is the node voltage vector, Y is the admittance matrix, Y_new=Y+B, Y_new is the updated admittance matrix, f and g are functional relationships established according to the physical principles of the power system, f(I,Y,B)=-k1Y*V–k2 B*V+k3 I; g(V,Y,B)=C*(-k1Y*V–k2 B*V+k3 I)+k4G*V; f(I,Y,B) represents the change of node voltage over time, which is determined by the admittance matrix Y, the compensation matrix B and the node current I; g(V,Y,B) represents the change of node current over time, which is determined by the capacitance matrix C, the conductance matrix G and the node voltage V, and k1, k2, k3 and k4 are weight parameters to be learned and determined.

2. The AVC joint control method based on dynamic reactive power compensation technology according to claim 1 is characterized in that: Determining the current admittance matrix of the power system according to the current operating parameters and the operating status data includes: Establish the node admittance matrix of the system and map the parameters of each power device in the power system to the admittance elements between nodes; According to the current operating status, the voltage amplitude and phase angle of each node are determined, and the injected power of each node is calculated; Using the node voltage and injected power, the node voltage of the current system is solved through power flow calculation; Substitute the calculated node voltage into the admittance matrix equation to obtain the admittance matrix of the current system.

3. The AVC joint control method based on dynamic reactive power compensation technology according to claim 2 is characterized in that: The neural network model is established based on physical model and data driven technology.

4. The AVC joint control method based on dynamic reactive power compensation technology according to claim 3 is characterized in that: Also includes: Obtaining node information and node numbers of power equipment nodes of the power system; Determining whether the power equipment node of the power system is a compensation hub power equipment node; The compensation hub power equipment node is directly electrically connected to more than a preset number of power equipment; If the power equipment node of the power system is not the compensation hub power equipment node, the following steps are performed: Obtaining the number and operation status data of the electric power equipment node to which the electric power equipment node is directly connected; If the power equipment node directly connected to the power equipment node is not directly connected to one of the compensation hub power equipment nodes, continue to obtain the number and operation status data of the directly connected power equipment node until the power equipment node directly connected to the current power equipment node is directly connected to one of the compensation hub power equipment nodes; The compensation matrix is ​​determined based on the operating status data of the current power device node, one of the compensation hub power device nodes, and the power device nodes directly connected to the current power device node.

5. The AVC joint control method based on dynamic reactive power compensation technology according to claim 3 is characterized in that: Determining the compensation matrix according to the operating status data of the current power device node, one of the compensation hub power device nodes, and the power device node directly connected to the current power device node includes: According to the current reactive power in the operating status data of the current power device node, one of the compensation hub power device nodes, and the power device node directly connected to the current power device node, combined with the allocation weight coefficient of each power device node itself, the current output reactive power of each power device node is calculated; wherein the allocation weight coefficient of the compensation hub power device node is greater than the allocation weight coefficients of other power device nodes; The compensation matrix is ​​determined according to the current output reactive power of each power device node and the current directional input divergence coefficient spectrum of the power device node itself, wherein the current directional input divergence coefficient spectrum includes the input coefficients of each directly connected node and the secondary directly connected node.

6. The AVC joint control method based on dynamic reactive power compensation technology according to claim 1 is characterized in that: According to the updated admittance matrix, AVC joint control is performed on the power system, including: According to the updated admittance matrix, the node voltage and output power of each power equipment node in the power system are controlled.

7. An AVC joint control system based on dynamic reactive power compensation technology, characterized in that: The AVC joint control system comprises: An acquisition module, for acquiring current operating parameters and operating status data of the power system to be controlled; A determination module, which determines a current admittance matrix of the power system according to the current operating parameters and operating status data; An input module, which takes the compensation matrix and the current admittance matrix as inputs and inputs them into a preset neural network model to obtain an updated admittance matrix; the neural network model is formed based on the training of the historical admittance matrix and the compensation matrix; A control module performs AVC joint control on the power system according to the updated admittance matrix; The neural network model is: dV / dt=f(I,Y,B), dI / dt=g(V,Y,B); Among them, I_comp=B*V, I_comp is the compensation current vector, B is the compensation matrix, I=Y*V, I is the node current vector, V is the node voltage vector, Y is the admittance matrix, Y_new=Y+B, Y_new is the updated admittance matrix, f and g are functional relationships established according to the physical principles of the power system, f(I,Y,B)=-k1Y*V–k2 B*V+k3 I; g(V,Y,B)=C*(-k1Y*V–k2 B*V+k3 I)+k4G*V; f(I,Y,B) represents the change of node voltage over time, which is determined by the admittance matrix Y, the compensation matrix B and the node current I; g(V,Y,B) represents the change of node current over time, which is determined by the capacitance matrix C, the conductance matrix G and the node voltage V, and k1, k2, k3 and k4 are weight parameters to be learned and determined.

8. An electronic device, characterized in that: include: A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 5 when executing the computer program.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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