Display panel, display module and display device

Abstract

Embodiments of the present disclosure provide a display panel, a display module and a display device, and relate to the technical field of display, and are used for improving the problem of black spots generated by the display panel at the edge of the hole. The display area includes an opening area, an isolation area and a pixel area. The display panel includes a substrate, a first isolation structure, a cathode layer and a conductive block. The first isolation structure surrounds at least part of the opening area. The first sub-part is located on the side of the first isolation structure away from the substrate, and the second sub-part is located on the side of the first isolation structure away from or close to the opening area; and the first sub-part and the second sub-part are electrically connected through the first isolation structure. The conductive block is arranged between the substrate and the first isolation structure and is located in the isolation area; the boundary of the conductive block close to the opening area is flush with the boundary of the opening area; the voltage difference between the conductive block and the first sub-part and the second sub-part is less than or equal to the driving voltage of the first ion; wherein the first ion reacts chemically with inorganic material. The above display panel is used for displaying images.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel, a display module, and a display device. Background Art

[0002] With the advancement of display technology, display devices (such as mobile phones, laptops, and tablets) are increasingly being used in people's lives. Organic Light-Emitting Diode (OLED) displays, in particular, have attracted widespread attention due to their advantages, including active illumination, wide viewing angles, high contrast, fast response times, low power consumption, and ultra-thinness. Summary of the Invention

[0003] An object of the embodiments of the present disclosure is to provide a display panel, a display module, and a display device, which are used to improve the problem of black spots on the edges of holes in the display panel.

[0004] To achieve the above objectives, the embodiments of the present disclosure provide the following technical solutions:

[0005] In one aspect, a display panel is provided. The display panel comprises a display area; the display area includes an aperture area, an isolation area, and a pixel area; the isolation area is located between the aperture area and the pixel area. The display panel comprises a substrate, a first isolation structure, a cathode layer, and a conductive block. The first isolation structure is disposed on the substrate and located in the isolation area; the first isolation structure surrounds at least a portion of the aperture area. The cathode layer covers the isolation area; the cathode layer comprises a first and a second partitioned subsection, the first and second subsections being located in the isolation area, the first subsection being located on a side of the first isolation structure away from the substrate, and the second subsection being located on a side of the first isolation structure away from or closer to the aperture area; and the first and second subsections being electrically connected via the first isolation structure. The conductive block is disposed between the substrate and the first isolation structure and located in the isolation area; the boundary of the conductive block adjacent to the aperture area is flush with the boundary of the aperture area; the voltage difference between the conductive block and the first and second subsections is less than or equal to the driving voltage of a first ion; wherein the first ion chemically reacts with an inorganic material.

[0006] In the above-mentioned display panel, the voltage difference between the conductive block and the first sub-section and the second sub-section is not sufficient to drive the first ions located between the conductive block and the first sub-section and the second sub-section to move into the first sub-section and the second sub-section, thereby reducing the number of first ions in the first sub-section and the second sub-section, so that the number of first ions in the first sub-section and the second sub-section is small or non-existent, which is beneficial to reducing the degree and speed of reaction between the first inorganic encapsulation layer and / or the second inorganic encapsulation layer on the side of the first sub-section and the second sub-section away from the substrate and the first ions, thereby reducing the risk of damage to the first inorganic encapsulation layer and / or the second inorganic encapsulation layer, and further improving the problem of black spots on the edge of the holes generated in the display panel.

[0007] In some embodiments, the conductive block is electrically insulated from the first isolation structure. The display panel further includes a first connecting line connected to the conductive block and to a first voltage terminal.

[0008] In some embodiments, the voltage on the cathode layer is the same as the voltage received at the first voltage terminal.

[0009] In some embodiments, the conductive block is connected to the first isolation structure or the second sub-portion.

[0010] In some embodiments, the display panel further includes a first insulating stack. The first insulating stack is located in the pixel region and extends to the isolation region. The first insulating stack is located between the first isolation structure and the conductive block. The first insulating stack has a first through hole extending through the first insulating stack. The first isolation structure extends into the first through hole and is connected to the conductive block.

[0011] In some embodiments, the display panel further includes a first connecting line connected to the conductive block and to a first voltage terminal; the conductive block is configured such that a voltage difference with the supporting layer is less than or equal to a driving voltage of the first ion.

[0012] In some embodiments, the first voltage terminal is grounded.

[0013] In some embodiments, the display panel further comprises a pixel circuit layer and a light emitting device layer. The pixel circuit layer is disposed between the substrate and the cathode layer, and comprises a plurality of first pixel circuits and a plurality of redundant pixel circuits. The plurality of first pixel circuits are located in the pixel region, and the plurality of redundant pixel circuits are located in the isolation region. The plurality of redundant pixel circuits are adjacent to the first pixel circuits located in the pixel region and close to the edge of the aperture region. The light emitting device layer is located on the side of the pixel circuit layer away from the substrate, and comprises a plurality of light emitting devices. The first pixel circuits are electrically connected to the light emitting devices, and the redundant pixel circuits are electrically insulated from the light emitting devices.

[0014] In some embodiments, the redundant pixel circuit comprises a second transistor. The pixel circuit layer further comprises an active layer, a first source-drain conductive layer, and at least one third insulating layer. The active layer comprises an active part of the second transistor. The first source-drain conductive layer is located between the active layer and the cathode layer, and comprises a first electrode of the second transistor. The first connection line and the first electrode of the second transistor are disposed in the same layer and connected to each other. The at least one third insulating layer is disposed between the first source-drain conductive layer and the conductive block, located in the pixel region, and extends to the isolation region. The at least one third insulating layer is provided with a second through hole penetrating the at least one third insulating layer. The first electrode of the second transistor extends into the second through hole and is connected to the conductive block.

[0015] In some embodiments, the redundant pixel circuit comprises a second transistor, and the pixel circuit layer further comprises an active layer, a first source-drain conductive layer, at least one third insulating layer, and at least one fourth insulating layer. The active layer comprises an active part of the second transistor. The first source-drain conductive layer is located between the active layer and the cathode layer, and comprises a first electrode of the second transistor. The at least one third insulating layer is disposed between the first source-drain conductive layer and the conductive block, located in the pixel region, and extends to the isolation region. The at least one third insulating layer is located between the conductive block and the first electrode of the second transistor. The at least one third insulating layer is provided with a second through hole penetrating the at least one third insulating layer. The first electrode of the second transistor extends into the second through hole and is connected to the conductive block. The at least one fourth insulating layer is disposed between the first source-drain conductive layer and the cathode layer, located in the pixel region, and extends to the isolation region. The at least one fourth insulating layer is provided with a third through hole. The first connection line is disposed between the at least one fourth insulating layer and the cathode layer, and extends into the third through hole and is connected to the first electrode of the second transistor.

[0016] In some embodiments, the display panel further comprises a fan-out region disposed on one side of the display region along the second direction; the display region further comprises a central region and an edge region disposed on at least one side of the central region along the first direction; wherein the first direction intersects the second direction. The display panel further comprises a plurality of data lines, a plurality of first adapter lines, and a plurality of second adapter lines. The multiple data lines are arranged on the substrate; the multiple data lines are arranged at intervals along the first direction; the multiple data lines include a first data line; the first data line is arranged in the edge area and extends along the second direction; the multiple first transfer lines are arranged on the same layer as the multiple data lines and are located in the central area; the first transfer line extends along the second direction and is connected to the fan-out area; the multiple second transfer lines are arranged between the multiple first transfer lines and the first source and drain conductive layer, or between the multiple first transfer lines and the cathode layer; the second transfer lines extend along the first direction, and one second transfer line is connected to a first data line and a first transfer line; wherein, the first connecting line is arranged on the same layer as the first transfer line and / or the second transfer line.

[0017] In some embodiments, the first connecting wires include a plurality of first sub-wires and a plurality of second sub-wires. The plurality of first sub-wires extend along the second direction and are spaced apart along the first direction; the first sub-wires and the first patch wires are disposed on the same layer; the plurality of second sub-wires extend along the first direction and are spaced apart along the second direction; the second sub-wires and the second patch wires are disposed on the same layer; and the plurality of second sub-wires and the plurality of first sub-wires are connected to form a mesh structure.

[0018] In some embodiments, the first connecting line and the conductive block are provided in the same layer.

[0019] In some embodiments, the display panel includes a plurality of first isolation structures; the plurality of first isolation structures are spaced apart along the direction from the isolation area to the opening area. The display panel also includes a spacer. The spacer is located between the substrate and the cathode layer; the spacer is partially located between two adjacent first isolation structures, partially located on the side of the first isolation structure away from the substrate, and covers part of the end face of the first isolation structure away from the substrate; the surface of the spacer away from the substrate protrudes in a direction away from the substrate. The cathode layer also includes a third sub-section, the third sub-section is located on the side of the spacer away from the substrate, and is connected to the adjacent first sub-section; the minimum distance between the surface of the third sub-section away from the substrate and the spacer is smaller than the minimum distance between the surface of the first sub-section away from the substrate and the first isolation structure, and smaller than the minimum distance between the surface of the second sub-section away from the substrate and the substrate.

[0020] In some embodiments, the display panel further comprises a plurality of stacked first conductive layers disposed between the first isolation structure and the substrate; the conductive block is located in the first conductive layer closest to the substrate among the plurality of stacked first conductive layers.

[0021] In some embodiments, the display panel further includes an inorganic encapsulation layer, a stacked multi-layer first conductive layer, and a second insulating stack. The inorganic encapsulation layer is located in the display area and extends to the isolation area; the inorganic encapsulation layer is located on the side of the cathode layer away from the substrate and covers the cathode layer; the stacked multi-layer first conductive layer is disposed between the first isolation structure and the substrate; the conductive block is located in the first conductive layer; the second insulating stack is located in the pixel area and extends to the isolation area, and is located between the first isolation structure and the first conductive layer including the conductive block; and the thickness of the second insulating stack in a direction perpendicular to the substrate is greater than the thickness of the inorganic encapsulation layer.

[0022] In some embodiments, the display panel further includes an active layer and a light shielding layer. The active layer is located in the pixel region and between the substrate and the cathode layer; the active layer includes a channel portion; the light shielding layer is located between the active layer and the substrate; the light shielding layer includes a plurality of light shielding blocks, the orthographic projections of the light shielding blocks on the substrate at least partially overlapping with the orthographic projections of the channel portion on the substrate.

[0023] In another aspect, a display module is provided. The display module includes a support layer, a display panel as described in any of the above embodiments, and a polarizer. The support layer is grounded; the display panel has a display side and a non-display side oppositely disposed, the display side being further away from the support layer than the non-display side; the polarizer is located on the side of the display panel away from the support layer; and the material of the polarizer includes a first ion.

[0024] The above-mentioned display module has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here.

[0025] On the other hand, a display device is provided, comprising: the display panel as described in any of the above embodiments, or the display module as described in any of the above embodiments.

[0026] The above-mentioned display device has the same structure and beneficial technical effects as the display panels provided in some of the above-mentioned embodiments, which will not be described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0028] Figure 1 is a structural diagram of a display device according to some embodiments;

[0029] Figure 2 is another structural diagram of a display device according to some embodiments;

[0030] Figure 3 is a cross-sectional view of a display device according to some embodiments;

[0031] Figure 4 is a structural diagram of a display panel according to some embodiments;

[0032] Figure 5 for Figure 4 A cross-sectional view along section line CC;

[0033] Figure 6 for Figure 4 Another cross-sectional view along section line CC;

[0034] Figure 7 for Figure 1 A cross-sectional view along section line DD;

[0035] Figure 8 for Figure 7 A partial enlarged view of middle E;

[0036] Figure 9 for Figure 1 Another cross-sectional view along section line DD;

[0037] Figure 10 for Figure 9 A partial enlarged view of middle F;

[0038] Figure 11 for Figure 1 Another cross-sectional view along section line DD;

[0039] Figure 12 for Figure 11 A partial enlarged view of G in the middle;

[0040] Figure 13 for Figure 1 Another cross-sectional view along section line DD;

[0041] Figure 14 for Figure 13 A partial enlarged view of middle H;

[0042] Figure 15 for Figure 4 A partial enlarged view of Figure I;

[0043] Figure 16 for Figure 4 A partial enlarged view of middle J;

[0044] Figure 17 for Figure 16 A cross-sectional view along section line KK;

[0045] Figure 18 for Figure 16 Another cross-sectional view along section line KK;

[0046] Figure 19 for Figure 16 Another cross-sectional view along section line KK;

[0047] Figure 20 for Figure 16 Another cross-sectional view along section line KK;

[0048] Figure 21 for Figure 4 A partial enlarged view of the middle L;

[0049] Figure 22 This is a structural diagram of a light shielding block and a conductive block arranged on the same layer according to some embodiments. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0051] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its alternative forms, such as the third-person singular form "comprises" and the present participle form "comprising," are to be interpreted as open and inclusive, meaning "including, but not limited to." Throughout the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0052] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0053] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0054] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0055] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0056] As used herein, the term "if" is optionally interpreted to mean "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]," depending on the context.

[0057] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0058] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0059] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0060] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0061] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0062] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0063] Some embodiments of the present disclosure provide a display device 1000, such as Figure 1 As shown, the display device 1000 can be any product or component with a display function, such as a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, or a car central control screen.

[0064] In some examples, such as Figure 1 As shown, the display device 1000 may be a portable display product. For example, the display device 1000 may be Figure 1 The phone shown.

[0065] In some other examples, such as Figure 2 As shown, the display device 1000 may be a wearable device. For example, the display device 1000 may be Figure 2 Watch shown.

[0066] The display device 1000 described above can be a liquid crystal display (LCD), an organic light emitting display, a quantum dot light emitting display (QLED), a micro light emitting diode (Micro LED), a mini light emitting diode (Mini LED), or an active-matrix organic light emitting diode (AMOLED) display device.

[0067] It should be noted that the Micro LED refers to an LED with a size (e.g., length) of less than 50 pm, and the Mini LED refers to an LED with a size (e.g., length) of 50 pm to 200 pm.

[0068] In the following, some embodiments of the present disclosure will be illustratively described taking an OLED display device as an example, but the embodiments of the present disclosure are not limited thereto, and other display devices can also be considered as long as the same technical idea is applied.

[0069] In some embodiments, as shown in FIG. 1, the display device 1000 includes a display module 100, which includes a support layer 10, a display panel 20, and a polarizer 30. Figure 3

[0070] The support layer 10 is configured to support the display panel 20. The material of the support layer 10 can include at least one of stainless steel, aluminum, or copper. In addition, the support layer 10 is also configured to be grounded, which can reduce the risk of the display panel 20 being interfered by external electromagnetic interference, and can also reduce the risk of the user being electrocuted due to the leakage of the display panel 20, so as to protect the safety of the user.

[0071] As shown in FIG. 1, the display panel 20 has a display side 20A and a non-display side 20B opposite to each other. Figure 3 It should be noted that the display side 20A refers to the side of the display panel 20 on which the image is displayed (the upper side of the display panel 20 in FIG. 1), and the non-display side 20B refers to the other side opposite to the display side 20A (the lower side of the display panel 20 in FIG. 1). The display side 20A is farther away from the support layer 10 than the non-display side 20B. Figure 3 Figure 3

[0072] As shown in FIG. 1, the display panel 20 has a display side 20A and a non-display side 20B opposite to each other. Figure 4 ​​​As shown, the display panel 20 has a display area AA and a peripheral area BB disposed on at least one side of the display area AA. Figure 4 In the example, the peripheral area BB is arranged around the display area AA. The peripheral area BB is an area where no image is displayed. The peripheral area BB is configured to set display pixel circuits, such as scanning pixel circuits and source pixel circuits.

[0073] like Figure 3 As shown, the polarizer 30 is located on the side of the display panel 20 away from the support layer 10. The polarizer 30 is disposed on the side of the display panel 20 away from the support layer 10. The orthographic projection of the polarizer 30 on the plane where the display panel 20 resides covers at least the display area AA of the display panel 20 to reduce the reflection of ambient light by the display panel 20. The material of the polarizer 30 includes a first ion that can chemically react with the inorganic material. For example, the first ion includes a potassium ion.

[0074] Exemplarily, the polarizer 30 includes a circular polarizer.

[0075] It is understandable that if Figure 3 As shown, the display module 100 further includes a first adhesive layer 40, which is located between the display panel 20 and the polarizer 30. The first adhesive layer 40 is used to bond the display panel 20 and the polarizer 30. The material of the first adhesive layer 40 includes an optically clear adhesive (OCA) or a pressure-sensitive adhesive (PSA), or other adhesive materials with high light transmittance (e.g., a light transmittance greater than or equal to 90%). For example, the material of the first adhesive layer 40 includes optical adhesive.

[0076] Based on the above embodiments, Figure 3 As shown, the display module 100 further includes a cover plate 50, which is located on a side of the polarizer 30 away from the display panel 20. The cover plate 50 may be made of glass, a transparent polyimide film (CPI), or polyethylene terephthalate (PET).

[0077] In this case, when an object collides with the display module 100 or the display module 100 collides with the ground, the object or the ground will first hit the cover plate 50 and will not hit the polarizer 30. In this way, the cover plate 50 can reduce the risk of objects outside the display module 100 directly colliding with the polarizer 30 and causing damage to the polarizer 30.

[0078] In some embodiments, as Figure 1As shown, the display device 1000 further includes a functional device 200, which can be a camera, an infrared sensor, a proximity sensor, an eye tracking module, a face recognition module, and the like. As shown in Figure 1 The functional device 200 is a camera.

[0079] As shown in Figure 4 The display panel 20 can be provided with a mounting hole H, and the functional device 200 can be mounted at the mounting hole H to avoid the display panel 20 blocking the light collection of the functional device 200.

[0080] Exemplarily, the mounting hole H can be cut by a knife wheel or a laser.

[0081] In some embodiments, as shown in Figure 4 The display area AA includes an aperture area AA1, an isolation area AA2, and a pixel area AA3. The isolation area AA2 is arranged between the aperture area AA1 and the pixel area AA3. The pixel area AA3 is used for displaying a picture, the aperture area AA1 is used for arranging the mounting hole H, and the isolation area AA2 is used for blocking water and oxygen from invading the pixel area AA3 from the aperture area AA1.

[0082] In some embodiments, as shown in Figure 4 , Figure 5 and Figure 6 The display panel 20 includes a substrate 21 and a plurality of sub-pixels 22.

[0083] As shown in Figure 5 and Figure 6As shown, the substrate 21 can be a flexible substrate 21 or a rigid substrate 21. The material used for the substrate 21 can include a polymer resin or glass. For example, the substrate 21 can be flexible, and the material used for the substrate 21 includes a polymer resin, such as one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate two formal acid glycol ester (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). Exemplarily, the substrate 21 may be rigid, and the material of the substrate 21 includes glass containing SiO 2 as a main component.

[0084] like Figure 4 As shown, a plurality of sub-pixels 22 are disposed on a substrate 21 and located in a pixel area AA3 .

[0085] For example, Figure 4 As shown, the plurality of sub-pixels 22 may be arranged in multiple rows and columns, where each row of sub-pixels 22 includes at least two sub-pixels 22 arranged along a first direction X, and each column of sub-pixels 22 includes at least two sub-pixels 22 arranged along a second direction Y. The first direction X intersects the second direction Y, for example, the first direction X is perpendicular to the second direction Y.

[0086] In some examples, the plurality of sub-pixels 22 may include a first sub-pixel emitting a first color, a second sub-pixel emitting a second color, and a third sub-pixel emitting a third color. The first, second, and third colors are three primary colors. For example, the first color is red, the second color is blue, and the third color is green. This is not specifically limited in the present disclosure.

[0087] In some examples, the plurality of sub-pixels 22 includes a first sub-pixel 221 emitting light of a first color, a second sub-pixel 222 emitting light of a second color, and a third sub-pixel 223 emitting light of a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green.

[0088] It can be understood that, as shown in Figure 5 and Figure 6 , the sub-pixel 22 includes a first pixel circuit 221 and a light emitting device 222.

[0089] In some embodiments, as shown in Figure 5 and Figure 6 , the display panel 20 further includes a pixel circuit layer 23 and a light emitting device layer 24 on the substrate 21 in a direction perpendicular to the substrate 21 and away from the substrate 21.

[0090] The pixel circuit layer 23 includes a plurality of pixel circuits 231, and each pixel circuit 231 includes a plurality of transistors 2311 and a storage capacitor 2312 (English: Capacitor, abbreviated: C). The plurality of pixel circuits 231 includes the first pixel circuit 221.

[0091] The transistors 2311 used in the circuit provided by the embodiments of the present disclosure can be thin film transistors, field effect transistors, or other switching devices with the same characteristics, and the embodiments of the present disclosure are all described by taking thin film transistors as an example.

[0092] For example, the transistors 2311 are oxide thin film transistors, and the carrier mobility of the oxide thin film transistors is relatively high.

[0093] Alternatively, for example, the transistors 2311 are low-temperature polysilicon thin film transistors, and the low-temperature polysilicon thin film transistors have high mobility and fast charging.

[0094] In some examples, as shown in Figure 5 , the plurality of transistors 2311 includes low-temperature polysilicon thin film transistors and oxide thin film transistors. In this way, the low-temperature polysilicon transistors and the oxide transistors can be integrated on one display panel 20, which can reduce the power consumption of the display panel 20 and improve the display quality of the display panel 20.

[0095] As shown in Figure 5 and Figure 6 , the plurality of sub-pixels 22 includes a first sub-pixel 221 emitting light of a first color, a second sub-pixel 222 emitting light of a second color, and a third sub-pixel 223 emitting light of a third color. The first color, the second color, and the third color are three primary colors. For example, the first color is red, the second color is blue, and the third color is green.As shown, the transistor 2311 includes an active portion 23111, a source 23112, a drain 23113, and a gate 23114. The source 23112 and the drain 23113 are respectively in contact with the active portion 23111. The storage capacitor 2312 includes two plates disposed opposite to each other.

[0096] It should be noted that the source 23112 and the drain 23113 can be interchanged. Figure 5 and Figure 6 23112 represents the drain, and 23113 represents the source.

[0097] The pixel circuit 231 may have various structures, which can be selected based on actual needs. For example, the pixel circuit 231 may have a structure of "2T1C," "3T1C," "6T1C," "7T1C," "6T2C," or "7T2C." "T" represents the transistor 2311, and the number preceding "T" represents the number of transistors 2311. "C" represents the storage capacitor 2312, and the number preceding "C" represents the number of storage capacitors 2312.

[0098] In some examples, the multiple transistors in the pixel circuit 231 may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit 231 may all be P-type transistors or N-type transistors. In this way, the process flow can be simplified, the process difficulty of the display panel 20 can be reduced, and the product yield can be improved.

[0099] In some embodiments, along a direction perpendicular to and close to the substrate 21, such as Figure 5 and Figure 6 As shown, the light emitting device stack 24 includes an anode layer 241 , a light emitting functional layer 242 and a cathode layer 243 which are stacked.

[0100] like Figure 5 and Figure 6 As shown, the anode layer 241 includes a plurality of anodes 2411, and the cathode layer 243 includes a plurality of cathodes 2431. Each anode 2411 is disposed opposite to each cathode 2431. The opposing anodes 2411 and cathodes 2431, and the light-emitting functional layer 242 located between the anodes 2411 and cathodes 2431, form a light-emitting device 222.

[0101] The anode 2411 can be electrically connected to the source 23112 or the drain 23113 of the plurality of transistors 2311 serving as a driving transistor, for example. Figure 5 and Figure 6 In the figure, the anode 2411 is electrically connected to the drain 23113 of the transistor 2311. In this way, the pixel circuit 231 can drive the corresponding light-emitting device 222 to emit light.

[0102] The light-emitting functional layer 242 may include only a light-emitting layer, or may include at least one of an electron transporting layer (ETL), an electron injection layer (EIL), a hole blocking layer (HBL), a hole transporting layer (HTL), a hole injection layer (HIL), and an electron blocking layer (EBL) in addition to the light-emitting layer.

[0103] In some embodiments, as Figure 5 and Figure 6 As shown, the display panel 20 further includes an encapsulation layer 25. The encapsulation layer 25 is disposed in the pixel area AA3 and extends to the isolation area AA2. The encapsulation layer 25 is disposed on a side of the light-emitting device stack 24 away from the substrate 21. The encapsulation layer 25 is used to encapsulate the light-emitting devices 222 and improve the service life of the light-emitting devices 222. The encapsulation layer 25 can be an encapsulation film or an encapsulation substrate, which is not specifically limited in the present embodiment.

[0104] For example, the encapsulation layer 25 may include a single layer of encapsulation film, or may include two or more layers of encapsulation films stacked together. Figure 3 and Figure 4 As shown, in a direction perpendicular to and away from the substrate 21, the encapsulation layer 25 includes a first inorganic encapsulation layer 251, a first organic encapsulation layer 252, and a second inorganic encapsulation layer 253, which are stacked. The materials of the first inorganic encapsulation layer 251 and the second inorganic encapsulation layer 253 include any one or more of silicon nitride, silicon oxynitride, or silicon oxide. The material of the first organic encapsulation layer 252 includes a polymer resin, such as polyimide.

[0105] The following takes the encapsulation layer including the first inorganic encapsulation layer 251, the first organic encapsulation layer 252 and the second inorganic encapsulation layer 253 as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited to this, and other encapsulation layers can also be considered as long as the same technical concept is applied.

[0106] It is understood that the cathode voltage of all light-emitting devices 222 is the same. Therefore, the cathode layer 243 can be a single-layer structure, that is, the cathode layer 243 is located in the pixel area AA3 and extends to the isolation area AA2. In this way, the difficulty of manufacturing the cathode layer 243 can be reduced, thereby reducing the manufacturing cost of the display panel 20.

[0107] In some embodiments, as Figure 4 As shown, the display panel 20 further includes a first isolation structure 26, which is disposed in the isolation area AA2. Figure 7 、 Figure 8 、 Figure 9 and Figure 10 As shown, the first isolation structure 26 is located between the substrate 21 and the cathode layer 243. The first isolation structure 26 surrounds at least a portion of the opening area AA1. Figure 4 In the example, the first isolation structure 26 is disposed around the opening area AA1.

[0108] like Figure 7 、 Figure 8 、 Figure 9 、 Figure 10 、 Figure 11 、 Figure 12 、 Figure 13 and Figure 14 As shown, the cathode layer 243 located in the isolation area AA2 includes a first sub-portion 2432 and a second sub-portion 2433 that are separated from each other. The first sub-portion 2432 is arranged on the side of the first isolation structure 26 away from the substrate 21, and the second sub-portion 2433 is arranged on the side of the first isolation structure 26 away from or close to the opening area AA1, that is, the cathode layer 243 is disconnected at the first isolation structure 26, which can reduce the risk of water and oxygen invading the pixel area AA3 from the opening area AA1 through the cathode layer 243, thereby improving the problem of black spots at the edge of the hole (English: Growing Dark Spot In Hole, abbreviated as: GDSH) generated by the display panel 20.

[0109] The specific structure of the first isolation structure 26 is described below with examples.

[0110] In some embodiments, as Figure 7 、 Figure 8 、 Figure 9 and Figure 10As shown, in a direction perpendicular to and away from the substrate 21, the first isolation structure 26 comprises a first isolation portion 261, a second isolation portion 262, and a third isolation portion 263 stacked in layers. Along the direction from the isolation area AA2 toward the aperture area AA1, the ends of the first isolation portion 261 extend beyond the second isolation portion 262, while the ends of the third isolation portion 263 extend beyond the second isolation portion 262 and are flush with the ends of the first isolation portion 261. The materials of the first isolation portion 261, the second isolation portion 262, and the third isolation portion 263 all comprise metal. The first sub-portion 2432 is located on the side of the third isolation portion 263 away from the substrate 21, while the second sub-portion 2433 is located on the side of the first isolation portion 261 away from or close to the aperture area AA1 and contacts the first isolation portion 261.

[0111] In some other embodiments, Figure 11 、 Figure 12 、 Figure 13 and Figure 14 As shown, along the direction perpendicular to the substrate 21 and away from the substrate 21, the first isolation structure 26 comprises a first isolation portion 261 and a second isolation portion 262 stacked together, and along the direction from the isolation area AA2 to the opening area AA1, both ends of the second isolation portion 262 extend beyond the first isolation portion 261.

[0112] In some examples, such as Figure 11 and Figure 12 As shown, the material of the first isolation portion 261 includes an insulating material, and the material of the second isolation portion 262 includes a metal material. The first sub-portion 2432 is located on the side of the second isolation portion 262 away from the substrate 21. The second sub-portion 2433 is located on the side of the first isolation portion 261 away from or close to the opening area AA1, and is located on the side of the second isolation portion 262 close to the substrate 21. The second sub-portion 2433 covers the sidewalls of the first isolation portion 261, and the second sub-portion 2433 and the surface of the second isolation portion 262 close to the substrate 21 are in contact.

[0113] Exemplarily, the display panel 20 further includes a third insulating stack 1. The third insulating stack 1 is disposed between the substrate 21 and the cathode layer 243. A surface of the third insulating stack 1 facing away from the substrate 21 includes multiple isolation trenches 101. The sidewalls of the isolation trenches 101 are inclined. The multiple isolation trenches 101 are disposed in the isolation area AA2, pointing from the isolation area AA2 toward the opening area AA1. The multiple isolation trenches 101 are spaced apart, and the isolation trenches 101 at least partially surround the opening area AA1. That is, the third insulating stack 1 between two adjacent isolation trenches 101 forms a first isolation portion 261. The boundary of the orthographic projection of the second isolation portion 262 on the substrate 21 is disposed within the range of the orthographic projection of the isolation trench 101 on the substrate 21. A second sub-portion 2433 is disposed within the isolation trench 101.

[0114] In some other examples, such as Figure 13 and Figure 14 As shown, the materials of the first isolation portion 261 and the second isolation portion 262 both include metal materials, the first sub-portion 2432 is located on the side of the second isolation portion 262 away from the substrate 21, and the second sub-portion 2433 is located on the side of the first isolation portion 261 away from or close to the opening area AA1, and is in contact with the first isolation portion 261.

[0115] In related art, display panels produce black spots at the edges of the hole. Research has revealed that although the first and second subsections are isolated, the second subsection contacts the first isolation structure, resulting in electrical connection between the second and first subsections via the first isolation structure. The voltage received at the cathode terminal is transmitted from the pixel region to the isolation region via the cathode layer, resulting in cathode voltages on the first and second subsections. The voltage difference between the support layer and the first and second subsections is greater than the driving voltage of potassium ions. First ions in the polarizer migrate along the edge of the mounting hole. Due to the voltage difference between the support layer and the first and second subsections, the first ions migrate into the second and first subsections. Under the influence of electrons and water vapor, the first ions react with the first and / or second inorganic encapsulation layers on the sides of the first and second subsections away from the substrate, causing damage to the first and / or second inorganic encapsulation layers, resulting in black spots at the edges of the hole (GDSH) in the display panel 20.

[0116] In order to solve the above technical problems, Figure 7 、 Figure 8 、 Figure 9 and Figure 10 As shown, some embodiments of the present disclosure provide a display panel 20, which further includes a conductive block 27. The conductive block 27 is disposed between the substrate 21 and the first isolation structure 26 and is located in the isolation area AA2. The conductive block 27 is flush with the boundary of the aperture area AA1 near the conductive block 27. The voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is less than or equal to the driving voltage of the first ion. Exemplarily, when the driving voltage of the first ion is 1.5V, the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is less than 1V.

[0117] Arranged in this manner, the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is not sufficient to drive the first ions located between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 to move into the first sub-section 2432 and the second sub-section 2433, thereby reducing the number of first ions in the first sub-section 2432 and the second sub-section 2433, so that the number of first ions in the first sub-section 2432 and the second sub-section 2433 is small or there is no first ion, which is beneficial to reducing the degree and speed of reaction between the first inorganic encapsulation layer 251 and / or the second inorganic encapsulation layer on the side of the first sub-section 2432 and the second sub-section 2433 away from the substrate 21 and the first ions, thereby reducing the risk of damage to the first inorganic encapsulation layer 251 and / or the second inorganic encapsulation layer 253, and thereby improving the problem of black spots on the edge of the holes in the display panel 20.

[0118] For example, Figure 15 As shown, the orthographic projection of the first isolation structure 26 on the substrate 21 is located within the range of the orthographic projection of the conductive block 27 on the substrate 21 .

[0119] In some embodiments, as Figure 15 As shown, the minimum distance between the first isolation structure 26 and the boundary of the aperture area AA3 is less than the precision of the cutter wheel or laser cutting (eg, ±15 μm), thereby reducing the risk of the first isolation structure 26 being cut off.

[0120] Exemplarily, the minimum distance between the first isolation structure 26 and the boundary of the opening area AA3 is 15 μm.

[0121] In some embodiments, as Figure 7 and Figure 8 As shown, the conductive block 27 is electrically insulated from the first isolation structure 26. The display panel 20 also includes a first connecting line 28. The first connecting line 28 is connected to the conductive block 27 and to the first voltage terminal. The difference between the voltage received at the first voltage terminal and the voltage on the first sub-section 2432 and the second sub-section 2433 is less than the driving voltage of the first ion. In this way, the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is less than or equal to the driving voltage of the first ion, which helps to improve the problem of black spots on the edges of the holes in the display panel 20.

[0122] In some examples, such as Figure 4As shown, the peripheral area BB also includes a binding area BB1, and along the second direction Y, the binding area BB1 is located on one side of the display area AA. The display panel 20 also includes a plurality of binding pins 29. The plurality of binding pins 29 are located on the substrate 21, and the plurality of binding pins 29 are located in the binding area BB1. The plurality of binding pins 29 are used for driving the chip and binding. The plurality of binding pins 29 include a first binding pin 291, and the first binding pin 291 is connected to the first voltage terminal. In this way, the signal on the first binding pin 291 can be transmitted to the conductive block 27 through the first voltage terminal and the first connecting line 28, so that the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is less than or equal to the driving voltage of the first ion.

[0123] For example, the first binding pin 291 is configured to transmit a cathode signal. This way, the voltage on the cathode layer 243 is the same as the voltage received at the first voltage terminal. This way, the voltage difference between the conductive block 27 and the first and second sub-sections 2432 and 2433 is zero, preventing the first ions located between the conductive block 27 and the first and second sub-sections 2432 and 2433 from moving. This helps alleviate the problem of black spots at the edges of the holes in the display panel 20.

[0124] Alternatively, illustratively, the first binding pin 291 is configured to transmit an initialization signal, so that the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is small and less than the driving voltage of the first ion. In this case, the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is not sufficient to drive the first ion located between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 to move into the first sub-section 2432 and the second sub-section 2433, which is beneficial to improving the problem of black spots on the edge of the hole generated by the display panel 20.

[0125] In addition, the first binding pin 291 transmits an initialization signal to the pixel circuit 231, thereby initializing the nodes in the pixel circuit 231. This can alleviate the problem of residual potential on the nodes from the previous image frame affecting the displayed image of the next image frame, thereby improving the brightness uniformity of the display panel 20.

[0126] In other embodiments, Figure 9 and Figure 10 As shown, the conductive block 27 is connected to the first isolation structure 26 or the second sub-portion 2433. In this way, the voltage difference between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 is zero, and the first ions located between the conductive block 27 and the first sub-portion 2432 and the second sub-portion 2433 cannot be driven to move, which helps to improve the problem of black spots on the edges of the holes in the display panel 20.

[0127] For example, Figure 9 and Figure 10 As shown, the display panel 20 further includes a first insulating stack 201. The first insulating stack 201 is located in the pixel area AA3 and extends to the isolation area AA2. The first insulating stack 201 is located between the first isolation structure 26 and the conductive block 27. The first insulating stack 201 has a first through hole 2011 that penetrates the first insulating stack 201. The first isolation structure 26 extends into the first through hole 2011 and is connected to the conductive block 27.

[0128] In some embodiments, the display panel 20 further includes a first connection line 28. The first connection line 28 is connected to the conductive block 27 and the first voltage terminal so that the voltage difference between the support layer 10 and the conductive block 27 is less than or equal to the driving voltage of the first ion.

[0129] In this way, the voltage difference between the supporting layer 10 and the conductive block 27 is not sufficient to drive the first ions located between the supporting layer 10 and the conductive block 27 to move into the conductive block 27, which can reduce the number of first ions in the conductive block 27, making the number of first ions in the conductive block 27 smaller or non-existent, which is beneficial to reducing the degree and speed of reaction between the inorganic film layer on the side of the conductive block 27 away from the substrate 21 and the first ions, thereby reducing the risk of damage to the inorganic film layer.

[0130] In some examples, the first voltage terminal is grounded. In this case, the voltage difference between the support layer 10 and the conductive block 27 is 0, which cannot drive the first ions located between the support layer 10 and the conductive block 27 to move, which is beneficial to reducing the risk of damage to the inorganic film layer.

[0131] Exemplarily, the first binding pin 291 is configured to transmit a ground signal, so that the conductive block 27 is grounded, so that the voltage difference between the supporting layer 10 and the conductive block 27 is zero.

[0132] In some embodiments, as Figure 16 As shown, the plurality of pixel circuits 231 further include a plurality of redundant pixel circuits 2301. The plurality of first pixel circuits 221 are located in the pixel area AA3, and the plurality of redundant pixel circuits 2301 are located in the isolation area AA2. The plurality of redundant pixel circuits 2301 are adjacent to the first pixel circuits 221 located in the pixel area AA3 and near the edge of the aperture area AA1. The redundant pixel circuits 2301 are electrically isolated from the light-emitting devices 222. That is, the redundant pixel circuits 2301 do not control any light-emitting device 222 to emit light. Even if the redundant pixel circuits 2301 exhibit poor uniformity, this will not affect the light-emitting devices 222.

[0133] In this arrangement, the edges of multiple pixel circuits 231 near the opening area AA1 are transferred from the first pixel circuit 221 to the redundant pixel circuit 2301, which improves the uniformity of the first pixel circuit 221. This allows the light-emitting devices 222 connected to the first pixel circuit 221 near the opening area AA1 to emit light normally. Furthermore, the redundant pixel circuit 2301 is electrically isolated from the light-emitting devices 222. That is, the redundant pixel circuit 2301 does not control any light-emitting device 222 to emit light. Even if the redundant pixel circuit 2301 has a problem with poor uniformity, it will not affect the light emission of any light-emitting device 222. This helps reduce the risk of display abnormalities in the display panel 20.

[0134] In some examples, the pixel circuit stack 23 includes a semiconductor layer ACT. The semiconductor layer ACT includes active layer patterns of a plurality of first pixel circuits 221 and an active layer pattern of a redundant pixel circuit 2301. The active layer patterns of the first pixel circuits 221 are connected to the anode 2411 of the light-emitting device 222, while the active layer patterns of the redundant pixel circuits 2301 are electrically insulated from the anode 2411 of the light-emitting device 222.

[0135] In this manner, the edge of the semiconductor layer ACT near the opening area AA1 is transferred from the active layer pattern of the first pixel circuit 221 to the active layer pattern of the redundant pixel circuit 2301. This avoids the problem of poor uniformity in the first pixel circuit 221 and improves the display quality of the display panel 20.

[0136] In some embodiments, as Figure 5 and Figure 6 As shown, the first pixel circuit 221 includes a first transistor 2211. Figure 17 、 Figure 18 、 Figure 19 and Figure 20 As shown, the redundant pixel circuit 2301 includes a second transistor 23011. The semiconductor layer ACT includes an active portion 23111 of the first transistor 2211 and an active portion 23111 of the second transistor 23011.

[0137] The display panel 20 further includes a first source-drain conductive layer SD1 and at least one third insulating layer 2302. The first source-drain conductive layer SD1 is located between the semiconductor layer ACT and the cathode layer 243. The first source-drain conductive layer SD1 includes a first electrode of the second transistor 23011, where the first electrode serves as either the source or the drain of the second transistor 23011. The at least one third insulating layer 2302 is disposed between the first electrode of the second transistor 23011 and the conductive block 27. The at least one third insulating layer 2302 is located in the pixel area AA3 and extends to the isolation area AA2.

[0138] In some examples, such as Figure 17As shown, the first connecting line 28 is provided in the same layer as the first electrode of the second transistor 23011 and is connected to the first electrode of the second transistor 23011. A second through hole 23021 is provided through the at least one third insulating layer 2302. The first electrode of the second transistor 23011 extends into the second through hole 23021 and is connected to the conductive block 27.

[0139] This arrangement allows, on the one hand, the conductive block 27 to be connected to the first voltage terminal. The first voltage terminal can apply an electrical signal to the conductive block 27, so that the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is less than or equal to the driving voltage of the first ion. Furthermore, the second through hole 23021 in the redundant pixel circuit 2301 can be utilized, eliminating the need to re-drill holes in at least one third insulating layer 2302, thereby connecting the first connecting line 28 to the conductive block 27, thereby simplifying the structure of the display panel 20.

[0140] In some other examples, such as Figure 18 、 Figure 19 and Figure 20 As shown, the display panel 20 further includes at least one fourth insulating layer 2303, which is disposed between the first electrode of the second transistor 23011 and the cathode layer 243. The at least one fourth insulating layer 2303 is located in the pixel area AA3 and extends to the isolation area AA2. The at least one fourth insulating layer 2303 is provided with a third through hole 23031.

[0141] A first connecting line 28 is disposed between at least one fourth insulating layer 2303 and the cathode layer 243. The first connecting line 28 extends into the third through-hole 23031 and connects to the first electrode of the second transistor 23011, thereby connecting the conductive block 27 to the first voltage terminal. The first voltage terminal applies an electrical signal to the conductive block 27 so that the voltage difference between the conductive block 27 and the first sub-section 2432 and the second sub-section 2433 is less than or equal to the driving voltage of the first ion.

[0142] For example, Figure 18 As shown, the pixel circuit stack 23 further includes a second source-drain conductive layer SD2. The second source-drain conductive layer SD2 is located between at least one fourth insulating layer 2303 and the cathode layer 243. A first connecting wire 28 is located in the second source-drain conductive layer SD2. There is one third through-hole 23031, which penetrates at least one fourth insulating layer 2303. The first connecting wire 28 extends into the third through-hole 23031 and contacts the first electrode of the second transistor 23011.

[0143] Or, for example, Figure 19 and Figure 20As shown, the pixel circuit stack 23 also includes a second source-drain conductive layer SD2 and a third source-drain conductive layer SD3. The at least one fourth insulating layer 2303 includes a first sublayer 23032 and a second sublayer 23033. The first sublayer 23032 is located between the second source-drain conductive layer SD2 and the first source-drain conductive layer SD1, and the second sublayer 23033 is located between the third source-drain conductive layer SD3 and the second source-drain conductive layer SD2. A first connecting line 28 is located in the third source-drain conductive layer SD3.

[0144] Among them, such as Figure 19 As shown, the number of the third through hole 23031 is one, and the third through hole 23031 passes through the first sub-layer 23032 and the second sub-layer 23033, and the first connecting line 28 is in contact with the first sub-layer 23032. Figure 20 As shown, the display panel 20 further includes a transfer block 5, which is located in the second source-drain conductive layer SD2. There are two third through-holes 23031, one of which penetrates the first sub-layer 23032. In this case, the transfer block 5 extends into the third through-hole 23031 and contacts the first electrode of the second transistor 23011. The other of which penetrates the second sub-layer 23033. In this case, the first connection line 28 extends into the third through-hole 23031 and contacts the transfer block 5.

[0145] In some embodiments, as Figure 4 As shown, the peripheral area BB includes a fan-out area BB2, and along the second direction Y, the fan-out area BB2 is arranged on one side of the display area AA. For example, the fan-out area BB2 is arranged on the lower side of the display area AA, and the fan-out area BB2 and the display area AA share a border (as shown in FIG. Figure 4 In the case where the peripheral area BB includes the binding area BB1, the fan-out area BB2 is located between the display area AA and the binding area BB1.

[0146] like Figure 4 As shown, the display area AA further includes a central area AA4 and an edge area AA5. Along the first direction X, the edge area AA5 is arranged on at least one side of the central area AA4. Figure 4 As shown, the edge area AA5 is arranged on both sides of the central area AA4.

[0147] It will be appreciated that the mounting hole H can be located in the central area AA4 and / or the edge area AA5. In some examples, the mounting hole H can be located in the central area AA4, i.e., the opening area AA1 and the isolation area AA2 are located in the central area AA4. In other examples, the mounting hole H can be located in the edge area AA5, i.e., the opening area AA1 and the isolation area AA2 are located in the edge area AA5. In still other examples, the mounting hole H is located partially in the central area AA4 and partially in the edge area AA5, i.e., the opening area AA1 and the isolation area AA2 are located in the central area AA4 and also in the edge area AA5.

[0148] As shown in Figure 21 The display panel 20 further includes a plurality of data lines 202, which are disposed on the substrate 21 and located at the side away from the substrate 21 of the first electrode of the second transistor 23011. The plurality of data lines 202 are arranged at intervals along the first direction X and extend along the second direction Y.

[0149] In this context, “the plurality of data lines 202 extend along the second direction Y” means that the overall wiring direction of the plurality of data lines 202 is along the second direction Y, but is not limited to that each position of the plurality of data lines 202 strictly extends along the second direction Y. That is, “extend along the second direction Y” here not only includes the plurality of data lines 202 that strictly extend along the second direction Y at each position, but also includes the plurality of data lines 202 that locally bend to avoid interference with other structures.

[0150] The plurality of data lines 202 include a first data line 2021, which is disposed in the edge area AA5.

[0151] On this basis, the display panel 20 further includes a plurality of first transfer lines 203 and a plurality of second transfer lines 204. The plurality of first transfer lines 203 are disposed in the same layer as the plurality of data lines 202 and located in the center area AA4. The plurality of first transfer lines 203 extend along the second direction Y and are connected to the fan-out area BB2. The plurality of second transfer lines 204 are disposed between the plurality of first transfer lines 203 and the first electrode of the second transistor 23011, or between the plurality of first transfer lines 203 and the cathode layer 243. The plurality of second transfer lines 204 extend along the first direction X, and one second transfer line 204 is connected to one first data line 2021 and one first transfer line 203.

[0152] As shown in Figure 21 The plurality of data lines 202 further include a plurality of second data lines 2022, which are disposed in the center area AA4 and arranged at intervals along the first direction X. The plurality of second data lines 2022 are directly connected to the fan-out area BB2.

[0153] That is, the second data lines 2022 disposed in the center area AA4 are directly connected to the fan-out area BB2, and the first data lines 2021 disposed in the edge area AA5 are connected through the first transfer lines 203, the second transfer lines 204 and the fan-out area BB2. This arrangement can be referred to as fan-out in AA (FIAA for short) or fan-out in panel (FIP for short). In this way, the size of the fan-out area BB2 along the second direction Y can be reduced, that is, the frame width of the display panel 20 can be reduced, and the display device 1000 can be implemented to have a narrow frame.

[0154] Based on the above embodiment, the first connecting line 28 is provided at the same layer as the first adapter line 203 and / or the second adapter line 204 .

[0155] In this manner, the first connecting line 28 and the first transfer line 203 and / or the second transfer line 204 can be formed through a single patterning process, thereby reducing the manufacturing cost of the display panel 20 .

[0156] In some examples, such as Figure 21 As shown, the first connection lines 28 include a plurality of first sub-lines 281 and a plurality of second sub-lines 282. The plurality of first sub-lines 281 extend along the second direction Y and are spaced apart along the first direction X. The first sub-lines 281 and the first adapter lines 203 are disposed on the same layer. This arrangement allows the first sub-lines 281 and the first adapter lines 203 to be formed through a single patterning process, thereby reducing the manufacturing cost of the display panel 20.

[0157] The plurality of second sub-lines 282 extend along the first direction X and are spaced apart along the second direction Y. The second sub-lines 282 and the second adapter lines 204 are disposed on the same layer. In this manner, the second sub-lines 282 and the second adapter lines 204 can be formed through a single patterning process, thereby reducing the manufacturing cost of the display panel 20.

[0158] Exemplarily, a plurality of second sub-lines 282 and a plurality of first sub-lines 281 are connected to form a mesh structure. Arranged in this manner, the capacitive load of the first connection line 28 can be reduced, which is beneficial to reducing the power consumption of the display panel 20 .

[0159] In some embodiments, as Figure 21 As shown, the display panel 20 further includes a plurality of first signal lines 205 and a plurality of second signal lines 206. The plurality of first signal lines 205 extend along the second direction Y and pass through the pixel area AA3. That is, within the pixel area AA3, the length of the first signal lines 205 along the second direction Y is substantially equal to the length of the display area AA.

[0160] Part of the first signal line 205 has a first opening K1, which divides the first signal line 205 into a first signal segment 2051 and a second signal segment 2052. The first signal segment 2051 is located on the side of the second signal segment 2052 that is closer to the fan-out area BB2. The first signal segment 2051 constitutes the first patch line 203. The second signal segment 2052 and at least the portion of the first signal line 205 that does not have an opening constitute the first sub-line 281.

[0161] The second signal line 206 extends along the first direction X and passes through the pixel area AA3 . That is, both ends of the second signal line 206 along the first direction X extend to the edge of the pixel area AA3 .

[0162] Part of the second signal line 206 has a second opening K2, which divides the first signal line 205 into a third signal segment 2061 and a fourth signal segment 2062. The third signal segment 2061 is located on the side of the fourth signal segment 2062 near the edge area AA5. Part of the second signal line 206 has a third opening K3 and a fourth opening K4, which divide the second signal line 206 into a fifth signal segment 2063, a sixth signal segment 2064, and a seventh signal segment 2065. The sixth signal segment 2064 is located between the fifth signal segment 2063 and the seventh signal segment 2065. The third signal segment 2061 and the sixth signal segment 2064 constitute the second patch line 204. The fourth signal segment 2062, the fifth signal segment 2063, the seventh signal segment 2065, and at least a portion of the second signal line 206 without an opening constitute the second sub-line 282.

[0163] In some embodiments, as Figure 22 As shown, the first connection lines 28 and the conductive blocks 27 are provided in the same layer. In this way, the first connection lines 28 and the conductive blocks 27 are formed in one patterning process, which can reduce the manufacturing cost of the display panel 20.

[0164] Exemplarily, the first connection line 28 extends along the first direction X and extends to the peripheral area BB to connect to the first voltage terminal. Alternatively, exemplary, the first connection line 28 extends along the second direction Y and extends to the peripheral area BB to connect to the first voltage terminal.

[0165] In some embodiments, as Figure 7 、 Figure 8 、 Figure 9 and Figure 10 As shown, the display panel 20 includes multiple first isolation structures 26. For example, the display panel 20 includes seven first isolation structures 26. The multiple first isolation structures 26 are arranged at intervals along the direction from the isolation area AA2 to the aperture area AA1. This can increase the number of disconnections in the cathode layer 243 in the isolation area AA2, further reducing the risk of water vapor invading the pixel area AA3 from the aperture area AA1 through the cathode layer 243, thereby improving the problem of black spots at the aperture edges of the display panel 20.

[0166] On this basis, if Figure 7 、 Figure 8 、 Figure 9 and Figure 10As shown in FIG. 1, the display panel 20 further includes a spacer 207. The spacer 207 is located between the substrate 21 and the cathode layer 243, and partially between two adjacent first isolation structures 26, partially on a side of the first isolation structure 26 away from the substrate 21, and covers an end surface of the first isolation structure 26 away from the substrate 21. A surface of the spacer 207 away from the substrate 21 protrudes away from the substrate 21. The cathode layer 243 further includes a third sub-portion 2434 located on a side of the spacer 207 away from the substrate 21, and connected with an adjacent first sub-portion 2432.

[0167] In the process of preparing the cathode layer 243, due to the effect of gravity, the minimum distance between the surface of the third sub-portion 2434 away from the substrate 21 and the spacer 207 is smaller than the minimum distance between the surface of the first sub-portion 2432 away from the substrate 21 and the first isolation structure 26, and smaller than the minimum distance between the surface of the second sub-portion 2433 away from the substrate 21 and the substrate 21, that is, the minimum thickness of the third sub-portion 2434 is smaller than the minimum thickness of the first sub-portion 2432, and smaller than the minimum thickness of the second sub-portion 2433. In this way, the resistance of the third sub-portion 2434 is larger, which can make the resistance of the cathode layer 243 larger (for example, the resistance of the cathode layer 243 is increased from 194 ohms to 5400 ohms), so as to make the current on the cathode layer 243 smaller, thereby reducing the power consumption of the display panel 20.

[0168] In the case that the conductive block 27 is connected with the first isolation structure 26 or the second sub-portion 2433, and the first connection line 28 is connected with the conductive block 27, at this time, the voltage difference between the cathode voltage terminal and the first voltage terminal is larger (for example, the voltage difference is 4.6V), the resistance of the third sub-portion 2434 is larger, which can make the resistance of the cathode layer 243 larger, can reduce the risk of short-circuiting between the cathode voltage terminal and the first voltage terminal, and is beneficial to improving the service life of the display panel 20.

[0169] In some embodiments, as shown in FIGS. 2 and 3, Figure 17 、 Figure 18 、 Figure 19 and Figure 20 As shown in FIG. 1, the display panel 20 further includes a plurality of first conductive layers 208 stacked, and the plurality of first conductive layers 208 are arranged between the first isolation structure 26 and the substrate 21.

[0170] It can be understood that the closer to the substrate 21 the first conductive layer 208 is, the more the number of insulating layers between the first conductive layer 208 and the first isolation structure 26, that is, the thicker the film thickness of the insulating layers between the first conductive layer 208 and the first isolation structure 26.

[0171] The conductive block 27 is located in the first conductive layer 208 closest to the substrate 21 among the multiple layers of the first conductive layer 208. In this way, when the first ion enters the conductive block 27, the insulating layer between the first conductive layer 208 and the first isolation structure 26 is thicker, which can make the reaction time of the first ion longer and improve the service life of the display panel 20.

[0172] In some embodiments, as Figure 17 、 Figure 18 、 Figure 19 and Figure 20 As shown, the display panel 20 further includes a stacked multi-layer first conductive layer 208 and a second insulating layer 209. The multi-layer first conductive layer 208 is disposed between the first isolation structure 26 and the substrate 21. The second insulating layer 209 is located in the pixel area AA3 and extends to the isolation area AA2. The second insulating layer 209 is located between the first isolation structure 26 and the first conductive layer 208 including the conductive blocks 27.

[0173] In a direction perpendicular to the substrate 21, the thickness of the second insulating stack 209 (e.g., 8 mm) is greater than the thickness of the inorganic encapsulation layer (e.g., 2 mm). This allows the second insulating stack 209 to prolong the reaction time of first ions when they enter the conductive block 27, thereby increasing the service life of the display panel 20. The inorganic encapsulation layer includes a first inorganic encapsulation layer 251 and a second inorganic encapsulation layer 253.

[0174] In some embodiments, as Figure 7 and Figure 9 As shown, the display panel 20 also includes at least one retaining wall structure 6. The retaining wall structure 6 is disposed in the isolation area AA2 and is located on the side of the first isolation structure 26 away from the aperture area. The retaining wall structure 6 is disposed around the aperture area AA1. The retaining wall structure 6 is used to block water and oxygen, thereby improving the water and oxygen barrier performance of the encapsulation layer 25. During the preparation of the first organic encapsulation layer 252, the retaining wall structure 6 is also used to block the first organic encapsulation layer 252, so that the first organic encapsulation layer 252 is located on the side of the retaining wall structure 6 away from the aperture area AA1. This allows the second inorganic encapsulation layer 253 to completely cover the first organic encapsulation layer 252, thereby improving the problem of water and oxygen corroding the first organic encapsulation layer 42 and causing the first organic encapsulation layer 252 to fail. That is to say, the portion of the encapsulation layer 25 located on the side of the retaining wall structure 6 away from the opening area AA1 includes a first inorganic encapsulation layer 251, a first organic encapsulation layer 252 and a second inorganic encapsulation layer 253 that are stacked together, and the portion of the encapsulation layer 25 located on the side of the retaining wall structure 6 close to the opening area AA1 includes a first inorganic encapsulation layer 251 and a second inorganic encapsulation layer 253 that are stacked together, and the first inorganic encapsulation layer 251 and the second inorganic encapsulation layer 253 are in contact.

[0175] On this basis, if Figure 7 and Figure 9 As shown, the display panel 20 further includes a second isolation structure 7, which is disposed in the isolation area AA2 and located on the side of the retaining wall structure 6 away from the first isolation structure 26. The structure of the second isolation structure 7 can be the same as that of the first isolation structure 26. That is, the cathode layer 243 in the isolation area AA2 is also disconnected at the second isolation structure 7, which can further reduce the risk of water vapor invading the pixel area AA3 from the aperture area AA1 through the cathode layer 243, thereby improving the problem of black spots at the edges of the apertures in the display panel 20.

[0176] In some embodiments, as Figure 7 、 Figure 9 and Figure 15 As shown, the orthographic projection of the second isolation structure 7 on the substrate 21 is also located within the range of the orthographic projection of the conductive block 27 on the substrate 21 .

[0177] In some embodiments, along a direction perpendicular to the substrate 21 and away from the substrate 21 , the pixel circuit stack 23 includes a light shielding layer BSM, at least one semiconductor layer ACT, and multiple gate conductive layers GT.

[0178] The conductive block 27 may be located in any one of the light shielding layer BSM, the semiconductor layer ACT or the gate conductive layer GT.

[0179] For example, Figure 22 As shown, the conductive block 27 is located in the light shielding layer BSM. In this way, the distance between the conductive block 27 and the first isolation structure 26 is maximized, so that the film thickness of the insulating layer between the conductive block 27 and the first isolation structure 26 is the thickest, which is beneficial to improving the reaction time of the first ion.

[0180] It can be understood that when the conductive block 27 is located in the low-temperature polysilicon semiconductor layer ACT1 or the oxide semiconductor layer ACT2 , the conductive block 27 is conductorized, and the properties of the conductive block 27 (eg, conductivity) are substantially the same as those of the conductor.

[0181] In addition, if Figure 22 As shown, the light shielding layer BSM includes a plurality of light shielding blocks 8, and the orthographic projections of the light shielding blocks 8 on the substrate 21 at least partially overlap with the orthographic projections of the active portion 23111 on the substrate 21. In this way, the conductive blocks 27 and the light shielding blocks 8 can be formed through a single patterning process, thereby reducing the manufacturing cost of the display panel 20.

[0182] The above embodiment is described below with reference to the film layers included in the pixel circuit stack 23 .

[0183] In some embodiments, as Figure 5As shown, the pixel circuit 231 includes a low-temperature polysilicon thin film transistor and an oxide thin film transistor. At this time, along a direction perpendicular to the substrate 21 and away from the substrate 21, the pixel circuit stack 23 includes a light shielding layer BSM, a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, a first interlayer insulating layer ILD1, an oxide semiconductor layer ACT2, a third gate insulating layer GI3, a third gate conductive layer GT3, a second interlayer insulating layer ILD2, a first source-drain conductive layer SD1, a first planarizing layer PLN1, a second planarizing layer PLN2, a third source-drain conductive layer SD3, and a third planarizing layer PLN3, which are arranged in sequence.

[0184] Conductive block 27 is located in light-shielding layer BSM. The active portion 23111 of the low-temperature polysilicon thin-film transistor is located in the low-temperature polysilicon semiconductor layer ACT1. The gate 23114 of the low-temperature polysilicon thin-film transistor is located in the first gate conductive layer GT1. The active portion 23111 of the oxide thin-film transistor is located in the oxide semiconductor layer ACT2. The gate 23114 of the oxide thin-film transistor is located in the third gate conductive layer GT3. The source 23112 and drain 23113 of the low-temperature polysilicon thin-film transistor, as well as the source 23112 and drain 23113 of the oxide thin-film transistor, are located in the first source-drain conductive layer SD1. The data line 202 and the first transfer line 203 are located in the second source-drain conductive layer SD2. The second transfer line 204 is located in the third source-drain conductive layer SD3.

[0185] In some examples, such as Figure 7 and Figure 9 As shown, along a direction perpendicular to and away from the substrate 21, the first source-drain conductive layer SD1 includes a stacked first sub-conductive layer 2, a second sub-conductive layer 3, and a third sub-conductive layer 4. The materials of the first sub-conductive layer 2 and the third sub-conductive layer 4 include titanium, and the material of the second sub-conductive layer 3 includes aluminum. The first isolation structure 26 includes a first isolation portion 261, a second isolation portion 262, and a third isolation portion 263. The first sub-conductive layer 2 and the first isolation portion 261 are provided in the same layer, the second sub-conductive layer 3 and the second isolation portion 262 are provided in the same layer, and the third sub-conductive layer 4 and the third isolation portion 263 are provided in the same layer.

[0186] In some examples, such as Figure 11 and Figure 12As shown, the conductive block 27 is located in the light shielding layer BSM. A first isolation structure 26 is formed by stacking a first isolation portion 261 and a second isolation portion 262 in a direction perpendicular to and away from the substrate 21. The first isolation portion 261 is made of an insulating material, and the second isolation portion 262 is made of a metal material. The second isolation portion 262 is located in the first source-drain conductive layer SD1. The third insulating layer stack 1 includes a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3, and a second interlayer insulating layer ILD2.

[0187] In some examples, such as Figure 13 and Figure 14 As shown, the conductive block 27 is located in the light shielding layer BSM. A first isolation structure 26 is formed by stacking a first isolation portion 261 and a second isolation portion 262 perpendicular to and away from the substrate 21. The first isolation portion 261 and the second isolation portion 262 are made of a metal material. The first isolation portion 261 is located in the first source-drain conductive layer SD1, and the second isolation portion 262 is located in the second source-drain conductive layer SD2.

[0188] In some examples, such as Figure 9 and Figure 10 As shown, the first isolation structure 26 is located in the first source and drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the first insulating stack 201 includes a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3 and a second interlayer insulating layer ILD2.

[0189] In some examples, such as Figure 9 and Figure 10 As shown, the first isolation structure 26 is located in the first source and drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the second insulating stack 209 includes a first gate insulating layer GI1, a second gate insulating layer GI2, a first interlayer insulating layer ILD1, a third gate insulating layer GI3 and a second interlayer insulating layer ILD2.

[0190] In some examples, the first connection line 28 and the first electrode of the second transistor 23011 are disposed in the same layer, and the first connection line 28 is located in the first source-drain conductive layer SD1.

[0191] In some examples, the first connection line 28 is located between the first electrode and cathode layers 243 , and the first connection line 28 is located in the second source-drain conductive layer SD2 and / or the third source-drain conductive layer SD3 .

[0192] Exemplarily, the first connection line 28 includes a first sub-line 281 and a second sub-line 282. The first sub-line 281 is located in the second first source-drain conductive layer SD1, and the second sub-line 282 is located in the first source-drain conductive layer SD1.

[0193] In some other embodiments, Figure 6 As shown, the pixel circuit 231 includes a low-temperature polysilicon thin film transistor. At this time, along a direction perpendicular to the substrate 21 and away from the substrate 21, the pixel circuit stack 23 includes a light shielding layer BSM, a low-temperature polysilicon semiconductor layer ACT1, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, an interlayer insulating layer ILD, a first source-drain conductive layer SD1, a first planarizing layer PLN1, a second planarizing layer PLN2, a third source-drain conductive layer SD3, and a third planarizing layer PLN3, which are arranged in sequence.

[0194] The conductive block 27 is located in the light-shielding layer BSM. The active portion 23111 of the low-temperature polycrystalline silicon thin-film transistor is located in the low-temperature polycrystalline silicon semiconductor layer ACT1. The gate 23114 of the low-temperature polycrystalline silicon thin-film transistor is located in the first gate conductive layer GT1. The source 23112 and drain 23113 of the low-temperature polycrystalline silicon thin-film transistor are located in the first source-drain conductive layer SD1. The data line 202 and the first transfer line 203 are located in the second source-drain conductive layer SD2. The second transfer line 204 is located in the third source-drain conductive layer SD3.

[0195] In some examples, such as Figure 7 and Figure 9 As shown, along a direction perpendicular to and away from the substrate 21, the first source-drain conductive layer SD1 includes a stacked first sub-conductive layer 2, a second sub-conductive layer 3, and a third sub-conductive layer 4. The materials of the first sub-conductive layer 2 and the third sub-conductive layer 4 include titanium, and the material of the second sub-conductive layer 3 includes aluminum. The first isolation structure 26 includes a first isolation portion 261, a second isolation portion 262, and a third isolation portion 263. The first sub-conductive layer 2 and the first isolation portion 261 are provided in the same layer, the second sub-conductive layer 3 and the second isolation portion 262 are provided in the same layer, and the third sub-conductive layer 4 and the third isolation portion 263 are provided in the same layer.

[0196] In some examples, such as Figure 11 and Figure 12 As shown, the conductive block 27 is located in the light shielding layer BSM. A first isolation structure 26 is formed by stacking a first isolation portion 261 and a second isolation portion 262 in a direction perpendicular to and away from the substrate 21. The first isolation portion 261 is made of an insulating material, and the second isolation portion 262 is made of a metal material. The second isolation portion 262 is located in the first source-drain conductive layer SD1. The third insulating stack 1 includes a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD.

[0197] In some examples, such as Figure 13 and Figure 14As shown, the conductive block 27 is located in the light shielding layer BSM, the first isolation structure 26 is located in the first isolation portion 261 and the second isolation portion 262 in a direction perpendicular to the substrate 21 and away from the substrate 21, and the material of the first isolation portion 261 and the second isolation portion 262 includes a metal material. The first isolation portion 261 is located in the first source-drain conductive layer SD1, and the second isolation portion 262 is located in the second source-drain conductive layer SD2.

[0198] In some examples, as shown in Figure 9 and Figure 10 As shown, the first isolation structure 26 is located in the first source-drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the first insulating layer stack 201 includes the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD.

[0199] In some examples, as shown in Figure 9 and Figure 10 As shown, the first isolation structure 26 is located in the first source-drain conductive layer SD1, and the conductive block 27 is located in the light shielding layer BSM. At this time, the second insulating layer stack 209 includes the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulating layer ILD.

[0200] In some examples, the first connection line 28 and the first electrode of the second transistor 23011 are located in the same layer, and the first connection line 28 is located in the first source-drain conductive layer SD1.

[0201] In some examples, the first connection line 28 is located between the first electrode and the cathode layer 243, and the first connection line 28 is located in the second source-drain conductive layer SD2 and / or the third source-drain conductive layer SD3.

[0202] Exemplarily, the first connection line 28 includes a first sub-line 281 and a second sub-line 282. The first sub-line 281 is located in the second first source-drain conductive layer SD1, and the second sub-line 282 is located in the first source-drain conductive layer SD1.

[0203] In the description of the present specification, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0204] The above description is merely specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, characterized in that: The display panel has a display side and a non-display side opposite to each other, and the display panel has a display area; the display area includes an opening area, an isolation area and a pixel area; The isolation area is located between the opening area and the pixel area; the display panel includes: substrate; A first isolation structure is disposed on the substrate and located in the isolation region; the first isolation structure surrounds at least a portion of the opening region; a cathode layer covering the isolation region; the cathode layer comprising a first sub-portion and a second sub-portion separated from each other, the first sub-portion and the second sub-portion being located in the isolation region, the first sub-portion being located on a side of the first isolation structure away from the substrate, and the second sub-portion being located on a side of the first isolation structure away from or close to the opening region; and the first sub-portion and the second sub-portion being electrically connected via the first isolation structure; a conductive block located between the substrate and the first isolation structure and located in the isolation region; the conductive block is close to a boundary of the opening region and flush with a boundary of the opening region; In which, a polarizer is provided on the display side of the display panel, the material of the polarizer includes a first ion, and the first ion chemically reacts with the inorganic material; the voltage difference between the conductive block and the first sub-section and the second sub-section is less than the driving voltage of the first ion.

2. The display panel according to claim 1, wherein: The conductive block is electrically insulated from the first isolation structure; and the display panel further comprises: The first connecting line is connected to the conductive block and to the first voltage terminal.

3. The display panel according to claim 2, wherein: The voltage on the cathode layer is the same as the voltage received at the first voltage terminal.

4. The display panel according to claim 1, wherein: The conductive block is connected to the first isolation structure or the second sub-portion.

5. The display panel according to claim 4, wherein: Also includes: A first insulating stack is located in the pixel area and extends to the isolation area. The first insulating stack is located between the first isolation structure and the conductive block. The first insulating stack has a first through hole that penetrates the first insulating stack. The first isolation structure extends into the first through hole and is connected to the conductive block.

6. The display panel according to claim 4, wherein: Also includes: The first connecting line is connected to the conductive block and to the first voltage terminal; the conductive block is configured such that a voltage difference between the conductive block and the supporting layer is less than or equal to a driving voltage of the first ion.

7. The display panel according to claim 6, wherein: The first voltage terminal is grounded.

8. The display panel according to any one of claims 2, 3, 6 and 7, wherein: Also includes: a pixel circuit stack, disposed between the substrate and the cathode layer, the pixel circuit stack comprising a plurality of first pixel circuits and a plurality of redundant pixel circuits; The plurality of first pixel circuits are located in the pixel area, and the plurality of redundant pixel circuits are located in the isolation area; the plurality of redundant pixel circuits are adjacent to the first pixel circuits located in the pixel area and close to the edge of the opening area; The light emitting device stack is located on a side of the pixel circuit stack away from the substrate; the light emitting device stack includes a plurality of light emitting devices; the first pixel circuit is electrically connected to the light emitting device, and the redundant pixel circuit is electrically insulated from the light emitting device.

9. The display panel according to claim 8, wherein: The redundant pixel circuit includes a second transistor, and the pixel circuit stack further includes: an active layer including an active portion of the second transistor; a first source-drain conductive layer, located between the active layer and the cathode layer; the first source-drain conductive layer includes the first electrode of the second transistor; the first connecting line is provided in the same layer as the first electrode of the second transistor and is connected to the first electrode of the second transistor; At least one third insulating layer is arranged between the first electrode of the second transistor and the conductive block, is located in the pixel area, and extends to the isolation area; the at least one third insulating layer is provided with a second through hole penetrating the at least one third insulating layer; the first electrode of the second transistor extends into the second through hole and is connected to the conductive block.

10. The display panel according to claim 8, wherein The redundant pixel circuit includes a second transistor, and the pixel circuit stack further includes: an active layer including an active portion of the second transistor; a first source-drain conductive layer, located between the active layer and the cathode layer; the first source-drain conductive layer includes a first electrode of the second transistor; At least one third insulating layer is disposed between the first source-drain conductive layer and the conductive block, is located in the pixel region, and extends to the isolation region; the at least one third insulating layer is located between the conductive block and the first electrode of the second transistor; the at least one third insulating layer is provided with a second through hole penetrating the at least one third insulating layer; the first electrode of the second transistor extends into the second through hole and is connected to the conductive block; at least one fourth insulating layer, disposed between the first source-drain conductive layer and the cathode layer, located in the pixel region, and extending to the isolation region; the at least one fourth insulating layer is provided with a third through hole; The first connecting line is provided between the at least one fourth insulating layer and the cathode layer, and extends into the third through hole to be connected to the first electrode of the second transistor.

11. The display panel according to claim 10, wherein: The display device further comprises a fan-out area, which is arranged on one side of the display area along the second direction; the display area further comprises a central area and an edge area, which is arranged on at least one side of the central area along the first direction; wherein the first direction intersects the second direction; The display panel further includes: A plurality of data lines are disposed on the substrate; the plurality of data lines are arranged at intervals along the first direction; the plurality of data lines include a first data line; the first data line is disposed in the edge region and extends along the second direction; A plurality of first transfer lines are provided in the same layer as the plurality of data lines and are located in the central area; the first transfer lines extend along the second direction and are connected to the fan-out area; a plurality of second transfer lines, arranged between the plurality of first transfer lines and the first source-drain conductive layer, or between the plurality of first transfer lines and the cathode layer; the second transfer lines extend along the first direction, and one second transfer line is connected to one first data line and one first transfer line; The first connecting line is arranged on the same layer as the first adapter line and / or the second adapter line.

12. The display panel according to claim 11, wherein: The first connecting line includes: A plurality of first sub-lines extending along the second direction and spaced apart along the first direction; the first sub-lines and the first patch line are arranged on the same layer; A plurality of second sub-wires extend along the first direction and are spaced apart along the second direction; the second sub-wires and the second adapter wires are arranged in the same layer; the plurality of second sub-wires and the plurality of first sub-wires are connected to form a mesh structure.

13. The display panel according to any one of claims 2, 3, 6 and 7, characterized in that: The first connecting line and the conductive block are arranged in the same layer.

14. The display panel according to any one of claims 1 to 7, wherein: comprising a plurality of first isolation structures; The plurality of first isolation structures are arranged at intervals along a direction from the isolation region to the opening region; The display panel further includes: a spacer located between the substrate and the cathode layer; the spacer is partially located between two adjacent first isolation structures, partially located on a side of the first isolation structure away from the substrate, and covering a portion of the end surface of the first isolation structure away from the substrate; the surface of the spacer away from the substrate protrudes in a direction away from the substrate; In which, the cathode layer also includes a third sub-section, which is located on the side of the pad away from the substrate and is connected to the adjacent first sub-section; the minimum distance between the surface of the third sub-section away from the substrate and the pad is smaller than the minimum distance between the surface of the first sub-section away from the substrate and the first isolation structure, and smaller than the minimum distance between the surface of the second sub-section away from the substrate and the substrate.

15. The display panel according to any one of claims 1 to 7, wherein: Also includes: The stacked multiple layers of first conductive layers are arranged between the first isolation structure and the substrate; the conductive block is located in the first conductive layer closest to the substrate among the multiple layers of first conductive layers.

16. The display panel according to any one of claims 1 to 7, wherein: Also includes: an inorganic encapsulation layer, located in the display area and extending to the isolation area; the inorganic encapsulation layer is located on a side of the cathode layer away from the substrate and covers the cathode layer; Multiple layers of stacked first conductive layers are arranged between the first isolation structure and the substrate; the conductive block is located in one layer of the first conductive layer; A second insulating stack is located in the pixel area and extends to the isolation area. The second insulating stack is located between the first isolation structure and the first conductive layer including the conductive block. Along the direction perpendicular to the substrate, the thickness of the second insulating stack is greater than the thickness of the inorganic encapsulation layer.

17. The display panel according to any one of claims 1 to 7, wherein: Also includes: an active layer, located in the pixel region and between the substrate and the cathode layer; The active layer includes a channel portion; a light shielding layer, located between the active layer and the substrate; The light shielding layer includes a plurality of light shielding blocks, wherein the orthographic projections of the light shielding blocks on the substrate at least partially overlap with the orthographic projections of the channel portion on the substrate; Wherein, the conductive block is located in the light shielding layer.

18. A display module, characterized in that: include: a supporting layer, wherein the supporting layer is grounded; The display panel according to any one of claims 1 to 17, wherein the display panel has a display side and a non-display side that are arranged opposite to each other, and the display side is farther away from the supporting layer than the non-display side; A polarizer is located on a side of the display panel away from the supporting layer; the material of the polarizer includes a first ion.

19. A display device, characterized in that: include: The display panel according to any one of claims 1 to 17, or the display module according to claim 18.

Images