Pixel circuit and display device

Abstract

The present invention provides a pixel circuit and display device. The pixel circuit includes a driving circuit, a compensation control circuit, a first energy storage circuit, a first control circuit, and a second control circuit. The compensation control circuit controls the connection between the first node and the third node under the control of the potential of the control node. The first end of the first energy storage circuit is electrically connected to the control node, and the second end of the first energy storage circuit is electrically connected to the first gate drive terminal. The first control circuit controls the connection between the first node and the control node under the control of a first control signal. The second control circuit controls the connection between the third node and the first gate drive terminal under the control of a second control signal. The present invention further performs threshold voltage compensation on threshold voltage-sensitive transistors to improve image quality and meet special needs.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] In related technologies, with the continuous updates and iterations of the OLED (organic light-emitting diode) industry, pixel circuits suitable for various new functions have also been proposed. In the related LTPO (low-temperature polycrystalline oxide) pixel architecture, the compensation transistor connected to the gate of the drive transistor is an oxide TFT (thin-film transistor). However, the PBTS (positive bias temperature stress) stability of the oxide TFT is poor, and the Vth (Vth is threshold voltage) sensitivity of the compensation transistor is poor, resulting in frequent reliability stripes and HRD (hybrid refresh display) split-screen brightness differences and other defects. Summary of the Invention

[0003] The main purpose of the present invention is to provide a pixel circuit and a display device to solve the problems in the prior art that a pixel circuit for threshold voltage compensation of oxide transistors cannot be provided, threshold voltage compensation cannot be continued for transistors sensitive to threshold voltage, and image quality cannot be improved to meet special needs.

[0004] In one aspect, an embodiment of the present invention provides a pixel circuit, including a driving circuit, a compensation control circuit, a first energy storage circuit, a first control circuit, and a second control circuit;

[0005] The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node, and the driving circuit is configured to generate a driving current under the control of the potential of the first node;

[0006] The compensation control circuit is electrically connected to the control node, the first node and the third node respectively, and is used to control the communication between the first node and the third node under the control of the potential of the control node;

[0007] A first end of the first energy storage circuit is electrically connected to the control node, a second end of the first energy storage circuit is electrically connected to the first gate driving end, and the first energy storage circuit is used to store electrical energy;

[0008] The first control circuit is electrically connected to the first control terminal, the first node and the control node respectively, and is used to control the communication between the first node and the control node under the control of a first control signal provided by the first control terminal;

[0009] The second control circuit is electrically connected to the second control terminal, the third node and the first gate driving terminal respectively, and is used to control the connection between the third node and the first gate driving terminal under the control of a second control signal provided by the second control terminal.

[0010] Optionally, both the first control end and the second control end are first scanning ends.

[0011] Optionally, the first control end is a first scanning end, and the second control end is a second scanning end.

[0012] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit;

[0013] The first initialization circuit is electrically connected to the first scanning terminal, the first initial voltage terminal and the control node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of the first scanning signal provided by the first scanning terminal;

[0014] The first control end and the second control end are second scanning ends.

[0015] Optionally, the transistor included in the compensation control circuit is an oxide transistor, and the transistor included in the first control circuit and the transistor included in the second control circuit are low-temperature polysilicon transistors.

[0016] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a data writing circuit and a second energy storage circuit;

[0017] The data writing circuit is electrically connected to the second gate driving terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate driving terminal;

[0018] The second energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node.

[0019] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit;

[0020] The first light emitting control circuit is electrically connected to the light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light emitting control signal provided by the light emitting control terminal;

[0021] The second light emitting control circuit is electrically connected to the light emitting control terminal, the third node, and the first electrode of the light emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal;

[0022] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0023] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit;

[0024] The second initialization circuit is electrically connected to the first reset terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first reset control signal provided by the first reset terminal.

[0025] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit;

[0026] The second initialization circuit is electrically connected to the first reset terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset terminal.

[0027] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a third initialization circuit;

[0028] The third initialization circuit is electrically connected to the second reset terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset terminal.

[0029] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit;

[0030] The fourth initialization circuit is electrically connected to the second reset terminal, the third initial voltage terminal and the second node respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset terminal.

[0031] Optionally, the pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit, a third control circuit and a fourth control circuit;

[0032] The first end of the third energy storage circuit is electrically connected to the intermediate node, the second end of the third energy storage circuit is electrically connected to the first reset end, and the third energy storage circuit is used to store electrical energy;

[0033] The third control circuit is electrically connected to the first control terminal, the first initial voltage terminal and the intermediate node respectively, and is used to control the connection between the first initial voltage terminal and the intermediate node under the control of the first control signal;

[0034] The fourth control circuit is electrically connected to the second control terminal, the first node and the first reset terminal respectively, and is used to control the connection between the first node and the first reset terminal under the control of the second control signal.

[0035] Optionally, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the first energy storage circuit includes a first capacitor; the first control circuit includes a second transistor, and the second control circuit includes a third transistor;

[0036] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0037] The gate of the first transistor is electrically connected to the control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node;

[0038] A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to the first gate driving end;

[0039] The gate of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the control node;

[0040] The gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first gate driving terminal.

[0041] Optionally, the first initialization circuit includes a fourth transistor;

[0042] A gate of the fourth transistor is electrically connected to the first scanning end, a first electrode of the fourth transistor is electrically connected to the first initial voltage end, and a second electrode of the fourth transistor is electrically connected to the control node.

[0043] Optionally, the data writing circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor;

[0044] The gate of the fifth transistor is electrically connected to the second gate driving terminal, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the second node;

[0045] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to a DC voltage end.

[0046] Optionally, the first light emitting control circuit includes a sixth transistor, and the second light emitting control circuit includes a seventh transistor;

[0047] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second node;

[0048] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0049] Optionally, the second initialization circuit includes an eighth transistor;

[0050] A gate of the eighth transistor is electrically connected to the first reset terminal, a first electrode of the eighth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the third node.

[0051] Optionally, the second initialization circuit includes an eighth transistor;

[0052] A gate of the eighth transistor is electrically connected to the first reset terminal, a first electrode of the eighth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first node.

[0053] Optionally, the third initialization circuit includes a ninth transistor;

[0054] The gate of the ninth transistor is electrically connected to the second reset terminal, the first electrode of the ninth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element.

[0055] Optionally, the fourth initialization circuit includes a tenth transistor;

[0056] A gate of the tenth transistor is electrically connected to the second reset terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the second node.

[0057] Optionally, the third energy storage circuit includes a third capacitor, the third control circuit includes an eleventh transistor, and the fourth control circuit includes a twelfth transistor;

[0058] A first end of the third capacitor is electrically connected to the intermediate node, and a second end of the third capacitor is electrically connected to the first reset end;

[0059] The gate of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the first initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the intermediate node;

[0060] The gate of the twelfth transistor is electrically connected to the second control terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the first reset terminal. In a second aspect, an embodiment of the present invention provides a display device including the above-mentioned pixel circuit.

[0061] An embodiment of the present invention provides a pixel circuit for threshold voltage compensation of oxide transistors, and further performs threshold voltage compensation on transistors that are sensitive to threshold voltage to improve image quality and meet special requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] Figure 1A is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0063] Figure 1B is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0064] Figure 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0065] Figure 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0066] Figure 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0067] Figure 5A is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0068] Figure 5B is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0069] Figure 6A is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0070] Figure 6B is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0071] Figure 7A is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0072] Figure 7B is a structural diagram of a pixel circuit according to at least one embodiment of the present invention;

[0073] Figure 8A yes Figure 7A An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0074] Figure 8B yes Figure 7B An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0075] Figure 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0076] Figure 10 yes Figure 9 An operation timing diagram of at least one embodiment of the pixel circuit shown;

[0077] Figure 11A is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0078] Figure 11B is a circuit diagram of a pixel circuit according to at least one embodiment of the present invention;

[0079] Figure 12 yes Figure 11A FIG. 1 is an operational timing diagram of at least one embodiment of a pixel circuit shown. DETAILED DESCRIPTION

[0080] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0081] The transistors used in all embodiments of the present invention may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present invention, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0082] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0083] like Figure 1A As shown, the pixel circuit according to the embodiment of the present invention includes a driving circuit 10, a compensation control circuit 11, a first energy storage circuit 12, a first control circuit 13 and a second control circuit 14;

[0084] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is configured to generate a driving current under the control of the potential of the first node N1;

[0085] The compensation control circuit 11 is electrically connected to the control node NC, the first node N1 and the third node N3, respectively, and is configured to control the connection between the first node N1 and the third node N3 under the control of the potential of the control node NC;

[0086] A first end of the first energy storage circuit 12 is electrically connected to the control node NC, a second end of the first energy storage circuit 12 is electrically connected to the first gate driving terminal NGT, and the first energy storage circuit 12 is used to store electrical energy;

[0087] The first control circuit 13 is electrically connected to the first control terminal S1, the first node N1 and the control node NC respectively, and is configured to control the connection between the first node N1 and the control node NC under the control of a first control signal provided by the first control terminal S1;

[0088] The second control circuit 14 is electrically connected to the second control terminal S2, the third node N3 and the first gate driving terminal NGT respectively, and is used to control the connection between the third node N3 and the first gate driving terminal NGT under the control of the second control signal provided by the second control terminal S2.

[0089] An embodiment of the present invention provides a pixel circuit for threshold voltage compensation of oxide transistors. Threshold voltage compensation is further performed on threshold voltage-sensitive transistors to improve image quality and meet special requirements, such as defects caused by HRD.

[0090] In at least one embodiment of the present invention, both the first control end and the second control end are first scanning ends.

[0091] In a specific implementation, the first control end and the second control end may be the same control end, which may be a first scanning end.

[0092] like Figure 1B As shown, in Figure 1A Based on at least one embodiment of the pixel circuit shown, the first control terminal and the second control terminal are both the first scanning terminal SC1.

[0093] In at least one embodiment of the present invention, the first control end is a first scanning end, and the second control end is a second scanning end.

[0094] The pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit;

[0095] The first initialization circuit is electrically connected to the first scanning terminal, the first initial voltage terminal and the control node respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of the first scanning signal provided by the first scanning terminal;

[0096] The first control end and the second control end are second scanning ends.

[0097] In a specific implementation, the first control end and the second control end can both be second scanning ends, and the pixel circuit can further include a first initialization circuit, which, under the control of a first scanning signal, writes a first initial voltage into the control node to reset the potential of the control node.

[0098] like Figure 2 As shown, in Figure 1A Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a first initialization circuit 21;

[0099] The first initialization circuit 21 is electrically connected to the first scan terminal SC1, the first initial voltage terminal I1 and the control node NC, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the control node NC under the control of the first scan signal provided by the first scan terminal SC1;

[0100] The first control end and the second control end may be second scanning ends.

[0101] In at least one embodiment of the present invention, the transistors included in the compensation control circuit are oxide transistors, and the transistors included in the first control circuit and the transistors included in the second control circuit are low-temperature polysilicon transistors.

[0102] The pixel circuit according to at least one embodiment of the present invention further includes a data writing circuit and a second energy storage circuit;

[0103] The data writing circuit is electrically connected to the second gate driving terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate driving terminal;

[0104] The second energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node.

[0105] In a specific implementation, the pixel circuit may further include a data writing circuit and a second energy storage circuit. The data writing circuit writes the data voltage to the second node under the control of the second gate driving signal, and the second energy storage circuit maintains the potential of the first node.

[0106] like Figure 3 As shown, in Figure 1A Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a data writing circuit 31 and a second energy storage circuit 32;

[0107] The data writing circuit 31 is electrically connected to the second gate driving terminal PGT, the data line DL and the second node N2, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the second gate driving signal provided by the second gate driving terminal PGT;

[0108] The second energy storage circuit 32 is electrically connected to the first node N1 and is configured to maintain the potential of the first node N1.

[0109] like Figure 4 As shown, in Figure 2 Based on at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a data writing circuit 31 and a second energy storage circuit 32;

[0110] The data writing circuit 31 is electrically connected to the second gate driving terminal PGT, the data line DL and the second node N2, and is used to write the data voltage Vdata provided by the data line DL into the second node N2 under the control of the second gate driving signal provided by the second gate driving terminal PGT;

[0111] The second energy storage circuit 32 is electrically connected to the first node N1 and is configured to maintain the potential of the first node N1.

[0112] The pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element, a first light-emitting control circuit and a second light-emitting control circuit;

[0113] The first light emitting control circuit is electrically connected to the light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light emitting control signal provided by the light emitting control terminal;

[0114] The second light emitting control circuit is electrically connected to the light emitting control terminal, the third node, and the first electrode of the light emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal;

[0115] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0116] In a specific implementation, the pixel circuit may further include a light-emitting element, a first light-emitting control circuit and a second light-emitting control circuit. The first light-emitting control circuit and the second light-emitting control circuit perform on-off control of the light-emitting path under the control of the light-emitting control signal.

[0117] Optionally, the first voltage terminal may be a low voltage terminal.

[0118] The pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit;

[0119] The second initialization circuit is electrically connected to the first reset terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first reset control signal provided by the first reset terminal.

[0120] In a specific implementation, the pixel circuit may further include a second initialization circuit, which writes a first initial voltage to a third node under the control of a first reset control signal, so that when the compensation control circuit controls the connection between the first node and the third node under the control of the potential of the control node, the first initial voltage can be written to the first node, and the potential of the first node can be reset, so that the driving circuit can be turned on at the beginning of the compensation stage.

[0121] The pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit;

[0122] The second initialization circuit is electrically connected to the first reset terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset terminal.

[0123] In a specific implementation, the pixel circuit may further include a second initialization circuit, which, under the control of a first reset control signal, writes a first initial voltage into the first node to reset the potential of the first node so that the driving circuit can be turned on at the beginning of the compensation phase.

[0124] The pixel circuit according to at least one embodiment of the present invention further includes a third initialization circuit;

[0125] The third initialization circuit is electrically connected to the second reset terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset terminal.

[0126] In a specific implementation, the pixel circuit may further include a third initialization circuit. Under the control of a second reset control signal, the third initialization circuit writes a second initial voltage into the first electrode of the light-emitting element to clear the residual charge in the first electrode of the light-emitting element.

[0127] The pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit;

[0128] The fourth initialization circuit is electrically connected to the second reset terminal, the third initial voltage terminal and the second node respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset terminal.

[0129] In a specific implementation, the pixel circuit may further include a fourth initialization circuit. Under the control of the second reset control signal, the fourth initialization circuit writes a second initial voltage into the second node to improve the hysteresis phenomenon of the driving transistor in the driving circuit.

[0130] like Figure 5A As shown, in Figure 3 On the basis of at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a first light-emitting control circuit 51 and a second light-emitting control circuit 52;

[0131] The first light emitting control circuit 51 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal VDD and the second node N2 respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0132] The second light emitting control circuit 52 is electrically connected to the light emitting control terminal EM, the third node N3, and the first electrode of the light emitting element E1, respectively, and is used to control the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal;

[0133] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0134] The pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit 53;

[0135] The second initialization circuit 53 is electrically connected to the first reset terminal RSTP, the first initial voltage terminal I1 and the third node N3, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the first reset control signal provided by the first reset terminal RSTP;

[0136] The pixel circuit according to at least one embodiment of the present invention further includes a third initialization circuit 54;

[0137] The third initialization circuit 54 is electrically connected to the second reset terminal RSTH, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset terminal RSTH;

[0138] The pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit 55;

[0139] The fourth initialization circuit 55 is electrically connected to the second reset terminal RSTH, the third initial voltage terminal I3 and the second node N2 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the second node N2 under the control of the second reset control signal provided by the second reset terminal RSTH.

[0140] like Figure 5B As shown, in Figure 3 On the basis of at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a first light-emitting control circuit 51 and a second light-emitting control circuit 52;

[0141] The first light emitting control circuit 51 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal VDD and the second node N2 respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0142] The second light emitting control circuit 52 is electrically connected to the light emitting control terminal EM, the third node N3, and the first electrode of the light emitting element E1, respectively, and is used to control the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal;

[0143] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0144] The pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit 53;

[0145] The second initialization circuit 53 is electrically connected to the first reset terminal RSTP, the first initial voltage terminal I1 and the first node N1 respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the first node N1 under the control of the first reset control signal provided by the first reset terminal RSTP;

[0146] The pixel circuit according to at least one embodiment of the present invention further includes a third initialization circuit 54;

[0147] The third initialization circuit 54 is electrically connected to the second reset terminal RSTH, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset terminal RSTH;

[0148] The pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit 55;

[0149] The fourth initialization circuit 55 is electrically connected to the second reset terminal RSTH, the third initial voltage terminal I3 and the second node N2 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the second node N2 under the control of the second reset control signal provided by the second reset terminal RSTH.

[0150] like Figure 6A As shown, in Figure 4 On the basis of at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a light-emitting element E1, a first light-emitting control circuit 51 and a second light-emitting control circuit 52;

[0151] The first light emitting control circuit 51 is electrically connected to the light emitting control terminal EM, the power supply voltage terminal VDD and the second node N2 respectively, and is used to control the connection between the power supply voltage terminal VDD and the second node N2 under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0152] The second light emitting control circuit 52 is electrically connected to the light emitting control terminal EM, the third node N3, and the first electrode of the light emitting element E1, respectively, and is used to control the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal;

[0153] The second electrode of the light emitting element E1 is electrically connected to the first voltage terminal V1;

[0154] The pixel circuit according to at least one embodiment of the present invention further includes a second initialization circuit 53;

[0155] The second initialization circuit 53 is electrically connected to the first reset terminal RSTP, the first initial voltage terminal I1 and the third node N3, respectively, and is configured to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the first reset control signal provided by the first reset terminal RSTP;

[0156] The pixel circuit according to at least one embodiment of the present invention further includes a third initialization circuit 54;

[0157] The third initialization circuit 54 is electrically connected to the second reset terminal RSTH, the second initial voltage terminal I2, and the first electrode of the light-emitting element E1, respectively, and is configured to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first electrode of the light-emitting element E1 under the control of the second reset control signal provided by the second reset terminal RSTH;

[0158] The pixel circuit according to at least one embodiment of the present invention further includes a fourth initialization circuit 55;

[0159] The fourth initialization circuit 55 is electrically connected to the second reset terminal RSTH, the third initial voltage terminal I3 and the second node N2 respectively, and is used to write the third initial voltage provided by the third initial voltage terminal I3 into the second node N2 under the control of the second reset control signal provided by the second reset terminal RSTH.

[0160] The pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit, a third control circuit, and a fourth control circuit;

[0161] The first end of the third energy storage circuit is electrically connected to the intermediate node, the second end of the third energy storage circuit is electrically connected to the first reset end, and the third energy storage circuit is used to store electrical energy;

[0162] The third control circuit is electrically connected to the first control terminal, the first initial voltage terminal and the intermediate node respectively, and is used to control the connection between the first initial voltage terminal and the intermediate node under the control of the first control signal;

[0163] The fourth control circuit is electrically connected to the second control terminal, the first node and the first reset terminal respectively, and is used to control the connection between the first node and the first reset terminal under the control of the second control signal.

[0164] In at least one embodiment of the present invention, when the transistor included in the second initialization circuit is an oxide transistor, the threshold voltage of the transistor included in the second initialization circuit can be compensated by the third energy storage circuit, the third control circuit and the fourth control circuit to improve image quality and special needs, such as defects caused by HRD.

[0165] like Figure 6B As shown, in Figure 5B On the basis of at least one embodiment of the pixel circuit shown, the pixel circuit according to at least one embodiment of the present invention further includes a third energy storage circuit 61, a third control circuit 62 and a fourth control circuit 63;

[0166] The first end of the third energy storage circuit 61 is electrically connected to the intermediate node NZ, the second end of the third energy storage circuit 61 is electrically connected to the first reset end RSTP, and the third energy storage circuit 61 is used to store electrical energy;

[0167] The third control circuit 62 is electrically connected to the first control terminal S1, the first initial voltage terminal I1 and the intermediate node NZ respectively, and is used to control the communication between the first initial voltage terminal I1 and the intermediate node NZ under the control of the first control signal;

[0168] The fourth control circuit 63 is electrically connected to the second control terminal S2, the first node N1, and the first reset terminal RSTP, respectively, and is configured to control the connection between the first node N1 and the first reset terminal RSTP under the control of the second control signal.

[0169] Optionally, the driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the first energy storage circuit includes a first capacitor; the first control circuit includes a second transistor, and the second control circuit includes a third transistor;

[0170] The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node;

[0171] The gate of the first transistor is electrically connected to the control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node;

[0172] A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to the first gate driving end;

[0173] The gate of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the control node;

[0174] The gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first gate driving terminal.

[0175] Optionally, the first initialization circuit includes a fourth transistor;

[0176] A gate of the fourth transistor is electrically connected to the first scanning end, a first electrode of the fourth transistor is electrically connected to the first initial voltage end, and a second electrode of the fourth transistor is electrically connected to the control node.

[0177] Optionally, the data writing circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor;

[0178] The gate of the fifth transistor is electrically connected to the second gate driving terminal, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the second node;

[0179] A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to a DC voltage end.

[0180] Optionally, the first light emitting control circuit includes a sixth transistor, and the second light emitting control circuit includes a seventh transistor;

[0181] The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second node;

[0182] The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

[0183] Optionally, the second initialization circuit includes an eighth transistor;

[0184] A gate of the eighth transistor is electrically connected to the first reset terminal, a first electrode of the eighth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the third node.

[0185] Optionally, the third initialization circuit includes a ninth transistor;

[0186] The gate of the ninth transistor is electrically connected to the second reset terminal, the first electrode of the ninth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element.

[0187] Optionally, the fourth initialization circuit includes a tenth transistor;

[0188] A gate of the tenth transistor is electrically connected to the second reset terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the second node.

[0189] like Figure 7A As shown, in Figure 5A Based on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1; the first control circuit includes a second transistor T2, and the second control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1;

[0190] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0191] The gate of the first transistor T1 is electrically connected to the control node NC, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0192] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first gate driving terminal NGT;

[0193] The gate of the second transistor T2 is electrically connected to the first scan terminal SC1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0194] The gate of the third transistor T3 is electrically connected to the first scanning terminal SC1, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the first gate driving terminal NGT;

[0195] The data writing circuit includes a fifth transistor T5, and the second energy storage circuit includes a second capacitor C2;

[0196] The gate of the fifth transistor T5 is electrically connected to the second gate driving terminal PGT, the source of the fifth transistor T5 is electrically connected to the data line DL, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0197] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0198] The first light emitting control circuit includes a sixth transistor T6, and the second light emitting control circuit includes a seventh transistor T7;

[0199] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0200] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1;

[0201] The second initialization circuit includes an eighth transistor T8;

[0202] The gate of the eighth transistor T8 is electrically connected to the first reset terminal RSTP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the third node N3;

[0203] The third initialization circuit includes a ninth transistor T9;

[0204] The gate of the ninth transistor T9 is electrically connected to the second reset terminal RSTH, the source of the ninth transistor T9 is electrically connected to the second initial voltage terminal I2, the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0205] The fourth initialization circuit includes a tenth transistor T10;

[0206] A gate of the tenth transistor T10 is electrically connected to the second reset terminal RSTH, a source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and a drain of the tenth transistor T10 is electrically connected to the second node N2.

[0207] exist Figure 7A In at least one embodiment of the pixel circuit shown, T1 is an n-type transistor, T0, T2, T3, T5, T6, T7, T8, T9, and T10 are p-type transistors; T1 is an oxide TFT;

[0208] T1 is a transistor sensitive to threshold voltage.

[0209] like Figure 8A As shown, the present invention Figure 7AWhen at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a compensation phase t1, a first reset phase t2, a data writing phase t3, a second reset phase t4, and a light emitting phase t5, which are arranged in sequence;

[0210] In the compensation phase t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, T2 and T3 are turned on, and the high voltage signal provided by NGT passes through T3, T1, and T2, pulling the potential of NC up. When the potential of NC reaches Vngt + Vth1, T1 is turned off, and C1 maintains the potential of NC to compensate for the threshold voltage of T1. Vngt is the voltage value of the voltage signal provided by NGT, and Vth1 is the threshold voltage of T1.

[0211] In the first reset phase t2, NGT provides a high voltage signal, SC1 provides a high voltage signal, RSTP provides a low voltage signal, T8 is turned on, Vinit1 is written to N3, T1 is turned on, Vinit1 is written to N1, and the potential of N1 is reset;

[0212] In the data writing phase t3, NGT provides a high voltage signal, PGT provides a low voltage signal, T5 is turned on, DL provides the data voltage Vdata to N2, and T1 is turned on;

[0213] At the beginning of the data writing phase t3, T0 is turned on, Vdata charges C2 through T5, T0 and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off;

[0214] After the data writing phase t3, when the potential of the first gate drive signal provided by NGT drops, the potential of NC is pulled down by C1. The potential of NC is equal to Vngt + Vth1 + ΔV × C1z / CNC. The potential of NC always includes Vth1. Therefore, the on-state of T1 is not affected by the threshold voltage of T1, achieving the purpose of compensating the threshold voltage of T1. Here, ΔV is the change in the potential of the first gate signal, Cz1 ​​is the capacitance value of C1, and CNC is the total capacitance of NC.

[0215] In the second reset phase t4, RSTH provides a low voltage signal, T9 and T10 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O1 to clear the residual charge on the anode of O1, and I3 provides a third initial voltage Vinit3 to N2 to improve the hysteresis phenomenon of T0;

[0216] In the light-emitting stage t5, EM provides a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0217] like Figure 7B As shown, in Figure 5BBased on at least one embodiment of the pixel circuit shown,

[0218] The driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, and the first energy storage circuit includes a first capacitor C1; the first control circuit includes a second transistor T2, and the second control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1;

[0219] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0220] The gate of the first transistor T1 is electrically connected to the control node NC, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0221] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first gate driving terminal NGT;

[0222] The gate of the second transistor T2 is electrically connected to the first scan terminal SC1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0223] The gate of the third transistor T3 is electrically connected to the first scanning terminal SC1, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the first gate driving terminal NGT;

[0224] The data writing circuit includes a fifth transistor T5, and the second energy storage circuit includes a second capacitor C2;

[0225] The gate of the fifth transistor T5 is electrically connected to the second gate driving terminal PGT, the source of the fifth transistor T5 is electrically connected to the data line DL, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0226] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0227] The first light emitting control circuit includes a sixth transistor T6, and the second light emitting control circuit includes a seventh transistor T7;

[0228] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0229] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1;

[0230] The second initialization circuit includes an eighth transistor T8;

[0231] The gate of the eighth transistor T8 is electrically connected to the first reset terminal RSTP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the first node N1;

[0232] The third initialization circuit includes a ninth transistor T9;

[0233] The gate of the ninth transistor T9 is electrically connected to the second reset terminal RSTH, the source of the ninth transistor T9 is electrically connected to the second initial voltage terminal I2, the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0234] The fourth initialization circuit includes a tenth transistor T10;

[0235] A gate of the tenth transistor T10 is electrically connected to the second reset terminal RSTH, a source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and a drain of the tenth transistor T10 is electrically connected to the second node N2.

[0236] exist Figure 7B In at least one embodiment of the pixel circuit shown, T1 and T8 are n-type transistors, T0, T2, T3, T5, T6, T7, T9, and T10 are p-type transistors; T1 and T8 are oxide TFTs;

[0237] T1 is a transistor sensitive to threshold voltage.

[0238] like Figure 8B As shown, the present invention Figure 7B When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a compensation phase t1, a first reset phase t2, a data writing phase t3, a second reset phase t4, and a light emitting phase t5, which are arranged in sequence;

[0239] In the compensation phase t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, T2 and T3 are turned on, and the high voltage signal provided by NGT passes through T3, T1, and T2, pulling the potential of NC up. When the potential of NC reaches Vngt + Vth1, T1 is turned off, and C1 maintains the potential of NC to compensate for the threshold voltage of T1. Vngt is the voltage value of the voltage signal provided by NGT, and Vth1 is the threshold voltage of T1.

[0240] In the first reset phase t2, NGT provides a high voltage signal, SC1 provides a high voltage signal, RSTP provides a high voltage signal, T8 is turned on, Vinit1 is written into N1, and the potential of N1 is reset;

[0241] In the data writing phase t3, NGT provides a high voltage signal, PGT provides a low voltage signal, T5 is turned on, DL provides the data voltage Vdata to N2, and T1 is turned on;

[0242] At the beginning of the data writing phase t3, T0 is turned on, Vdata charges C2 through T5, T0 and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off;

[0243] After the data writing phase t3, when the potential of the first gate drive signal provided by NGT drops, the potential of NC is pulled down by C1. The potential of NC is equal to Vngt + Vth1 + ΔV × C1z / CNC. The potential of NC always includes Vth1. Therefore, the on-state of T1 is not affected by the threshold voltage of T1, achieving the purpose of compensating the threshold voltage of T1. Here, ΔV is the change in the potential of the first gate signal, Cz1 ​​is the capacitance value of C1, and CNC is the total capacitance of NC.

[0244] In the second reset phase t4, RSTH provides a low voltage signal, T9 and T10 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O1 to clear the residual charge on the anode of O1, and I3 provides a third initial voltage Vinit3 to N2 to improve the hysteresis phenomenon of T0;

[0245] In the light-emitting stage t5, EM provides a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0246] like Figure 9 As shown, in Figure 5ABased on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1; the first control circuit includes a second transistor T2, and the second control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1;

[0247] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0248] The gate of the first transistor T1 is electrically connected to the control node NC, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0249] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first gate driving terminal NGT;

[0250] The gate of the second transistor T2 is electrically connected to the first scan terminal SC1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0251] The gate of the third transistor T3 is electrically connected to the second scanning terminal SC2, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the first gate driving terminal NGT;

[0252] The data writing circuit includes a fifth transistor T5, and the second energy storage circuit includes a second capacitor C2;

[0253] The gate of the fifth transistor T5 is electrically connected to the second gate driving terminal PGT, the source of the fifth transistor T5 is electrically connected to the data line DL, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0254] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0255] The first light emitting control circuit includes a sixth transistor T6, and the second light emitting control circuit includes a seventh transistor T7;

[0256] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0257] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1;

[0258] The second initialization circuit includes an eighth transistor T8;

[0259] The gate of the eighth transistor T8 is electrically connected to the first reset terminal RSTP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the third node N3;

[0260] The third initialization circuit includes a ninth transistor T9;

[0261] The gate of the ninth transistor T9 is electrically connected to the second reset terminal RSTH, the source of the ninth transistor T9 is electrically connected to the second initial voltage terminal I2, the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0262] The fourth initialization circuit includes a tenth transistor T10;

[0263] A gate of the tenth transistor T10 is electrically connected to the second reset terminal RSTH, a source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and a drain of the tenth transistor T10 is electrically connected to the second node N2.

[0264] exist Figure 9 In at least one embodiment of the pixel circuit shown, T1 is an n-type transistor, T0, T2, T3, T5, T6, T7, T8, T9, and T10 are p-type transistors; T1 is an oxide TFT;

[0265] T1 is a transistor sensitive to threshold voltage.

[0266] like Figure 10 As shown, the present invention Figure 9 When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a first reset phase t0, a compensation phase t1, a second reset phase t4, a data writing phase t3, a third reset phase t6, and a light emitting phase t5, which are arranged in sequence;

[0267] In the first reset phase t0, NGT provides a high voltage signal, SC1 provides a low voltage signal, SC2 provides a high voltage signal, RSTP provides a low voltage signal, T8 and T2 are open, and when the potential of the voltage signal provided by NGT jumps high, the potential of NC is pulled high. Vinit1 provided by I1 passes through T1 and T2, and resets the potential of NC to Vinit1+Vth1. When the potential of NC is Vinit1+Vth1, T1 is closed, C1 maintains the potential of NC, and Vth1 is the threshold voltage of T1;

[0268] In the compensation phase t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, SC2 provides a low voltage signal, T2 and T3 are turned on, and the high voltage signal provided by NGT passes through T3, T1 and T2, pulling the potential of NC high. When the potential of NC is Vngt + Vth1, T1 is turned off and C1 maintains the potential of NC. Vngt is the potential of the first gate drive signal provided by NGT, and Vth1 is the threshold voltage of T1.

[0269] In the second reset phase t4, SC1 and SC2 provide high voltage signals, RSTP provides a low voltage signal, T8 is turned on, T1 is opened, and the potential of N1 is reset by the first initial voltage Vinit1 provided by I1;

[0270] In the data writing phase t3, PGT provides a low voltage signal, NGT provides a high voltage signal, PGT provides a low voltage signal, T5 is turned on, DL provides the data voltage Vdata to N2, and T1 is turned on;

[0271] At the beginning of the data writing phase t3, T0 is turned on, and C2 is charged through Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off.

[0272] After the data writing phase t3, when the potential of the first gate drive signal provided by NGT drops, the potential of NC is pulled down by C1. The potential of NC is equal to Vngt + Vth1 + ΔV × C1z / CNC. The potential of NC always includes Vth1. Therefore, the on-state of T1 is not affected by the threshold voltage of T1, achieving the purpose of compensating the threshold voltage of T1. Here, ΔV is the change in the potential of the first gate signal, Cz1 ​​is the capacitance value of C1, and CNC is the total capacitance of NC.

[0273] In the third reset phase t6, RSTH provides a low voltage signal, T9 and T10 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O1 to clear the residual charge on the anode of O1, and I3 provides a third initial voltage Vinit3 to N2 to improve the hysteresis phenomenon of T0;

[0274] In the light-emitting stage t5, EM provides a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0275] like Figure 11A As shown, in Figure 6A Based on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1; the first control circuit includes a second transistor T2, and the second control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1;

[0276] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0277] The gate of the first transistor T1 is electrically connected to the control node NC, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0278] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first gate driving terminal NGT;

[0279] The gate of the second transistor T2 is electrically connected to the second scan terminal SC2, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0280] The gate of the third transistor T3 is electrically connected to the second scanning terminal SC2, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the first gate driving terminal NGT;

[0281] The first initialization circuit includes a fourth transistor T4;

[0282] The gate of the fourth transistor T4 is electrically connected to the first scanning terminal SC1, the source of the fourth transistor is electrically connected to the first initial voltage terminal I1, and the drain of the fourth transistor T4 is electrically connected to the control node NC;

[0283] The data writing circuit includes a fifth transistor T5, and the second energy storage circuit includes a second capacitor C2;

[0284] The gate of the fifth transistor T5 is electrically connected to the second gate driving terminal PGT, the source of the fifth transistor T5 is electrically connected to the data line DL, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0285] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0286] The first light emitting control circuit includes a sixth transistor T6, and the second light emitting control circuit includes a seventh transistor T7;

[0287] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0288] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1;

[0289] The second initialization circuit includes an eighth transistor T8;

[0290] The gate of the eighth transistor T8 is electrically connected to the first reset terminal RSTP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the third node N3;

[0291] The third initialization circuit includes a ninth transistor T9;

[0292] The gate of the ninth transistor T9 is electrically connected to the second reset terminal RSTH, the source of the ninth transistor T9 is electrically connected to the second initial voltage terminal I2, the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0293] The fourth initialization circuit includes a tenth transistor T10;

[0294] A gate of the tenth transistor T10 is electrically connected to the second reset terminal RSTH, a source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and a drain of the tenth transistor T10 is electrically connected to the second node N2.

[0295] exist Figure 11AIn at least one embodiment of the pixel circuit shown, T1 is an n-type transistor, T0, T2, T3, T4, T5, T6, T7, T8, T9, and T10 are p-type transistors; T1 is an oxide TFT;

[0296] T1 is a transistor sensitive to threshold voltage.

[0297] like Figure 12 As shown, the present invention Figure 11A When at least one embodiment of the pixel circuit shown is in operation, a display cycle may include a first reset phase t0, a compensation phase t1, a second reset phase t4, a data writing phase t3, a third reset phase t6, and a light emitting phase t5, which are arranged in sequence;

[0298] In the first reset phase t0, NGT provides a high voltage signal, SC1 provides a low voltage signal, T4 is turned on, the first initial voltage Vinit1 provided by I1 is written into N1, and C2 maintains the potential of N1;

[0299] In the compensation phase t1, NGT provides a high voltage signal, SC1 provides a high voltage signal, SC2 provides a low voltage signal, T2 and T3 are turned on, and the high voltage signal provided by NGT passes through T3, T1, and T2, pulling the potential of NC high. When the potential of NC is Vngt + Vth1, T1 is turned off and C1 maintains the potential of NC. Vngt is the potential of the first gate drive signal provided by NGT, and Vth is the threshold voltage of T1.

[0300] In the second reset phase t4, SC1 and SC2 provide high voltage signals, RSTP provides a low voltage signal, T8 is turned on, I1 provides the first initial voltage Vinit1 to N3, T1 is turned on, and reset is performed by setting Vinit1 to the potential of N1;

[0301] In the data writing phase t3, PGT provides a low voltage signal, T5 is turned on, DL provides the data voltage Vdata to N2, and T1 is turned on;

[0302] At the beginning of the data writing phase t3, T0 is turned on, and C2 is charged through Vdata, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off.

[0303] After the data writing phase t3, when the potential of the first gate drive signal provided by NGT drops, the potential of NC is pulled down by C1. The potential of NC is equal to Vngt + Vth1 + ΔV × C1z / CNC. The potential of NC always includes Vth1. Therefore, the on-state of T1 is not affected by the threshold voltage of T1, achieving the purpose of compensating the threshold voltage of T1. Here, ΔV is the change in the potential of the first gate signal, Cz1 ​​is the capacitance value of C1, and CNC is the total capacitance of NC.

[0304] In the third reset phase t6, RSTH provides a low voltage signal, T10 and T9 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O1 to clear the residual charge on the anode of O1; I3 provides a third initial voltage Vinit3 to N2 to improve the hysteresis phenomenon of T0;

[0305] In the light-emitting stage t5, EM provides a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0306] like Figure 11B As shown, in Figure 7B Based on at least one embodiment of the pixel circuit shown, the driving circuit includes a driving transistor T0, the compensation control circuit includes a first transistor T1, the first energy storage circuit includes a first capacitor C1; the first control circuit includes a second transistor T2, and the second control circuit includes a third transistor T3; the light-emitting element is an organic light-emitting diode O1;

[0307] The gate of the driving transistor T0 is electrically connected to the first node N1, the source of the driving transistor T0 is electrically connected to the second node N2, and the drain of the driving transistor T0 is electrically connected to the third node N3;

[0308] The gate of the first transistor T1 is electrically connected to the control node NC, the source of the first transistor T1 is electrically connected to the first node N1, and the drain of the first transistor T1 is electrically connected to the third node N3;

[0309] A first end of the first capacitor C1 is electrically connected to the control node NC, and a second end of the first capacitor C1 is electrically connected to the first gate driving terminal NGT;

[0310] The gate of the second transistor T2 is electrically connected to the first scan terminal SC1, the source of the second transistor T2 is electrically connected to the first node N1, and the drain of the second transistor T2 is electrically connected to the control node NC;

[0311] The gate of the third transistor T3 is electrically connected to the first scanning terminal SC1, the source of the third transistor T3 is electrically connected to the third node N3, and the drain of the third transistor T3 is electrically connected to the first gate driving terminal NGT;

[0312] The data writing circuit includes a fifth transistor T5, and the second energy storage circuit includes a second capacitor C2;

[0313] The gate of the fifth transistor T5 is electrically connected to the second gate driving terminal PGT, the source of the fifth transistor T5 is electrically connected to the data line DL, and the drain of the fifth transistor T5 is electrically connected to the second node N2;

[0314] A first end of the second capacitor C2 is electrically connected to the first node N1, and a second end of the second capacitor C2 is electrically connected to the power supply voltage terminal VDD;

[0315] The first light emitting control circuit includes a sixth transistor T6, and the second light emitting control circuit includes a seventh transistor T7;

[0316] The gate of the sixth transistor T6 is electrically connected to the light emitting control terminal EM, the source of the sixth transistor T6 is electrically connected to the power supply voltage terminal VDD, and the drain of the sixth transistor T6 is electrically connected to the second node N2;

[0317] The gate of the seventh transistor T7 is electrically connected to the light emitting control terminal EM, the source of the seventh transistor T7 is electrically connected to the third node N3, and the drain of the seventh transistor T7 is electrically connected to the anode of the organic light emitting diode O1;

[0318] The second initialization circuit includes an eighth transistor T8;

[0319] The gate of the eighth transistor T8 is electrically connected to the first reset terminal RSTP, the source of the eighth transistor T8 is electrically connected to the first initial voltage terminal I1, and the drain of the eighth transistor T8 is electrically connected to the first node N1;

[0320] The third initialization circuit includes a ninth transistor T9;

[0321] The gate of the ninth transistor T9 is electrically connected to the second reset terminal RSTH, the source of the ninth transistor T9 is electrically connected to the second initial voltage terminal I2, the drain of the ninth transistor T9 is electrically connected to the anode of the organic light emitting diode O1; the cathode of O1 is electrically connected to the low voltage terminal VSS;

[0322] The fourth initialization circuit includes a tenth transistor T10;

[0323] The gate of the tenth transistor T10 is electrically connected to the second reset terminal RSTH, the source of the tenth transistor T10 is electrically connected to the third initial voltage terminal I3, and the drain of the tenth transistor T10 is electrically connected to the second node N2;

[0324] The third energy storage circuit includes a third capacitor C3, the third control circuit includes an eleventh transistor T11, and the fourth control circuit includes a twelfth transistor T12;

[0325] A first end of the third capacitor is electrically connected to the intermediate node NZ, and a second end of the third capacitor is electrically connected to the first reset terminal RSTP;

[0326] The gate of the eleventh transistor is electrically connected to the first scanning terminal SC1, the source of the eleventh transistor T11 is electrically connected to the first initial voltage terminal I1, and the drain of the eleventh transistor T11 is electrically connected to the intermediate node NZ;

[0327] A gate of the twelfth transistor T12 is electrically connected to the first scan terminal SC1 , a source of the twelfth transistor T12 is electrically connected to the first node N1 , and a drain of the twelfth transistor T12 is electrically connected to the first reset terminal RSTP.

[0328] exist Figure 11B In at least one embodiment of the pixel circuit shown, T1 and T8 are n-type transistors, and all transistors except T1 and T8 are p-type transistors; T1 and T8 are oxide transistors.

[0329] like Figure 8B As shown, the present invention Figure 11B At least one embodiment of the pixel circuit shown is in operation.

[0330] The display cycle may include a compensation phase t1, a first reset phase t2, a data writing phase t3, a second reset phase t4 and a light emitting phase t5 which are arranged in sequence;

[0331] In the compensation phase t1, NGT provides a high voltage signal, SC1 provides a low voltage signal, T2 and T3 are turned on, and the high voltage signal provided by NGT passes through T3, T1 and T2 to pull up the potential of NC. When the potential of NC is Vngt+Vth1, T1 is turned off and C1 maintains the potential of NC to enable threshold voltage compensation for T1; wherein Vngt is the voltage value of the voltage signal provided by NGT, and Vth1 is the threshold voltage of T1; T11 and T12 are turned on, and the high voltage provided by NGT passes through T12, T8 and T11 to pull up the potential of NZ; when the potential of NZ is Vrstp+Vth8, T8 is turned off and C3 maintains the potential of NZ to enable threshold voltage compensation for T8, wherein Vrstp is the voltage value of the voltage signal provided by RSTP, and Vth8 is the threshold voltage of T8;

[0332] In the first reset phase t2, NGT provides a high voltage signal, SC1 provides a high voltage signal, RSTP provides a high voltage signal, T8 is turned on, Vinit1 is written to N1, and the potential of N1 is reset;

[0333] In the data writing phase t3, NGT provides a high voltage signal, PGT provides a low voltage signal, T5 is turned on, DL provides the data voltage Vdata to N2, and T1 is turned on;

[0334] At the beginning of the data writing phase t3, T0 is turned on, Vdata charges C2 through T5, T0 and T1, changing the potential of N1 until the potential of N1 becomes Vdata+Vth, where Vth is the threshold voltage of T0, and T0 is turned off;

[0335] After the data writing phase t3, when the potential of the first gate drive signal provided by NGT drops, the potential of NC is pulled down by C1. The potential of NC is equal to Vngt + Vth1 + ΔV × C1z / CNC. The potential of NC always includes Vth1. Therefore, the on-state of T1 is not affected by the threshold voltage of T1, achieving the purpose of compensating the threshold voltage of T1. Here, ΔV is the change in the potential of the first gate signal, Cz1 ​​is the capacitance value of C1, and CNC is the total capacitance of NC.

[0336] In the second reset phase t4, RSTH provides a low voltage signal, T9 and T10 are turned on, I2 provides a second initial voltage Vinit2 to the anode of O1 to clear the residual charge on the anode of O1, and I3 provides a third initial voltage Vinit3 to N2 to improve the hysteresis phenomenon of T0;

[0337] In the light-emitting stage t5, EM provides a low voltage signal, T6 and T7 are turned on, and T0 drives O1 to emit light.

[0338] The display device according to the embodiment of the present invention includes the above-mentioned pixel circuit.

[0339] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A pixel circuit, characterized in that: It includes a driving circuit, a compensation control circuit, a first energy storage circuit, a first control circuit and a second control circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node, and the driving circuit is configured to generate a driving current under the control of the potential of the first node; The compensation control circuit is electrically connected to the control node, the first node and the third node respectively, and is used to control the communication between the first node and the third node under the control of the potential of the control node; A first end of the first energy storage circuit is electrically connected to the control node, a second end of the first energy storage circuit is electrically connected to the first gate driving end, and the first energy storage circuit is used to store electrical energy; The first control circuit is electrically connected to the first control terminal, the first node and the control node respectively, and is used to control the communication between the first node and the control node under the control of a first control signal provided by the first control terminal; The second control circuit is electrically connected to the second control terminal, the third node and the first gate driving terminal respectively, and is used to control the connection between the third node and the first gate driving terminal under the control of a second control signal provided by the second control terminal.

2. The pixel circuit according to claim 1, wherein: The first control end and the second control end are both first scanning ends.

3. The pixel circuit according to claim 1, wherein: The first control end is a first scanning end, and the second control end is a second scanning end.

4. The pixel circuit according to claim 1, wherein: Also included is a first initialization circuit; The first initialization circuit is electrically connected to the first scanning terminal, the first initial voltage terminal, and the control node, respectively, and is configured to write the first initial voltage provided by the first initial voltage terminal into the control node under the control of the first scanning signal provided by the first scanning terminal; The first control end and the second control end are second scanning ends.

5. The pixel circuit according to any one of claims 1 to 4, wherein: The transistors included in the compensation control circuit are oxide transistors, and the transistors included in the first control circuit and the transistors included in the second control circuit are low-temperature polysilicon transistors.

6. The pixel circuit according to any one of claims 1 to 4, wherein: Also includes a data writing circuit and a second energy storage circuit; The data writing circuit is electrically connected to the second gate driving terminal, the data line and the second node respectively, and is used to write the data voltage provided by the data line into the second node under the control of the second gate driving signal provided by the second gate driving terminal; The second energy storage circuit is electrically connected to the first node and is configured to maintain the potential of the first node.

7. The pixel circuit according to any one of claims 1 to 4, wherein: Also includes a light emitting element, a first light emitting control circuit and a second light emitting control circuit; The first light emitting control circuit is electrically connected to the light emitting control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection between the power supply voltage terminal and the second node under the control of the light emitting control signal provided by the light emitting control terminal; The second light emitting control circuit is electrically connected to the light emitting control terminal, the third node, and the first electrode of the light emitting element, respectively, and is used to control the connection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal; The second electrode of the light emitting element is electrically connected to the first voltage end.

8. The pixel circuit according to claim 7, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the first reset terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first reset control signal provided by the first reset terminal.

9. The pixel circuit according to claim 7, wherein: Also comprising a second initialization circuit; The second initialization circuit is electrically connected to the first reset terminal, the first initial voltage terminal and the first node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the first node under the control of a first reset control signal provided by the first reset terminal.

10. The pixel circuit according to claim 7, wherein: Also included is a third initialization circuit; The third initialization circuit is electrically connected to the second reset terminal, the second initial voltage terminal and the first electrode of the light-emitting element respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second reset control signal provided by the second reset terminal.

11. The pixel circuit according to claim 7, wherein: Also comprising a fourth initialization circuit; The fourth initialization circuit is electrically connected to the second reset terminal, the third initial voltage terminal and the second node respectively, and is used to write the third initial voltage provided by the third initial voltage terminal into the second node under the control of the second reset control signal provided by the second reset terminal.

12. The pixel circuit according to claim 9, wherein: Also includes a third energy storage circuit, a third control circuit and a fourth control circuit; The first end of the third energy storage circuit is electrically connected to the intermediate node, the second end of the third energy storage circuit is electrically connected to the first reset end, and the third energy storage circuit is used to store electrical energy; The third control circuit is electrically connected to the first control terminal, the first initial voltage terminal and the intermediate node respectively, and is used to control the connection between the first initial voltage terminal and the intermediate node under the control of the first control signal; The fourth control circuit is electrically connected to the second control terminal, the first node and the first reset terminal respectively, and is used to control the first node to be connected to the first reset terminal under the control of the second control signal.

13. The pixel circuit according to claim 1, wherein: The driving circuit includes a driving transistor, the compensation control circuit includes a first transistor, the first energy storage circuit includes a first capacitor; the first control circuit includes a second transistor, and the second control circuit includes a third transistor; The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node; The gate of the first transistor is electrically connected to the control node, the first electrode of the first transistor is electrically connected to the first node, and the second electrode of the first transistor is electrically connected to the third node; A first end of the first capacitor is electrically connected to the control node, and a second end of the first capacitor is electrically connected to the first gate driving end; The gate of the second transistor is electrically connected to the first control terminal, the first electrode of the second transistor is electrically connected to the first node, and the second electrode of the second transistor is electrically connected to the control node; The gate of the third transistor is electrically connected to the second control terminal, the first electrode of the third transistor is electrically connected to the third node, and the second electrode of the third transistor is electrically connected to the first gate driving terminal.

14. The pixel circuit according to claim 4, wherein: The first initialization circuit includes a fourth transistor; A gate of the fourth transistor is electrically connected to the first scanning end, a first electrode of the fourth transistor is electrically connected to the first initial voltage end, and a second electrode of the fourth transistor is electrically connected to the control node.

15. The pixel circuit according to claim 6, wherein: The data writing circuit includes a fifth transistor, and the second energy storage circuit includes a second capacitor; The gate of the fifth transistor is electrically connected to the second gate driving terminal, the first electrode of the fifth transistor is electrically connected to the data line, and the second electrode of the fifth transistor is electrically connected to the second node; A first end of the second capacitor is electrically connected to the first node, and a second end of the second capacitor is electrically connected to a DC voltage end.

16. The pixel circuit according to claim 7, wherein: The first light emitting control circuit includes a sixth transistor, and the second light emitting control circuit includes a seventh transistor; The gate of the sixth transistor is electrically connected to the light emitting control terminal, the first electrode of the sixth transistor is electrically connected to the power supply voltage terminal, and the second electrode of the sixth transistor is electrically connected to the second node; The gate of the seventh transistor is electrically connected to the light emitting control terminal, the first electrode of the seventh transistor is electrically connected to the third node, and the second electrode of the seventh transistor is electrically connected to the first electrode of the light emitting element.

17. The pixel circuit according to claim 8, wherein: The second initialization circuit includes an eighth transistor; A gate of the eighth transistor is electrically connected to the first reset terminal, a first electrode of the eighth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the third node.

18. The pixel circuit according to claim 9, wherein: The second initialization circuit includes an eighth transistor; A gate of the eighth transistor is electrically connected to the first reset terminal, a first electrode of the eighth transistor is electrically connected to the first initial voltage terminal, and a second electrode of the eighth transistor is electrically connected to the first node.

19. The pixel circuit according to claim 10, wherein: The third initialization circuit includes a ninth transistor; The gate of the ninth transistor is electrically connected to the second reset terminal, the first electrode of the ninth transistor is electrically connected to the second initial voltage terminal, and the second electrode of the ninth transistor is electrically connected to the first electrode of the light emitting element.

20. The pixel circuit according to claim 11, wherein: The fourth initialization circuit includes a tenth transistor; A gate of the tenth transistor is electrically connected to the second reset terminal, a first electrode of the tenth transistor is electrically connected to the third initial voltage terminal, and a second electrode of the tenth transistor is electrically connected to the second node.

21. The pixel circuit according to claim 12, wherein: The third energy storage circuit includes a third capacitor, the third control circuit includes an eleventh transistor, and the fourth control circuit includes a twelfth transistor; A first end of the third capacitor is electrically connected to the intermediate node, and a second end of the third capacitor is electrically connected to the first reset end; The gate of the eleventh transistor is electrically connected to the first control terminal, the first electrode of the eleventh transistor is electrically connected to the first initial voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the intermediate node; The gate of the twelfth transistor is electrically connected to the second control terminal, the first electrode of the twelfth transistor is electrically connected to the first node, and the second electrode of the twelfth transistor is electrically connected to the first reset terminal.

22. A display device, characterized in that: The method comprises a pixel circuit according to any one of claims 1 to 21.

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