Capacitive MEMS Microphone Based on Charge-Controlled Structure

Abstract

This invention discloses a capacitive MEMS microphone based on a charge-controlled structure, primarily addressing the problem of decreased microphone sensitivity caused by the reduction in the size of the diaphragm and backplate in traditional capacitive MEMS microphones. From bottom to top, it includes a silicon substrate, a first insulating layer, a diaphragm layer, a second insulating layer, a backplate, a acoustic cavity between the diaphragm layer and the backplate, an acoustic aperture on the backplate, and a hollow cylindrical back cavity inside the silicon substrate. The diaphragm layer comprises three layers: a second diaphragm layer embedded within the first diaphragm layer and flush with its upper surface; and a third diaphragm layer located on the common upper surface of the first and second diaphragm layers, forming an integrated charge-controlled structure for the capacitive MEMS microphone. This invention, by embedding a piezoelectric thin film inside the diaphragm of a traditional capacitive MEMS microphone, can control the amount of charge on the microphone diaphragm surface, ultimately improving the sensitivity of the capacitive MEMS microphone, which can be used for sound pickup in hearing aids and mobile electronic smart devices.

Description

Technical Field

[0001] This invention belongs to the field of sensor technology, specifically relating to a capacitive microelectromechanical system (MEMS) microphone that can be used for sound recording in smart devices such as hearing aids and mobile electronics. Technical Background

[0002] Currently, capacitive MEMS microphones play an important role in mobile intelligent devices such as hearing aids, consumer electronics, and autonomous driving due to their superior performance and technical advantages, including small size, high sensitivity, high reliability, mass production capability, and ease of integration and intelligent implementation.

[0003] Traditional condenser MEMS microphone structures, such as Figure 1 As shown, it includes a substrate structure with a back cavity, and a diaphragm and backplate structure located on the substrate. The diaphragm and backplate form a miniature capacitor structure. When the diaphragm is subjected to external sound pressure, it vibrates towards and away from the backplate, causing a change in the capacitance between the diaphragm and the backplate, thereby achieving sound-to-electric conversion. However, when the bias voltage remains constant, in traditional capacitive MEMS microphones, as the size of the microphone diaphragm and backplate decreases, the amount of charge on the diaphragm surface decreases during stable microphone operation, ultimately leading to a decrease in microphone sensitivity.

[0004] In their paper "Anovel MEMS capacitive microphone using spring-type diaphragm" published in the journal Microsystem Technologies, Sedighe Babaei Sedaghat proposed a capacitive MEMS microphone with a spring-supported diaphragm structure resembling a frog's arm. The diaphragm structure of this microphone is supported and fixed at its edge by four springs similar to frog arms. Compared with traditional capacitive MEMS microphones, the microphone's sensitivity can be effectively improved by simply manufacturing four spring support structures. Although this microphone can improve the sensitivity, the diaphragm is prone to sticking to the back plate under high bias voltage, which can lead to device failure and low reliability.

[0005] In his paper "Design of a Poly Silicon MEMS Microphone for High Signal-to-Noise Ratio" presented at the 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), Alfons Dehé proposed a corrugated diaphragm capacitive MEMS microphone. This microphone improves the vibration deflection of the diaphragm by etching multiple grooves on the diaphragm, thereby increasing the microphone's sensitivity. However, the corrugated diaphragm MEMS microphone still suffers from the problem of decreased sensitivity as the size of the diaphragm and backplate decreases. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and propose a capacitive MEMS microphone based on a charge-controlled structure to improve the microphone's sensitivity and enhance its performance.

[0007] The key technology of this invention is: by embedding an aluminum nitride piezoelectric thin film inside the diaphragm, the polarization charge generated by the deformation of the piezoelectric thin film inside the diaphragm is used to regulate the amount of charge on the diaphragm surface, thereby compensating for the impact of the reduction in the amount of charge on the diaphragm surface caused by the reduction in the size of the microphone device on the microphone sensitivity. The implementation scheme includes the following:

[0008] 1. A capacitive MEMS microphone based on a charge-controlled structure, comprising a silicon substrate, a first insulating layer, a diaphragm layer, a second insulating layer, a back plate, a acoustic cavity, an acoustic aperture, and a back cavity, characterized in that:

[0009] The diaphragm layer consists of three layers: a first diaphragm layer is a circular film with radius R1 and thickness D1; ​​a second diaphragm layer is a circular piezoelectric film with radius R2 and thickness D2, embedded inside the first diaphragm layer and flush with its upper surface; and a third diaphragm layer is a circular film with radius R3 and thickness D3, located above the first and second diaphragm layers. Where R1 = R3 > R2, and D1 ≥ D3 > D2.

[0010] Furthermore, the first insulating layer is located on the silicon substrate; the second insulating layer is located at the upper edge of the third diaphragm layer.

[0011] Furthermore, the first diaphragm layer is located above the first insulating layer; the back plate is located above the second insulating layer and the acoustic cavity.

[0012] Furthermore, the acoustic cavity is located between the third diaphragm layer and the back plate, and its edge is a second insulating layer with the same height as the thickness of the second insulating layer.

[0013] Furthermore, the acoustic hole is located on the back plate, is cylindrical in shape, and has a radius r of 20–30 μm.

[0014] Furthermore, the depth of the back cavity is 302–504 μm, the width of its upper surface is smaller than that of the first diaphragm layer region in the horizontal direction, and the distance L between the upper surface boundary and the boundary of the first diaphragm layer in the horizontal direction is equal, 20 μm ≤ L ≤ 30 μm.

[0015] Furthermore, the silicon substrate is selected as a p-type (100) silicon wafer with a thickness of 300-500 μm; the first insulating layer has a thickness of 2-4 μm; and the second insulating layer has a thickness of 4-5 μm.

[0016] The acoustic cavity has a height of 4–5 μm; the radius of the back plate is the same as the radius R1 of the first diaphragm layer, and its thickness D4 ranges from 4–5 μm.

[0017] 2. A method for fabricating a capacitive MEMS microphone based on a charge-controlled structure, characterized by comprising the following steps:

[0018] A) A first insulating layer is formed by using thermal oxidation technology to fabricate a SiO2 insulating dielectric with a thickness of 2-4 μm on a silicon substrate;

[0019] B) Fabrication of a three-layer diaphragm:

[0020] B1) A mask is fabricated on the first insulating layer, and an amorphous silicon layer with radius R1 and thickness D1 is deposited on the first insulating layer using the mask. The amorphous silicon is crystallized into polycrystalline silicon by rapid thermal annealing, which serves as the first diaphragm layer. The value of R1 ranges from 400 to 600 μm, and the value of D1 ranges from 0.25 to 0.3 μm.

[0021] B2) Fabricate a mask on the first diaphragm layer, and use the mask to etch a groove with radius R2 and depth D2 at the center of the first diaphragm layer; deposit and fill a layer of aluminum nitride piezoelectric film in the groove of the first diaphragm layer as a second diaphragm layer, the thickness of which is the same as the depth of the groove etched in the first diaphragm layer, R2 ranges from 200 to R1-10 μm, and D2 ranges from 0.05 to 0.1 μm;

[0022] B3) A mask is fabricated on the common upper surface of the first and second diaphragm layers. Using this mask, a layer of amorphous silicon with a radius of R3 and a thickness of D3 is deposited on the common upper surface of the first and second diaphragm layers, so that it completely covers the first and second diaphragm layers. The amorphous silicon is crystallized into polycrystalline silicon through rapid thermal annealing, which serves as the third diaphragm layer. The value of R3 is consistent with that of R1, and the value of D3 ranges from 0.2 to 0.25 μm. The first, second, and third diaphragm layers together serve as the charge control structure of the MEMS microphone.

[0023] C) A silicon dioxide sacrificial layer is deposited on the third diaphragm layer and planarized to form a sacrificial layer with a thickness of 4 μm; then an amorphous silicon layer is deposited on the silicon dioxide sacrificial layer, and the amorphous silicon is crystallized into polycrystalline silicon by rapid thermal annealing. After planarization, a backplate with a thickness of D4 is formed, where D4 ranges from 4 to 5 μm.

[0024] D) A mask is fabricated on the backplane, and the mask is used to etch until the upper surface of the sacrificial layer is reached, forming several cylindrical acoustic holes with a radius of r, where the value of r ranges from 20 to 30 μm.

[0025] F) Using the several cylindrical acoustic holes formed in step D), the central sacrificial layer is etched away using a wet etching process to form an acoustic cavity, and the unetched sacrificial layer at the edge serves as the second insulating layer.

[0026] G) A mask is fabricated on the back of the silicon substrate. The back of the silicon substrate is etched using reactive ion etching process with the mask up to the lower surface of the first diaphragm layer to form a back cavity, thus completing the fabrication of the entire MEMS microphone.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] Firstly, because the present invention embeds a piezoelectric thin film inside the diaphragm layer, it can compensate for the reduced amount of charge on the diaphragm surface caused by the reduction in the size of the microphone diaphragm and backplate when the bias voltage of the MEMS microphone remains unchanged, thereby improving the sensitivity of the MEMS microphone.

[0029] Secondly, because the present invention adopts a three-layer integrated diaphragm structure with embedded piezoelectric film, it can generate a sensitive response to ultrasonic waves above 20kHz, thus broadening the flat frequency response range of MEMS microphones in the high-frequency range and making it suitable for the capture and sensing of ultrasonic waves. Attached Figure Description

[0030] Figure 1 This is a structural diagram of a traditional condenser MEMS microphone;

[0031] Figure 2 This is a structural diagram of the capacitive MEMS microphone provided in an embodiment of the present invention;

[0032] Figure 3 This is a process flow diagram of the fabrication of a capacitive MEMS microphone based on a charge compensation structure according to the present invention.

[0033] Figure 4 This is a simulation comparison of the frequency response of the present invention and a traditional capacitive MEMS microphone. Detailed Implementation

[0034] The present invention will be further described in detail below with reference to the embodiments and accompanying drawings.

[0035] Reference Figure 2 The present invention is a MEMS microphone based on a charge-controlled structure, comprising: a silicon substrate 1, a first insulating layer 2, a diaphragm layer 3, a second insulating layer 4, a sound cavity 5, a back plate 6, a sound hole 7, and a back cavity 8.

[0036] The silicon substrate 1 is selected as a p-type (100) silicon wafer with a thickness of 300-500 μm.

[0037] The first insulating layer 2 is located on the silicon substrate and has a thickness of 2 to 4 μm.

[0038] The diaphragm layer 3 is configured as three layers, namely the first diaphragm layer 31, the second diaphragm layer 32 and the third diaphragm layer 33.

[0039] The first diaphragm layer 31 is a circular film with a radius R1 of 400-600 μm and a thickness D1 of 0.25-0.3 μm;

[0040] The second diaphragm layer 32 is a circular piezoelectric film with a radius R2 of 200 to R1-10 μm and a thickness D2 of 0.05 to 0.1 μm. It is embedded inside the first diaphragm layer and is flush with the upper surface of the first diaphragm layer.

[0041] The third diaphragm layer is a circular membrane with a radius R3 of 400-600 μm and a thickness D3 of 0.2-0.25 μm, located above the first and second diaphragm layers.

[0042] The second insulating layer 4 is located at the upper edge of the third diaphragm layer 31, and its thickness ranges from 4 to 5 μm.

[0043] The acoustic cavity 5 is located between the third diaphragm layer 33 and the back plate 6, and its edge is the second insulating layer 4, the height of which is the same as the thickness of the second insulating layer 4.

[0044] The back plate 6 is located above the second insulating layer 4 and the acoustic cavity 5, and its thickness D5 is 4 to 5 μm.

[0045] The acoustic hole 7 is located on the back plate 6, and is cylindrical in shape with a radius r of 20-30 μm.

[0046] The back cavity 8 is located inside the silicon substrate and is formed by etching through the silicon substrate and the first insulating layer from the back side of the substrate. Its radius is 470-480 μm and its depth is 302-504 μm. The width of its upper surface is smaller than that of the first diaphragm layer region in the horizontal direction, and the distance L between the upper surface boundary and the boundary of the first diaphragm layer in the horizontal direction is equal, 20 μm ≤ L ≤ 30 μm.

[0047] Reference Figure 3 This invention provides the following three embodiments for fabricating a MEMS microphone based on a charge-controlled structure:

[0048] Example 1 uses a MEMS microphone with a silicon substrate thickness of 500 μm, a first insulating layer thickness of 4 μm, a first diaphragm layer radius of 500 μm and a thickness of 0.3 μm, a second diaphragm layer radius of 480 μm and a thickness of 0.1 μm, a third diaphragm layer radius of 500 μm and a thickness of 0.2 μm, a second insulating layer thickness of 5 μm, a acoustic cavity radius of 490 μm and a height of 5 μm, a backplate radius of 500 μm, a sound hole radius of 30 μm, and a back cavity radius of 480 μm and a depth of 504 μm.

[0049] Step 1: A 500μm thick p-type (100) silicon wafer is selected as the substrate and placed in a reactor. Using thermal oxidation technology at an O2 flow rate of 50 sccm, a pressure of 120 mT, and a temperature of 600℃, a 4μm thick SiO2 insulating dielectric layer is grown on the silicon substrate, forming the first insulating layer. Figure 3 a.

[0050] Step two: Fabricate the diaphragm layer on the first insulating layer.

[0051] First, a mask is fabricated on the first insulating layer. Using this mask, chemical vapor deposition is performed under the following conditions: reaction chamber temperature is 1200℃, SiCl4 flow rate in H2 is 6% (molar percentage), and film growth rate is 2.3 μm / min. Amorphous silicon with a radius of 500 μm and a thickness of 0.3 μm is deposited on the first insulating layer. Then, it is subjected to rapid thermal annealing at 850℃ for 3 hours to crystallize the amorphous silicon into polycrystalline silicon, forming the first diaphragm layer.

[0052] Next, a second mask was fabricated on the first diaphragm layer. Using this mask, reactive ion etching was employed under conditions of Cl2 flow rate of 18 sccm, pressure of 12 mT, and power of 120 W to etch a groove with a radius of 480 μm and a depth of 0.1 μm at the center of the first diaphragm layer. Figure 3 b.

[0053] Next, using atomic layer deposition (ALD) technology with TMA and NH3 as reaction sources, N2 as the carrier gas, a carrier gas flow rate of 300 sccm, a substrate temperature of 300°C, and a gas pressure of 800 Pa, aluminum nitride piezoelectric material was deposited in the grooves of the first diaphragm layer until the aluminum nitride piezoelectric material completely filled the entire groove. Planarization was then performed to form a second diaphragm layer with a radius of 480 μm, a thickness of 0.1 μm, and flush with the upper surface of the first diaphragm layer. Figure 3 c.

[0054] Next, a third mask was fabricated on the common upper surface of the first and second diaphragm layers. Using this mask, chemical vapor deposition was employed at a reaction chamber temperature of 1200℃, a SiCl4 flow rate in H2 of 6% molar percentage, and a film growth rate of 2.3 μm / min to deposit an amorphous silicon layer with a radius of 500 μm and a thickness of 0.2 μm on the common upper surface of the first and second diaphragm layers. Then, rapid thermal annealing at 850℃ for 3 hours was used to crystallize the amorphous silicon into polycrystalline silicon, forming the third diaphragm layer. Figure 3 d. At this point, the first, second, and third diaphragm layers as a whole have been fabricated as the charge control structure of the MEMS microphone.

[0055] Step three: A fourth mask is fabricated on the third diaphragm layer. Using this mask, plasma-enhanced chemical vapor deposition (PECVD) is employed under the following conditions: N2O flow rate of 950 sccm, SiH4 flow rate of 300 sccm, temperature of 250℃, RF power of 35W, and pressure of 1300mT. This allows for the deposition of a 5μm thick SiO2 sacrificial layer with a radius of 500μm on the third diaphragm layer. Figure 3 e.

[0056] Step four: A fifth mask is fabricated on the sacrificial layer. Using this mask, chemical vapor deposition is performed at a reaction chamber temperature of 1200℃, a SiCl4 flow rate in H2 with a molar percentage of 6%, and a film growth rate of 2.3 μm / min to deposit an amorphous silicon layer with a radius of 500 μm and a thickness of 5 μm. Rapid thermal annealing at 850℃ for 3 hours is then used to crystallize the amorphous silicon into polycrystalline silicon, forming the backplane. Figure 3 f.

[0057] Step 5: A sixth mask is fabricated on the backplane. Using this mask, reactive ion etching is employed under the conditions of a Cl2 flow rate of 30 sccm, an O2 flow rate of 3 sccm, a pressure of 30 mT, and a bias voltage of 120 V to etch the backplane until the upper surface of the sacrificial layer is reached, forming several acoustic holes with a radius of 30 μm. Their function is to release the pressure damping of the air in the acoustic cavity, such as... Figure 3 g.

[0058] Step six: Using a wet etching process at a tetramethylammonium hydroxide (TMAH) solution concentration of 25% and a temperature of 90°C, the central sacrificial layer is etched away to form an acoustic cavity with a radius of 490 μm and a height of 5 μm. The unetched sacrificial layer at the edges forms the second insulating layer. Figure 3 h.

[0059] Step seven: A mask is fabricated for the seventh time on the back of the silicon substrate. Using this mask, reactive ion etching is employed under the conditions of a Cl2 flow rate of 30 sccm, an O2 flow rate of 4 sccm, a pressure of 40 mT, and a bias voltage of 130 V to etch the back of the silicon substrate. The etching radius is 480 μm and the depth is 504 μm, etching down to the lower surface of the first diaphragm layer to form the back cavity, thus completing the fabrication of the entire capacitive MEMS microphone. Figure 3 i.

[0060] Example 2: A MEMS microphone was fabricated with a silicon substrate thickness of 300 μm, a first insulating layer thickness of 2 μm, a first diaphragm layer radius of 400 μm and a thickness of 0.25 μm, a second diaphragm layer radius of 200 μm and a thickness of 0.05 μm, a third diaphragm layer radius of 400 μm and a thickness of 0.2 μm, a second insulating layer thickness of 4 μm, a acoustic cavity radius of 390 μm and a height of 4 μm, a backplate radius of 400 μm, a sound hole radius of 20 μm, and a back cavity radius of 380 μm and a depth of 302 μm.

[0061] Step 1: A 300μm thick p-type (100) silicon wafer is selected as the substrate and placed in a reactor. A 2μm thick SiO2 insulating dielectric layer is grown on the silicon substrate using thermal oxidation technology to form the first insulating layer, as shown below. Figure 3 a.

[0062] The process conditions for the thermal oxidation technology are: O2 flow rate of 30 sccm, pressure of 80 mT, and temperature of 550℃.

[0063] Step 2: Fabricate a diaphragm layer on the first insulating layer.

[0064] 2.1) A mask is first fabricated on the first insulating layer. Using this mask, amorphous silicon with a radius of 400 μm and a thickness of 0.25 μm is deposited on the first insulating layer using chemical vapor deposition. Rapid thermal annealing at 850℃ for 3 hours is then used to crystallize the amorphous silicon into polycrystalline silicon, forming the first diaphragm layer. A second mask is fabricated on the first diaphragm layer. Using this mask, a groove with a radius of 200 μm and a depth of 0.05 μm is etched at the center of the first diaphragm layer using reactive ion etching. Figure 3 b;

[0065] The process conditions for the chemical vapor deposition technology are as follows: reaction chamber temperature is 1200℃, SiCl4 flow rate in H2 is 5% (molar percentage), and film growth rate is 2.2 μm / min.

[0066] The process conditions for the reactive ion etching technology are: Cl2 flow rate of 15 sccm, pressure of 10 mT, and power of 100 W.

[0067] 2.2) In the grooves of the first diaphragm layer, an aluminum nitride piezoelectric film is deposited using atomic layer deposition (ALD) with trimethylaluminum (TMA) and ammonia (NH3) as the reaction source until the aluminum nitride completely fills the entire groove. After planarization, a second diaphragm layer with a radius of 200 μm and a thickness of 0.05 μm is formed, flush with the upper surface of the first diaphragm layer. Figure 3 c);

[0068] The process conditions for the atomic layer deposition technology are as follows: TMA and NH3 are used as reaction sources, N2 is used as the carrier gas, the carrier gas flow rate is 200 sccm, the substrate temperature is 300℃, and the gas pressure is 700 Pa.

[0069] 2.3) A third mask is fabricated on the common surface of the first and second diaphragm layers. Using this mask, an amorphous silicon layer with a radius of 400 μm and a thickness of 0.25 μm is deposited on the common surface of the first and second diaphragm layers using chemical vapor deposition. Then, a rapid thermal annealing technique at 850℃ for 3 hours is used to crystallize the amorphous silicon into polycrystalline silicon, forming the third diaphragm layer. Figure 3 d. At this point, the overall diaphragm layer, consisting of the first, second, and third diaphragm layers, is complete, forming the charge-controlled structure.

[0070] The process conditions for the chemical vapor deposition technology are as follows: reaction chamber temperature is 1200℃, SiCl4 flow rate in H2 is 5% (molar percentage), and film growth rate is 2.2 μm / min.

[0071] Step 3: A fourth mask is fabricated on the third diaphragm layer. Using this mask, a SiO2 sacrificial layer with a radius of 400 μm and a thickness of 4 μm is deposited on the third diaphragm layer using plasma-enhanced chemical vapor deposition (PECVD). Figure 3 e.

[0072] The process conditions for the plasma-enhanced chemical vapor deposition technology are as follows: N2O flow rate of 850 sccm, SiH4 flow rate of 200 sccm, temperature of 250℃, RF power of 25W, and pressure of 1100mT.

[0073] Step 4: A fifth mask is fabricated on the sacrificial layer. Using this mask, an amorphous silicon layer with a radius of 400 μm and a thickness of 4 μm is deposited using chemical vapor deposition. Rapid thermal annealing at 850℃ for 3 hours is then used to crystallize the amorphous silicon into polycrystalline silicon, forming the backplane. Figure 3 f;

[0074] The process conditions for the chemical vapor deposition technology are as follows: reaction chamber temperature is 1200℃, SiCl4 flow rate in H2 is 5% (molar percentage), and film growth rate is 2.2 μm / min.

[0075] Step 5: A sixth mask is fabricated on the backplane. Reactive ion etching is used to etch the backplane down to the surface of the sacrificial layer, forming several acoustic holes with a radius of 20 μm. These holes are used to release the pressure damping of the air in the acoustic cavity. Figure 3 g;

[0076] The process conditions for the reactive ion etching technology are: Cl2 flow rate of 20 sccm, O2 flow rate of 2 sccm, pressure of 20 mT, and bias voltage of 100 V.

[0077] Step 6: Using a wet etching process, the center of the sacrificial layer is etched to form a acoustic cavity with a radius of 390 μm and a height of 4 μm. The unetched edges of the sacrificial layer form a second insulating layer. Figure 3 h.

[0078] The process conditions for the wet etching technology are: a tetramethylammonium hydroxide (TMAH) solution concentration of 20% and a temperature of 90°C.

[0079] Step 7: A seventh mask is fabricated on the back of the silicon substrate. Using this mask, reactive ion etching is employed to etch the back of the silicon substrate down to the lower surface of the first diaphragm layer, forming a back cavity with a radius of 380 μm and a depth of 302 μm. This back cavity serves as the channel for sound to enter the microphone, completing the fabrication of the entire condenser MEMS microphone. Figure 3 i;

[0080] The process conditions for the reactive ion etching technology are: Cl2 flow rate of 20 sccm, O2 flow rate of 2 sccm, pressure of 20 mT, and bias voltage of 100 V.

[0081] Example 3: A MEMS microphone was fabricated with a silicon substrate thickness of 450 μm, a first insulating layer thickness of 3 μm, a first diaphragm layer radius of 450 μm and a thickness of 0.3 μm, a second diaphragm layer radius of 400 μm and a thickness of 0.08 μm, a third diaphragm layer radius of 450 μm and a thickness of 0.2 μm, a second insulating layer thickness of 4.5 μm, a acoustic cavity radius of 440 μm and a height of 4.5 μm, a backplate radius of 450 μm, a sound hole radius of 25 μm, and a back cavity radius of 430 μm and a depth of 453 μm.

[0082] Step A, generate the first insulating layer, such as Figure 3 a.

[0083] A p-type (100) silicon wafer with a thickness of 450 μm was selected as the silicon substrate and placed in a reactor. The process conditions were set as follows: O2 flow rate of 30 sccm, pressure of 80 mT, and temperature of 600 °C. A layer of SiO2 insulating medium with a thickness of 3 μm was grown on the silicon substrate by thermal oxidation technology to form the first insulating layer.

[0084] Step B: Fabricate a diaphragm layer on the first insulating layer.

[0085] (B1) A mask is first fabricated on the first insulating layer. The reaction chamber temperature is set to 1200℃, the molar percentage of SiCl4 in H2 is 4%, and the film growth rate is 2.1μm / min. Using this mask, chemical vapor deposition is used to deposit amorphous silicon with a radius of 450μm and a thickness of 0.3μm on the first insulating layer. Then, rapid thermal annealing is performed at a temperature of 850℃ for 3 hours to crystallize the amorphous silicon into polycrystalline silicon, forming the first diaphragm layer.

[0086] (B2) A second mask was fabricated on the first diaphragm layer. The process conditions were set as follows: Cl2 flow rate of 12 sccm, pressure of 8 mT, and power of 80 W. Using this mask, reactive ion etching was employed to etch a groove with a radius of 400 μm and a depth of 0.08 μm at the center of the first diaphragm layer. Figure 3 b.

[0087] (B3) Under the following process conditions: TMA and NH3 as reaction sources, N2 as carrier gas, a carrier gas flow rate of 100 sccm, a substrate temperature of 300℃, and a gas pressure of 600 Pa, atomic layer deposition (ALD) is used to deposit aluminum nitride piezoelectric material in the grooves of the first diaphragm layer until the aluminum nitride piezoelectric material completely fills the entire groove. Planarization is then performed to form a second diaphragm layer with a radius of 400 μm, a thickness of 0.08 μm, and flush with the upper surface of the first diaphragm layer. Figure 3 c.

[0088] (B4) A third mask is fabricated on the common upper surface of the first and second diaphragm layers. The process conditions are set as follows: reaction chamber temperature 1200℃, SiCl4 flow rate in H2 molar percentage 4%, and film growth rate 2.1 μm / min. Using the mask, a layer of amorphous silicon with a radius of 500 μm and a thickness of 0.2 μm is deposited on the common upper surface of the first and second diaphragm layers via chemical vapor deposition. Then, a rapid thermal annealing technique at 850℃ for 3 hours is used to crystallize the amorphous silicon into polycrystalline silicon, forming the third diaphragm layer. Figure 3 d.

[0089] Thus, the first, second, and third diaphragm layers together constitute the charge control structure of a MEMS microphone.

[0090] Step C, deposit a sacrificial layer on the third diaphragm layer, such as Figure 3 e.

[0091] (C1) A mask was fabricated for the fourth time on the third diaphragm layer, and the process conditions were set as follows: N2O flow rate of 650 sccm, SiH4 flow rate of 100 sccm, temperature of 250℃, RF power of 15W, and pressure of 900mT.

[0092] (C2) Using this mask, plasma-enhanced chemical vapor deposition is used to deposit a SiO2 sacrificial layer with a radius of 450 μm and a thickness of 4.5 μm on the third diaphragm layer.

[0093] Step D: Fabricate a backplate on the sacrificial layer, such as... Figure 3 f.

[0094] (D1) A mask was fabricated for the fifth time on the sacrificial layer, and the reaction chamber temperature was set to 1200℃, the molar percentage of SiCl4 in H2 was 4%, and the film growth rate was 2.1 μm / min.

[0095] (D2) Using this mask, a layer of amorphous silicon with a radius of 450 μm and a thickness of 4.5 μm was deposited on the sacrificial layer using chemical vapor deposition.

[0096] (D3) Set the temperature to 850℃ and the time to 3 hours for rapid thermal annealing of amorphous silicon, causing it to crystallize into polycrystalline silicon to form a backplate, such as... Figure 3 f.

[0097] Step E: Etch acoustic holes on the backplate, such as... Figure 3 g.

[0098] (E1) A sixth mask was fabricated on the backplane, with the following process conditions: Cl2 flow rate of 10 sccm, O2 flow rate of 1 sccm, pressure of 10 mT, and bias voltage of 80 V.

[0099] (E2) Using this mask, reactive ion etching is employed to etch the backplate up to the upper surface of the sacrificial layer, forming several circular acoustic holes with a radius of 25 μm to release the pressure damping of the air in the acoustic cavity, such as... Figure 3 g.

[0100] Step F: Fabricate the acoustic cavity and the second insulating layer.

[0101] The process conditions were set at a tetramethylammonium hydroxide (TMAH) solution concentration of 15% and a temperature of 90°C. A wet etching process was used to etch the central sacrificial layer, forming a acoustic cavity with a radius of 440 μm and a height of 4.5 μm. The unetched edges of the sacrificial layer were used to form a second insulating layer. Figure 3 h.

[0102] Step G: Etch the back side of the silicon substrate to create a back cavity, such as... Figure 3 i.

[0103] (G1) A mask is fabricated for the seventh time on the back of the silicon substrate, with the following process conditions: Cl2 flow rate of 15 sccm, O2 flow rate of 1.5 sccm, pressure of 15 mT, and bias voltage of 90 V.

[0104] (G2) Using this mask, reactive ion etching technology is used to etch a silicon substrate with a radius of 430μm and a depth of 453μm to form a back cavity, which serves as the channel for sound to enter the microphone, thus completing the fabrication of the entire condenser MEMS microphone.

[0105] The effects of this invention can be further illustrated by the following simulation.

[0106] I. Simulation Parameters

[0107] Assuming that both the conventional capacitive MEMS microphone and the microphone of this invention use the same dimensions except for the diaphragm layer, the thickness of the silicon substrate is 400μm, the thickness of the first insulating layer is 2μm, the radius of the acoustic cavity is 490μm and the thickness is 4μm, the thickness of the second insulating layer is 4μm, the radius of the back plate is 500μm and the thickness is 4μm, the radius of the sound hole is 30μm, and the radius of the back cavity is 480μm and the depth is 402μm.

[0108] Traditional capacitive MEMS microphones have a single-layer diaphragm structure. The microphone of this invention has a three-layer diaphragm structure, comprising a first diaphragm layer, a second diaphragm layer, and a third diaphragm layer. The first diaphragm layer has a radius of 500 μm and a thickness of 0.3 μm, the second diaphragm layer has a radius of 480 μm and a thickness of 0.1 μm, and the third diaphragm layer has a radius of 500 μm and a thickness of 2 μm.

[0109] II. Simulation Content

[0110] Simulations were performed on the spectral distribution of the sensitivity of a traditional capacitive MEMS microphone and the microphone of this invention under the same bias voltage. The results are as follows: Figure 4 .

[0111] Combination Figure 4 The distribution of open-circuit sensitivity in the spectrum clearly shows that the three-layer integrated diaphragm structure with embedded piezoelectric thin film in this invention can significantly improve the open-circuit sensitivity of the microphone. Therefore, the performance of the microphone of this invention is far superior to that of traditional condenser MEMS microphones. In addition, the high-frequency response of the microphone of this invention is also flatter than that of traditional microphones, indicating that the microphone of this invention can be used for the capture and sensing of ultrasonic waves.

[0112] The above description is merely a specific example of the present invention and does not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principle of the present invention, may make various modifications and changes in form and details without departing from the principle and structure of the present invention. For example, the charge control structure can be configured as four or even more layers in addition to the three-layer structure set in this example, and the piezoelectric film can be configured as two or even more layers in addition to the one-layer structure set in this example. However, these modifications and changes based on the concept of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A method for fabricating a capacitive MEMS microphone based on a charge-controlled structure, characterized in that, Includes the following steps: A) A first insulating layer is formed by using thermal oxidation technology to fabricate a SiO2 insulating dielectric with a thickness of 2-4 μm on a silicon substrate; B) Fabrication of a three-layer diaphragm: B1) A mask is fabricated on the first insulating layer. Using the mask, a layer of amorphous silicon with radius R1 and thickness D1 is deposited on the first insulating layer by chemical vapor deposition. The amorphous silicon is crystallized into polycrystalline silicon by rapid thermal annealing and used as the first diaphragm layer. The value of R1 ranges from 400 to 600 μm, and the value of D1 ranges from 0.25 to 0.3 μm. B2) A mask is fabricated on the first diaphragm layer. Using this mask, reactive ion etching is employed to etch a groove with a radius of R2 and a depth of D2 in the first diaphragm layer. The mask is then used in the groove of the first diaphragm layer to deposit and fill a layer of aluminum nitride piezoelectric film as the second diaphragm layer. The thickness of the second diaphragm layer is the same as the depth of the groove formed by etching in the first diaphragm layer. The value of R2 ranges from 200 to R1-10 μm, and the value of D2 ranges from 0.05 to 0.1 μm. B3) A mask is fabricated on the common upper surface of the first and second diaphragm layers. Using this mask, a layer of amorphous silicon with a radius of R3 and a thickness of D3 is deposited on the common upper surface of the first and second diaphragm layers using chemical vapor deposition technology, so that it completely covers the first and second diaphragm layers. The amorphous silicon is then crystallized into polycrystalline silicon through rapid thermal annealing, which serves as the third diaphragm layer. The value of R3 is consistent with that of R1, and the value of D3 ranges from 0.2 to 0.25 μm. The first, second, and third diaphragm layers together serve as the charge control structure of the MEMS microphone. C) A silicon dioxide sacrificial layer with a thickness D4 ranging from 4 to 5 μm is deposited on the third diaphragm layer using plasma-enhanced chemical vapor deposition (PECVD) and then planarized. An amorphous silicon layer is then deposited on the silicon dioxide sacrificial layer and rapidly thermally annealed to crystallize the amorphous silicon into polycrystalline silicon. After planarization, a backplate with a thickness D5 ranging from 4 to 5 μm is formed. D) A mask is fabricated on the backplane, and chemical vapor deposition is used to etch the mask until the upper surface of the sacrificial layer is reached, forming several cylindrical acoustic holes with a radius of r, where the value of r ranges from 20 to 30 μm. F) Using the several cylindrical acoustic holes formed in step D), the central sacrificial layer is etched away using a wet etching process to form an acoustic cavity, and the unetched sacrificial layer at the edge serves as the second insulating layer. G) A mask is fabricated on the back of the silicon substrate. Using this mask, reactive ion etching is used to etch the back of the silicon substrate down to the lower surface of the first diaphragm layer to form a back cavity, which serves as the channel for sound to enter the microphone, thus completing the fabrication of the entire MEMS microphone.

2. The method according to claim 1, characterized in that: The chemical vapor deposition technique used in step B1) has the following process conditions: reaction chamber temperature is 1200℃, SiCl4 flow rate in H2 is 4-6% molar percentage, and film growth rate is 2.1-2.3 μm / min. The reactive ion etching technology used in step B2) has the following process conditions: Cl2 flow rate of 12-18 sccm, pressure of 8-12 mT, and power of 80-120 W. The atomic layer deposition technology used in step B2) has the following process conditions: TMA and NH3 are used as reaction sources, N2 is used as the carrier gas, the carrier gas flow rate is 100-300 sccm, the substrate temperature is 300℃, and the gas pressure is 700-900 Pa. The rapid thermal annealing process in step B3) is carried out at a temperature of 850°C for 3 hours.

3. The method according to claim 1, characterized in that: The thermal oxidation technology in step A) has the following process conditions: O2 flow rate of 30-50 sccm, pressure of 80-120 mT, and temperature of 550℃. Step C) employs plasma-enhanced chemical vapor deposition (PECVD) with the following process conditions: N2O flow rate of 650–950 sccm, SiH4 flow rate of 100–300 sccm, temperature of 250°C, RF power of 15–35 W, and pressure of 900–1300 mT. The wet etching process conditions for step F) are as follows: the concentration of tetramethylammonium hydroxide (TMAH) solution is 15-25%, and the temperature is 90°C.

4. A capacitive MEMS microphone prepared according to the method of claim 1, comprising a silicon substrate (1), a first insulating layer (2), a diaphragm layer (3), a second insulating layer (4), a sound cavity (5), a back plate (6), a sound hole (7), and a hollow cylindrical back cavity (8) inside the silicon substrate, characterized in that: The diaphragm layer (3) is configured as three layers (31, 32, 33). The first diaphragm layer (31) is a circular film with radius R1 and thickness D1. The second diaphragm layer (32) is a circular piezoelectric film with radius R2 and thickness D2, which is embedded in the upper part of the first diaphragm layer (31) and is flush with the upper surface of the first diaphragm layer (31). The third diaphragm layer (33) is a circular film with radius R3 and thickness D3, which is located above the first diaphragm layer (31) and the second diaphragm layer (32). Among them, R1 = R3 > R2, D1 ≥ D3 > D2.

5. The capacitive MEMS microphone according to claim 4, characterized in that: The first insulating layer (2) is located on the silicon substrate (1); The second insulating layer (4) is located at the upper edge of the third diaphragm layer (33).

6. The capacitive MEMS microphone according to claim 4, characterized in that: The first diaphragm layer (31) is located above the first insulating layer (2); The back plate (6) is located above the second insulating layer (4) and the acoustic cavity (5).

7. The capacitive MEMS microphone according to claim 4, characterized in that: The acoustic cavity (5) is located between the third diaphragm layer (33) and the back plate (6), and its edge is the second insulating layer (4), the height of which is the same as the thickness of the second insulating layer (4).

8. The capacitive MEMS microphone according to claim 4, characterized in that: The acoustic hole (7) is located on the back plate (6), and is cylindrical in shape with a radius r of 20-30 μm.

9. The capacitive MEMS microphone according to claim 4, characterized in that, The depth of the back cavity (8) is 302-504 μm, the width of its upper surface is smaller than that of the first diaphragm layer (31) in the horizontal direction, and the distance L between the upper surface boundary and the boundary of the first diaphragm layer (31) in the horizontal direction is equal, 20 μm ≤ L ≤ 30 μm.

10. The capacitive MEMS microphone according to claim 4, characterized in that: The silicon substrate (1) is selected as a p-type (100) silicon wafer with a thickness of 300-500 μm; The first insulating layer (2) has a thickness of 2 to 4 μm; The second insulating layer (4) has a thickness of 4-5 μm; The acoustic cavity (5) has a height of 4-5 μm; The radius of the back plate (6) is the same as the radius R1 of the first diaphragm layer (31), and its thickness D5 ranges from 4 to 5 μm.

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