Conditional instruction prediction

Abstract

The processor may include a bias prediction circuit and an instruction prediction circuit to provide a corresponding prediction for a conditional instruction. The bias prediction circuit may provide a bias prediction that the condition of the conditional instruction is biased true or biased false. The instruction prediction circuit may provide an instruction prediction that the condition of the conditional instruction is true or false. In response to the bias prediction that the condition of the conditional instruction is biased true or biased false, the processor may use the bias prediction from the bias prediction circuit to speculatively process the conditional instruction. Otherwise, the processor may use the instruction prediction from the instruction prediction circuit to speculatively process the conditional instruction.

Description

Technical Field

[0001] Embodiments described herein relate to processors, and more particularly, to processors including circuitry for predicting an outcome of a conditional instruction and / or processing the conditional instruction based on the prediction. Background Art

[0002] A computing system typically includes one or more processors that serve as a central processing unit (CPU). The CPU executes control software (e.g., an operating system) that controls the operation of various peripheral devices. The CPU may also execute applications that provide user functionality in the system. Sometimes, a processor may implement an instruction pipeline comprising multiple levels, wherein instructions are divided into a series of steps that are respectively executed at the corresponding levels of the pipeline. Therefore, the instruction pipeline may execute multiple instructions in parallel. In order to improve efficiency, the processor may also implement a conditional instruction prediction circuit (also referred to as a "conditional instruction predictor") that can predict the conditions of conditional instructions. Based on the prediction, the processor may speculatively obtain instructions from a target address for execution. However, if the conditional instruction is mispredicted, the speculative work must be discarded, and the processor may have to re-acquire instructions from the correct target address for execution. Therefore, the accuracy of the prediction of the conditional instruction may play a key role in the performance of the processor, and therefore it becomes necessary to have a technology that improves the accuracy of the prediction. In addition, as the width and depth of the execution pipeline increase, the processor may process multiple conditional instructions and / or mispredictions in a cycle. Therefore, it is also necessary to have a technology for improving the efficiency of conditional instruction processing in the processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The following detailed description refers to the accompanying drawings, which are now briefly described.

[0004] Figure 1 is a block diagram of one embodiment of a portion of a processor including biased prediction circuitry and instruction prediction circuitry.

[0005] Figure 2A One embodiment of a bias table for a bias prediction circuit is shown.

[0006] Figure 2B One embodiment of a basic table for the instruction prediction circuit is shown.

[0007] Figure 3A is a block diagram of one embodiment of the operation of a bias prediction circuit.

[0008] Figure 3B is a block diagram of one embodiment of the operation of instruction prediction circuitry.

[0009] Figure 4 is a flow chart illustrating one embodiment of the operation of a processor including biased prediction circuitry and instruction prediction circuitry.

[0010] Figure 5 is a block diagram of one embodiment of a portion of a processor including instruction dispatch circuitry and multiple execution pipelines.

[0011] Figure 6 is a flow chart illustrating one embodiment of the operation of a processor including instruction dispatch circuitry and multiple execution pipelines.

[0012] Figure 7 is a block diagram of another embodiment of a portion of a processor including instruction dispatch circuitry and multiple execution pipelines.

[0013] Figure 8 is a flow chart illustrating another embodiment of the operation of a processor including instruction dispatch circuitry and multiple execution pipelines.

[0014] Fig. 9 yes Figures 1 to 8 A block diagram of one embodiment of a processor including biased prediction circuitry, instruction prediction circuitry, and / or instruction dispatch circuitry is shown in FIG.

[0015] Fig.10 Yes, it can include Fig. 9 A block diagram of one embodiment of a system on a chip (SOC) of one or more processors is shown.

[0016] Fig.11 is a block diagram of one embodiment of a system for use in various contexts.

[0017] Fig.12 It is a block diagram of a computer accessible storage medium.

[0018] Although the embodiments described in the present disclosure may be subject to various modifications and alternatives, specific embodiments thereof are shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the drawings and specific embodiments thereof are not intended to limit the embodiments to the specific forms disclosed, but on the contrary, the present invention is intended to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of the specification. DETAILED DESCRIPTION

[0019] Now turn to Figure 1, a block diagram of one embodiment of a portion of the processor 30 including the biased prediction circuit 156 and the instruction prediction circuit 160 is shown. In the illustrated embodiment, the biased prediction circuit 156 and the instruction prediction circuit 160 may be implemented as part of the fetch and decode circuit 100 of the processor 30. Alternatively, in some other embodiments, the biased prediction circuit 156 and / or the instruction prediction circuit 160 may be implemented as a separate component from the fetch and decode circuit 100.

[0020] like Figure 1 As indicated in , in the illustrated embodiment, the fetch and decode circuit 100 may implement a pipeline having several stages. For example, to process an instruction, the fetch and decode circuit 100 may first load the instruction from the memory or cache 12 to the instruction cache (Icache) 102 using the prefetch circuit 150 (hereinafter referred to as the "prefetch" stage). Next, the instruction may be fetched from the Icache 102 by the fetch circuit 152 to the decoder 154 for decoding (hereinafter referred to as the "fetch" stage). The decoder 154 may decode the instruction, convert it into operations and / or micro-operations (hereinafter referred to as the "decode" stage), and send the operations and / or micro-operations to the execution pipeline 164 for execution. It should be noted that sometimes the instruction may already exist in the Icache 102, for example, when the Icache 102 stores instructions previously loaded from the memory or cache 12 in the Icache 102. In this case, the prefetch stage may be avoided, and the instruction may be fetched directly from the Icache 102 for execution. In the illustrated embodiment, execution pipeline 164 may use Fig. 9 1 and 12. In addition, for the purpose of illustration, Figure 1 Not all components of the processor 30 may be depicted. For example, sometimes the fetch and decode circuitry 100 may not necessarily be directly coupled to the execution pipeline 112. Instead, there may be one or more other components in between. For example, sometimes the processor 30 may include a map-dispatch-rename (MDR) unit 106 between the fetch and decode circuitry 100 and the execution pipeline 112, which may map operations and / or micro-ops to speculative resources (e.g., physical registers) to permit out-of-order and / or speculative execution, and may dispatch operations and / or micro-ops to reservation stations 110.

[0021] The execution of code including conditional instructions may depend on the condition of the conditional instructions. When the condition of the conditional instruction is true, a first instruction from a first target address may be loaded, retrieved, and executed. Conversely, when the condition of the conditional instruction is false, a second instruction from a second target address may be loaded, retrieved, and executed. For purposes of illustration, the following is example code including conditional instructions:

[0022] ===================================================================If(a>b) / / Conditional instruction

[0023] {

[0024] x=1; / / Instructions to be executed when the condition is true

[0025] }

[0026] else

[0027] {

[0028] x=2; / / Instructions to be executed when the condition is false

[0029] }

[0030] ==========================================================

[0031] In this example, the conditional instruction involves only a comparison between the values ​​of two variables, "a" and "b". If the condition of the conditional instruction is true (i.e., the value of "a" is greater than the value of "b"), then the first instruction from the first target address may be executed to assign the value of the variable "x" to 1. Conversely, if the condition of the conditional instruction is false (i.e., the value of "a" is less than or equal to the value of "b"), then the second instruction from the second target address may be executed to assign the value of the variable "x" to 2.

[0032] In the illustrated embodiment, the acquisition and decoding circuit 100 can process conditional instructions speculatively. For example, the acquisition and decoding circuit 100 can predict the condition of the conditional instruction before the (actual) execution of the conditional instruction, and based on the prediction, speculatively determine the target address, based on the target address, subsequent instructions can be obtained for execution. As described above, the target address can reside in a memory or cache 12 or Icache 102. In addition, as illustrated in the above example, the subsequent instruction may or may not be immediately followed by the conditional instruction. In order to improve efficiency, the acquisition and decoding circuit 100 can also use a bias prediction circuit 156 with a bias table 158 to provide a bias prediction of whether the conditional instruction is biased true or biased false. When the conditional instruction is predicted to be biased true or biased false, the acquisition and decoding circuit 100 can use the bias prediction from the bias prediction circuit 156 to process the conditional instruction. Conversely, when a conditional instruction is predicted to be not biased true or biased false, the fetch and decode circuitry 100 may use instruction prediction circuitry 160 having one or more tables 162 to provide another prediction (such as an instruction prediction whether the condition of the conditional instruction is true or false) and use the instruction prediction to speculatively process the conditional instruction.

[0033] In the illustrated example, the biased prediction circuit 156 and the instruction prediction circuit 160 may perform respective predictions at different stages of the processing of conditional instructions in the fetch and decode circuit 100. For example, in the illustrated embodiment, when the conditional instruction is loaded from the memory or cache 12 to the Icache 102, the biased prediction circuit may provide a biased prediction for the conditional instruction at the prefetch stage. By comparison, in the illustrated embodiment, the instruction prediction circuit 160 may provide instruction predictions at a relatively "later" stage (such as, the fetch stage when the conditional instruction is fetched from the Icache 102 to the decoder 154). It should be noted that the above is provided for illustrative purposes only. In some embodiments, the biased prediction circuit 156 and the instruction prediction circuit 160 may provide their respective predictions at approximately the same time, for example, both at the same stage (such as, the prefetch stage, the fetch stage, etc.).

[0034] Sometimes, when the conditional instruction is predicted as biased true or biased false, the fetch and decode circuit 100 may simply cause the conditional instruction to "bypass" the instruction prediction circuit 160. In other words, the instruction prediction circuit 160 may not necessarily provide a second prediction such as an instruction prediction. Alternatively, sometimes the fetch and decode circuit 100 may still use the instruction prediction circuit 160 to provide an instruction prediction. However, when the conditional instruction is predicted as biased true or biased false, the fetch and decode circuit 100 may ignore the instruction prediction from the instruction prediction circuit 160 and instead use the biased prediction from the biased prediction circuit 156 to speculatively process the conditional instruction, as described above.

[0035] In the illustrated embodiment, the bias prediction from the bias prediction circuit 156 and the instruction prediction from the instruction prediction circuit 160 may indicate different properties of the conditional instruction. In addition, as described in Figures 2 to 3, they can be generated in different ways. In the illustrated embodiment, the bias prediction from the bias prediction circuit 156 may indicate whether the conditional instruction is predicted to be biased (e.g., biased true or biased false). The conditional instruction being biased refers to the scenario in which the condition of the conditional instruction is always true or false. For example, if the condition is always true, the condition of the conditional instruction is considered to be biased true. On the contrary, if it is always false, the condition is considered to be biased false. Referring again to the bias prediction, when the condition of the conditional instruction is predicted to be biased true (or biased false), it means that the condition of the conditional instruction is predicted to be always true (or always false), and therefore it is assumed that the conditional instruction is always operated in one way (or another way). By comparison, the instruction prediction from the instruction prediction circuit 160 may indicate that the condition of the conditional instruction is predicted to be true or false. However, unlike a biased prediction, an instruction prediction may not necessarily indicate whether a conditional instruction is biased true or biased false, or in other words, always true or always false.

[0036] It should be noted that both the bias prediction and the instruction prediction are only predictions. Therefore, any one of them may be wrong. In the illustrated embodiment, the quality of the prediction can be determined, for example, after the conditional instruction is executed by the execution pipeline 164. Considering the above example code, once the values ​​of the operands (e.g., variables "a" and "b") are obtained and the operator (e.g., comparator ">") is applied to the operands, the processor 30 may be able to determine whether the condition of the conditional instruction is actually true or false, and therefore evaluate whether the bias prediction and / or instruction prediction is correct. In the illustrated embodiment, the bias prediction circuit 156 and / or the instruction prediction circuit 160 can be updated based on the evaluation of the conditional instruction. For example, when the bias prediction and / or the instruction prediction is a misprediction, the bias table 158 of the bias prediction circuit 156 and / or the table 162 of the instruction prediction circuit 160 can be updated.

[0037] When a misprediction occurs, the processor 30 may have to discard the speculative work and obtain another instruction from the correct target address for execution. For example, the execution pipeline 164 may discard the instruction speculatively obtained within the execution pipeline, and the acquisition and decoding circuit 100 may have to redirect the prefetch circuit 150 and / or the acquisition circuit 152 to obtain the instruction from the correct target address for execution (also known as re-acquisition). Sometimes, this will cause additional delays in the operation of the processor 30. However, in implementation, most conditional instructions may be biased instructions. Therefore, even with the above-mentioned losses caused by misprediction, the use of additional biased prediction circuits can still increase the overall efficiency of the processor 30. In particular, if the processor 30 allows predictive biased conditional instructions to "bypass" the instruction prediction circuit 160, this can greatly reduce the overall workload and improve the efficiency of the processor 30.

[0038] In the illustrated embodiment, biased prediction circuit 156 may use bias table 158 to provide biased predictions for conditional instructions. Figure 2AAn example bias table 158 is shown. In the figure, the bias table 158 can be organized into one or more entries, each of which can be identified by a corresponding index and include a corresponding value. In the illustrated embodiment, the index of the bias table 158 can be associated with the address of the conditional instruction. For example, the index can be created by hashing the address of the conditional instruction using a hash function. In the context of hashing, the address of the conditional instruction can be regarded as a "key", and the value in the entry can be regarded as a "value", both of which can be associated with each other via an index (and a hash function). Therefore, for a given conditional instruction, the bias prediction circuit 156 can identify the value (e.g., "value") in the corresponding entry of the bias table 158 based on the address (e.g., "key") of the conditional instruction, and then provide a bias prediction for the conditional instruction based on the identified value in the bias table 158. For example, when the bias prediction circuit 156 receives the conditional instruction, the bias prediction circuit 156 can (e.g.) obtain the address of the conditional instruction from the program counter (PC). The bias prediction circuit 156 may determine an index based on the address of the conditional instruction (e.g., using a hash function). The bias prediction circuit 156 may then use the index to search the bias table 158 to find an entry that matches the index, identify the value in the entry, and use the value to determine the bias prediction for the conditional instruction. It should be noted that sometimes the index of the bias table 158 may be subject to hash conflicts, for example, a phenomenon where different addresses of different conditional instructions may be hashed to the same index. In other words, different keys may correspond to the same value in the bias table 158. Sometimes, hash conflicts may cause mispredictions of conditional instructions.

[0039] exist Figure 2A In the illustrated embodiment, the values ​​in the bias table 158 may be 2-bit values ​​indicating different predictions about the bias of the conditional instruction. For example, a value of "00" may indicate that the bias prediction circuit 156 has not previously encountered a conditional instruction corresponding to an entry of that value. A value of "01" may indicate that the condition of the conditional instruction is biased false. A value of "10" may indicate that the condition of the conditional instruction is biased true. And a value of "11" may indicate that the condition of the conditional instruction is not biased (e.g., neither biased true nor biased false), even though the bias prediction circuit 156 has previously encountered a conditional instruction corresponding to an entry of that value. Note that Figure 2A The bias table 158 in FIG. 1 is provided as an example only for the purpose of illustration. In some embodiments, the values ​​in the bias table 158 may have fewer or more bits. For example, sometimes these values ​​may have more than two bits to provide a certain level of hysteresis.

[0040] In the illustrated embodiment, the instruction prediction circuit 160 may also use one or more tables 162 to predict instruction predictions for conditional instructions. However, unlike the bias prediction circuit 156, at least some of the tables 162 may be highly correlated with a history of previous predictions (e.g., by the instruction prediction circuit 160) and / or evaluations of conditional instructions. Furthermore, sometimes the history may relate to the history of a particular conditional instruction, but may also relate to the history of other conditional instructions in the same code. For example, sometimes the instruction prediction circuit 162 may be a tagged geometry length predictor (also called a TAGE predictor) that includes a basic predictor T0 and a set of (partial) tagged predictors T1. i (1≤i≤M). Base predictor T0 may use base table 162(0) to provide base predictions. In the illustrated embodiment, an index to base table 162(0) may be generated by hashing the address of the conditional instruction. By comparison, tag predictor T i (1≤i≤M) may each have a table 162(i)(1≤i≤M), the index of which may be created by hashing (a) the address of the conditional instruction and (b) the previous prediction and / or evaluation history of the conditional instruction. The history may be considered a geometric sequence. For example, the address of the conditional instruction may be concatenated with the history, and then the two may be hashed together to generate an index. Different tag predictors T i Table 162(i) ​​of (1≤i≤M) may be associated with different history lengths. For example, the higher the order of the tag predictor (eg, the larger i), the history may be used to generate the tag predictor T i The longer the index of table 162(i) ​​of (1≤i≤M). Therefore, the marker predictor T i (1≤i≤M) may use their corresponding tables 162(i)(1≤i≤M) to provide corresponding predictions for conditional instructions. Sometimes, the hash functions of the base table 158 of the bias prediction circuit 156 and the base table 162(0) of the instruction prediction circuit 160 may be different. In addition, sometimes different predictors T i The hash functions of different tables 162 (i) of (0≤i≤M) may also be different. In addition, the above hash function may be implemented based on any appropriate hash function, including an exclusive OR (or XOR) operation.

[0041] In the illustrated embodiment, for a given conditional instruction, in order to provide an instruction prediction, the instruction prediction circuit 160 may determine the indices of the corresponding (M+1) predictors (0≤i≤M) based on the address and history (for tag predictors only) of the conditional instruction, identify the matching predictor with the longest history (e.g., with the highest order), and use the prediction from the matching predictor as the (final) instruction prediction for the conditional instruction. From the above description, it can be seen that the instruction prediction circuit 160 may be more complex than the biased prediction circuit 156, and therefore consumes more time to make predictions. Therefore, using an additional biased prediction circuit 156 to allow predictive biased conditional instructions to "bypass" the instruction prediction circuit 160 can reduce the overall workload and improve the efficiency of the processor 30.

[0042] Figure 2B An example basic table 162(0) of the instruction prediction circuit 160 is shown. For the purpose of illustration, the basic table 162(0) is also provided as an example to illustrate the tag predictor T i Table 162(i) ​​of (1≤i≤M). In the illustrated embodiment, the marker predictor T i Table 162(i) ​​for (1≤i≤M) may be similar to basic table 162(0), for example, also providing a value at each entry, but also including additional information such as a historically relevant geometric sequence. In addition, basic table 162(0) may also account for the difference between bias prediction circuit 156 and instruction prediction circuit 160. Figure 2B As indicated in , in the illustrated embodiment, the values ​​in the basic table 162(0) may be 2-bit values. For example, the value "00" may indicate that the condition of the conditional instruction is strongly false. The value "01" may indicate that the condition of the conditional instruction is weakly false. The value "10" may indicate that the condition of the conditional instruction is weakly true. The value "11" may indicate that the condition of the conditional instruction is strongly true. Therefore, the values ​​in the table 162(0) of the instruction prediction circuit 160 may not necessarily indicate the bias of the conditional instruction, but only indicate whether it is true or false with a certain relativity. For example, compared with the value "01", the value "00" may indicate that the conditional instruction is predictively more likely to be false. Similarly, compared with the value "10", the value "11" may indicate that the conditional instruction is predictively more likely to be true. Note that Figure 2B The basic table 162(0) in is provided as an example for illustration purposes only. In some embodiments, the marker predictor T i The values ​​in the basic table 162 ( 0 ) and / or table 162 ( i ) (1≤i≤M) may have fewer or more bits.

[0043] Now turn to Figure 3A and Figure 3B , the state machines of the bias prediction circuit 156 and the instruction prediction circuit 160 are shown to illustrate the operation of the corresponding prediction circuits. Figure 3AAs indicated in FIG. , circles 302, 304, 306, and 308 may correspond to Figure 2A The four possible predictions in the bias table 158 of the bias prediction circuit 156 in Figure 3B In FIG. 1 , circles 312, 314, 316, and 318 may correspond to Figure 2B The four possible predictions in table 162 of instruction prediction circuit 160 in FIG. 16A and 16B are shown in FIG. 16B . In addition, the edges connecting the circles in the corresponding tables may indicate changes in values ​​when updated.

[0044] See again Figure 3A In the illustrated embodiment, the value "00" may be designed as the initial state or default value of the conditional instruction. For example, at startup, the value of the conditional instruction in the offset table 158 may be set to the default value "00". When the conditional instruction is loaded from the memory or cache 12 to the Icache 102 for the first time, assuming that there is no hash conflict about the conditional instruction, the offset prediction circuit 156 may encounter the conditional instruction corresponding to the entry of the conditional instruction in the offset table 158 for the first time. Therefore, the value of the conditional instruction in the offset table 158 may be "00" (for example, corresponding to circle 302). Because the value "00" does not indicate that the condition of the conditional instruction is biased true or biased false, the acquisition and decoding circuit 100 may also use the instruction prediction circuit 160 to provide a second prediction for the conditional instruction, such as an instruction prediction. As described above, the instruction prediction circuit 160 may use the table 162 to provide an instruction prediction. In the illustrated embodiment, similarly, the processor 30 may specify one of the four possible states as the initial state or default value of the conditional instruction. For purposes of illustration, assume that the initial state or default value of the conditional instruction is "10" (e.g., corresponding to circle 316), thereby indicating that the condition is predicted to be weakly true. Based on the instruction prediction from the instruction prediction circuit 160, the fetch and decode circuit 100 can determine a target address based on which subsequent instructions can be speculatively obtained for execution. Consider the above example code including the conditional instruction "if (a>b)". Since the conditional instruction is predicted to be "weakly true", the fetch and decode circuit 100 can speculatively obtain the subsequent instruction "x=1" for execution.

[0045] After the instruction is executed (e.g., in the execution pipeline 164), the condition of the conditional instruction can be actually determined, and the bias prediction from the bias prediction circuit 156 and the instruction prediction from the instruction prediction circuit 160 can be evaluated based on the execution result of the conditional instruction. In the illustrated embodiment, the bias table 158 of the bias prediction circuit 156 and / or the table 162 of the instruction prediction circuit 160 can be updated based on the evaluation. For example, when the result of the evaluation is that the condition of the conditional instruction is actually true, this means that the previous bias prediction from the bias prediction circuit 156 (which is the initial state or default value "00") is an incorrect prediction. Therefore, in the bias table 158, the value of the conditional instruction can be changed from "00" (e.g., the initial state) to "10" (e.g., the bias is true). Figure 3A , this is illustrated by the change from circle 302 (e.g., corresponding to "00") to circle 306 (e.g., corresponding to "10"). By comparison, the evaluation of the conditional instruction may confirm that the previous instruction prediction from the instruction prediction circuitry 160 was not a misprediction. Therefore, in table 162, the value of the conditional instruction may change from "10" (e.g., weakly true) to "11" (e.g., strongly true), thereby indicating that the instruction prediction circuitry 160 received a reward. Figure 3B , this is illustrated by the change from circle 316 (eg, corresponding to "10") to circle 318 (eg, corresponding to "11").

[0046] Conversely, when the result of the evaluation of the conditional instruction is that the condition of the conditional instruction is actually false, it means that the previous bias prediction from the bias prediction circuit 156 is a wrong prediction. Therefore, in the bias table 158, the value of the conditional instruction may be changed from "00" (e.g., initial state) to "01" (e.g., bias false). Figure 3A In table 162, this is illustrated by the change from circle 302 (e.g., corresponding to "00") to circle 304 (e.g., corresponding to "01"). In addition, the evaluation of the conditional instruction may indicate that the previous instruction prediction from the instruction prediction circuitry 160 was also a misprediction. Therefore, in table 162, the value of the conditional instruction may change from "10" (e.g., weakly true) to "01" (e.g., weakly true), thereby indicating that the instruction prediction circuitry 160 has earned a penalty. Figure 3B This is illustrated in FIG. 1 by the change from circle 316 (eg, corresponding to “10”) to circle 314 (eg, corresponding to “01”).

[0047] like Figure 3AAs indicated in , once updated to the value "10" (e.g., biased true) or "01" (e.g., biased false), the value of the conditional instruction in the bias table 158 may remain at "10" or "01" until a misprediction occurs. In other words, once the value of the conditional instruction in the bias table 158 is updated from the initial state, the bias prediction circuit 156 may refrain from changing it to another value until a misprediction occurs. From an operational perspective, this means that the bias prediction circuit 158 ​​may unconditionally predict the condition of the conditional instruction in the same manner until an evaluation of the conditional instruction indicates that the bias prediction is a misprediction. When this misprediction occurs, the value of the conditional instruction in the bias table 158 may be updated from "10" or "01" to "11" (e.g., unbiased). In Figure 3A , this is illustrated by the change from circle 304 (e.g., corresponding to "01") or 306 (e.g., corresponding to "10") to circle 308 (e.g., corresponding to "11"). Additionally, once updated to the value "11", the value of the conditional instruction in bias table 158 may remain at "11" (e.g., unbiased) until the prediction circuit 156 resets the value to the initial state or default value "00".

[0048] like Figure 3B As indicated in , the value of the conditional instruction in table 162 may change from one value to another value when updated, depending on whether the instruction prediction circuit 160 receives a reward or a penalty. For example, when the evaluation of the conditional instruction confirms that the instruction prediction from the instruction prediction circuit 160 is not a misprediction, the instruction prediction circuit 160 may receive a reward to change the value of the conditional instruction in table 162 from a relatively weak prediction to a relatively strong prediction (e.g., from weak true to strong true, or from weak false to strong false), or to remain at a relatively strong prediction (e.g., strong true or strong false). Conversely, when the evaluation of the conditional instruction indicates that the instruction prediction from the instruction prediction circuit 160 is a misprediction, the instruction prediction circuit 160 may receive a penalty to change the value of the conditional instruction in table 162 from a relatively strong prediction to a relatively weak prediction (e.g., from strong true to weak true, or from strong false to weak false), or even from a relatively weak prediction to an opposite relatively weak prediction (e.g., from weak true or weak false, or vice versa). Note that in the illustrated embodiment, the values ​​of the conditional instructions in table 162 may not change directly from one relatively strong prediction to an opposite relatively strong prediction (e.g., from strongly true to strongly false, or vice versa). Therefore, table 162 may be viewed as having a certain level of hysteresis.

[0049] Furthermore, as described above, when the condition of the conditional instruction is predicted to be biased true or biased false, for example, when the value of the conditional instruction in the bias table 158 is "10" or "01", the fetch and decode circuit 100 may use the biased prediction from the biased prediction 156 to speculatively process the conditional instruction. Conversely, when the condition of the conditional instruction is predicted to not be biased true or biased false, for example, when the value of the conditional instruction in the bias table 158 is "00" or "11", the fetch and decode circuit 100 may use the instruction prediction from the instruction prediction circuit 160 to speculatively process the conditional instruction.

[0050] In the illustrated embodiment, the bias table 158 and / or the table 162 may be implemented using one or more registers. In addition, the fetch and decode circuit 100 may encode the bias prediction from the bias prediction circuit 156 and / or the instruction prediction from the instruction prediction circuit 160 in the instruction line containing the conditional instruction. For example, the fetch and decode circuit 100 may append the value (e.g., 2-bit value) of the conditional instruction from the bias table 158 and / or the table 162 to the machine code of the instruction line including the conditional instruction in the front, back, or middle. Alternatively, the fetch and decode circuit 100 may re-encode the machine code of the instruction line including the conditional instruction to embed the prediction for the conditional instruction. For example, the fetch and decode circuit 100 may change the value of one or more bits of the machine code. Therefore, when an instruction with the appended value is received at the Icache 102 and / or the decoder 154, the Icache 102 and / or the decoder 154 may identify the prediction of the conditional instruction and speculatively process the conditional instruction based on the prediction as described above.

[0051] In the illustrated embodiment, when a conditional instruction is predicted as biased true or biased false, sometimes the fetch and decode circuitry 100 may cause the conditional instruction to "bypass" the instruction prediction circuitry 160. In the illustrated embodiment, to implement the "bypass", the fetch and decode circuitry 100 may re-encode the conditional instruction as a non-conditional instruction. Therefore, the instruction prediction circuitry 160 may treat the conditional instruction as a non-conditional instruction, and therefore may not necessarily provide an instruction prediction for the recorded conditional instruction.

[0052] As described above, the bias prediction circuit 156 and / or the instruction prediction circuit 160 may incorrectly predict conditional instructions. Therefore, the bias prediction circuit 156 and / or the instruction prediction circuit 160 may be saturated. For example, when the code is executed by the processor 30 for a relatively long time, the bias prediction circuit 156 may experience enough mispredictions for one or more conditional instructions of the code. Therefore, the value of the conditional instruction in the bias table 158 may be changed to the value "11". As described above, once the value is changed to "11", they may remain as "11" until reset. Therefore, in order to solve the saturation, in the illustrated embodiment, the bias prediction circuit 156 and / or the instruction prediction circuit 160 may respectively detect the occurrence of saturation, and responsively reset the bias table 158 and / or the table 162. For example, the bias prediction circuit 156 may monitor the number of values ​​"11" in the bias table 158. When it reaches a specified threshold (e.g., a specified percentage), the bias prediction circuit 156 may determine that the bias table 158 is saturated. Therefore, the bias prediction circuit 156 may reset those values ​​“11” to the initial state “00.” Sometimes, the bias prediction circuit 156 may also reset other values ​​in the bias table 158 (eg, the entire bias table 158) to the initial state “00.”

[0053] Now turn to Figure 4 , a flow chart illustrating one embodiment of the operation of the processor 30 including the biased prediction circuit 156 and the instruction prediction circuit 160 is shown. In the illustrated embodiment, a conditional instruction may be received at the fetch and decode circuit 100, as indicated in block 402. As described above, the conditional instruction may be loaded from the memory or cache 12 to the Icache 102, or fetched from the Icache 102 to the decoder 154. The fetch and decode circuit 100 may use the biased prediction circuit 156 to provide a biased prediction of whether the condition of the conditional instruction is biased true or biased false, as indicated in block 404. In the illustrated embodiment, the biased prediction circuit 156 may use the bias table 158 to make the biased prediction, as indicated in block 404. As described above, when the condition of the conditional instruction is predicted to be biased true or biased false, it indicates that the biased prediction circuit 156 predicts that the condition of the conditional instruction is always true or always false.

[0054] When the biased prediction from biased prediction circuitry 156 predicts that the condition of the conditional instruction is not biased true or biased false, the fetch and decode circuitry 100 may use instruction prediction circuitry 160 to provide an instruction prediction of whether the condition of the conditional instruction is true or false, as indicated in block 406. As described above, in the illustrated embodiment, instruction prediction circuitry 160 may be a TAGE predictor having a total of (M+1) predictors, such as a base predictor T0 having a base table 162(0) and one or more additional (partial) tag predictors T1 having corresponding tables 162(i) ​​(1≤i≤M). i. Tag predictor T i Table 162(i) ​​of (1≤i≤M) may be associated with a history-dependent geometric sequence of corresponding history length.

[0055] As described above, in the illustrated embodiment, when the biased prediction circuit 156 predicts that the condition of the conditional instruction is biased true or biased false, the fetch and decode circuit 156 may cause the conditional instruction to "bypass" the instruction prediction circuit 160. Therefore, the operation in block 406 may be avoided. For example, the fetch and decode circuit 100 may re-encode the conditional instruction as a non-conditional instruction. In addition, as described above, in the illustrated embodiment, the biased prediction from the biased prediction circuit 156 and the instruction prediction from the instruction prediction circuit 160 may be provided at different stages of processing the conditional instruction in the fetch and decode circuit. For example, when the conditional instruction is loaded from the memory or cache 12 to the Icache 102, the biased prediction circuit 156 may provide the biased prediction at the prefetch stage, and when the conditional instruction is fetched from the Icache 102 to the decoder 154, the instruction prediction circuit 160 may perform the instruction prediction at the fetch stage.

[0056] In the illustrated embodiment, the fetch and decode circuitry 100 may use one of the biased prediction from the biased prediction circuitry 156 and the instruction prediction from the instruction prediction circuitry 160 to speculatively determine the target address of the conditional instruction, as indicated in block 408. For example, the fetch and decode circuitry 100 may speculatively determine, based on the biased prediction from the biased prediction circuitry 156 or the instruction prediction from the instruction prediction circuitry 160, the target address of the conditional instruction from which a subsequent instruction may be obtained for execution.

[0057] In the illustrated embodiment, the fetch and decode circuitry 100 may send the conditional instruction to the execution pipeline 164 for execution, as indicated in block 410. In addition, the fetch and decode circuitry 100 may receive an evaluation of the conditional instruction based on the result of the execution of the conditional instruction, as indicated in block 412. As described above, the execution of the conditional instruction may determine whether the condition of the conditional instruction is actually true or false, and therefore determine whether a previous biased prediction from the biased prediction circuitry 156 and / or a previous instruction prediction from the instruction prediction circuitry 160 was a misprediction.

[0058] In the illustrated embodiment, the bias prediction circuit 156 and / or the instruction prediction circuit 160 updates its bias table 158 and table 162, respectively, based on the evaluation of the conditional instruction, as indicated in blocks 414 and 416. As described above in FIGS. 2-3 , the update of the bias table 158 may change the value of the conditional instruction from an initial state such as “00” to “01” (e.g., indicating biased false) or “10” (e.g., indicating biased true) when the evaluation indicates that the condition of the conditional instruction is actually true or false, respectively, or from “01” or “10” to “11” (e.g., indicating no bias) when the evaluation indicates that the previous biased true or biased false prediction is actually a misprediction. By comparison, when the evaluation confirms that the instruction prediction from the instruction prediction circuit 160 is not a wrong prediction, the instruction prediction circuit 160 may update the value of the conditional instruction in the table 162(i) ​​of the basic and tag predictor Ti (0≤i≤M) from a relatively weak prediction to a relatively strong prediction (e.g., from weak true "10" to strong true "11", or from weak false "01" to strong false "00"), or maintain the value at the relatively strong prediction (e.g., strong true "11" or strong false "00"); or when the evaluation indicates that the instruction prediction from the instruction prediction circuit 160 is a wrong prediction, from a relatively strong prediction to a relatively weak prediction (e.g., from strong true "11" to weak true "10", or from strong false "00" to weak false "01"), or from a relatively weak prediction to the opposite relatively weak prediction (e.g., from weak true "10" or weak false "01", or vice versa).

[0059] Now turn to Figure 5 , a block diagram of one embodiment of a portion of processor 30 including instruction dispatch circuitry 520 and execution pipelines 504 and 506 is shown. Figure 5 , instruction dispatch circuitry 520 may receive a conditional instruction associated with a prediction from fetch and decode circuitry 100, and dispatch the conditional instruction to one of a plurality of execution pipelines (such as 504 and 506) based on a confidence level of the prediction of the conditional instruction. When the conditional instruction is determined to have a relatively high confidence level, the instruction dispatch circuitry may dispatch the conditional instruction to a first execution pipeline 504. Conversely, when the conditional instruction is determined to have a relatively low confidence level, the instruction dispatch circuitry may dispatch the conditional instruction to a second execution pipeline 506. One difference between execution pipeline 504 and execution pipeline 506 may be that execution pipeline 506 (but not execution pipeline 504) may have the ability to redirect fetch and decode 100 to obtain the instruction from the correct target address for execution when a conditional instruction is mispredicted (also referred to as re-fetch).

[0060] Therefore, when the execution pipeline 504 detects the misprediction of the conditional instruction, the execution pipeline 504 may have to use the execution pipeline 506 to instruct to re-acquire the instruction from the correct target address for execution. For example, the execution pipeline 504 may create a bubble in the execution pipeline 506, and then insert the conditional instruction into the bubble for execution by the execution pipeline 506. Once the execution pipeline 506 executes the conditional instruction and also determines that the conditional instruction is mispredicted, the execution pipeline 506 can redirect the acquisition and decoding 100 to re-acquire the instruction from the correct target address for execution. For example, the execution pipeline 506 (rather than the execution pipeline 504) may have a communication path to the acquisition and decoding circuit 100, and the execution pipeline 506 may perform re-acquisition via the communication path instruction acquisition and decoding circuit 100. Given that the conditional instruction has been executed in the execution pipeline 504, the second execution of the conditional instruction in the execution pipeline 506 can also be regarded as the re-execution or replay of the conditional instruction. In addition, in the illustrated embodiment, the execution pipeline 506 can also use bubbles to execute one or more unconditional instructions and mispredicted conditional instructions. For example, the execution pipeline 506 may execute one or more unconditional instructions created by the bubble in the same cycle as the mispredicted conditional instruction.

[0061] In the illustrated embodiment, when it detects a mispredicted conditional instruction, the execution pipeline 504 may not necessarily write the result back to any register or memory until the instruction from the correct target address is successfully executed by the execution pipeline 504. This ensures that only the correct result is written to the register or memory. However, this may also delay the exit of the execution pipeline 504, and thus cause additional delays to the execution pipeline 404. By comparison, when the mispredicted conditional instruction is initially assigned to the execution pipeline 506, the execution pipeline 506 can detect the misprediction and directly cause the acquisition and decoding circuit 100 to obtain execution from the correct target address for execution, thus causing the minimum delay to execution. Therefore, due to the different delays in the processing of the mispredicted conditional instruction, the execution pipeline 504 can be regarded as a "slow" execution pipeline, while the execution pipeline 506 can be regarded as a "fast" execution pipeline. Sometimes, the execution pipeline 504 and the execution pipeline 506 may include the same level or the same number of levels. In other words, execution pipeline 504 and execution pipeline 506 may not necessarily have different latencies for conditional instructions that are not mispredicted, and may only have different latencies for conditional instructions that are mispredicted because execution pipeline 504 lacks the ability to directly fetch and decode instruction circuitry 100. Alternatively, sometimes execution pipeline 504 may have more stages or a greater number of stages than execution pipeline 506. Therefore, regardless of whether the conditional instruction is mispredicted, execution pipeline 504 may always have greater latency than execution pipeline 506.

[0062] In the illustrated embodiment, the prediction of the conditional instruction used by the instruction dispatch circuit 502 to dispatch the conditional instruction may be (a) a biased prediction from the biased prediction circuit 156 or (b) an instruction prediction from the instruction prediction circuit 160. For example, as described above, when the biased prediction circuit 156 provides a biased prediction that the condition of the conditional instruction is biased true or biased false, the fetch and decode circuit 100 may use the biased prediction to speculatively process the conditional instruction. In this case, the instruction dispatch circuit 502 may use the biased prediction from the biased prediction circuit 156 to determine the dispatch of the conditional instruction. Conversely, when the biased prediction circuit 156 predicts that the condition of the conditional instruction is not biased true or biased false, the fetch and decode circuit 100 may use the instruction prediction from the instruction prediction circuit 160 to speculatively process the conditional instruction. In this case, the instruction dispatch circuit 502 may use the instruction prediction from the instruction prediction circuit 160 to determine the dispatch of the conditional instruction. In other words, the prediction of the conditional instruction disclosed herein may be a prediction of the conditional instruction, and the fetch and decode circuit 100 speculatively processes the conditional instruction based on the prediction.

[0063] In the illustrated embodiment, the confidence of the prediction may be determined with respect to one or more criteria. For example, when the prediction of the conditional instruction is a biased prediction from the biased prediction circuit 156 (e.g., when the conditional instruction is predicted as biased true or biased false), the instruction dispatch circuit 502 may determine that the prediction has a high confidence. In addition, when the prediction is an instruction prediction from the instruction prediction circuit 160 (e.g., when the conditional instruction is not predicted as biased true or biased false), if the instruction prediction is made by the tag predictor T having a saturating counter, the confidence of the prediction may be determined with respect to one or more criteria. i or a marker predictor T with a high-order table i If the conditional instruction prediction circuit 160 is provided (e.g., when the instruction prediction circuit 160 is a TAGE predictor), the instruction dispatch circuit 502 may determine that the prediction has a high confidence. Otherwise, when the prediction of the conditional instruction fails to meet one or more of the above criteria, the instruction dispatch circuit 502 may determine that the prediction has a low confidence.

[0064] When the confidence is high, the instruction allocation circuit 502 may allocate the conditional instruction to the "slow" execution pipeline 504. Conversely, when the confidence is low, the instruction allocation circuit 502 may allocate the conditional instruction to the execution pipeline 506 (e.g., the "slow" execution pipeline). From an operational perspective, this means that when the conditional instruction is predicted with high confidence, the instruction allocation circuit 502 may assume that the conditional instruction is less likely to be mispredicted, and therefore the execution of the conditional instruction in the execution pipeline 504 (e.g., the "slow" execution pipeline) may have a lower probability of causing re-acquisition. By comparison, when the conditional instruction is predicted with low confidence, the instruction allocation circuit 502 may assume that the prediction is more likely to be wrong. Therefore, the instruction allocation circuit 502 may allocate the conditional instruction to the execution pipeline 506 (e.g., the "fast" execution pipeline) to reduce the potential delay of re-acquisition.

[0065] Sometimes, instruction dispatch circuitry 502 may perform load balancing between execution pipeline 504 and execution pipeline 506. For example, instruction dispatch circuitry 502 may dispatch conditional instructions to execution pipeline 504 and execution pipeline 506 based on the occupancy of the execution pipelines rather than the prediction of the conditional instructions. For example, when execution pipeline 504 is overloaded and execution pipeline 506 is not fully occupied, instruction dispatch circuitry 502 may dispatch conditional instructions associated with high confidence predictions to execution pipeline 506 for execution.

[0066] Now turn to Figure 6 , shows a flow chart illustrating one embodiment of the operation of the processor 30 including the instruction dispatch circuitry 502 and the different execution pipelines 504 and 506. In the illustrated embodiment, a conditional instruction associated with a prediction may be received at the instruction dispatch circuitry 502, as indicated in block 602. As described above, the prediction for the conditional instruction may be (a) a biased prediction from the biased prediction circuitry 156 or (b) an instruction prediction from the instruction prediction circuitry 160.

[0067] In the illustrated embodiment, the instruction dispatch circuitry 502 may evaluate the prediction of the conditional instruction with respect to one or more criteria to determine the confidence of the prediction, as indicated in block 604. For example, the instruction dispatch circuitry 502 may determine whether the prediction is a biased prediction (e.g., biased true or biased false) provided by the biased prediction circuitry 156 or a tag predictor T with a saturating counter. i or a tag predictor T with a high-order table of instruction prediction circuit 160 i The instruction prediction (e.g., true or false) provided (e.g., when the instruction prediction circuitry 160 is a TAGE predictor). If yes, the instruction dispatch circuitry 502 may determine that the conditional instruction has a high confidence. Otherwise, the instruction dispatch circuitry 502 may determine that the conditional instruction has a low confidence.

[0068] The instruction dispatch circuitry 502 may dispatch the conditional instruction to one of the plurality of execution pipelines based on a confidence level of the prediction of the conditional instruction with respect to one or more criteria. For example, when the confidence level is high, the instruction dispatch circuitry 502 may dispatch the conditional instruction to the execution pipeline 504 (e.g., a “slow” execution pipeline) for execution, as indicated in block 606. Otherwise, when the confidence level is low, the instruction dispatch circuitry 502 may dispatch the conditional instruction to the execution pipeline 506 (e.g., a “fast” execution pipeline) for execution, as indicated in block 610.

[0069] When the conditional instruction is dispatched to the execution pipeline 504, execution of the conditional instruction may determine that the prediction of the conditional instruction is a misprediction, as indicated in block 608. In response, the execution pipeline 504 may cause the mispredicted conditional instruction to be re-executed or replayed in the execution pipeline 506, as indicated in block 610. As described above, in the illustrated embodiment, the execution pipeline 504 may create a bubble in the execution pipeline 506 and insert the mispredicted conditional instruction into the bubble for execution by the execution pipeline 506. As described above, execution of the conditional instruction in the execution pipeline 506 may determine that the conditional instruction is mispredicted, as indicated in block 612. The execution pipeline 506 may direct the fetch and decode circuitry 100 to obtain the instruction for execution from the correct target address of the conditional instruction, as indicated in block 614.

[0070] Now turn to Figure 7 , shows a block diagram of one embodiment of a portion of a processor 30 including instruction dispatch circuitry 520 and execution pipelines 504, 506, 708, and 710. In the illustrated embodiment, execution pipeline 708 may be similar to execution pipeline 504 (e.g., a "slow" execution pipeline) such that execution pipeline 708 lacks the ability to direct instruction fetch and decode circuitry 100 to perform re-fetch for mispredicted conditional instructions. By comparison, execution pipeline 710 may be similar to execution pipeline 506 (e.g., a "fast" execution pipeline) such that execution pipeline 710 may also be able to direct instruction fetch and decode circuitry 100 to perform re-fetch for mispredicted conditional instructions. For example, similar to execution pipeline 506, execution pipeline 710 may also have a communication path to the fetch and decode circuitry to direct re-fetch for mispredicted conditional instructions. Thus, in Figure 7 , processor 30 includes two "slow" execution pipelines (e.g., execution pipeline 504 and execution pipeline 708) and two "fast" execution pipelines (e.g., execution pipeline 507 and execution pipeline 710). Note that Figure 7 This is provided for purposes of illustration only as an example.At times, processor 30 may include fewer or more "slow" execution pipelines, and / or fewer or more "fast" execution pipelines.

[0071] like Figure 7 , the instruction dispatch circuit 502 may dispatch the conditional instruction to the execution pipelines 504, 506, 708, and 710 according to the confidence level of the prediction of the conditional instruction. In the illustrated embodiment, the confidence level of the prediction of the conditional instruction may be determined with respect to one or more criteria, as described above in Figure 5 to Figure 6 Thus, instruction dispatch circuitry 502 may dispatch conditional instructions associated with predictions of high confidence to execution pipeline 504 and execution pipeline 708 (e.g., a “slow” execution pipeline) for execution, and dispatch conditional instructions associated with predictions of low confidence to execution pipeline 506 and execution pipeline 710 (e.g., a “fast” execution pipeline) for execution.

[0072] In the illustrated embodiment, execution pipelines 504, 506, 708, and 710 may operate in parallel and thus process one or more conditional instructions at approximately the same time. However, in the illustrated embodiment, only one of the "fast" execution pipelines (such as execution pipeline 506) may be used to re-execute or replay (so as to cause retrieval) an incorrectly predicted conditional instruction provided from a "slow" execution pipeline (such as execution pipeline 504 and execution pipeline 708). Thus, when both execution pipeline 504 and execution pipeline 708, respectively, detect an incorrectly predicted conditional instruction, processor 30 may use first misprediction selection circuit 712 to select one of the incorrectly predicted conditional instructions from execution pipeline 504 and execution pipeline 708 for re-execution or replay in execution pipeline 506, such as execution pipeline 506. Figure 7 As indicated in .

[0073] In the illustrated embodiment, selection may be performed according to the age of the two mispredicted conditional instructions of the execution pipeline 504 and the execution pipeline 708, respectively. For example, the first misprediction selection circuit 712 may compare the age of the first mispredicted conditional instruction in the execution pipeline 504 with the age of the second mispredicted conditional instruction in the execution pipeline 708, and cause the older of the two conditional instructions to be executed in the execution pipeline 506. The age of the conditional instruction may be obtained in one of various ways. For example, the acquisition and decoding circuit 100 may assign a number (such as Gnum) to the conditional instruction when the conditional instruction is decoded by the decoder 154. For each instruction, Gnum may be a unique, monotonically increasing (or decreasing) number. Therefore, a newer instruction may be assigned a smaller Gnum (or a larger Gnum), while an older instruction may be assigned a larger Gnum (or a smaller Gnum). Therefore, the first misprediction selection circuit 712 may compare the Gnum of the two conditional instructions to select the older conditional instruction. Additionally, the age of the conditional instructions may sometimes be determined based on the order of the conditional instructions in a re-order buffer (ROB) 108 of the processor 30 .

[0074] Once the first misprediction selection circuit 712 makes a selection, the corresponding execution pipeline (e.g., execution pipeline 504) may create a bubble in the execution pipeline 506 and insert the selected conditional instruction into the bubble for execution by the execution pipeline 506. Once the execution pipeline 506 executes the conditional instruction and detects that it is mispredicted, the execution pipeline 506 may direct the acquisition and decoding circuit 100 to obtain the instruction from the correct target address of the mispredicted conditional instruction for execution, as described above. It should be noted that the selection of the first misprediction selection circuit 712 may not necessarily mean that the unselected mispredicted conditional instruction will not be re-executed or replayed by the execution pipeline 506. Instead, it only means that when both the "slow" execution pipeline 504 and the execution pipeline 708 detect mispredictions at about the same time, in order to resolve the conflict, one of the conditional instructions may be selected to cause re-acquisition first. Afterwards, the other unselected conditional instruction may be re-executed or replayed by the execution pipeline 506 to direct the other re-acquisition.

[0075] However, in the illustrated embodiment, given that multiple execution pipelines including two "fast" execution pipelines 506 and execution pipeline 710 can process instructions in parallel, it is possible that execution pipeline 710 (e.g., the second "fast" execution pipeline) can also detect an incorrectly predicted conditional instruction at about the same time as execution pipeline 506 (e.g., the first "fast" execution pipeline) detects an incorrectly predicted conditional instruction. This may also result in conflicts. Figure 7 , in this case, the processor 30 may use the second prediction selection circuit 714 to select one of the two mispredicted conditional instructions for re-fetching from the two "fast" execution pipelines 506 and the execution pipeline 710. For example, the second misprediction circuit 714 may compare the age of the first mispredicted conditional instruction in the execution pipeline 506 with the age of the second mispredicted conditional instruction in the execution pipeline 710, and select the older of the two conditional instructions to direct the fetch and decode circuit 100 to obtain the instruction from the target address for execution.

[0076] Now turn to Figure 8 , shows a flow chart illustrating one embodiment of the operation of the processor 30 including the instruction dispatch circuitry 502 and the different execution pipelines 504, 506, 708, and 710. In the illustrated embodiment, a conditional instruction associated with a prediction may be received at the instruction dispatch circuitry 502, as indicated in block 802. As described above, the prediction for the conditional instruction may be (a) a biased prediction from the biased prediction circuitry 156 or (b) an instruction prediction from the instruction prediction circuitry 160.

[0077] In the illustrated embodiment, the instruction allocation circuitry 502 may evaluate the prediction of the conditional instruction with respect to one or more criteria to determine the confidence of the prediction, as indicated in block 704. The instruction allocation circuitry 502 may allocate the conditional instruction to one of the plurality of execution pipelines according to the confidence of the prediction of the conditional instruction with respect to the one or more criteria. For example, when the confidence is high, the instruction allocation circuitry 502 may allocate the conditional instruction to one of the execution pipelines 504 and 708 (e.g., a "slow" execution pipeline) for execution, as indicated in block 806. Otherwise, when the confidence is low, the instruction allocation circuitry 502 may allocate the conditional instruction to one of the execution pipelines 506 and 710 (e.g., a "fast" execution pipeline) for execution, as indicated in block 812.

[0078] When the conditional instruction is assigned to one of the execution pipeline 504 and the execution pipeline 708, the execution of the conditional instruction may determine that the prediction of the conditional instruction is a misprediction, as indicated in block 808. However, the other of the execution pipeline 504 and the execution pipeline 708 may also detect the mispredicted conditional instruction at about the same time. Therefore, in order to resolve the conflict, the processor 30 may use the first misprediction selection circuit 712 to select one of the two mispredicted conditional instructions to be re-executed or replayed by the execution pipeline 506 from the execution pipeline 504 and the execution pipeline 708, as indicated in block 810. In the illustrated embodiment, the selection may be performed based on the age of the two conditional instructions. For example, the first misprediction selection circuit 712 may compare the age of the first mispredicted conditional instruction in the execution pipeline 504 with the age of the second mispredicted conditional instruction in the execution pipeline 708, and cause the older of the two conditional instructions to be executed in the execution pipeline 506, as indicated in block 812.

[0079] In the illustrated embodiment, execution of the conditional instruction in the execution pipeline 506 may determine that the conditional instruction is mispredicted, as indicated in block 814. Additionally, another execution pipeline 710 (e.g., a second "fast" execution pipeline) may also detect the mispredicted conditional instruction at approximately the same time as the execution pipeline 506 detects the mispredicted conditional instruction. Thus, the processor 30 may use the second misprediction circuitry 714 to select one of the two mispredicted conditional instructions from the execution pipeline 506 and the execution pipeline 710, as indicated in block 816. Thus, the execution pipeline 506 or the execution pipeline 710 of the selected mispredicted conditional instruction may instruct the fetch and decode circuitry 100 to obtain the instruction for execution from the correct target address of the selected mispredicted conditional instruction, as indicated in block 818.

[0080] Fig. 9 is a block diagram of one embodiment of a processor 30, the processor comprising Figures 1 to 8The bias prediction circuit 156, instruction prediction circuit 160 and / or instruction dispatch circuit 502 described in FIG. Fig. 9 These are provided for illustration purposes only as examples. Therefore, sometimes the processor 30 may not include all but only some of the illustrated components. For example, sometimes the processor 30 may include the bias prediction circuit 156 and the instruction prediction circuit 160, but not the instruction dispatch circuit 502.

[0081] In the illustrated embodiment, processor 30 includes a fetch and decode unit 100 (including an instruction cache or ICache 102), a map-dispatch-rename (MDR) unit 106 (including a reorder buffer (ROB) 108), one or more reservation stations 110, one or more execution units 112, a register file 114, a data cache (DCache) 104, a load / store unit (LSU) 118, a reservation station (RS) 116 for the load / store unit, and a core interface unit (CIF) 122. Fetch and decode unit 100 is coupled to MDR unit 106, which is coupled to reservation stations 110, reservation stations 116, and LSU 118. Reservation stations 110 are coupled to execution units 28. Register file 114 is coupled to execution units 112 and LSU 118. LSU 118 is also coupled to DCache 104, which is coupled to CIF 122 and register file 114. LSU 118 includes a store queue 120 (STQ 120) and a load queue (LDQ 124).

[0082] The acquisition and decoding unit 100 may be configured to acquire instructions for execution by the processor 30 and decode the instructions into ops for execution. More specifically, the acquisition and decoding unit 100 may be configured to cache instructions previously acquired from memory (via CIF 122) in ICache 102, and may be configured to acquire speculative paths for instructions for the processor 30. As described above, in the illustrated embodiment, the acquisition and decoding unit 100 may include bias prediction circuitry 156 and instruction prediction circuitry 160 to provide corresponding predictions for conditional instructions. The acquisition and decoding unit 100 may implement various prediction structures to predict acquisition paths. For example, a next acquisition predictor may be used to predict an acquisition address based on previously executed instructions. Various types of branch predictors may be used to verify the next acquisition prediction, or if the next acquisition predictor is not used, may be used to predict the next acquisition address. The acquisition and decoding unit 100 may be configured to decode instructions into instruction operations. In some embodiments, a given instruction may be decoded into one or more instruction operations, depending on the complexity of the instruction. In some embodiments, particularly complex instructions may be microcoded. In such embodiments, the microcoded routine for the instruction may be encoded in the instruction operation. In other embodiments, each instruction in the instruction set architecture implemented by processor 30 may be decoded into a single instruction operation, and thus an instruction operation may be substantially synonymous with the instruction (although its form may be modified by the decoder). The term "instruction operation" may be more briefly referred to herein as an "operation" or "op".

[0083] MDR unit 106 may be configured to map ops to speculative resources (eg, physical registers) to allow out-of-order and / or speculative execution, and may dispatch ops to reservation stations 110 and 116. Fig. 9 As indicated in , in the illustrated embodiment, the MDR unit 106 may include an instruction allocation circuit 502. The op may be mapped from the architectural registers used in the corresponding instruction to the physical registers in the register file 114. That is, the register file 114 may implement a set of physical registers, the number of which may be greater than the architectural registers specified by the instruction set architecture implemented by the processor 30. The MDR unit 106 may manage the mapping of architectural registers to physical registers. In one embodiment, for different operand types (e.g., integer, media, floating point, etc.), separate physical registers may exist. In other embodiments, physical registers may be shared among operand types. The MDR unit 106 may also be responsible for tracking speculative execution and exiting the op or refreshing the mis-speculated op. The reorder buffer 108 may be used to track the program order of the op and manage exit / refresh. That is, the reorder buffer 108 may be configured to track multiple instruction operations corresponding to instructions that the processor acquires and the processor does not exit.

[0084] When source operands for an op are ready, the op may be scheduled for execution. In the illustrated embodiment, decentralized scheduling is used for each execution unit in execution unit 28 and LSU 118, such as in reservation stations 116 and reservation stations 110. Other embodiments may implement a centralized scheduler if desired.

[0085] LSU 118 may be configured to perform load / store memory ops. Generally speaking, a memory operation (memory op) may be an instruction operation that specifies access to memory (although memory access may be performed in a cache such as DCache 104). A load memory operation may specify a data transfer from a memory location to a register, while a store memory operation may specify a data transfer from a register to a memory location. A load memory operation may be referred to as a load memory op, a load op, or a load; and a store memory operation may be referred to as a store memory op, a store op, or a store. In one embodiment, a store op may be executed as a store address op and a store data op. A store address op may be defined as generating an address for storage, probing a cache to determine an initial hit / miss, and updating a store queue with address and cache information. Thus, a store address op may take an address operand as a source operand. A store data op may be defined as delivering store data to a store queue. Thus, a store data op may not take an address operand as a source operand, but may take a store data operand as a source operand. In many cases, the address operand of storage may be available before the storage data operand, and therefore the address may be determined and become available earlier than the storage data. In some embodiments, for example, if a storage data operand is provided before one or more operands in the storage address operand, the storage data op may be executed before the corresponding storage address op. Although in some embodiments, the storage op may be executed as a storage address op and a storage data op, other embodiments may not implement the storage address / storage data split. As an example, the remainder of this disclosure will generally use the storage address op (and storage data op), but specific implementations that do not use the storage address / storage data optimization are also envisioned. The address generated by the execution of the storage address op may be referred to as the address corresponding to the storage op.

[0086] The load / store op may be received in a reservation station 116, which may be configured to monitor the source operands of the operation to determine when they are available, and then issue these operations to the load or store pipeline, respectively. When the operation is received in the reservation station 116, some source operands may be available, which may be indicated in the data received by the reservation station 116 from the MDR unit 106 for the corresponding operation. Other operands may become available via execution of the operation by other execution units 112 or even via execution of an earlier load op. The operands may be collected by the reservation station 116, or may be read from the register file 114 when issued from the reservation station 116, such as Figure 6 shown.

[0087] In one embodiment, the reservation station 116 may be configured to issue load / store ops out of order (different from their original order in the code sequence executed by the processor 30 (referred to as "program order")) as these operands become available. To ensure that there is space in the LDQ 124 or STQ 120 for older operations that are bypassed by newer operations in the reservation station 116, the MDR unit 106 may include circuitry that pre-allocates LDQ 124 or STQ 120 entries to operations transferred to the load / store unit 118. If there are no available LDQ entries for a load being processed in the MDR unit 106, the MDR unit 106 may stall dispatching of load ops and subsequent ops in program order until one or more LDQ entries become available. Similarly, if there are no STQ entries available for stores, the MDR unit 106 may stall op dispatching until one or more STQ entries become available. In other embodiments, the reservation station 116 may issue operations in program order, and the LRQ 46 / STQ 120 assignments may occur upon issue from the reservation station 116.

[0088] LDQ 124 may track loads from initial execution to retirement by LSU 118. LDQ 124 may be responsible for ensuring that memory ordering rules are not violated (between loads that are executed out of order, and between loads and stores). If a memory ordering violation is detected, LDQ 124 may signal a redirection for the corresponding load. The redirection may cause the processor 30 to flush the load op and subsequent ops in program order and re-fetch the corresponding instructions. The speculative state of the load op and subsequent ops may be discarded, and these ops may be re-fetched and re-processed by the fetch and decode unit 100 for execution again.

[0089] When the load / store address op is issued by the reservation station 116, the LSU 118 may be configured to generate an address accessed by the load / store, and may be configured to convert the address from an effective address or a virtual address created by the address operand of the load / store address op to a physical address actually used for the address memory. The LSU 118 may be configured to generate access to the DCache 104. For a load operation that hits the DCache 104, data may be speculatively forwarded from the DCache 104 to the target operand of the load operation (e.g., a register in the register file 114), unless the address hits a previous operation in the STQ 120 (i.e., an older store in program order) or the load is replayed. Data may also be forwarded to a dependent op that was once speculatively scheduled and is now located in the execution unit 112. In such a case, the execution unit 112 may bypass the forwarded data instead of the data output from the register file 114. If the storage data is available for forwarding when the STQ hits, the data output by the STQ 120 may be forwarded instead of the cache data. Cache misses and STQ hits where data cannot be forwarded may be the cause of a replay, and in those cases the load data cannot be forwarded. The cache hit / miss status from DCache 104 may be recorded in STQ 120 or LDQ 124 for later processing.

[0090] LSU 118 may implement multiple load pipelines. For example, in one embodiment, three load pipelines ("pipelines") may be implemented, but more or fewer pipelines may be implemented in other embodiments. Each pipeline may execute different loads independently and in parallel with other loads. That is, RS 116 may issue any number of loads in the same clock cycle, up to the number of load pipelines. LSU 118 may also implement one or more storage pipelines, and specifically may implement multiple storage pipelines. However, the number of storage pipelines need not be equal to the number of load pipelines. In one embodiment, for example, two storage pipelines may be used. Reservation station 116 may issue storage address ops and storage data ops independently and in parallel with the storage pipelines. The storage pipeline may be coupled to STQ 120, which may be configured to hold storage operations that have been executed but not yet committed.

[0091] The CIF 122 may be responsible for communicating with the rest of the system including the processor 30 on behalf of the processor 30. For example, the CIF 122 may be configured to request data for DCache 104 misses and ICache 102 misses. When the data is returned, the CIF 122 may signal a cache fill to the corresponding cache. For a DCache fill, the CIF 122 may also notify the LSU 118. The LDQ 124 may attempt to schedule a replayed load that is waiting on a cache fill so that the replayed load can forward the fill data when the fill data is provided to the DCache 104 (referred to as a fill forwarding operation). If the replayed load is not successfully replayed during the fill, the replayed load may then be scheduled and replayed through the DCache 104 as a cache hit. The CIF 122 may also write back modified cache lines that have been evicted by the DCache 104, merge store data that is not cacheable, and the like. In another example, the CIF 122 may transmit interrupt-related signals, such as interrupt requests and / or acknowledgement / non-acknowledgement signals from / to a peripheral device of a system including the processor 30 , to the processor 30 .

[0092] In various embodiments, execution unit 112 may include any type of execution unit. For example, execution unit 112 may include integer, floating point, and / or vector execution units. An integer execution unit may be configured to execute an integer op. Generally, an integer op is an op that performs a defined operation (e.g., arithmetic, logic, shift / rotate, etc.) on integer operands. An integer may be a numeric value, where each value corresponds to a mathematical integer. An integer execution unit may include branch processing hardware for processing a branch op, or there may be a separate branch execution unit. As described above, execution unit 112 and associated reservation station 110 may implement the following. Figures 1 to 8 One or more execution pipelines 164, 504, 506, 708 and / or 710 described in.

[0093] The floating point execution unit may be configured to execute a floating point op. Generally speaking, a floating point op may be an op that has been defined to operate on a floating point operand. A floating point operand is an operand represented as a mantissa (or significant digit) multiplied by an exponent of a base. The exponent, the sign of the operand, and the mantissa / significant digit may be explicitly represented in the operand, and the base (e.g., in one embodiment, base 2) may be implicit.

[0094] The vector execution unit may be configured to execute a vector op. A vector op may be used, for example, to process media data (e.g., image data such as pixels, audio data, etc.). Media processing may be characterized by performing the same processing on a large amount of data, where each datum is a relatively small value (e.g., 8 bits or 16 bits, compared to 32 bits to 64 bits for integers). Therefore, a vector op includes a single instruction multiple data (SIMD) or vector operation on operands representing multiple media data.

[0095] Thus, each execution unit 112 may include hardware configured to perform operations defined as operations that are restricted to ops processed by a specific execution unit. The execution units may generally be independent of each other in the sense that each execution unit may be configured to operate on ops that are issued for that execution unit and are independent of other execution units. From another perspective, each execution unit may be an independent pipeline for executing ops. Different execution units may have different execution latencies (e.g., different pipeline lengths). In addition, different execution units may have different latencies for pipeline stages where bypassing occurs, and the clock cycle at which speculative scheduling of related ops occurs based on load ops may vary based on the op and the type of execution unit 28 that will execute the op.

[0096] Note that any number and types of execution units 112 may be included in various implementations, including implementations with one execution unit and implementations with multiple execution units.

[0097] A cache line can be an allocation / deallocation unit in a cache. That is, data within a cache line can be allocated / deallocated in a cache as a unit. The size of a cache line can vary (e.g., 32 bytes, 64 bytes, 128 bytes, or larger or smaller cache lines). Different caches can have different cache line sizes. ICache 102 and DCache 104 can each be a cache with any desired capacity, cache line size, and configuration. In various embodiments, there can be more additional levels of cache between DCache 104 / ICache 102 and main memory.

[0098] At various points, a load / store operation is referred to as being newer or older than other load / store operations. A first operation may be newer than a second operation if it follows the second operation in program order. Similarly, a first operation may be older than a second operation if it precedes the second operation in program order.

[0099] Now turn to Fig.10, which is a block diagram of an embodiment of a system 10 that may include one or more processors 30. In the illustrated embodiment, the system 10 may be implemented as a system on chip (SOC) 10 coupled to a memory 12. As the name implies, the components of the SOC 10 may be integrated onto a single semiconductor substrate that is an integrated circuit "chip". In some embodiments, these components may be implemented on two or more discrete chips in the system. However, the SOC 10 will be used as an example in this article. In the illustrated embodiment, the components of the SOC 10 include multiple processor clusters 14A-14n, an interrupt controller 20, one or more peripheral components 18 (more briefly, "peripherals"), a memory controller 22, and a communication structure 27. Components 14A-14n, 18, 20, and 22 may all be coupled to the communication structure 27. The memory controller 22 may be coupled to the memory 12 during use. In some embodiments, there may be more than one memory controller coupled to the corresponding memory. The memory address space may be mapped across the memory controllers in any desired manner. In the illustrated embodiment, the processor clusters 14A-14n may include a corresponding plurality of processors (P) 30, and the corresponding processors (P) 30 may also include the following: Figures 1 to 9 1. The processor 30 may form a central processing unit (CPU) of the SOC 10. In one embodiment, one or more processor clusters 14A-14n may not function as a CPU.

[0100] As described above, the processor cluster 14A-14n may include one or more processors 30 that may be used as the CPU of the SOC 10. The CPU of the system includes a processor that executes the main control software of the system (such as an operating system). Generally speaking, the software executed by the CPU during use can control other components of the system to achieve the desired functions of the system. The processor may also execute other software such as application programs. The application program may provide user functions and may rely on the operating system for lower-level device control, scheduling, memory management, etc. Therefore, the processor may also be referred to as an application processor.

[0101] In general, a processor may include any circuitry and / or microcode configured to execute instructions defined in an instruction set architecture implemented by the processor. A processor may encompass a processor core implemented on an integrated circuit with other components as a system on a chip (SOC 10) or other level of integration. A processor may also include a discrete microprocessor, a processor core and / or a microprocessor integrated into a multi-chip module implementation, a processor implemented as multiple integrated circuits, and the like.

[0102] The memory controller 22 may generally include a circuit system for receiving memory operations from other components of the SOC 10 and for accessing the memory 12 to complete the memory operations. The memory controller 22 may be configured to access any type of memory 12. For example, the memory 12 may be a static random access memory (SRAM), a dynamic RAM (DRAM) such as a synchronous DRAM (SDRAM) including a double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low power / mobile versions of DDR DRAM (e.g., LPDDR, mDDR, etc.) may be supported. The memory controller 22 may include a memory operation queue for ordering (and potentially reordering) these operations and presenting these operations to the memory 12. The memory controller 22 may also include a data buffer for storing write data waiting to be written to the memory and read data waiting to be returned to the memory operation source. In some embodiments, the memory controller 22 may include a memory cache for storing recently accessed memory data. For example, in a SOC specific implementation, the memory cache may reduce power consumption in the SOC by avoiding re-accessing data from the memory 12 when it is expected to be accessed again soon. In some cases, the memory cache may also be referred to as a system cache, which is different from a private cache such as an L2 cache or a cache in a processor, which only serves certain components. In addition, in some embodiments, the system cache does not need to be located in the memory controller 22.

[0103] Peripherals 18 may be any collection of additional hardware functions included in SOC 10. For example, peripherals 18 may include video peripherals, such as: an image signal processor configured to process image capture data from a camera or other image sensor; a GPU; a video encoder / decoder; a scaler; a rotator; a mixer; a display controller, etc. Peripherals may include audio peripherals, such as: a microphone; a speaker; an interface to a microphone and a speaker; an audio processor; a digital signal processor; a mixer, etc. Peripherals may include interface controllers for various interfaces external to SOC 10, including interfaces such as universal serial bus (USB), peripheral component interconnect (PCI) (including PCI Express (PCIe)), serial and parallel ports, etc. Peripherals may include networking peripherals, such as a media access controller (MAC). Any set of hardware may be included.

[0104] The communication fabric 27 may be any communication interconnect and protocol for communicating between components of the SOC 10. The communication fabric 27 may be bus-based, including a shared bus configuration, a crossbar configuration, and a hierarchical bus with bridges. The communication fabric 27 may also be packet-based, and may be a hierarchical, crossbar, point-to-point, or other interconnect with bridges.

[0105] Note that the number of components of the SOC 10 (and Figure 4 Subcomponents of those components shown in FIG. 1 , such as the number of processors 30 in each processor cluster 14A-14n, may vary from implementation to implementation. In addition, the number of processors 30 in one processor cluster 14A-14n may be different from the number of processors 30 in another processor cluster 14A-14n. The number of each component / subcomponent may be more or less than Figure 4 Quantity shown.

[0106] Computer Systems

[0107] Next turn Fig.11 , a block diagram of one embodiment of a system 700 is shown. In the illustrated embodiment, the system 700 includes at least one instance of a system on a chip (SOC) 10 coupled to one or more peripheral devices 704 and an external memory 702, such as Fig.10 A power supply (PMU) 708 is provided that supplies supply voltages to the SOC 10 and one or more supply voltages to the memory 702 and / or the peripherals 154. In some embodiments, more than one instance of the SOC 10 (e.g., SOCs 10A-10q) may be included (and more than one memory 702 may also be included). In one embodiment, the memory 702 may include Figures 1 to 10 The memory 12 is illustrated in FIG.

[0108] Depending on the type of system 700, peripheral device 704 may include any desired circuit system. For example, in one embodiment, system 704 may be a mobile device (e.g., a personal digital assistant (PDA), a smart phone, etc.), and peripheral device 704 may include equipment for various types of wireless communications, such as Wi-Fi, Bluetooth, cellular, global positioning systems, etc. Peripheral device 704 may also include additional storage devices, which include RAM storage devices, solid-state storage devices, or disk storage devices. Peripheral device 704 may include user interface devices, such as a display screen, which includes a touch display screen or a multi-touch display screen, a keyboard or other input device, a microphone, a speaker, etc. In other embodiments, system 700 may be any type of computing system (e.g., a desktop personal computer, a laptop, a workstation, a network set-top box, etc.).

[0109] The external memory 702 may include any type of memory. For example, the external memory 702 may be an SRAM, a dynamic RAM (DRAM) such as a synchronous DRAM (SDRAM), a double data rate (DDR, DDR2, DDR3, etc.) SDRAM, a RAMBUS DRAM, a low power version of a DDR DRAM (e.g., LPDDR, mDDR, etc.), etc. The external memory 702 may include one or more memory modules to which a memory device may be mounted, such as a single inline memory module (SIMM), a dual inline memory module (DIMM), etc. Alternatively, the external memory 702 may include one or more memory devices mounted on the SOC 10 in a chip-on-chip or package-on-package implementation.

[0110] As illustrated, system 700 is shown as having applications in a wide range of fields. For example, system 700 can be used as a part of a chip, circuit system, component, etc. of a desktop computer 710, a laptop computer 720, a tablet computer 730, a cellular or mobile phone 740, or a TV 750 (or a set-top box coupled to a TV). Smart watches and health monitoring devices 760 are also illustrated. In some embodiments, smart watches may include various general computing related functions. For example, smart watches may provide access to email, mobile phone services, user calendars, etc. In various embodiments, health monitoring devices may be dedicated medical devices or otherwise include dedicated health-related functions. For example, health monitoring devices may monitor the vital signs of users, track the proximity of users to other users for the purpose of epidemiological social distance, contact tracking, provide communications to emergency services in the event of a health crisis, etc. In various embodiments, the above-mentioned smart watches may include or may not include some or any health monitoring related functions. Other wearable devices are also envisioned, such as devices worn around the neck, devices that can be implanted in the human body, glasses designed to provide enhanced and / or virtual reality experiences, etc.

[0111] The system 700 may also be used as part of a cloud-based service 770. For example, the previously mentioned devices and / or other devices may access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Still further, the system 700 may be used in one or more devices in a home other than those previously mentioned. For example, a home appliance may monitor and detect situations that warrant attention. For example, various devices in a home (e.g., a refrigerator, a cooling system, etc.) may monitor the status of the device, and an alert may be provided to the homeowner (or, for example, a maintenance agency) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in a home, and may automatically adjust the heating / cooling system based on a history of responses by the homeowner to various situations. Fig.11The system 700 is also illustrated in the application to various modes of transportation. For example, the system 700 can be used for control and / or entertainment systems of airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, scooters (for rental or private use), etc. In various cases, the system 700 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Any of these and many other embodiments are possible and contemplated. Note that Fig.11 The illustrated devices and applications are merely illustrative and are not intended to be limiting. Other devices are possible and contemplated.

[0112] Computer readable storage medium

[0113] Now turn to Fig.12 , a block diagram of an embodiment of a computer-readable storage medium 800 is shown. Generally speaking, a computer-accessible storage medium may include any storage medium that can be accessed by a computer during use to provide instructions and / or data to a computer. For example, a computer-accessible storage medium may include a storage medium such as a magnetic or optical medium, for example, a disk (fixed or removable), a tape, a CD-ROM, a DVD-ROM, a CD-R, a CD-RW, a DVD-R, a DVD-RW or a blue-ray. The storage medium may also include a volatile or non-volatile memory medium, such as a RAM (for example, a synchronous dynamic RAM (SDRAM), a Rambus DRAM (RDRAM), a static RAM (SRAM) etc.), a ROM or a flash memory. The storage medium may be physically included in a computer to which the storage medium provides instructions / data. Alternatively, the storage medium may be connected to a computer. For example, the storage medium may be connected to a computer via a network or a wireless link such as a network attached storage device. The storage medium may be connected via a peripheral interface such as a universal serial bus (USB). Generally speaking, the computer-accessible storage medium 800 can store data in a non-transitory manner, where non-transitory in this context can refer to not transmitting instructions / data via signals. For example, a non-transitory storage device can be volatile (and may lose the stored instructions / data in response to a power outage) or non-volatile.

[0114] Fig.12 The computer accessible storage medium 800 may store the above Fig.1010. In general, the database 804 may be a database that can be read by a program and used directly or indirectly to manufacture hardware including the SOC 10. For example, the database may be a behavioral level description or a register transfer level (RTL) description of hardware functions in a high-level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool, which may synthesize the description to generate a netlist including a list of gate circuits from a synthesis library. The netlist includes a set of gate circuits that also represent the functions of the hardware including the SOC 10. The netlist may then be placed and routed to generate a data set for describing the geometry to be applied to the mask. The mask may then be used in various semiconductor manufacturing steps to generate one or more semiconductor circuits corresponding to the SOC 10. Alternatively, the database 804 on the computer accessible storage medium 800 may be a netlist (with or without a synthesis library) or a data set as desired.

[0115] Although computer-accessible storage medium 800 stores a representation of SOC 10, other embodiments may carry a representation of any portion of SOC 10 as desired, including Figure 4 Any subset of the components shown. Database 804 may represent any of the above.

[0116] ***

[0117] The present disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. do not necessarily refer to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0118] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why a particular implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuit systems outside the scope of the present disclosure, which, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0119] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0120] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0121] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0122] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0123] ***

[0124] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0125] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" item refers to a collection of two or more items.

[0126] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0127] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0128] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0129] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0130] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "first circuit," "second circuit," "particular circuit," "given circuit," etc.) refer to different instances of the feature. In addition, unless otherwise specified, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0131] The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0132] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "in response to B, A is performed." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0133] ***

[0134] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0135] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0136] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform the particular function.

[0137] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use a “means for [performing the function]” structure to phrase the claim element.

[0138] Different "circuits" may be described in the present disclosure. These circuits or "circuitry" constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. The circuitry may be custom designed or taken from a standard library. In various specific implementations, the circuitry may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuitry.

[0139] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0140] In various embodiments, as discussed in the preceding paragraphs, circuits, units, and other elements defined by the functions or operations they are configured to implement, with respect to the arrangement of each other and such circuits / units / components and the manner in which they interact, form a microarchitecture definition of hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by encoding a description of the circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without undue experimentation and with the application of ordinary technicians. HDL descriptions are often expressed in a manner that can be rendered functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is transmitted to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit system design along with the synthesized circuit system. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0141] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0142] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

[0143] The following clauses describe example implementations consistent with the drawings and above description.

[0144] 1. A processor, comprising:

[0145] An instruction distribution circuit, wherein the instruction distribution circuit is configured to:

[0146] receiving a first conditional instruction associated with a prediction; and

[0147] assigning the first conditional instruction to one of a plurality of execution pipelines for execution according to the prediction of the first conditional instruction, wherein the plurality of execution pipelines include a first execution pipeline and a second execution pipeline, the first execution pipeline and the second execution pipeline providing different latencies for processing mispredicted conditional instructions; and

[0148] The first execution pipeline is configured as follows:

[0149] In response to receiving the first conditional instruction:

[0150] executing the first conditional instruction;

[0151] determining that the prediction of the first conditional instruction is a misprediction; and

[0152] In response to determining that the prediction of the first conditional instruction is a misprediction, causing the first conditional instruction to be executed in the second execution pipeline. 2. The processor of clause 1, wherein the second execution pipeline is configured to:

[0153] executing the first conditional instruction;

[0154] determining that the prediction of the first conditional instruction is a misprediction; and

[0155] In response to determining that the prediction of the first conditional instruction was a misprediction, an instruction is caused to be obtained for execution from a target address of the first conditional instruction.

[0156] 3. A processor according to clause 1, wherein the prediction of the first conditional instruction is associated with a confidence level with respect to one or more criteria, and wherein the one or more criteria include at least one of (a) the prediction is provided by a biased prediction circuit using a biased table or (b) the prediction is provided by an instruction prediction circuit using one or more tables based at least in part on a prediction history of conditional instructions.

[0157] 4. A processor according to clause 3, wherein the instruction allocation circuit is configured to allocate the first conditional instruction to the first execution pipeline for execution when the prediction of the first conditional instruction is associated with a high confidence, or to allocate the first conditional instruction to the second execution pipeline for execution when the prediction of the first conditional instruction is associated with a low confidence.

[0158] 5. The processor of clause 3, further comprising:

[0159] A third execution pipeline, wherein the third execution pipeline is configured as follows:

[0160] executing a second conditional instruction associated with the high confidence prediction; and

[0161] determining that the prediction of the second conditional instruction was a misprediction; and

[0162] A first error prediction selection circuit, wherein the first error prediction selection circuit is configured to:

[0163] before causing the first conditional instruction to be executed in the second execution pipeline, comparing the age of the first conditional instruction from the first execution pipeline with the age of the second conditional instruction from the third execution pipeline; and

[0164] In response to determining that the first conditional instruction is older than the second conditional instruction, causing the first conditional instruction to be executed in the second execution pipeline.

[0165] 6. The processor of clause 3, further comprising:

[0166] A fourth execution pipeline, wherein the fourth execution pipeline is configured as follows:

[0167] executing a third conditional instruction associated with the prediction with a low confidence; and

[0168] determining that the prediction of the third conditional instruction was a misprediction; and

[0169] A second error prediction selection circuit, wherein the second error prediction selection circuit is configured to:

[0170] comparing the age of the first conditional instruction from the second execution pipeline to the age of the third conditional instruction from the fourth execution pipeline; and

[0171] An instruction is caused to be obtained for execution from a target address of an older one of the first conditional instruction and the third conditional instruction.

[0172] 7. The processor of clause 1, wherein the second execution pipeline provides less latency than the first execution pipeline for processing the mispredicted conditional instruction, and wherein to provide the less latency, the second execution pipeline is configured to directly instruct the processing of the mispredicted conditional instruction in response to determining that the prediction of the first conditional instruction is a misprediction.

[0173] Another circuit of the processor obtains an instruction for execution from the target address of the first conditional instruction.

[0174] 8. The processor of clause 1, wherein the second execution pipeline provides less latency than the first execution pipeline for processing the mispredicted conditional instruction, and wherein the second execution pipeline includes fewer stages than the first execution pipeline.

[0175] 9. The processor of clause 1, wherein to cause execution of the first conditional instruction in the second execution pipeline, the first execution pipeline is configured to:

[0176] creating a bubble in the second execution pipeline; and

[0177] The first conditional instruction is caused to be inserted into the bubble so that the first conditional instruction is executed by the second execution pipeline.

[0178] 10. The processor of clause 9, wherein the second execution pipeline is further configured to:

[0179] The unconditional instruction is executed in the same cycle as the first conditional instruction.

[0180] 11. A method comprising:

[0181] receiving, at an instruction dispatch circuit of the processor, a first conditional instruction associated with a prediction;

[0182] using the instruction dispatch circuitry to dispatch the first conditional instruction to one of a plurality of execution pipelines for execution according to the prediction of the first conditional instruction, wherein the plurality of execution pipelines include a first execution pipeline and a second execution pipeline, the first execution pipeline and the second execution pipeline providing different latencies for processing mispredicted conditional instructions;

[0183] executing the first conditional instruction using the first execution pipeline;

[0184] determining, using the first execution pipeline, that the prediction of the first conditional instruction was a misprediction; and

[0185] In response to determining that the prediction of the first conditional instruction is a misprediction, causing execution of the first conditional instruction in the second execution pipeline.

[0186] 12. The method according to clause 11, further comprising:

[0187] Using the second execution pipeline causes an instruction to be obtained for execution from a target address of the first conditional instruction.

[0188] 13. A method according to clause 11, wherein the prediction of the first conditional instruction is associated with a confidence level regarding one or more criteria, and wherein the one or more criteria include at least one of (a) the prediction is provided by a biased prediction circuit using a bias table or (b) the prediction is provided by an instruction prediction circuit using one or more tables based at least in part on a prediction history of conditional instructions.

[0189] 14. The method according to clause 13, further comprising:

[0190] The first conditional instruction is assigned to the first execution pipeline for execution when the prediction of the first conditional instruction satisfies the one or more criteria, or the first conditional instruction is assigned to the second execution pipeline for execution when the prediction of the first conditional instruction fails to satisfy the one or more criteria.

[0191] 15. The method according to clause 13, further comprising:

[0192] executing, using a third execution pipeline, a second conditional instruction associated with a prediction that the criterion is satisfied;

[0193] determining that the prediction of the second conditional instruction is a misprediction,

[0194] Wherein causing the first conditional instruction to be executed in the second execution pipeline further comprises:

[0195] comparing the age of the first conditional instruction to the age of the second conditional instruction using a first misprediction selection circuit; and

[0196] In response to determining that the first conditional instruction is older than the second conditional instruction, causing the first conditional instruction to be executed in the second execution pipeline.

[0197] 16. The method according to clause 13, further comprising:

[0198] executing, using a fourth execution pipeline, a third conditional instruction associated with a prediction that the criterion fails to be satisfied;

[0199] determining that the prediction of the third conditional instruction is a misprediction;

[0200] comparing the age of the first conditional instruction to the age of the third conditional instruction using a second misprediction selection circuit; and

[0201] An instruction is caused to be obtained for execution from a target address of an older one of the first conditional instruction and the third conditional instruction.

[0202] 17. The method according to clause 13, further comprising:

[0203] receiving, at the instruction dispatch circuitry, a fourth conditional instruction associated with a prediction that the criterion is satisfied; and

[0204] The fourth conditional instruction is assigned to the second execution pipeline for execution based on the occupancy of the second execution pipeline.

[0205] 18. A method according to clause 11, wherein the second execution pipeline provides less latency than the first execution pipeline for processing the mispredicted conditional instruction, and wherein the second execution pipeline has a communication path to directly obtain an instruction from a target address for execution in response to determining that the prediction of the first conditional instruction is a misprediction.

[0206] 19. A system, comprising:

[0207] One or more processors, each of which comprises:

[0208] An instruction distribution circuit, wherein the instruction distribution circuit is configured to:

[0209] receiving a first conditional instruction associated with a prediction; and selecting one of a plurality of execution pipelines for executing the first conditional instruction based on the prediction of the first conditional instruction, wherein the plurality of execution pipelines include a first execution pipeline and a second execution pipeline, the first execution pipeline and the second execution pipeline providing different latencies for processing the mispredicted conditional instruction; and

[0210] The first execution pipeline is configured as follows:

[0211] In response to receiving the first conditional instruction:

[0212] executing the first conditional instruction;

[0213] determining that the prediction of the first conditional instruction is a misprediction;

[0214] as well as

[0215] In response to determining that the prediction of the first conditional instruction is a misprediction, causing execution of the first conditional instruction in the second execution pipeline.

[0216] 20. The system of clause 19, wherein the second execution pipeline is configured to:

[0217] executing the first conditional instruction;

[0218] determining that the prediction of the first conditional instruction is a misprediction; and

[0219] In response to determining that the prediction of the first conditional instruction was a misprediction, an instruction is caused to be obtained for execution from a target address of the first conditional instruction.

[0220] Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to include all such variations and modifications.

Claims

1. A processor, comprising: An acquisition and decoding circuit, the acquisition and decoding circuit comprising: biased prediction circuitry configured to predict a biased prediction for a conditional instruction based on one or more previous executions of the conditional instruction, the biased prediction comprising a biased condition or an unbiased condition, wherein the biased condition indicates that a condition of the conditional instruction is always true or always false; and instruction prediction circuitry configured to provide an instruction prediction for the conditional instruction; Wherein for the execution of the conditional instruction, the acquisition and decoding circuit is configured as follows: In response to the bias prediction circuit predicting the bias condition for the execution of the conditional instruction: determining a target address of the conditional instruction; and bypassing the instruction prediction provided by instruction prediction circuitry for the conditional instruction; and providing, by instruction prediction circuitry, the instruction prediction for the conditional instruction in response to the biased prediction circuitry predicting the non-biased condition for the execution of the conditional instruction; wherein the biased prediction from the biased prediction circuitry and the instruction prediction from the instruction prediction circuitry are provided at different stages of processing of the conditional instruction in the fetch and decode circuitry.

2. The processor of claim 1 , wherein to predict the bias prediction, the bias prediction circuit is configured to: identifying a value for the conditional instruction in an offset table based on an address of the conditional instruction; and The bias prediction is provided based on the identified value in the bias table for the conditional instruction.

3. The processor of claim 2, wherein the value of the conditional instruction in the offset table is one of a plurality of values, the plurality of values ​​comprising: a first value indicating that the bias prediction circuit has not encountered a conditional instruction corresponding to an entry in the bias table corresponding to the value; a second value indicating that the condition of the conditional instruction is biased to false; a third value indicating that the condition of the conditional instruction is biased to be true; as well as A fourth value indicates that the condition of the conditional instruction is not biased.

4. The processor of claim 3 , wherein: (a) when execution of a conditional branch indicates that the condition of the conditional instruction is true or false, respectively, the value in the offset table for the conditional instruction is set from the first value to the second value or the third value, or (b) when the execution of the conditional instruction indicates that the value in the offset table for the conditional instruction does not match a result of the execution of the conditional instruction, the value in the offset table for the conditional instruction is set from the second value or the third value to the fourth value.

5. The processor of claim 1 , wherein the fetch and decode circuit is further configured to: In response to the biased prediction circuit predicting a non-biased condition, the target address of the conditional instruction is determined using the instruction prediction from the instruction prediction circuit.

6. The processor of claim 1 , wherein the fetch and decode circuit is further configured to: In response to the biased prediction circuit predicting a biased condition, the conditional instruction is re-encoded as a non-conditional instruction.

7. The processor of claim 1 , wherein the biased prediction circuit is configured to predict the biased prediction at a first level corresponding to loading the conditional instruction into a cache of the processor, and wherein the instruction prediction circuit is configured to provide the instruction prediction at a second level corresponding to fetching the conditional instruction from the cache.

8. The processor of claim 1, wherein the instruction prediction circuit comprises at least a first table and a second table, wherein the first table is indexed based on an address of a conditional instruction, and wherein the second table is indexed based on the address and prediction history of the conditional instruction.

9. The processor of claim 8, wherein a bias table of the bias prediction circuit and the first table of the instruction prediction circuit are indexed separately based on the address of the conditional instruction using different hash functions.

10. The processor of claim 1, further comprising: Instruction dispatch circuitry is configured to dispatch the conditional instruction to one of the different execution pipelines based on at least one of (a) the biased prediction from the biased prediction circuitry or (b) the instruction prediction from the instruction prediction circuitry.

11. A method comprising: using biased prediction circuitry of fetch and decode circuitry of a processor to predict a biased prediction of a condition of a conditional instruction based on one or more prior executions of the conditional instruction, wherein the condition comprises a biased condition or an unbiased condition, and wherein the biased condition indicates that the condition of the conditional instruction is predicted to be always true or always false; providing instruction prediction using instruction prediction circuitry of said fetch and decode circuitry; as well as For the execution of the conditional instruction, the following operations are performed: In response to predicting the bias condition for the execution of the conditional instruction using the bias prediction circuit: providing said instruction prediction for said conditional instruction by bypassing instruction prediction circuitry using said fetch and decode circuitry; as well as providing, by instruction prediction circuitry, the instruction prediction for the conditional instruction in response to the biased prediction circuitry predicting the non-biased condition for the execution of the conditional instruction; Wherein the biased prediction and the instruction prediction are provided at different stages of processing the conditional instruction using the fetch and decode circuitry.

12. The method of claim 11 , wherein predicting the biased prediction comprises: identifying a value in an offset table based on an address of the conditional instruction; as well as The bias prediction is provided based on the identified value of the conditional instruction in the bias table.

13. The method of claim 12, wherein a first table includes a value corresponding to the conditional instruction, and wherein the value in the first table is one of a plurality of values, the plurality of values ​​comprising: a first value indicating that the condition of the conditional instruction is strongly false; a second value indicating that the condition of the conditional instruction is weakly false; a third value indicating that the condition of the conditional instruction is weakly true; as well as A fourth value indicates that the condition of the conditional instruction is strongly true.

14. The method of claim 12, wherein the value of the conditional instruction in the offset table is one of a plurality of values, the plurality of values ​​comprising: a first value indicating that the bias prediction circuit has not encountered a conditional instruction corresponding to an entry in the bias table corresponding to the value; a second value indicating that the condition of the conditional instruction is biased to false; a third value indicating that the condition of the conditional instruction is biased to be true; as well as A fourth value indicates that the condition of the conditional instruction is not biased.

15. The method according to claim 14, comprising: (a) in response to an execution of a conditional branch indicating that the condition of the conditional instruction is true or false, respectively, changing the value in the offset table for the conditional instruction from the first value to the second value or the third value, or (b) in response to an execution of the conditional instruction indicating that the value in the offset table for the conditional instruction does not match a result of the execution of the conditional instruction, changing the value in the offset table for the conditional instruction from the second value or the third value to the fourth value.

16. The method according to claim 14, comprising: Detect saturation of the bias table; as well as In response to detecting the saturation of the offset table, at least one value in the offset table is changed from a fourth value to a first value.

17. The method according to claim 11, further comprising: In response to predicting a non-bias condition, a target address of the conditional instruction is determined using the instruction prediction from the instruction prediction circuitry.

18. The method of claim 11, wherein the predicting is performed at a first level corresponding to loading the conditional instruction into a cache of the processor, and wherein providing the instruction prediction is performed at a second level corresponding to fetching the conditional instruction from the cache.

19. A system comprising: One or more processors, each of the one or more processors comprising: An acquisition and decoding circuit, the acquisition and decoding circuit comprising: biased prediction circuitry configured to predict a biased prediction for a conditional instruction based on one or more previous executions of the conditional instruction, the biased prediction comprising a biased condition or an unbiased condition, wherein the biased condition indicates that a condition of the conditional instruction is always true or always false; and instruction prediction circuitry configured to provide an instruction prediction for the conditional instruction; Wherein for the execution of the conditional instruction, the acquisition and decoding circuit is configured as follows: In response to the bias prediction circuit predicting a bias condition for the execution of the conditional instruction: determining a target address of the conditional instruction; and bypassing the instruction prediction provided by instruction prediction circuitry for the conditional instruction; and providing, by instruction prediction circuitry, the instruction prediction for the conditional instruction in response to the biased prediction circuitry predicting the non-biased condition for the execution of the conditional instruction; wherein the biased prediction from the biased prediction circuit and the instruction prediction from the instruction prediction circuit are provided at different stages of processing the conditional instruction in the fetch and decode circuit.

20. The system of claim 19, wherein to predict the bias prediction, the bias prediction circuit is configured to: identifying a value in an offset table based on an address of the conditional instruction; as well as providing the bias prediction based on the identified value of the conditional instruction in the bias table, wherein the value for the conditional instruction in the offset table is one of a plurality of values, the plurality of values ​​comprising: a first value indicating that the bias prediction circuit has not encountered a conditional instruction corresponding to an entry in the bias table corresponding to the value; a second value indicating that the condition of the conditional instruction is biased to false; a third value indicating that the condition of the conditional instruction is biased to be true; and A fourth value indicates that the condition of the conditional instruction is not biased.

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