Display substrate, driving method thereof, and display device

Abstract

The application discloses a display substrate and a driving method thereof, and a display device, and relates to the technical field of display technology.The display substrate comprises a display area and a frame area located at least one side of the display area, the display area comprises a first display area and a second display area, and the display substrate comprises a substrate, and display signal lines, communication signal lines and compensation signal lines located at least one side of the substrate; wherein the display signal lines are used for transmitting display signals to pixel units of the display area; the communication signal lines are mutually coupled with the display signal lines to form coupling capacitances, and the communication signal lines comprise first communication signal lines, at least part of the first communication signal lines is located in the first display area, and the first communication signal lines are used for transmitting communication signals; the compensation signal lines are located in the frame area, are connected with the first communication signal lines, and are used for transmitting compensation signals to the first communication signal lines, and the compensation signals are used for inhibiting voltage fluctuation on the first communication signal lines caused by display signal fluctuation on the display signal lines and the coupling capacitances.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display substrate and its driving method, and a display device. Background Technology

[0002] The design of screen-integrated antenna coils offers advantages such as integration and thinness, making it a key research direction for the integration of display substrates and sensors. By forming coil structures through specific film layers within the display substrate, the screen can provide communication functions in addition to display capabilities, thereby enriching the content of display products and enhancing their competitiveness. Summary of the Invention

[0003] This disclosure provides a display substrate, including a display area and a border area located on at least one side of the display area. The display area includes a first display area and a second display area. The display substrate includes:

[0004] A substrate, and display signal lines, communication signal lines and compensation signal lines located on at least one side of the substrate;

[0005] The display signal line is used to transmit display signals to the pixel units of the display area;

[0006] The communication signal line is coupled to the display signal line to form a coupling capacitor, including a first communication signal line, at least a portion of which is located in the first display area, and the first communication signal line is used to transmit communication signals.

[0007] The compensation signal line is located in the frame area and connected to the first communication signal line. It is used to transmit a compensation signal to the first communication signal line. The compensation signal is used to suppress voltage fluctuations on the first communication signal line caused by display signal fluctuations on the display signal line and the coupling capacitor.

[0008] In some implementations, the compensation signal line is set independently.

[0009] In some embodiments, the display substrate further includes:

[0010] A common signal line, located in the border area, is used to transmit a common voltage signal to the common electrode of the pixel unit, and multiple pixel units share the common electrode;

[0011] The common signal line is multiplexed as the compensation signal line.

[0012] In some embodiments, the display substrate further includes:

[0013] A switching circuit, located in the frame area, has a first end connected to a control signal line, a second end connected to the first communication signal line, and a third end connected to the compensation signal line. It is used to turn on or off the connection between the first communication signal line and the compensation signal line according to the control signal input from the control signal line.

[0014] In some embodiments, the switching circuit includes:

[0015] The first transistor has its control electrode connected to the control signal line, its first electrode connected to the compensation signal line, and its second electrode connected to the first communication signal line.

[0016] In some embodiments, the pixel unit includes:

[0017] The second transistor has a control electrode connected to the scan signal line, a first electrode connected to the display signal line, and a second electrode connected to the pixel electrode of the pixel unit. It is used to control the on / off connection between the display signal line and the pixel electrode according to the scan signal input from the scan signal line.

[0018] The display substrate further includes:

[0019] The GOA circuit, located in the border area and connected to the scan signal line, is used to output the scan signal to the scan signal line;

[0020] The switching circuit is located on the side of the GOA circuit closer to the display area, and the compensation signal line is located on the side of the switching circuit closer to the display area.

[0021] In some embodiments, the display substrate includes two compensation signal lines, which are a first compensation signal line and a second compensation signal line, respectively located on opposite sides of the display area along the row direction;

[0022] In the multiple first communication signal lines extending along the row direction and arranged along the column direction, the first communication signal line in each row is connected to the first compensation signal line and the second compensation signal line.

[0023] In some embodiments, the display substrate includes two compensation signal lines, which are a first compensation signal line and a second compensation signal line, respectively located on opposite sides of the display area along the row direction;

[0024] Among the multiple first communication signal lines extending along the row direction and arranged along the column direction, the first communication signal line located in the odd-numbered row is connected to the first compensation signal line, and the first communication signal line located in the even-numbered row is connected to the second compensation signal line.

[0025] In some embodiments, the display substrate further includes:

[0026] A communication signal input terminal is located in the border area and connected to the first communication signal line, used to provide the communication signal to the first communication signal line;

[0027] The communication signal input terminal is multiplexed as the compensation signal line.

[0028] In some embodiments, the display substrate further includes: a common signal line located in the frame area for transmitting a common voltage signal to a common electrode of the pixel unit, wherein multiple pixel units share the common electrode;

[0029] The communication signal line further includes: a second communication signal line, at least a portion of which is located in the second display area;

[0030] The second communication signal line is connected to the common signal line.

[0031] This disclosure provides a display device, including:

[0032] The display substrate as described in any embodiment;

[0033] A driving circuit is configured to provide a driving signal to the display substrate, the driving signal including the display signal, the communication signal, and the compensation signal; and

[0034] A power supply circuit is configured to provide power to the display substrate.

[0035] This disclosure provides a driving method for a display substrate, applied to a display substrate as described in any embodiment, the driving method comprising:

[0036] A display signal is provided to the display signal line to drive the display area to display an image;

[0037] A communication signal is provided to the first communication signal line so that the first communication signal line transmits the communication signal.

[0038] A compensation signal is provided to the compensation signal line so that the compensation signal is transmitted to the first communication signal line to suppress voltage fluctuations on the first communication signal line caused by display signal fluctuations on the display signal line and the coupling capacitor.

[0039] In some implementations, the compensation signal is a DC regulated signal.

[0040] In some embodiments, the step of providing a display signal to the display signal line includes:

[0041] During the refresh display phase, a refresh display signal is provided to the display signal line to drive the display area to refresh the display screen; and

[0042] During the display hold phase, a display hold signal is provided to the display signal line to keep the display area displaying the image.

[0043] When the display substrate further includes a switching circuit, and the switching circuit is connected to the control signal line, the first communication signal line, and the compensation signal line respectively, after the step of providing a compensation signal to the compensation signal line, the method further includes:

[0044] During the first conduction phase, a conduction signal is provided to the control signal line to enable the switching circuit to connect the first communication signal line and the compensation signal line.

[0045] In the first disconnection phase, a shutdown signal is provided to the control signal line to cause the switching circuit to disconnect the connection between the first communication signal line and the compensation signal line;

[0046] The first conduction phase includes: a refresh display phase in the non-communication state, and a start and end phase of the maintain display phase in the non-communication state.

[0047] The first disconnection phase includes: an intermediate segment of the display holding phase in non-communication state, a refresh display phase in communication state, and a display holding phase in communication state.

[0048] In some implementations, the compensation signal is an AC signal, and the AC signal is out of phase with the voltage fluctuation.

[0049] In some implementations, the amplitude of the AC signal is equal to that of the voltage fluctuation.

[0050] In some embodiments, the frequency of the compensation signal is less than or equal to the scanning frequency of the display substrate, wherein the scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal lines in the display substrate.

[0051] In some embodiments, the step of providing a display signal to the display signal line includes:

[0052] During the refresh display phase, a refresh display signal is provided to the display signal line to drive the display area to refresh the display screen; and

[0053] During the display hold phase, a display hold signal is provided to the display signal line to keep the display area displaying the image.

[0054] When the display substrate further includes a switching circuit, and the switching circuit is connected to the control signal line, the first communication signal line, and the compensation signal line respectively, after the step of providing a compensation signal to the compensation signal line, the method further includes:

[0055] During the second conduction phase, a conduction signal is provided to the control signal line to enable the switching circuit to connect the first communication signal line and the compensation signal line.

[0056] In the second disconnection phase, a shutdown signal is provided to the control signal line to cause the switching circuit to disconnect the connection between the first communication signal line and the compensation signal line;

[0057] The second conduction phase includes: the refresh display phase and the start and end segments of the hold display phase;

[0058] The second disconnection phase includes: the middle segment of the display holding phase.

[0059] In some embodiments, the communication signal includes a high-frequency signal, the frequency of which is greater than the scanning frequency of the display substrate, the scanning frequency being the product of the frame refresh frequency of the display substrate and the number of scan signal lines in the display substrate.

[0060] In some embodiments, the step of providing the display signal to the display signal line includes:

[0061] During the refresh display phase, a refresh display signal is provided to the display signal line to drive the display area to refresh the display screen; and

[0062] During the display hold phase, a display hold signal is provided to the display signal line to keep the display area displaying the image.

[0063] The step of providing a communication signal to the first communication signal line includes:

[0064] During the refresh display phase and the hold display phase, the high-frequency signal is provided to the first communication signal line; or

[0065] The high-frequency signal is provided to the first communication signal line during the middle segment of the display phase in the non-communication state, the refresh display phase in the communication state, and the display holding phase in the communication state.

[0066] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure are described below. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0068] Figure 1 A schematic diagram of a planar structure of a display substrate provided in this disclosure is shown;

[0069] Figure 2 A schematic diagram of the first display substrate connection structure provided in this disclosure is shown;

[0070] Figure 3 A schematic diagram of the second display substrate connection structure provided in this disclosure is shown;

[0071] Figure 4a A schematic diagram of the third type of display substrate connection structure provided in this disclosure is shown;

[0072] Figure 4b A schematic diagram of the fourth display substrate connection structure provided in this disclosure is shown;

[0073] Figure 5 A schematic diagram of the fifth type of display substrate connection structure provided in this disclosure is shown;

[0074] Figure 6 A cross-sectional structural schematic diagram and a planar layout of a display substrate provided in this disclosure are shown;

[0075] Figure 7 A cross-sectional structural schematic diagram and a planar layout of another display substrate provided in this disclosure are shown;

[0076] Figure 8 This illustration shows a planar layout of a display substrate at the junction of the display area and the bezel area provided in this disclosure;

[0077] Figure 9 A timing diagram of the driving signals for the first type of display substrate provided in this disclosure is shown;

[0078] Figure 10A timing diagram of the driving signals for the second type of display substrate provided in this disclosure is shown;

[0079] Figure 11 A timing diagram of the driving signals for the third type of display substrate provided in this disclosure is shown;

[0080] Figure 12 A timing diagram of the driving signals for the fourth type of display substrate provided in this disclosure is shown;

[0081] Figure 13 A schematic diagram of the connection structure of a GOA circuit provided in this disclosure is shown. Detailed Implementation

[0082] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0083] This disclosure provides a display substrate, with reference to... Figure 1 A schematic diagram of the planar structure of the display substrate is shown, as follows. Figure 1 As shown, the display substrate includes a display area 10 and a border area 11 located on at least one side of the display area 10. The display area 10 includes a first display area 101 and a second display area 102.

[0084] The border area 11 can be located on one side, two sides, three sides, or all four sides of the display area 10 (e.g., ...). Figure 1 (As shown), this disclosure does not limit it.

[0085] In specific implementations, the display area 10 may include one or more first display areas 101 and one or more second display areas 102. Figure 1 In the middle, the display area 10 includes a first display area 101 and two second display areas 102, with the two second display areas 102 located on both sides of the first display area 101.

[0086] For example, such as Figure 1 As shown, the first display area 101 is U-shaped. The U-shaped first display area 101 can form a closed coil with the lines located on the printed circuit board, which helps to improve the sensitivity of the coil.

[0087] like Figures 2 to 5As shown in any one of them, the display substrate includes: a substrate 20, and a display signal line 21, a communication signal line 22, and a compensation signal line 23 located on at least one side of the substrate 20.

[0088] like Figures 2 to 5 As shown in any one of the figures, the display signal line 21 is used to transmit display signals to the pixel unit P within the display area 10. Exemplarily, the display signal line 21 can be connected to a display signal input terminal Vs located within the border area 11 (on the DP side as shown), the display signal input terminal Vs being used to provide display signals to the display signal line 21.

[0089] like Figures 2 to 5 As shown in any one of the diagrams, the communication signal line 22 and the display signal line 21 are coupled to form a coupling capacitor. The communication signal line 22 includes a first communication signal line 221, at least a portion of which is located in the first display area 101. The first communication signal line 221 is used to transmit communication signals, thereby enabling the first display area 101 to have functions such as Near Field Communication (NFC). For example, the first communication signal line 221 can be connected to a communication signal input terminal Vnfc located in the bezel area 11 (the DO side as shown in the diagram). The communication signal input terminal Vnfc is used to provide communication signals to the first communication signal line 221.

[0090] like Figures 2 to 5 As shown in any one of the figures, the compensation signal line 23 is located in the frame region 11 and connected to the first communication signal line 221. It is used to transmit a compensation signal to the first communication signal line 221, which is used to suppress voltage fluctuations on the first communication signal line 221 caused by display signal fluctuations and coupling capacitance on the display signal line 21. Exemplarily, the compensation signal line 23 can be connected to a compensation signal input terminal Vcp located within the frame region 11 (on the DP side as shown). The compensation signal input terminal Vcp is used to provide a compensation signal to the compensation signal line 23.

[0091] In a specific implementation, a display signal can be provided to the display signal line 21 to drive the display area 10 to display the image; a communication signal can be provided to the first communication signal line 221 to enable the first communication signal line 221 to transmit the communication signal; and a compensation signal can be provided to the compensation signal line 23 to enable the compensation signal to be transmitted to the first communication signal line 221 to suppress the voltage fluctuation on the first communication signal line 221 caused by the display signal fluctuation on the display signal line 21 and the coupling capacitance.

[0092] During the display of the image in the first display area 101, due to the display signal (such as...) on the display signal line 21 Figures 9 to 12As shown in the figure, Vs changes continuously, and due to the coupling capacitance between the display signal line 21 and the first communication signal line 221, a low-frequency voltage fluctuation (such as Vs) will be superimposed on the communication signal on the first communication signal line 221. Figures 9 to 12 As shown in V221, V211 is the voltage signal on the first communication signal line 221 that has not been compensated by the compensation signal.

[0093] Based on the principle of capacitive coupling and considering the influence of the main coupling capacitor, the voltage fluctuation ΔVn on the first communication signal line 221 can be calculated as follows:

[0094] △Vn=(V2-V1)*C ns / (C ns +C np +C nc ),

[0095] Where V1 is the initial voltage on display signal line 21, V2 is the changed voltage on display signal line 21, and C ns To show the coupling capacitance between signal line 21 and communication signal line 22, C np C is the coupling capacitance between the pixel electrode Ep and the communication signal line 22. nc This is the coupling capacitance between the common electrode Ec and the communication signal line 22. The voltage difference between the common electrode Ec and the pixel electrode Ep can drive the liquid crystal molecules at the corresponding positions to deflect, thereby controlling the transmittance at that location. Multiple pixel units P located in the display area 10 can share the common electrode Ec.

[0096] Due to the coupling capacitance C between the pixel electrode Ep and the communication signal line 22 np The voltage fluctuation ΔVn on the first communication signal line 221 causes a voltage fluctuation on the pixel electrode Ep. Based on the voltage fluctuation ΔVn on the first communication signal line 221, the voltage fluctuation ΔVp on the pixel electrode Ep can be calculated as follows:

[0097] △Vp=△Vn*C np / (C np +C pc ),

[0098] Among them, C pc This is the coupling capacitance between the common electrode Ec and the pixel electrode Ep. The inventors tested a 5.65-inch display substrate and measured the voltage fluctuation ΔVn on the first communication signal line 221 to be approximately 0.5V.

[0099] When the voltage fluctuation ΔVp on the pixel electrode Ep exceeds a certain value, the grayscale of the first display area 101 and the second display area 102 may be inconsistent under a certain screen, making the first display area 101 visible to the naked eye.

[0100] The display substrate provided in this disclosure reduces or eliminates voltage fluctuations on the pixel electrode Ep by providing a compensation signal line 23 in the bezel region 11. The compensation signal line 23 provides a compensation signal to the first communication signal line 221 that can suppress voltage fluctuations caused by display signal fluctuations and coupling capacitance. Figures 9 to 12 As shown in V221' (V211' is the voltage signal on the first communication signal line 221 after compensation by the compensation signal), it reduces the display difference between the first display area 101 and the second display area 102, and improves the display uniformity of the display area 10.

[0101] In specific implementation, the first communication signal line 221 and the compensation signal line 23 can be set on the same layer or on different layers, and this disclosure does not limit this.

[0102] In some implementations, such as Figures 2 to 5 As shown in any one of the illustrations, the display substrate further includes: a common signal line 24 located in the bezel area 11, used to transmit a common voltage signal to the common electrode Ec of the pixel unit P, wherein multiple pixel units P share the common electrode Ec. The communication signal line 22 further includes: a second communication signal line 222, at least a portion of which is located in the second display area 102. The second communication signal line 222 is connected to the common signal line 24.

[0103] For example, the common signal line 24 can be connected to the common signal input terminal Vcom located within the frame area 11 (DP side as shown in the figure), and the common signal input terminal Vcom is used to provide a common voltage signal to the common signal line 24.

[0104] Since the common electrode Ec is distributed across the entire surface and the common voltage signal is generally a constant value (such as a value between 0 and -2V), even if there is a coupling capacitor between the second communication signal line 222 and the display signal line 21, the voltage on the second communication signal line 222 is difficult to be driven by the display signal. Therefore, it can ensure the stability of the voltage of the second communication signal line 222 and the pixel electrode Ep, thereby ensuring the stability of the display effect of the second display area 102.

[0105] In specific implementation, the second communication signal line 222 and the common signal line 24 can be set on the same layer or on different layers, and this disclosure does not limit this.

[0106] like Figures 2 to 5 As shown in any one of the examples, in the display area 10, multiple communication signal lines 22 can be arranged to intersect each other to form a grid structure, and the intersecting communication signal lines 22 are connected to each other at the intersection positions.

[0107] In some implementations, such as Figure 2 As shown, the compensation signal line 23 is set independently (e.g. Figure 2 (As shown). In this embodiment, the compensation signal line 23 is set independently of other signal lines (such as the common signal line 24), which helps to maintain the signal stability on other signal lines (such as the common signal line 24).

[0108] In actual driving process, a compensation signal with the opposite phase and the same amplitude as the voltage fluctuation ΔVn on the first communication signal line 221 can be provided to the compensation signal line 23.

[0109] In some implementations, such as Figure 3 As shown, the common signal line 24 is multiplexed as the compensation signal line 23. Accordingly, the common voltage signal on the common signal line 24 is multiplexed as the compensation signal.

[0110] By multiplexing the common signal line 24 into a compensation signal line 23, that is, connecting the first communication signal line 221 to the common signal line 24, since the common voltage signal transmitted on the common signal line 24 is generally a constant value, the voltage on the first communication signal line 221 is difficult to be driven by the display signal. Therefore, it can ensure the stability of the voltage of the first communication signal line 221 and the pixel electrode Ep, thereby ensuring the stability of the display effect of the first display area 101.

[0111] In addition, Figure 3 Since both the first communication signal line 221 and the second communication signal line 222 are connected to the common signal line 24, this can minimize the display difference between the first display area 101 and the second display area 102, and further improve the display uniformity of the display area 10.

[0112] In addition, by multiplexing the common signal line 24 as the compensation signal line 23, there is no need to arrange the compensation signal line 23 separately, which can save space in the border area 11 and is conducive to achieving a narrow border.

[0113] In specific implementation, the compensation signal line 23 and the first communication signal line 221 can be directly connected and always remain connected. Alternatively, a switching circuit can be set between the compensation signal line 23 and the first communication signal line 221 to control their connection and disconnection.

[0114] In some implementations, such as Figure 2 or Figure 3 As shown, the display substrate also includes a switch circuit 29 located in the frame area 11, which includes a first end, a second end and a third end. The first end is connected to the control signal line 210, the second end is connected to the first communication signal line 221, and the third end is connected to the compensation signal line 23. It is used to turn on or off the connection between the first communication signal line 221 and the compensation signal line 23 according to the control signal input by the control signal line 210.

[0115] By setting the switching circuit 29 and matching a specific control signal timing, the conduction and cutoff between the first communication signal line 221 and the compensation signal line 23 can be controlled in a time-division manner, which greatly reduces the visibility time of the first display area 101, improves the display effect of the display area 10, and realizes the normal communication function of the first display area 101.

[0116] In specific implementation, a switching circuit 29 may be connected to one or more first communication signal lines 221, and this disclosure does not limit this.

[0117] In some implementations, such as Figure 2 or Figure 3 As shown, the switching circuit 29 includes: a first transistor T1, the control terminal of the first transistor T1 (i.e., the first end of the switching circuit 29) is connected to the control signal line 210, the first terminal of the first transistor T1 (i.e., the third end of the switching circuit 29) is connected to the compensation signal line 23, and the second terminal of the first transistor T1 (i.e., the second end of the switching circuit 29) is connected to the first communication signal line 221.

[0118] The first transistor T1 can be an N-type transistor or a P-type transistor, etc., and this disclosure does not limit it.

[0119] In some implementations, such as Figure 2 or Figure 3 As shown, the pixel unit P includes a second transistor T2. The control electrode of the second transistor T2 is connected to the scan signal line 25, the first electrode of the second transistor T2 is connected to the display signal line 21, and the second electrode of the second transistor T2 is connected to the pixel electrode Ep of the pixel unit P. This is used to control the on / off state between the display signal line 21 and the pixel electrode Ep according to the scan signal input from the scan signal line 25. The display substrate also includes a GOA circuit 111, located in the bezel area 11 and connected to the scan signal line 25, used to output a scan signal to the scan signal line 25. The switching circuit 29 is located in the bezel area 11, on the side of the GOA circuit 111 closest to the display area 10. The compensation signal line 23 can be located on the side of the switching circuit 29 closest to the display area 10 (e.g., ...). Figure 2 and Figure 3 As shown, it can also be located on the side of the switch circuit 29 close to the GOA circuit 111.

[0120] Reference Figure 8 This diagram illustrates a design layout of a display substrate at the junction of the display area and the bezel area. Figure 2 or Figure 8In this configuration, the common signal line 24, the compensation signal line 23, the switching circuit 29, and the control signal line 210 are arranged sequentially between the display area 10 and the GOA circuit 111. The common signal line 24 is positioned closer to the display area 10, and the control signal line 210 is positioned closer to the GOA circuit 111.

[0121] exist Figure 3 In this circuit, the common signal line 24 and the compensation signal line 23 share a single signal line, and the common signal line 24, the switching circuit 29, and the control signal line 210 are arranged sequentially between the display area 10 and the GOA circuit 111. The common signal line 24 is positioned closer to the display area 10, and the control signal line 210 is positioned closer to the GOA circuit 111.

[0122] For example, such as Figure 2 or Figure 3 As shown, the GOA circuit 111 can be connected to the gate drive signal input terminal Vgoa located within the frame region 11 (DP side as shown in the figure). The gate drive signal input terminal Vgoa is used to provide the gate drive signal to the GOA circuit 111.

[0123] The second transistor T2 can be an N-type transistor or a P-type transistor, etc., and this disclosure does not limit it. The first transistor T1 and the second transistor T2 can be formed simultaneously.

[0124] In some implementations, such as Figures 2 to 4a As shown in any one of the illustrations, compensation signal lines 23 are provided on both sides of the display substrate, that is, the compensation signal lines 23 are provided on both sides of the display area 10. For example, the display substrate includes two compensation signal lines 23, namely a first compensation signal line 231 and a second compensation signal line 232, which are respectively located on opposite sides of the display area 10 along the row direction (e.g., ...). Figures 2 to 4a (The left and right sides of display area 10).

[0125] In some implementations, such as Figure 2 or Figure 3 As shown, among the multiple first communication signal lines 221 extending along the row direction and arranged along the column direction, the first communication signal line 221 in each row is connected to both the first compensation signal line 231 and the second compensation signal line 232. That is, for each row of first communication signal lines 221, both the first compensation signal line 231 and the second compensation signal line 232 are connected.

[0126] exist Figure 2 or Figure 3In the display area 10, the first communication signal line 221 is connected to the compensation signal line 23 via a switching circuit 29, and the switching circuit 29 includes a first transistor T1. In the left border area 11 of the display area 10, the first electrode of the first transistor T1 is connected to the first compensation signal line 231, the second electrode is connected to the corresponding row of the first communication signal line 221, and the control electrode is connected to the left-side control signal line 210. In the right border area 11 of the display area 10, the first electrode of the first transistor T1 is connected to the second compensation signal line 232, the second electrode is connected to the corresponding row of the first communication signal line 221, and the control electrode is connected to the right-side control signal line 210.

[0127] In order to make reasonable use of the space in the border area 11, such as Figure 4a or Figure 8 As shown, among the multiple first communication signal lines 221 extending along the row direction and arranged along the column direction, the first communication signal lines 221 located in odd-numbered rows (such as...) Figure 8 The odd-numbered 221 shown is connected to the first compensation signal line 231, and the first communication signal line 221 located in the even-numbered row (as shown) is connected to the first compensation signal line 231. Figure 8 The even number 221 shown is connected to the second compensation signal line 232.

[0128] exist Figure 4a In the display area 10, the first communication signal line 221 is connected to the compensation signal line 23 via a switching circuit 29, and the switching circuit 29 includes a first transistor T1. Within the left border area 11 of the display area 10, the first electrode of the first transistor T1 is connected to the first compensation signal line 231, the second electrode is connected to the first communication signal line 221 in the odd-numbered rows, and the control electrode is connected to the control signal line 210 on the left side. Within the right border area 11 of the display area 10, the first electrode of the first transistor T1 is connected to the second compensation signal line 232, the second electrode is connected to the first communication signal line 221 in the even-numbered rows, and the control electrode is connected to the control signal line 210 on the right side.

[0129] In some embodiments, a compensation signal line 23 is provided on one side of the display substrate, that is, the compensation signal line 23 is provided on one side of the display area 10. For example, as shown... Figure 4b As shown, the display substrate includes a compensation signal line 23, which is located on the right side of the display area 10.

[0130] like Figure 4bAs shown, among the multiple first communication signal lines 221 extending along the row direction and arranged along the column direction, the first communication signal line 221 in each row is connected to the compensation signal line 23. The first communication signal line 221 is connected to the compensation signal line 23 through a switching circuit 29, and the switching circuit 29 includes a first transistor T1. In the border area 11 located on the right side of the display area 10, the first electrode of the first transistor T1 is connected to the compensation signal line 23, the second electrode is connected to the first communication signal line 221 of the corresponding row, and the control electrode is connected to the control signal line 210.

[0131] In some implementations, such as Figures 2 to 4a As shown in any one of the diagrams, the display substrate includes two common signal lines 24, which are a first common signal line 241 and a second common signal line 242, respectively. The first common signal line 241 and the second common signal line 242 are located on opposite sides of the display area 10 along the row direction (e.g., ...). Figures 2 to 4a (The left and right sides of display area 10).

[0132] In some implementations, such as Figure 2 or Figure 3 As shown, among the multiple second communication signal lines 222 extending along the row direction and arranged along the column direction, the second communication signal line 222 in each row is connected to both the first common signal line 241 and the second common signal line 242. That is, for each row of second communication signal lines 222, both the first common signal line 241 and the second common signal line 242 are connected.

[0133] In order to make reasonable use of the space in the border area 11, such as Figure 4a As shown, among the multiple second communication signal lines 222 extending along the row direction and arranged along the column direction, the second communication signal lines 222 located in odd-numbered rows (such as...) Figure 8 The odd-numbered 222 shown is connected to the first common signal line 241, and the second communication signal line 222 located in the even-numbered row (as shown) is connected to the first common signal line 241. Figure 8 The even number 222 shown is connected to the second common signal line 242.

[0134] To improve the aperture ratio, in some embodiments, as shown in 2, the communication signal line 22 has a first extension 26, the extension direction of the first extension 26 is parallel to the extension direction of the display signal line 21, and in a first direction, the orthographic projection of the first extension 26 on the substrate 20 at least partially overlaps with the orthographic projection of the display signal line 21 on the substrate 20, and the first direction is perpendicular to the extension direction of the display signal line 21.

[0135] Wherein, the orthographic projection of the first extension 26 on the substrate 20 at least partially overlaps with the orthographic projection of the display signal line 21 on the substrate 20, including: the orthographic projection of the first extension 26 on the substrate 20 covering the orthographic projection of the display signal line 21 on the substrate 20, and the orthographic projection of the display signal line 21 on the substrate 20 covering the orthographic projection of the first extension 26 on the substrate 20 (e.g., Figure 6 and Figure 7 (As shown), or the orthographic projection of the first extension 26 on the substrate 20 completely overlaps with the orthographic projection of the display signal line 21 on the substrate 20.

[0136] in, Figure 6 Figure a shows a schematic diagram of a partial cross-sectional structure of a display substrate in the display area. Figure 6 Figure b in the figure shows a schematic diagram of a partial planar structure of the display substrate in the display area. Figure 7 Figure a shows a schematic diagram of a partial cross-sectional structure of another display substrate in the display area. Figure 7 Figure b in the figure shows a schematic diagram of a partial planar structure of the display substrate in the display area.

[0137] To increase the opening ratio, in some implementations, such as Figure 2 As shown, the display substrate also includes a scan signal line 25, which is used to transmit scan signals to pixel units P. The communication signal line 22 has a second extension 27, the extension direction of which is parallel to the extension direction of the scan signal line 25. In a second direction, the orthographic projection of the second extension 27 on the substrate 20 at least partially overlaps with the orthographic projection of the scan signal line 25 on the substrate 20. The second direction is perpendicular to the extension direction of the scan signal line 25.

[0138] Wherein, the orthographic projection of the second extension 27 on the substrate 20 and the orthographic projection of the scan signal line 25 on the substrate 20 at least partially overlap, including: the orthographic projection of the second extension 27 on the substrate 20 covering the orthographic projection of the scan signal line 25 on the substrate 20, the orthographic projection of the scan signal line 25 on the substrate 20 covering the orthographic projection of the second extension 27 on the substrate 20, or the orthographic projection of the second extension 27 on the substrate 20 completely overlapping the orthographic projection of the scan signal line 25 on the substrate 20.

[0139] The first direction and the second direction intersect each other. For example, in... Figure 2 In the middle, the first direction and the second direction are perpendicular to each other. The first direction is the extension direction of the scan signal line 25 (such as the row direction), and the second direction is the extension direction of the display signal line 21 (such as the column direction).

[0140] It should be noted that, in the first direction, the orthographic projection of the first extension 26 on the substrate 20 and the orthographic projection of the display signal line 21 on the substrate 20 may not overlap. In the second direction, the orthographic projection of the second extension 27 on the substrate 20 and the orthographic projection of the scan signal line 25 on the substrate 20 may not overlap (e.g., Figure 6 and Figure 7 (As shown). To visually illustrate the communication signal line 22, the scanning signal line 25, and the display signal line 21, Figures 2 to 5 The communication signal line 22 shown is displayed in a non-overlapping manner with the scanning signal line 25 and the display signal line 21.

[0141] In some implementations, such as Figure 2 As shown, the communication signal line 22 has a bend 28, which is used to avoid the second transistor T2 in the pixel unit P. This avoids the potential film breakage problem caused by excessive film thickness at the location of the second transistor T2. Furthermore, a spacer can be placed at the location of the second transistor T2 to support the cell thickness of the liquid crystal display substrate. The bend 28 prevents excessive cell thickness at the location of the second transistor T2, thus avoiding uneven display.

[0142] The bent portion 28 can be connected between two adjacent first extension portions 26 (e.g., Figure 2 (as shown), or connected between two adjacent second extensions 27, which is not limited in this disclosure.

[0143] In some implementations, such as Figure 5 As shown, the display substrate also includes a communication signal input terminal Vnfc, located in the bezel area 11, connected to the first communication signal line 221, and used to provide communication signals to the first communication signal line 221. The communication signal input terminal Vnfc is multiplexed as a compensation signal line 23.

[0144] In a specific implementation, a superimposed signal of compensation signal and communication signal can be provided to the communication signal input terminal Vnfc. The communication signal input terminal Vnfc transmits the compensation signal and communication signal to the first communication signal line 221. The compensation signal can suppress the communication signal fluctuation caused by the display signal fluctuation of the display signal line 21 and the coupling capacitance on the first communication signal line 221, thereby avoiding voltage fluctuation on the pixel electrode Ep, reducing the display difference between the first display area 101 and the second display area 102, and improving the display uniformity of the display area 10.

[0145] By multiplexing the communication signal input terminal Vnfc as the compensation signal line 23, on the one hand, wiring can be reduced, thereby saving space in the bezel area and helping to achieve a narrow bezel. On the other hand, it can avoid the fluctuation of the common voltage signal caused by the connection of the first communication signal line 221 and the common signal line 24, ensuring the stability of the electric field between the common electrode Ec and the pixel electrode Ep, and preventing the liquid crystal molecules from undergoing rhythmic orientation changes, thus ensuring the stable display effect of the display area.

[0146] In some implementations, such as Figure 6 or Figure 7 As shown, the first transistor T1 and the second transistor T2 include a gate G, a gate insulating layer GI, an active layer ACT, and source / drain electrodes SD stacked sequentially. The gate G is disposed close to the substrate 20, and the source / drain electrodes SD include a source S and a drain D. One of the first electrode and the second electrode is the source S, and the other is the drain D. The control electrode is the gate G.

[0147] In some embodiments, the display substrate provided in this disclosure can be fabricated using a 7Mask process. (See also...) Figure 6 The 7Mask process includes 7 patterning processes, which may specifically include the following steps:

[0148] Step S01: Using the first patterning process, a first metal layer 61 is prepared on the substrate 20. The first metal layer 61 may include a gate G, a scan signal line 25 and a control signal line 210. The scan signal line 25 is interconnected with the gate G of the second transistor T2, and the control signal line 210 is interconnected with the gate G in the first transistor T1.

[0149] Step S02: Prepare a gate insulating layer GI on the side of the first metal layer 61 that is away from the substrate 20;

[0150] Step S03: Using the second patterning process, the active layer ACT is fabricated on the side of the gate insulating layer GI that is away from the substrate 20;

[0151] Step S04: Using the third patterning process, a pixel electrode Ep is fabricated on the side of the active layer ACT that is away from the substrate 20;

[0152] Step S05: Using the fourth patterning process, a second metal layer 62 is fabricated on the side of the pixel electrode Ep facing away from the substrate 20. The second metal layer 62 may include source and drain electrodes SD, display signal line 21, compensation signal line 23 and common signal line 24. The display signal line 21 is connected to the first electrode of the second transistor T2, the second electrode of the second transistor T2 is connected to the pixel electrode Ep, and the compensation signal line 23 is connected to the first electrode of the first transistor T1.

[0153] Step S06: Prepare a first passivation layer 63 on the side of the second metal layer 62 that is away from the substrate 20;

[0154] Step S07: Using the fifth patterning process, a third metal layer 64 is prepared on the side of the first passivation layer 63 away from the substrate 20. The third metal layer 64 may include a first communication signal line 221 and a second communication signal line 222. The first communication signal line 221 extends to the frame region 11 and is connected to the second electrode in the first transistor T1 through a via. The second communication signal line 222 extends to the frame region 11 and is connected to the common signal line 24 through a via.

[0155] Step S08: Using the sixth patterning process, a second passivation layer 65 is prepared on the side of the third metal layer 64 facing away from the substrate 20, and a via is provided on the second passivation layer 65.

[0156] Step S09: Using the seventh patterning process, a common electrode Ec is fabricated on the side of the second passivation layer 65 away from the substrate 20. The common electrode Ec extends to the frame region 11 and is connected to the common signal line 24 through a via.

[0157] Display substrates prepared using the 7Mask process, such as Figure 6 As shown, the thickness of the communication signal line 22 (such as copper wire) can be greater than or equal to the thickness of the copper wire. and less than or equal to For example, it can be...

[0158] In some embodiments, the display substrate provided in this disclosure can be fabricated using a 9Mask process. (See also...) Figure 7 The 9Mask process includes 9 patterning steps, which may specifically include the following steps:

[0159] Step S11: Using the first patterning process, a first metal layer 61 is prepared on the substrate 20. The first metal layer 61 may include a gate G, a scan signal line 25 and a control signal line 210. The scan signal line 25 is interconnected with the gate G of the second transistor T2, and the control signal line 210 is interconnected with the gate G in the first transistor T1.

[0160] Step S12: Prepare a gate insulating layer GI on the side of the first metal layer 61 that faces away from the substrate 20;

[0161] Step S13: Using the second patterning process, the active layer ACT is fabricated on the side of the gate insulating layer GI that is away from the substrate 20;

[0162] Step S14: Using the third patterning process, a second metal layer 62 is prepared on the side of the active layer ACT away from the substrate 20. The second metal layer 62 may include source and drain electrodes SD, display signal line 21, compensation signal line 23 and common signal line 24. The display signal line 21 is connected to the first electrode of the second transistor T2, and the compensation signal line 23 is connected to the first electrode of the first transistor T1.

[0163] Step S15: Prepare a first passivation layer 63 on the side of the second metal layer 62 that is away from the substrate 20;

[0164] Step S16: Using the fourth patterning process, a third metal layer 64 is prepared on the side of the first passivation layer 63 away from the substrate 20. The third metal layer 64 may include a first communication signal line 221 and a second communication signal line 222. The first communication signal line 221 extends to the frame region 11 and is connected to the second electrode in the first transistor T1 through a via. The second communication signal line 222 extends to the frame region 11 and is connected to the common signal line 24 through a via.

[0165] Step S17: Using the fifth patterning process, form vias on the first passivation layer 63;

[0166] Step S18: Prepare a buffer layer 66 on the side of the third metal layer 64 facing away from the substrate 20;

[0167] Step S19: Using the sixth patterning process, a planarization layer 67 is prepared on the side of the buffer layer 66 facing away from the substrate 20, and a via is provided on the planarization layer 67.

[0168] Step S20: Using the seventh patterning process, a pixel electrode Ep is fabricated on the side of the planarization layer 67 away from the substrate 20. The pixel electrode Ep is connected to the second electrode of the second transistor T2 through a via.

[0169] Step S110: Using the eighth patterning process, a second passivation layer 65 is prepared on the side of the pixel electrode Ep away from the substrate 20, and a via is provided on the second passivation layer 65.

[0170] Step S111: Using the ninth patterning process, a common electrode Ec is fabricated on the side of the second passivation layer 65 away from the substrate 20. The common electrode Ec extends to the frame region 11 and is connected to the common signal line 24 through a via.

[0171] Display substrates prepared using the 9Mask process, such as Figure 7 As shown, the thickness of the communication signal line 22 (such as copper wire) can be greater than or equal to the thickness of the copper wire. and less than or equal to For example, it can be... Compared to the 7Mask process, the 9Mask process can produce communication signal lines 22 with greater thickness.

[0172] In specific implementations, the pixel electrode Ep and the common electrode Ec can be made of transparent conductive materials, such as indium tin oxide, etc., and this disclosure does not limit this. The first metal layer 61, the second metal layer 62 and the third metal layer 64 can be made of metal materials such as copper, aluminum, molybdenum, magnesium, silver, etc.

[0173] The following describes several specific implementation methods for display substrates.

[0174] In the first implementation, such as Figure 3 As shown, the common signal line 24 is multiplexed into the compensation signal line 23, meaning the compensation signal, which is also the common voltage signal, is a DC regulated signal. In this embodiment, a switching circuit 29 is provided between the first communication signal line 221 and the compensation signal line 23, and the switching circuit 29 controls the on / off state between the first communication signal line 221 and the compensation signal line 23.

[0175] Reference Figure 9 A timing diagram of each signal in the first embodiment is shown. This timing diagram is illustrated using the example of the first transistor T1 being an N-type transistor. Specifically, V211 is the voltage signal on the first communication signal line 221 before compensation, V211' is the voltage signal on the first communication signal line 221 after compensation, Vg1 is the control signal on the control signal line 210, Vcom is the common voltage signal on the common signal line 24, and Vs is the display signal on the display signal line 21.

[0176] like Figure 9 As shown, a conduction signal can be provided to the control signal line 210 during the first conduction phase (e.g., ...). Figure 9 The high-level signal in Vg1 shown is used to enable the switching circuit 29 to connect the first communication signal line 221 and the compensation signal line 23; in the first disconnection phase, a turn-off signal (such as...) is provided to the control signal line 210. Figure 9 The low-level signal in Vg1 shown causes the switching circuit 29 to disconnect the connection between the first communication signal line 221 and the compensation signal line 23.

[0177] The first disconnection phase can include the entire period of the communication state. That is, in the communication state, disconnecting the connection between the first communication signal line 221 and the compensation signal line 23 (such as the common signal line 24) can prevent the DC regulated signal from affecting the communication signal on the first communication signal line 221, thereby ensuring the normal communication function.

[0178] The first disconnection phase may also include a period of time in the non-communication state. That is, in the non-communication state, by disconnecting the connection between the first communication signal line 221 and the compensation signal line 23 (such as the common signal line 24), on the one hand, the DC regulated signal can be prevented from affecting the communication signal on the first communication signal line 221, thereby ensuring that the first communication signal line 221 can realize the function of scanning cards. On the other hand, the performance degradation caused by the first transistor T1 in the switching circuit 29 being in the conducting state for a long time can be avoided, thereby improving the performance stability of the switching circuit 29.

[0179] The first conduction phase may include another period of time in the non-communication state. That is, in the non-communication state, by conducting the connection between the first communication signal line 221 and the compensation signal line 23 (such as the common signal line 24), the voltage shift caused by the pull of the first communication signal line 221 by external display signals can be suppressed, thereby avoiding voltage shift on the pixel electrode Ep and improving the display uniformity of the display area 10.

[0180] In practice, during the refresh display phase, a refresh display signal can be provided to the display signal line 21 to drive the display area 10 to refresh the display screen; and during the hold display phase (Blanking period), a hold display signal can be provided to the display signal line 21 to keep the display area 10 displaying the screen.

[0181] During the display holding phase, the second transistor T2 in the pixel unit P is in the off state, that is, the display signal line 21 is disconnected from the pixel electrode Ep, and the charging and discharging of the pixel electrode Ep is stopped. Therefore, the display area 10 maintains the display image during this period.

[0182] Accordingly, the first conduction phase may include: a refresh display phase in the non-communication state and a start and end segment of the hold display phase in the non-communication state. The first disconnection phase includes: an intermediate segment of the hold display phase in the non-communication state and the entire time period in the communication state, the entire time period in the communication state including: a refresh display phase in the communication state and a hold display phase in the communication state.

[0183] During the middle of the display phase, since the display signal on the display signal line 21 remains basically unchanged, the voltage fluctuation on the first communication signal line 221 caused by the fluctuation of the display signal can be ignored. During this period, even if the connection between the first communication signal line 221 and the compensation signal line 23 is disconnected, the display uniformity of the display area 10 can be ensured.

[0184] By controlling the first communication signal line 221 and the compensation signal line 23 to be turned on during the start and end of the display holding phase, the voltage shift on the first communication signal line 221 and the pixel electrode Ep caused by the display signal fluctuation during the switching between the refresh display phase and the display holding phase can be suppressed, thereby further improving the display uniformity of the display area 10.

[0185] like Figure 9 As shown, in the non-communication state, during the refresh display phase of each frame and the start and end segments of the display holding phase between two frames, a conduction signal is provided to the control signal line 210 (when the first transistor T1 is an N-type transistor, the conduction signal is a positive voltage signal such as +12V). At this time, the switching circuit 29 connects the first communication signal line 221 and the compensation signal line 23, that is, the first communication signal line 221 is connected to a DC regulated signal (such as a common voltage signal). The voltage on the first communication signal line 221 and the pixel electrode Ep is not easily pulled by external signals, thus ensuring uniform display. In the middle segment of the display holding phase between two frames, a shutdown signal is provided to the control signal line 210 (when the first transistor T1 is an N-type transistor, the shutdown signal is a negative voltage signal such as -12V). At this time, the switching circuit 29 shuts off the connection between the first communication signal line 221 and the compensation signal line 23. At this time, the first communication signal line 221 is no longer connected to the DC regulated signal, but only to the communication signal, thus activating the card scanning function. If no card is detected, the process repeats in the next frame; once a card is detected, the system enters communication mode.

[0186] In the communication state, a turn-off signal is provided to the control signal line 210 (when the first transistor T1 is an N-type transistor, the turn-off signal is a negative voltage signal such as -12V). At this time, the switching circuit 29 turns off the connection between the first communication signal line 221 and the compensation signal line 23. At this time, the first communication signal line 221 is no longer connected to the DC regulated signal, but only connected to the communication signal to start the communication function until the communication ends and enters the non-communication state.

[0187] In the first embodiment, through the above timing control, the visibility problem of the first display area 101 only exists in the card swiping process, i.e., the communication state. However, since the screen is blocked during the card swiping process, the first display area 101 will not be seen visually.

[0188] In the second implementation, such as Figure 2 As shown, the compensation signal line 23 is set independently, and a switch circuit 29 is set between the first communication signal line 221 and the compensation signal line 23. The switch circuit 29 controls the connection and disconnection between the first communication signal line 221 and the compensation signal line 23.

[0189] Since the compensation signal line 23 is a signal line independent of the common signal line 24, it can avoid the fluctuation of the common voltage signal caused by the connection between the first communication signal line 221 and the common signal line 24, ensure the stability of the electric field between the common electrode Ec and the pixel electrode Ep, and prevent the liquid crystal molecules from undergoing rhythmic orientation changes, thus ensuring the stability of the display effect in the display area.

[0190] Reference Figure 10 A timing diagram of each signal in the second embodiment is shown. This timing diagram is illustrated using an N-type transistor as an example for the first transistor T1. Specifically, V211 is the uncompensated voltage signal on the first communication signal line 221, V211' is the compensated voltage signal on the first communication signal line 221, Vg1 is the control signal on the control signal line 210, Vcp is the compensation signal on the compensation signal line 23, Vcom is the common voltage signal on the common signal line 24, and Vs is the display signal on the display signal line 21.

[0191] When the display signal on the display signal line 21 is reversed horizontally, the display signal has the greatest impact on the voltage fluctuation ΔVn on the first communication signal line 221. The voltage fluctuation ΔVn on the first communication signal line 221 fluctuates rhythmically with the horizontal reversal of the display signal, and the voltage on the pixel electrode Ep fluctuates synchronously with ΔVn. When the voltage fluctuation ΔVp on the pixel electrode Ep exceeds a certain value, the first display area 101 becomes macroscopically visible.

[0192] To reduce or eliminate the voltage fluctuation ΔVn on the first communication signal line 221, the compensation signal on the compensation signal line 23 can be an AC signal, and the AC signal is out of phase with the voltage fluctuation ΔVn on the first communication signal line 221, while the amplitude can be approximately equal. The frequency of the AC signal can be less than or equal to the scanning frequency of the display substrate, where the scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal line rows in the display substrate.

[0193] like Figure 10 As shown, a conduction signal can be provided to the control signal line 210 during the second conduction phase (e.g., ...). Figure 10 The high-level signal in Vg1 shown is used to enable the switching circuit 29 to connect the first communication signal line 221 and the compensation signal line 23; in the second disconnection phase, a turn-off signal (such as...) is provided to the control signal line 210. Figure 10 The low-level signal in Vg1 shown causes the switching circuit 29 to disconnect the connection between the first communication signal line 221 and the compensation signal line 23.

[0194] In practice, during the refresh display phase, a refresh display signal can be provided to the display signal line 21 to drive the display area 10 to refresh the display screen; and during the hold display phase (Blanking period), a hold display signal can be provided to the display signal line 21 to keep the display area 10 displaying the screen.

[0195] The second conduction phase may include the start and end segments of the refresh display phase and the hold display phase; the second disconnection phase may include the middle segment of the hold display phase.

[0196] By switching the connection between the first communication signal line 221 and the compensation signal line 23 during the start and end segments of the refresh display phase and the hold display phase, the switching circuit 29 can compensate for or cancel the voltage shift caused by the first communication signal line 221 being pulled by the display signal, thereby reducing the voltage shift on the pixel electrode Ep and improving the display uniformity of the display area 10.

[0197] By switching the first communication signal line 221 and the compensation signal line 23 in the middle of the display stage, the performance degradation caused by the first transistor T1 in the switching circuit 29 being in a conducting state for a long time can be avoided, thereby improving the performance stability of the switching circuit 29.

[0198] In the second embodiment, during the middle section of the display stage, since the display signal on the display signal line 21 remains basically unchanged, the voltage fluctuation on the first communication signal line 221 caused by the fluctuation of the display signal can be ignored. During this period, even if the connection between the first communication signal line 221 and the compensation signal line 23 is disconnected, it can be ensured that the display uniformity of the display area 10 will not be affected.

[0199] By controlling the first communication signal line 221 and the compensation signal line 23 to be turned on during the start and end of the display holding phase, the voltage shift on the first communication signal line 221 and the pixel electrode Ep caused by the display signal fluctuation during the switching between the refresh display phase and the display holding phase can be suppressed, thereby further improving the display uniformity of the display area 10.

[0200] like Figure 10As shown, during the refresh display phase of each frame and the start and end segments of the display phase between two frames, a conduction signal is provided to the control signal line 210 (when the first transistor T1 is an N-type transistor, the conduction signal is a positive voltage signal, such as +12V). At this time, the switching circuit 29 connects the first communication signal line 221 and the compensation signal line 23, that is, the first communication signal line 221 is connected to the compensation signal, and the voltage fluctuation ΔVn on the first communication signal line 221 is compensated (e.g., the compensation signal and the voltage fluctuation ΔVn are out of phase and have different amplitudes) or canceled out. (If the compensation signal is out of phase with the voltage fluctuation ΔVn and has the same amplitude), the voltage pull on the pixel electrode Ep is reduced, thereby ensuring uniform display; in the middle segment of the display stage between two frames, a shutdown signal is provided to the control signal line 210 (when the first transistor T1 is an N-type transistor, the shutdown signal is a negative voltage signal such as -12V). At this time, the switching circuit 29 shuts off the connection between the first communication signal line 221 and the compensation signal line 23. At this time, the first communication signal line 221 is no longer connected to the compensation signal, but only to the communication signal.

[0201] During the second disconnect phase in the non-communication state, the first display area can perform card scanning. It remains in the non-communication state if no card is scanned, and enters the communication state once a card is scanned. During the second disconnect phase and the second connection phase in the communication state, the first display area can perform communication functions until communication ends and it returns to the non-communication state.

[0202] In the second embodiment, the above timing control can improve the visibility problem of the first display area 101 in both the communication state and the non-communication state, and can completely suppress the voltage offset on the first communication signal line 221 and the pixel electrode Ep, thereby improving the display uniformity of the display area 10.

[0203] It should be noted that the timing diagrams of each signal in the second implementation can also be as follows: Figure 11 As shown. In Figure 10 In this process, a non-full-time communication scheme is adopted, that is, high-frequency communication signals are provided to the first communication signal line 221 only during the middle segment of the display phase in the non-communication state and throughout the entire communication state. Figure 11 In this system, a full-time communication scheme is adopted, that is, high-frequency communication signals are continuously provided to the first communication signal line 221 throughout the entire communication state and in non-communication state.

[0204] In the third implementation, such as Figure 5 As shown, the first communication signal line 221 and the compensation signal line 23 are directly connected, and there is no need for the switching circuit 29 to control the on / off state between them, so they remain connected.

[0205] Reference Figure 12The timing diagram of each signal in the third embodiment is shown. Among them, V211 is the voltage signal on the first communication signal line 221 without compensation signal, V211' is the voltage signal on the first communication signal line 221 after compensation signal, Vcp is the compensation signal on the compensation signal line 23, Vcom is the common voltage signal on the common signal line 24, and Vs is the display signal on the display signal line 21.

[0206] When the display signal on the display signal line 21 is reversed horizontally, the display signal has the greatest impact on the voltage fluctuation ΔVn on the first communication signal line 221. The voltage fluctuation ΔVn on the first communication signal line 221 fluctuates rhythmically with the horizontal reversal of the display signal, and the voltage on the pixel electrode Ep fluctuates synchronously with ΔVn. When the voltage fluctuation ΔVp on the pixel electrode Ep exceeds a certain value, the first display area 101 becomes macroscopically visible.

[0207] To reduce or eliminate the voltage fluctuation ΔVn on the first communication signal line 221, the compensation signal on the compensation signal line 23 can be an AC signal, and the AC signal is out of phase with the voltage fluctuation ΔVn on the first communication signal line 221, while the amplitude can be approximately equal. The frequency of the AC signal can be less than or equal to the scanning frequency of the display substrate, where the scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal line rows in the display substrate.

[0208] In a specific implementation, by providing a compensation signal to the compensation signal line 23 that is opposite in phase to the voltage fluctuation ΔVn on the first communication signal line 221, and keeping the first communication signal line 221 and the compensation signal line 23 in a conducting state, the voltage shift caused by the pulling of the first communication signal line 221 by external display signals can be compensated or canceled, thereby reducing the voltage shift on the pixel electrode Ep and improving the display uniformity of the display area 10.

[0209] In this embodiment, since the first communication signal line 221 and the compensation signal line 23 remain connected, the visibility problem of the first display area 101 can be improved whether in the communication state or the non-communication state. The voltage offset on the first communication signal line 221 and the pixel electrode Ep can be completely suppressed, thereby improving the display uniformity of the display area 10.

[0210] like Figure 11 As shown, since the first communication signal line 221 and the compensation signal line 23 remain connected, the first communication signal line 221 is always connected to the compensation signal. As a result, the voltage fluctuation ΔVn on the first communication signal line 221 is compensated (e.g., the compensation signal is out of phase with the voltage fluctuation ΔVn and the amplitude is different) or canceled (e.g., the compensation signal is out of phase with the voltage fluctuation ΔVn and the amplitude is equal). This reduces the voltage pull on the pixel electrode Ep, thereby ensuring uniform display.

[0211] In some implementations, the GOA circuit 111 may be an 11T1C circuit, see reference. Figure 13 A schematic diagram of the connection structure of an 11T1C circuit is shown. This 11T1C circuit includes 11 transistors (such as...). Figure 13 (as shown in M1 to M11) and 1 capacitor (as shown in M1 to M11) Figure 13 C1 (as shown).

[0212] This disclosure also provides a display device, including: a display substrate as provided in any embodiment; a driving circuit configured to provide a driving signal to the display substrate, the driving signal including a display signal, a communication signal, and a compensation signal; and a power supply circuit configured to provide power to the display substrate.

[0213] Those skilled in the art will understand that this display device has the advantages of a front-mounted display substrate.

[0214] The display device is a product with image display capabilities. For example, a display device can be any of the following: monitor, television, billboard, digital photo frame, laser printer with display function, telephone, mobile phone, personal digital assistant (PDA), digital camera, portable camcorder, viewfinder, navigator, vehicle, large-area wall, home appliance, information query equipment (such as business query equipment for e-government, banks, hospitals, power companies, etc.), and monitor. The display device can also be a microdisplay or a product containing a microdisplay. Products containing microdisplays can be any of the following: smartwatch, smart bracelet, helmet display, stereoscopic display, AR device (e.g., AR glasses), and VR device (e.g., VR glasses).

[0215] This disclosure provides a driving method for a display substrate, applicable to a display substrate provided in any embodiment, the driving method comprising:

[0216] Step S21: Provide a display signal to the display signal line 21 to drive the display area 10 to display the screen.

[0217] Step S22: Provide a communication signal to the first communication signal line 221 so that the first communication signal line 221 transmits the communication signal.

[0218] Step S23: Provide a compensation signal to the compensation signal line 23 so that the compensation signal is transmitted to the first communication signal line 221 to suppress voltage fluctuations on the first communication signal line 221 caused by display signal fluctuations and coupling capacitance on the display signal line 21.

[0219] In some implementations, the compensation signal is a DC regulated signal. For example, this DC regulated signal may be a common voltage signal.

[0220] In some embodiments, step S21, the step of providing a display signal to the display signal line 21, includes:

[0221] During the refresh display phase, a refresh display signal is provided to the display signal line 21 to drive the display area 10 to refresh the display screen; and

[0222] During the display holding phase, a display holding signal is provided to the display signal line 21 so that the display area 10 holds the display image.

[0223] In some embodiments, when the display substrate further includes a switching circuit 29, and the switching circuit 29 is connected to the control signal line 210, the first communication signal line 221, and the compensation signal line 23 respectively, the following may be included after step S23:

[0224] Step S31: In the first conduction stage, a conduction signal is provided to the control signal line 210 so that the switching circuit 29 conducts the connection between the first communication signal line 221 and the compensation signal line 23.

[0225] Step S32: In the first disconnection phase, a shutdown signal is provided to the control signal line 210 to cause the switching circuit 29 to disconnect the connection between the first communication signal line 221 and the compensation signal line 23.

[0226] like Figure 9 As shown, the first conduction phase includes: a refresh display phase in the non-communication state, and a start and end segment of the hold display phase in the non-communication state; the first disconnection phase includes: an intermediate segment of the hold display phase in the non-communication state, a refresh display phase in the communication state, and a hold display phase in the communication state.

[0227] In some implementations, the compensation signal is an AC signal, and the AC signal is out of phase with the voltage fluctuation.

[0228] In some implementations, the amplitude of the aforementioned AC signal is equal to that of the voltage fluctuation.

[0229] In some implementations, the frequency of the compensation signal is less than or equal to the scanning frequency of the display substrate, where the scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal lines in the display substrate.

[0230] In some embodiments, when the display substrate further includes a switching circuit 29, and the switching circuit 29 is connected to the control signal line 210, the first communication signal line 221, and the compensation signal line 23 respectively, the following may be included after step S23:

[0231] Step S41: In the second conduction stage, a conduction signal is provided to the control signal line 210 so that the switching circuit 29 conducts the connection between the first communication signal line 221 and the compensation signal line 23.

[0232] Step S42: In the second disconnection phase, a shutdown signal is provided to the control signal line 210 to cause the switching circuit 29 to disconnect the connection between the first communication signal line 221 and the compensation signal line 23.

[0233] like Figure 10 or Figure 11 As shown, the second conduction phase includes the start and end segments of the refresh display phase and the hold display phase; the second disconnection phase includes the middle segment of the hold display phase.

[0234] In practice, the amplitude of the compensation signal is related to the displayed image. When different images are displayed on the display substrate, the corresponding compensation signal also changes dynamically. The compensation signal can be determined based on factors such as the display signal on the display data line and the coupling capacitance, and this disclosure does not impose specific limitations on it.

[0235] In practical implementation, the compensation signal can also be an AC signal with the same phase as the voltage fluctuation, and the amplitudes of the two signals can be equal or unequal. When the compensation signal has the same phase as the voltage fluctuation, the amplitude of the voltage fluctuation on the first communication signal line 221 can be increased, thereby increasing the amplitude of the voltage fluctuation on the pixel electrode Ep, increasing the display difference between the first display area 101 and the second display area 102, making the first display area 101 clearly visible when needed. For example, when the card is close to the display substrate, the macroscopic visibility of the first display area 101 can be improved, allowing the user to intuitively see the coil position.

[0236] In some implementations, such as Figures 9 to 12 As shown in any one of them, the communication signal includes a high-frequency signal, the frequency of which is greater than the scanning frequency of the display substrate. The scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal lines in the display substrate.

[0237] Among them, the frequency of high-frequency signals can be, for example, at the megahertz level. Since liquid crystal molecules cannot respond effectively to such high-frequency signals, the impact of high-frequency signals in communication signals on display effects can be ignored.

[0238] In some implementations, such as Figure 9 or Figure 10 As shown, in step S22, the step of providing a communication signal to the first communication signal line 221 includes:

[0239] In the middle segment of the display holding phase in non-communication state, the refresh display phase in communication state, and the display holding phase in communication state, a high-frequency signal is provided to the first communication signal line 221.

[0240] In this embodiment, a non-full-time communication scheme is adopted. During the start and end segments of the display holding phase in the non-communication state and the refresh display phase in the non-communication state, high-frequency signals are not provided to the first communication signal line 221. High-frequency signals are only provided to the first communication signal line 221 during the middle segment of the display holding phase in the non-communication state, the refresh display phase in the communication state, and the display holding phase in the communication state. Adopting a non-full-time communication scheme can further improve the display effect.

[0241] In some implementations, such as Figure 11 or Figure 12 As shown, in step S22, the step of providing a communication signal to the first communication signal line 221 includes:

[0242] During the refresh display phase and the hold display phase, a high-frequency signal is provided to the first communication signal line 221.

[0243] In this embodiment, a constant-time communication scheme is adopted, that is, high-frequency signals are continuously provided to the first communication signal line 221 during the refresh display phase and the hold display phase in the communication state, as well as during the refresh display phase and the hold display phase in the non-communication state. Adopting a constant-time communication scheme can improve the sensitivity of the communication function.

[0244] It should be noted that when the compensation signal is a DC regulated signal, a non-full-time communication scheme can be used to ensure that the communication function is not affected by the DC regulated signal.

[0245] It should be noted that this driving method may include more steps, depending on actual needs, and this disclosure does not impose any limitations on it. For a detailed description of the driving method and its technical effects, please refer to the description of the display substrate above; it will not be repeated here.

[0246] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise expressly and specifically defined.

[0247] In this disclosure, the terms "upper" and "lower" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this disclosure.

[0248] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0249] The terms "an embodiment," "some embodiments," "exemplary embodiments," "one or more embodiments," "example," "one example," "some examples," etc., used herein are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

[0250] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0251] In describing some embodiments, the terms "coupled" and "connected" may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0252] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0253] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0254] As used herein, depending on the context, the term “if” may optionally be interpreted as meaning “when”, “in the event of”, “in response to determination”, or “in response to detection”. Similarly, depending on the context, the phrase “if it is determined that…” or “if [the stated condition or event] is detected” may optionally be interpreted as meaning “in the event of determination that…”, “in response to determination that…”, “when [the stated condition or event] is detected”, or “in response to the detection of [the stated condition or event]”.

[0255] The use of “for” or “configured to” in this article implies an open and inclusive language that does not preclude the applicability to or configuration of devices to perform additional tasks or steps.

[0256] The use of "based on" or "according to" in this document implies openness and inclusiveness. A process, step, calculation, or other action based on one or more of the stated conditions or values ​​may, in practice, be based on other conditions or values ​​beyond those stated.

[0257] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0258] As used herein, “parallel,” “perpendicular,” “equal,” and “flush” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where the acceptable range of deviation for approximate parallelism can be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where the acceptable range of deviation for approximate perpendicularity can also be, for example, within 5°. “Equal” includes absolute equality and approximate equality, where the acceptable range of deviation for approximate equality can be, for example, the difference between the two equals being less than or equal to 5% of either one. “Flush” includes absolute flush and approximate flush, where the acceptable range of deviation for approximate flush can be, for example, the distance between the flush twos being less than or equal to 5% of either one of the dimensions.

[0259] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0260] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0261] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A display substrate, comprising a display area and a border area located on at least one side of the display area, the display area comprising a first display area and a second display area, the display substrate comprising: A substrate, and display signal lines, communication signal lines and compensation signal lines located on at least one side of the substrate; The display signal line is used to transmit display signals to the pixel units of the display area; The communication signal line is coupled to the display signal line to form a coupling capacitor, including a first communication signal line, at least a portion of which is located in the first display area, and the first communication signal line is used to transmit communication signals. The compensation signal line is located in the frame area and connected to the first communication signal line. It is used to transmit a compensation signal to the first communication signal line. The compensation signal is used to suppress the voltage fluctuation on the first communication signal line caused by the display signal fluctuation on the display signal line and the coupling capacitor. The display substrate further includes: A common signal line, located in the border area, is used to transmit a common voltage signal to the common electrode of the pixel unit, and multiple pixel units share the common electrode; The common signal line is multiplexed as the compensation signal line.

2. The display substrate according to claim 1, wherein, The compensation signal line is set independently.

3. The display substrate according to claim 1 or 2, wherein, The display substrate further includes: A switching circuit, located in the frame area, has a first end connected to a control signal line, a second end connected to the first communication signal line, and a third end connected to the compensation signal line. It is used to turn on or off the connection between the first communication signal line and the compensation signal line according to the control signal input from the control signal line.

4. The display substrate according to claim 3, wherein, The switching circuit includes: The first transistor has its control electrode connected to the control signal line, its first electrode connected to the compensation signal line, and its second electrode connected to the first communication signal line.

5. The display substrate according to claim 4, wherein, The pixel unit includes: The second transistor has a control electrode connected to the scan signal line, a first electrode connected to the display signal line, and a second electrode connected to the pixel electrode of the pixel unit. It is used to control the on / off state between the display signal line and the pixel electrode according to the scan signal input from the scan signal line. The display substrate further includes: The GOA circuit, located in the border area and connected to the scan signal line, is used to output the scan signal to the scan signal line; The switching circuit is located on the side of the GOA circuit closer to the display area, and the compensation signal line is located on the side of the switching circuit closer to the display area.

6. The display substrate according to claim 1, 2, 4, or 5, wherein, The display substrate includes two compensation signal lines, which are a first compensation signal line and a second compensation signal line, respectively located on opposite sides of the display area along the row direction; In the multiple first communication signal lines extending along the row direction and arranged along the column direction, the first communication signal line in each row is connected to the first compensation signal line and the second compensation signal line.

7. The display substrate according to claim 1, 2, 4, or 5, wherein, The display substrate includes two compensation signal lines, which are a first compensation signal line and a second compensation signal line, respectively located on opposite sides of the display area along the row direction; Among the multiple first communication signal lines extending along the row direction and arranged along the column direction, the first communication signal line located in the odd-numbered row is connected to the first compensation signal line, and the first communication signal line located in the even-numbered row is connected to the second compensation signal line.

8. The display substrate according to claim 1, wherein, The display substrate further includes: A communication signal input terminal is located in the border area and connected to the first communication signal line, used to provide the communication signal to the first communication signal line; The communication signal input terminal is multiplexed as the compensation signal line.

9. The display substrate according to claim 1, 2, 4, 5, or 8, wherein, The display substrate further includes: a common signal line located in the frame area, used to transmit a common voltage signal to the common electrode of the pixel unit, wherein multiple pixel units share the common electrode; The communication signal line further includes: a second communication signal line, at least a portion of which is located in the second display area; The second communication signal line is connected to the common signal line.

10. A display device, comprising: The display substrate as described in any one of claims 1 to 9; A driving circuit is configured to provide a driving signal to the display substrate, the driving signal including the display signal, the communication signal, and the compensation signal; and A power supply circuit is configured to provide power to the display substrate.

11. A driving method for a display substrate, applied to the display substrate according to any one of claims 1 to 9, the driving method comprising: A display signal is provided to the display signal line to drive the display area to display an image; A communication signal is provided to the first communication signal line so that the first communication signal line transmits the communication signal. A compensation signal is provided to the compensation signal line so that the compensation signal is transmitted to the first communication signal line to suppress voltage fluctuations on the first communication signal line caused by display signal fluctuations on the display signal line and the coupling capacitor.

12. The driving method according to claim 11, wherein, The compensation signal is a DC regulated signal.

13. The driving method according to claim 12, wherein, The step of providing a display signal to the display signal line includes: During the refresh display phase, a refresh display signal is provided to the display signal line to drive the display area to refresh the display screen; and During the display hold phase, a display hold signal is provided to the display signal line to keep the display area displaying the image. When the display substrate further includes a switching circuit, and the switching circuit is connected to the control signal line, the first communication signal line, and the compensation signal line respectively, after the step of providing a compensation signal to the compensation signal line, the method further includes: During the first conduction phase, a conduction signal is provided to the control signal line to enable the switching circuit to connect the first communication signal line and the compensation signal line. In the first disconnection phase, a shutdown signal is provided to the control signal line to cause the switching circuit to disconnect the connection between the first communication signal line and the compensation signal line; The first conduction phase includes: a refresh display phase in the non-communication state, and a start and end phase of the maintain display phase in the non-communication state. The first disconnection phase includes: an intermediate segment of the display holding phase in non-communication state, a refresh display phase in communication state, and a display holding phase in communication state.

14. The driving method according to claim 11, wherein, The compensation signal is an AC signal, and the AC signal is out of phase with the voltage fluctuation.

15. The driving method according to claim 14, wherein, The amplitude of the AC signal is equal to that of the voltage fluctuation.

16. The driving method according to claim 14 or 15, wherein, The frequency of the compensation signal is less than or equal to the scanning frequency of the display substrate, whereby the scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal lines in the display substrate.

17. The driving method according to claim 14 or 15, wherein, The step of providing a display signal to the display signal line includes: During the refresh display phase, a refresh display signal is provided to the display signal line to drive the display area to refresh the display screen; and During the display hold phase, a display hold signal is provided to the display signal line to keep the display area displaying the image. When the display substrate further includes a switching circuit, and the switching circuit is connected to the control signal line, the first communication signal line, and the compensation signal line respectively, after the step of providing a compensation signal to the compensation signal line, the method further includes: During the second conduction phase, a conduction signal is provided to the control signal line to enable the switching circuit to connect the first communication signal line and the compensation signal line. In the second disconnection phase, a shutdown signal is provided to the control signal line to cause the switching circuit to disconnect the connection between the first communication signal line and the compensation signal line; The second conduction phase includes: the refresh display phase and the start and end segments of the hold display phase; The second disconnection phase includes: the middle segment of the display holding phase.

18. The driving method according to any one of claims 11 to 15, wherein, The communication signal includes a high-frequency signal, the frequency of which is greater than the scanning frequency of the display substrate. The scanning frequency is the product of the frame refresh frequency of the display substrate and the number of scan signal lines in the display substrate.

19. The driving method according to claim 18, wherein, The step of providing the display signal to the display signal line includes: During the refresh display phase, a refresh display signal is provided to the display signal line to drive the display area to refresh the display screen; and During the display hold phase, a display hold signal is provided to the display signal line to keep the display area displaying the image. The step of providing a communication signal to the first communication signal line includes: During the refresh display phase and the hold display phase, the high-frequency signal is provided to the first communication signal line; or The high-frequency signal is provided to the first communication signal line during the middle segment of the display phase in the non-communication state, the refresh display phase in the communication state, and the display holding phase in the communication state.

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