Reconfigurable digital in-memory computing apparatus based on multiplexed booth computing cells and 6t-sram
By employing time-division multiplexing Booth computing units and alternating adder trees in digital in-memory computing devices, the problems of large area and power consumption overhead and insufficient flexibility of adder trees are solved, achieving high energy efficiency and flexible convolution computation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG UNIV
- Filing Date
- 2024-05-24
- Publication Date
- 2026-07-14
AI Technical Summary
Existing digital in-memory computing devices suffer from problems such as large adder tree area and power consumption, insufficient flexibility, and low system utilization when facing neural network applications of different scales.
It adopts a time-division multiplexing strategy, with each four rows of SRAM sharing a Booth computing unit. The input data is preprocessed through Booth encoding, and the adder tree, which runs alternately at 11T and 28T, reduces the area and power consumption of the adder tree. At the same time, it supports flexible configuration of the convolution computing scale.
It achieves higher energy efficiency and system flexibility, and can flexibly configure the convolution calculation scale according to the size of the neural network, reduce the number of operation cycles, and improve the system's energy efficiency ratio.
Smart Images
Figure CN118657181B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of in-memory computing technology, and specifically to a reconfigurable digital in-memory computing device based on a multiplexed Booth computing unit and 6T-SRAM. Background Technology
[0002] In recent years, with the rapid development and widespread application of artificial intelligence (AI) technology, the amount of data that AI-related algorithms need to process has become increasingly massive. The frequent data transfers between the central processing unit (CPU) and memory in the traditional von Neumann architecture have generated enormous power consumption. At the same time, the mismatch between memory bandwidth and processor performance has also limited the computing power of computing hardware. Computing-in-Memory (CIM) architecture, by giving memory certain computational functions, performs calculations directly on large amounts of data within memory, reducing the frequency of bus interactions between memory and the CPU, lowering data transfer power consumption, and thus significantly improving the system's energy efficiency. Therefore, it has received widespread attention from industry and academia in recent years.
[0003] In-memory computing technology is divided into analog in-memory computing design and digital in-memory computing design. Analog in-memory computing design can achieve high computing speeds, and the system performance and energy efficiency are good. However, with the high precision requirements of large-scale neural network applications and application scenarios with frequent algorithm iterations, the performance of analog in-memory computing is not ideal. Digital in-memory computing, on the other hand, performs operations in the digital domain, and its computational accuracy is not affected by PVT (Process, Voltage, Temperature) and noise, achieving 100% computational accuracy. This is very suitable for large-scale, high-precision neural network applications with frequent algorithm iterations. Currently proposed digital in-memory computing devices are mostly characterized by high parallelism computing. This approach brings huge computing power to the architecture, thereby achieving good energy efficiency. However, it also results in a large area and power consumption of the adder tree within the architecture. Furthermore, the 1:1 configuration of storage units and computing units leads to a large array area, resulting in increased static power consumption. This approach also makes the architecture less flexible, requiring repeated refreshing of weight values within the array when dealing with small-scale neural network applications, leading to reduced array utilization. Therefore, how to reduce the area and power consumption of the adder tree in the system while ensuring high throughput and improving the system's energy efficiency ratio, and improving the system's configurability when facing different neural networks, is a key problem that needs to be solved in digital in-memory computing design. Summary of the Invention
[0004] To address the problems in the prior art, the present invention provides a reconfigurable digital in-memory computing device based on a multiplexed Booth computing unit and 6T-SRAM.
[0005] The reconfigurable digital in-memory computing device based on multiplexed Booth computing units and 6T-SRAM includes one input encoding module and 64 Booth multiplication in-memory computing processors.
[0006] The input encoding module encodes the externally received symbol flag signal and 64 consecutive 3-bit data to obtain the control signal for the Booth operation;
[0007] The Booth multiplication in-memory computation processor includes an in-memory computation array, a bit extension unit, an adder tree unit, and an accumulator unit. The in-memory computation array consists of 1 row and 64 columns of Booth multiplication in-memory computation data blocks. Each Booth multiplication in-memory computation data block includes an SRAM subarray and a Booth computation unit. The SRAM subarray consists of 4 rows and 4 columns of 6T-SRAM units.
[0008] The in-memory computing array has two working modes: storage mode and computing mode. In storage mode, the in-memory computing array stores externally input weight data, and the weight data is stored in the 6T-SRAM cells of the SRAM subarray.
[0009] In computation mode, the Booth computation unit receives the control signal of the Booth operation and performs calculations based on the weight data stored in the SRAM subarray to obtain 64 intermediate computation results. The bit extension unit performs bit extension operations on the 64 intermediate computation results to obtain 64 6-bit intermediate products. The adder tree unit accumulates the intermediate products to obtain a partial sum. The accumulator unit performs shift accumulation on the partial sum and outputs a 20-bit convolution computation result.
[0010] Furthermore, the 64 consecutive 3-bit data points are consecutive 3-bit data points from the same group of 64*N values to be convolved, and each consecutive 3-bit data point has the same bit weight; the 64*N values to be convolved are all in binary format, where N is an array, 1≤N≤4.
[0011] Furthermore, the specific calculation steps of the accumulator unit are as follows:
[0012] 1) The accumulator unit receives a partial sum from the current cycle adder tree output and performs bit extension;
[0013] 2) Add the bit-extended partial sum to the accumulated value stored in the accumulator. If the accumulated value of the current period is the accumulated value obtained by accumulating the partial sums of the previous N periods, then add two zeros to the value of the accumulated value, and add the accumulated value with the two zeros added to the bit-extended partial sum. The result of the addition is stored in the accumulator as a new accumulated value. If the accumulated value of the current period is not the accumulated value obtained by accumulating the partial sums of the previous N periods, add the bit-extended partial sum to the accumulated value, and store the result of the addition in the accumulator as a new accumulated value.
[0014] 3) Repeat steps 1) and 2) until all 64*N partial sums are accumulated. The accumulator finally outputs a 20-bit convolution calculation result.
[0015] Compared with the prior art, the present invention has the following advantages:
[0016] (1) The present invention adopts a time-division multiplexing strategy, with each four rows of SRAM sharing a Booth computing unit, which reduces the number of data groups to be computed in parallel within each operation cycle, thereby greatly reducing the area and power consumption of the adder tree. At the same time, the present invention performs Booth encoding preprocessing on the 3-bit input computation data, and then drives the Booth computing unit and bit extension unit designed in the architecture to operate with the obtained operation signal. Therefore, it can process 3 bits of computation data in a single cycle, which greatly reduces the number of cycles required for operation. Thus, the device can achieve higher energy efficiency.
[0017] (2) The scale of convolution calculation can be flexibly configured according to the scale of the applied neural network. The system can support 64N×64 parallel operation groups in a single cycle (N is a maximum of 4). Attached Figure Description
[0018] Figure 1 This is the overall architecture diagram of the in-memory computing design based on the reused Booth computing unit and 6T SRAM.
[0019] Figure 2 This is a layout diagram of a 1Kb in-memory computing array.
[0020] Figure 3 This is a schematic diagram of the Booth multiplication memory calculation data block circuit.
[0021] Figure 4 This is the circuit diagram of the Booth multiplier encoder.
[0022] Figure 5 This is the truth table of the Booth multiplication encoder circuit.
[0023] Figure 6It is a circuit diagram of an adder tree that alternates between 11T and 28T.
[0024] Figure 7 This is a schematic diagram of the internal structure of the Booth multiplication in-memory computing processor.
[0025] Figure 8 This is a timing diagram of the reconfigurable convolution computation operation of the in-memory computing device.
[0026] Figure 9 This is a transient simulation diagram of the Booth multiplication in-memory computation data block.
[0027] Figure 10 It is a transient simulation diagram of the device's computational operation. Detailed Implementation
[0028] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. The following embodiments will help to further understand the present invention.
[0029] First, the following explanations are given for some of the nouns or terms that appear in the description of this invention:
[0030] The sign flag signal is used to determine whether the input data is signed or not. In a specific embodiment of the present invention, if the sign flag signal is at logic level "1", it indicates that the input data is a signed number; if the sign flag signal is at logic level "0", it indicates that the input data is an unsigned number.
[0031] For example, consider 64 consecutive 3-bit data points: Let three of these values to be convolved be "10110101, 10010011, 11001101". If input according to the highest bit weight, they will be "101, 100, 110"; if input according to the second highest bit weight, they will be "110, 010, 001". Each value to be convolved has a maximum of 8 bits.
[0032] The weight data consists of the weight values to be written to the in-memory computing array.
[0033] This invention provides a reconfigurable digital in-memory computing device based on a multiplexed Booth computing unit and 6T-SRAM. Figure 1The diagram shows the architecture of the entire reconfigurable digital in-memory computing device. The main components of the architecture include: 64 Booth multiplication in-memory computing processors, an input encoding module, an address decoder, and a clock control module. Each Booth multiplication in-memory computing processor contains five modules: a 1Kb in-memory computing array, an array read / write driver circuit, a bit extension unit, an adder tree circuit, and an accumulator circuit. The in-memory computing array consists of 64 Booth multiplication in-memory computing data blocks. Each data block contains a 4x4 SRAM subarray and a Booth multiplication computing unit. During computation, four rows of SRAM banks share one Booth multiplication computing unit, with weight values read into the Booth multiplication computing unit for calculation in a time-sharing manner. The bit extension unit performs corresponding extension operations on the 64 sets of intermediate calculation results output from the Booth multiplication in-memory computing data blocks according to the control signals output by the input encoding module, obtaining 64 sets of 6-bit intermediate products.
[0034] The adder tree unit sums these intermediate accumulations, and the resulting partial sum is then fed into the accumulator unit for shifting and accumulation.
[0035] The accumulator unit has a configurable shift period, thereby enabling the reconstruction of the convolution operation scale.
[0036] The read / write driver unit is used to control the read and write operations of the in-memory computing array. The read / write driver unit is responsible for writing the weight values input from the outside and reading the weight values already stored in the in-memory computing array.
[0037] The input encoding module consists of 64 Booth multiplication encoders. In computation mode, it encodes 64 sets of 3-bit data from external input according to the Booth encoding principle to obtain the control signal for Booth operation, which drives the Booth multiplication in-memory computation processor to perform corresponding operations. In storage mode, the 64 sets of 3-bit data are not sampled and are encoded as "0".
[0038] The address decoder is responsible for compiling externally input address signals to obtain row and column address signals, thereby performing read weighting, write weighting, or computation operations on the selected memory cells within the in-memory computing array. The clock control module is responsible for the timing control and operating mode switching of the entire reconfigurable digital in-memory computing device.
[0039] In a specific embodiment of the present invention, the Booth multiplication in-memory computation data block is computed using a time-division multiplexing method. Each SRAM subarray consists of four SRAM banks, and each SRAM bank consists of 1 row and 4 columns of 6T-SRAM units. The four SRAM banks in a Booth multiplication in-memory computation data block time-division multiplex one Booth computation unit, and the Booth computation unit performs multiplication operations.
[0040] In one specific embodiment of the present invention, the address decoder receives an externally input address signal. When the in-memory computing array is in storage mode, the address decoder outputs a column address signal to the read / write driving unit. The read / write driving unit reads out or writes the weight data into the corresponding Booth multiplication in-memory computing data block according to the column address signal. The address decoder outputs a row address signal to the Booth multiplication in-memory computing data block. The Booth multiplication in-memory computing data block stores the weight data written by the read / write driving unit into the corresponding SRAM Bank according to the row address signal, or the Booth multiplication in-memory computing data block reads out the weight data stored in the corresponding SRAM Bank through the read / write driving unit according to the row address signal. When the in-memory computing array is in computing mode, the address decoder outputs a row address signal to the Booth multiplication in-memory computing data block. The Booth multiplication in-memory computing data block reads out the weight data from the 64 SRAM Banks at that row address according to the row address signal. Each SRAM Bank stores 4 bits of weight data.
[0041] The clock control module receives an externally input enable signal, outputs a state transition control signal to the address decoder, and outputs a read / write drive signal to the read / write drive unit. The address decoder determines the current working mode of the in-memory computing array based on the state transition control signal and performs the corresponding decoding operation. The read / write drive unit determines whether to read or write weight data based on the read / write drive signal.
[0042] In a specific embodiment of the present invention, the input encoding module includes 64 Booth multiplication encoders, which input a sign flag signal and 64 consecutive 3-bit data, and output control signals for 64 Booth operations to 64 Booth calculation units; the 64 consecutive 3-bit data are the 3-bit data of any 64 data points in the total data to be convolutionally calculated; the control signals for the Booth operations include a shift enable signal SHIFT, a clear enable signal ZERO, an inverse enable signal INV, and a triple multiplication enable signal TRIPLE.
[0043] When the sign flag signal is 1, if the input 3-bit data is 001 or 010, the shift enable signal SHIFT, the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 011, the shift enable signal SHIFT is 1, and the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 100, the clear enable signal ZERO and the triple enable signal TRIPLE are both 0, and the shift enable signal SHIFT and the invert enable signal INV are both 1. If the input 3-bit data is 101 or 110, the invert enable signal INV is 1, and the shift enable signal SHIFT, the clear enable signal ZERO, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 000 or 111, the clear enable signal ZERO is 1.
[0044] When the sign flag signal is 0, if the input 3-bit data is 000 or 001, the clear enable signal ZERO is 1. If the input 3-bit data is 010 or 011, the shift enable signal SHIFT, the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 100 or 101, the shift enable signal SHIFT is 1, and the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 110 or 111, the shift enable signal SHIFT, the clear enable signal ZERO, and the invert enable signal INV are all 0, and the triple enable signal TRIPLE is 1.
[0045] As a preferred embodiment of the present invention, the Booth multiplication in-memory computation data block adopts a time-sharing multiplexing strategy, referring to... Figure 2 The diagram shows the layout of a 1Kb in-memory computing array within the device, arranged in a 4-row × 64-column × 4-bit configuration. Each column represents a group of Booth multiplication in-memory computing data blocks. When the device is in memory mode, read or write operations are performed on the selected SRAM Bank (SRAM bank, 1 row × 4 columns) by simultaneously selecting the row select signal WL and the column select signal CSL. When the device is in compute mode, all column select signals CSL are low, and the word line WL is enabled, selecting one row to input 64 4-bit weight values into the BMCC (Booth Computation Unit) for Booth operations.
[0046] As a preferred embodiment of the present invention, the Booth computing unit (BMCC) circuit is as follows: Figure 3As shown. The Booth computing unit can operate in two modes: storage mode and computing mode. In storage mode, the dual to single converter (DTSC) in the Booth computing unit is disabled, so it cannot sample the weight values on the bit lines. At this time, the input encoding module performs the operation of encoding zero. Therefore, the clear enable signal ZERO input to the Booth computing unit is "1", so the output Q[4:0] of the Booth multiplication memory computing data block is always low. In computing mode, DTSC is enabled, and one of the word lines WL[3]-WL[0] of the 64 SRAM subarray is enabled. The 4-bit weight value stored in one row of the SRAM subarray is read out into BMCC. After sampling by DTSC, the weight value is input into the 5-bit shifter through the bus GBL[3:0]. The shifter determines whether to shift GBL[3:0] left by one bit according to the value of the shift enable signal. If the shift enable signal SHIFT=1, the weight value is shifted left by one bit, and the least significant bit is filled with "0". If the shift enable signal SHIFT = 0, the weight value is bit-extended according to the value of the sign flag SIGN. When the sign flag SIGN = 1, sign bit extension is performed; when the sign flag SIGN = 0, zero extension is performed. The shifter then sends the processed 5-bit data to one end of the XOR gate unit, with the other end receiving the inverting enable signal INV. From the XOR logic expression, we can obtain A⊕INV = A'·INV + A·INV'. When INV = 1, A⊕INV = A'; when INV = 0, A⊕INV = A. Therefore, the XOR gate unit inverts the 5-bit data according to the value of the inverting enable signal INV, ultimately outputting Q[4:0].
[0047] As a preferred embodiment of the present invention, the Booth multiplication encoder is constructed based on the principle of Booth encoding. (See reference...) Figure 4 and Figure 5 The diagrams show the circuit structure and truth table of the Booth multiplier encoder. The design involves padding the n-bit input INPUT with a zero at the end, then inputting INPUT in 3-bit increments from the MSB (Most Significant Bit) to the LSB (Least Significant Bit). The encoding circuit, based on the input data and the value of the sign flag (SIGN), encodes the following control signals: invert enable (INV), shift enable (SHIFT), clear enable (ZERO), and triple enable (TRIPLE). These signals are combined to drive the Booth calculation unit and bit extension unit to perform corresponding operations, thereby outputting the correct partial product. Figure 5As shown, when the sign flag SIGN = 1, the system performs Booth multiplication. The encoding circuit performs Booth encoding on the input data according to the Booth encoding principle. It can be seen that if the zero-clear enable signal ZERO = 1, the multiplier (weight value) is cleared to zero regardless of the values of the other three control signals. If the zero-clear enable signal ZERO = 0, and only the shift enable signal SHIFT = 1, the multiplier is doubled; if only the inverse enable signal INV = 1, the multiplier is complemented; if both the shift enable signal SHIFT and the inverse enable signal INV are 1, the multiplier is first doubled and then complemented; if both the shift enable signal SHIFT and the inverse enable signal INV are 0, no operation is performed on the multiplier. When the sign flag SIGN = 0, the system performs arithmetic multiplication, and the encoding module only performs arithmetic encoding based on the high two bits of the 3-bit input. When the two highest digits are "00", the multiplier is cleared to zero; when the two highest digits are "01", no operation is performed on the multiplier; when the two highest digits are "10", the multiplier is doubled; when the two highest digits are "11", the multiplier is tripled.
[0048] The Booth multiplication encoder is built based on the principle of Booth encoding. The principle of Booth encoding is as follows: when multiplying an m-bit signed number x with an n-bit signed number y, the two's complement of the n-bit signed number y can be represented as:
[0049]
[0050] From the above expression, we can deduce that the three consecutive bits of data encoded by y (i.e., y) i-1 y i 2y i+1 The partial product can be obtained in five ways: 0, x, -x, 2x, and -2x. Then, based on the bit weight of the current processing bit, the partial product is shifted left by i bits (where i is an even number). Finally, all partial products are summed to obtain the product of x and y. Similarly, when the digital in-memory computing device performs operations, the input data is processed from high to low bits in 3-bit increments, shifting two bits to the right each time. This data is gradually fed into the Booth multiplication encoder for encoding. The resulting control signal drives the Booth multiplication in-memory computing processor to perform calculations with its internally stored weight values. The partial sum generated by the high-weight data is shifted left by two bits each time. Through multiple cycles of iterative processing, a pipelined Booth multiplication operation is achieved.
[0051] As a preferred embodiment of the present invention, the adder circuit employs a hybrid parallel adder tree with alternating operation of 11-transistor and 28-transistor full adders. Compared to the previously proposed parallel adder tree structure that mixes 14-transistor and 28-transistor full adders, replacing the 14-transistor full adders with 11-transistor full adders further reduces the area and power consumption of the adder tree, as described above. Figure 6 As shown, compared to traditional 28-transistor and 14-transistor full adders, the 11-transistor full adder simplifies some of the computational logic, resulting in a smaller area and advantages such as low latency and low power consumption, making it very suitable for the design of high-efficiency adder trees. However, the 11-transistor full adder also has the disadvantage of threshold loss. If all 11-transistor full adders are used to build a parallel adder tree, in the case of multi-stage cascaded adder units, the output voltage of the subsequent adder units may experience a large threshold loss, leading to calculation errors. Therefore, a method of alternating operation of 11-transistor and 28-transistor full adders is ultimately used to implement the parallel adder tree. The hybrid adder tree not only uses two types of full adders to implement adder units horizontally, but also uses an alternating method to implement the progression within the adder tree vertically, significantly reducing the area and power consumption of the adder tree and improving the energy efficiency of the in-memory computing architecture.
[0052] Reference Figure 7 The diagram shows the internal structure of the Booth Multiplication In-Memory Processor (BM-CIM Macro). The BM-CIM Macro operates as follows: Weights within the device are divided into four groups. Weights stored in the same row of the SRAM subarray of the in-memory computation array belong to the same weight set. When performing convolution calculations, one row of the SRAM subarray is activated, sending one weight set to the Booth Multiplication Computation Unit (BMCC) for Booth operations. The BMCC outputs 64 intermediate calculation results to the bit extension unit for bit extension, outputting 64 sets of 6-bit intermediate products to the adder tree unit. Due to time-division multiplexing, the number of parallel operation groups within the device is reduced, thus reducing the circuit size of the adder tree unit. It only needs to go through 6 stages of step-by-step accumulation to output the 12-bit partial sum PSUM to the accumulator unit. The accumulator unit captures the partial sum PSUM and performs bit extension on it. "If the partial sum PSUM is a signed number, its sign bit (most significant bit) is extended; if the partial sum PSUM is an unsigned number, it is zero-extended." Simultaneously, depending on the number of operation groups configured in the device, it is determined whether to shift the accumulated SUM value two bits to the left, and then add the two processed addends together. After multiple cycles of iteration, a 20-bit convolution calculation result R is obtained through clock sampling.
[0053] The accumulator unit needs to perform three operations: (1) sample the partial sum PSUM output by the adder tree unit in the current cycle and perform bit expansion on the partial sum PSUM; (2) shift the accumulated value SUM obtained in the previous N cycles to the left by two bits (1≤N≤4), where N can be configured according to the scale of the applied convolutional neural network; (3) add the bit-expanded partial sum PSUM to the shifted accumulated value SUM to obtain a new accumulated value SUM and temporarily store it in the accumulator unit; (4) iterate the above operations (1)-(3) repeatedly through several cycles to finally sample the output convolution operation and output R. Therefore, relying on the dynamic configuration of the shift period of the accumulator, when performing convolution operation, the device can adjust the number of operation groups according to the scale of the applied convolutional neural network, thereby realizing reconfigurable convolution operation.
[0054] As a solution of the present invention, the reconfigurable convolution operation timing is as follows: Figure 8 As shown, for large-scale networks, the device may need to process four different weight sets simultaneously. In this case, the device inputs computational data with the same bit weights over four consecutive clock cycles. These four sets of computational data are sequentially computed with the four weight sets, generating four 12-bit partial sums as outputs. Since the bit weights are the same, the accumulator does not need to shift during these four cycles; it simply accumulates these partial sums. When the bit weights of the input data change in the fifth clock cycle, the accumulator activates a shift signal, shifting the previously accumulated result two bits to the left and adding it to the new partial sum. Therefore, in the case of large-scale networks, the accumulator shifts once every four clock cycles. Conversely, for small-scale convolutional neural networks, the system may only need to process one set of weights. In this case, the bit weights of the input data change after each clock cycle, so the accumulator performs a shift operation after each clock cycle to adapt to the rapidly changing data bit weights. In summary, the architecture can flexibly adjust the number of convolutional computation sets to efficiently process convolutional neural networks of varying sizes, thereby optimizing computational resources and improving processing efficiency.
[0055] Reference Figure 9The figure shows the transient simulation waveform during the Booth Multiplication In-Memory Computation Data Block (BMCDB) computation operation. Before the computation operation, four sets of weight values, 0111, 0111, 1000, and 0001, are pre-stored in the SRAM subarray (4×4). Then, in four consecutive operation cycles, the four sets of weight values are sequentially sent to the BMCDB for computation. The input data in the four cycles are 110, 110, 111, and 010, respectively. In the first and second cycles, the Booth encoding result of 110 is "-x", so the complement of 0111 is taken and the sign bit is extended to obtain a 6-bit intermediate product 111001. In the third cycle, the Booth encoding result of 111 is "0", so the intermediate product output is cleared to 000000. In the fourth cycle, the Booth encoding result of 010 is "x", so the intermediate product is the sign bit extended of 0001, i.e., 000001.
[0056] like Figure 10 The figure shows the transient simulation waveform of the device performing convolution operations. During the test, all input data IN is 4 bits (i.e., the actual data used for convolution calculation is 4 bits, and the data input to the input encoding module is 3 consecutive bits of this 4-bit data, padded with 0s where necessary). The number of convolution calculation groups is 64×64 groups. Starting from the MSB, 2 bits of input data are input into the architecture for operation each operation cycle. The input with bit weight IN<3:2> is input into the architecture sequentially in four consecutive operation cycles to obtain the corresponding partial sum through multiplication and accumulation operations. When the input bit weight changes to IN<1:0> in the fifth cycle, the partial sum generated by IN<3:2> is shifted two bits to the left and accumulated with the partial sum generated by IN<1:0>. Finally, after nine operation cycles, the final 20-bit convolution calculation result R is output. As can be seen from the waveform, at 517ns, the calculation validity signal ACTIVE is set to "1", and the sign flag SIGN is valid. At this time, the system starts to perform multiplication and accumulation operations based on Booth encoding. During the calculation process, multiple intermediate products P and partial sums PSUM are continuously flipped. After 8 operation cycles, all 4 bits IN are input. The shift accumulator sets the calculation completion signal DONE to "1", enabling the flip-flops in the accumulator to sample the final calculation result. At 535ns, the 20-bit convolution calculation result R is output.
Claims
1. A reconfigurable digital in-memory computing device based on a multiplexed Booth computing unit and 6T-SRAM, characterized in that, It includes one input encoding module and 64 Booth multiplication in-memory computation processors; The input encoding module takes the externally received symbol flag signal and 64 consecutive 3-bit data to obtain the control signal for the Booth operation; The Booth multiplication in-memory computation processor includes an in-memory computation array, a bit extension unit, an adder tree unit, and an accumulator unit. The in-memory computation array consists of 1 row and 64 columns of Booth multiplication in-memory computation data blocks. Each Booth multiplication in-memory computation data block includes an SRAM subarray and a Booth computation unit. The SRAM subarray consists of 4 rows and 4 columns of 6T-SRAM units. The in-memory computing array has two working modes: storage mode and computing mode. In storage mode, the in-memory computing array stores externally input weight data, and the weight data is stored in the 6T-SRAM cells of the SRAM subarray. In computation mode, the Booth computation unit receives the control signal of the Booth operation and performs calculations based on the weight data stored in the SRAM subarray to obtain 64 intermediate computation results. The bit extension unit performs bit extension operations on the 64 intermediate computation results to obtain 64 6-bit intermediate products. The adder tree unit accumulates the intermediate products to obtain a partial sum. The accumulator unit performs shift accumulation on the partial sum and outputs a 20-bit convolution computation result.
2. The apparatus according to claim 1, characterized in that, The Booth multiplication in-memory computation data block is computed using a time-division multiplexing method. Each SRAM subarray consists of four SRAM banks, and each SRAM bank consists of 1 row and 4 columns of 6T-SRAM cells. The four SRAM banks in a Booth multiplication in-memory computation data block time-division multiplex one Booth computation unit, which performs multiplication operations.
3. The apparatus according to claim 2, characterized in that, The Booth multiplication in-memory computing processor also includes a read / write driver unit, which is used to control the read and write operations of the in-memory computing array.
4. The apparatus according to claim 3, characterized in that, The device also includes an address decoder and a clock control module; The address decoder receives an externally input address signal. When the in-memory computing array is in storage mode, the address decoder outputs a column address signal to the read / write driver unit. The read / write driver unit reads out or writes the weight data into the corresponding Booth multiplication in-memory computing data block according to the column address signal. The address decoder outputs a row address signal to the Booth multiplication in-memory computing data block. The Booth multiplication in-memory computing data block stores the weight data written by the read / write driver unit into the corresponding SRAM Bank according to the row address signal, or the Booth multiplication in-memory computing data block reads out the weight data stored in the corresponding SRAM Bank through the read / write driver unit according to the row address signal. When the in-memory computing array is in computing mode, the address decoder outputs a row address signal to the Booth multiplication in-memory computing data block. The Booth multiplication in-memory computing data block reads out the weight data from the 64 SRAM Banks at that row address according to the row address signal. Each SRAM Bank stores 4 bits of weight data. The clock control module receives an externally input enable signal, outputs a state transition control signal to the address decoder, and outputs a read / write drive signal to the read / write drive unit. The address decoder determines the current working mode of the in-memory computing array based on the state transition control signal and performs the corresponding decoding operation. The read / write drive unit determines whether to read or write weight data at the current moment based on the read / write drive signal.
5. The apparatus according to claim 1, characterized in that, The 64 consecutive 3-bit data points are consecutive 3-bit data points from the same group of 64*N values to be convolved, and each consecutive 3-bit data point has the same bit weight; the 64*N values to be convolved are all in binary format, where N is an array, 1≤N≤4.
6. The apparatus according to claim 1, characterized in that, The input encoding module includes 64 Booth multiplier encoders, which input a sign flag signal and 64 3-bit continuous data, and output control signals for 64 Booth operations to 64 Booth calculation units. The control signals for the Booth operation include the shift enable signal SHIFT, the clear enable signal ZERO, the inverse enable signal INV, and the triple enable signal TRIPLE.
7. The apparatus according to claim 6, characterized in that, When the sign flag signal is 1, if the input 3-bit data is 001 or 010, the shift enable signal SHIFT, the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 011, the shift enable signal SHIFT is 1, and the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 100, the clear enable signal ZERO and the triple enable signal TRIPLE are both 0, and the shift enable signal SHIFT and the invert enable signal INV are both 1. If the input 3-bit data is 101 or 110, the invert enable signal INV is 1, and the shift enable signal SHIFT, the clear enable signal ZERO, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 000 or 111, the clear enable signal ZERO is 1.
8. The apparatus according to claim 7, characterized in that, When the sign flag signal is 0, if the input 3-bit data is 000 or 001, the clear enable signal ZERO is 1. If the input 3-bit data is 010 or 011, the shift enable signal SHIFT, the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 100 or 101, the shift enable signal SHIFT is 1, and the clear enable signal ZERO, the invert enable signal INV, and the triple enable signal TRIPLE are all 0. If the input 3-bit data is 110 or 111, the shift enable signal SHIFT, the clear enable signal ZERO, and the invert enable signal INV are all 0, and the triple enable signal TRIPLE is 1.
9. The apparatus according to claim 5, characterized in that, The specific calculation steps of the accumulator unit are as follows: 1) The accumulator unit receives a partial sum from the adder tree output during the current clock cycle and performs bit extension; 2) Add the bit-extended partial sum to the accumulated value stored in the accumulator. If the accumulated value of the current clock cycle is the accumulated value obtained by accumulating the partial sums of the previous N clock cycles, then add two zeros to the value of the accumulated value, and add the accumulated value after adding the two zeros to the bit-extended partial sum. The result of the addition is stored in the accumulator as a new accumulated value. If the accumulated value in the current clock cycle is not the accumulated value obtained by summing the partial sums of the previous N clock cycles, the partial sum after bit extension is added to the accumulated value, and the result is stored in the accumulator as the new accumulated value. 3) Repeat steps 1) and 2) until all 64*N partial sums are accumulated. The accumulator finally outputs a 20-bit convolution calculation result.