A clock synchronization method between multiple EtherCAT network segments

Abstract

The present invention discloses a method for clock synchronization between multiple EtherCAT network segments, including: Step 1, synchronize the clocks of multiple slave stations within each of the multiple EtherCAT network segments; Step 2, the MCU generates a pulse signal LATCH; Step 3, when ESC1 and ESC5 detect the rising edge of the LATCH signal, latch the local system time, which are T1 and T5 respectively; Step 4, the MCU reads the time T1 of the rising edge of the LATCH latched by ESC1 and writes T1 into ESC5; Step 5, ESC5 compares T5 and T1, if T5 > T1, slow down the local time; if T5 < T1, speed up the local time; Step 6, the MCU periodically generates the LATCH signal, reads T1 and writes T1 into ESC5; Step 7, ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, realizing clock synchronization of multiple network segments. Timestamp latching and time adjustment are both implemented by ESC, and the MCU software only responsible for data transmission and does not participate in clock adjustment, so clock errors will not be introduced.

Description

Technical Field

[0001] The present invention relates to the field of clock synchronization, and specifically to a clock synchronization method between multiple EtherCAT network segments. Background Art

[0002] EtherCAT is a high-performance, low-cost, and topologically flexible industrial Ethernet technology, which is widely used in the field of industrial automation and can achieve high-precision control of multi-axis servo drives.

[0003] EtherCAT supports direct-mode and open-mode;

[0004] In direct mode, the clock synchronization accuracy within 1 us can be achieved between各级 ESC (Ethernet Slave Controller).

[0005] In open mode, the clock synchronization between different EtherCAT network segments can only be achieved through the communication between EtherCAT masters. The clock synchronization accuracy achieved by this software solution is relatively low, only reaching the millisecond level.

[0006] With the development of networks and intelligence, the application scenarios of the EtherCAT open mode will increase day by day. Therefore, a solution with higher clock synchronization accuracy is needed to solve the problem of relatively low clock synchronization accuracy between different EtherCAT network segments. Summary of the Invention

[0007] Object of the Invention: To provide a clock synchronization method between multiple EtherCAT network segments to solve the above problems existing in the prior art.

[0008] Technical Solution: A clock synchronization method between multiple EtherCAT network segments includes:

[0009] Step 1: Synchronize the clocks of multiple slave stations within their respective internal of multiple EtherCAT network segments;

[0010] Step 2: The MCU generates a pulse signal LATCH;

[0011] Step 3: When ESC1 and ESC5 detect the rising edge of the LATCH signal, latch the local system time, which are T1 and T5 respectively;

[0012] Step 4: The MCU reads the time T1 of the rising edge of the LATCH latched by ESC1 and writes T1 into ESC5;

[0013] Step 5: ESC5 compares T5 and T1. If T5>T1, slow down the local time; if T5<T1, speed up the local time;

[0014] Step 6, MCU periodically generates LATCH signal, reads T1 and writes T1 into ESC5;

[0015] Step 7: ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, thereby achieving clock synchronization of multiple network segments;

[0016] ESC1 represents the slave station of EtherCAT segment 1;

[0017] ESC5 indicates the slave station of EtherCAT segment 2;

[0018] The above only describes the clock synchronization process between two network segments. This method can be extended to more EtherCAT network segments. You only need to connect the LATCH signal generated by the MCU to the ESC where the reference clock of different network segments is located.

[0019] In the above solution, timestamp latching and time adjustment are both implemented by ESC. The MCU software is only responsible for data transmission and does not participate in clock adjustment, so it will not introduce clock errors. The clock synchronization process between network segments is completely implemented by hardware and will not reduce the clock synchronization accuracy that has been achieved within the network segment. Compared with the software solution, the clock synchronization accuracy of the hardware solution is significantly improved. This hardware synchronization solution, applied to the field of industrial control, can also achieve better control accuracy.

[0020] In a further embodiment, step 1 further comprises:

[0021] When synchronizing the clocks within multiple EtherCAT segments, the system time error within each level of ESC is maintained less than 1us. To achieve clock synchronization within the segment, the EtherCAT master and ESC execute:

[0022] Step 11: Propagation delay measurement;

[0023] Step 111, the master station sends a broadcast frame and writes the 0x900 register;

[0024] Step 112: When the ports of each level of ECS receive the SOF of the broadcast frame, the local clock is latched;

[0025] Step 113, the master station reads the port time saved by each ESC, calculates the propagation delay between each level of ESC and the reference clock, and then distributes the propagation delay to each level of ESC;

[0026] When each level of ECS latches the local clock, ESC-A saves T(A0) and T(A1), where T(A1) is the local clock of port 1 of ESC-A executing step 112. ESC-B saves T(B0) and T(B1), and ESC-C saves T(C0);

[0027] T(A0): local clock of port 0 of ESC-A executing step 112;

[0028] T(A1): local clock of port 1 of ESC-A executing step 112;

[0029] T(B0): local clock of port 0 of ESC-B executing step 112;

[0030] T(B1): local clock of port 1 of ESC-B executing step 112;

[0031] T(C0): local clock of port 0 of ESC-C executing step 112;

[0032] Assume ESC-A is the reference clock, whose propagation delay is 0, ESC-C and ESC-B represent slave clocks;

[0033] The propagation delay of ESC-C is: T(AC) = (T(A1) - T(A0)) / 2;

[0034] The propagation delay of ESC-B is: T(AB) = (T(A1) - T(A0)) / 2 - (T(B1) - T(B0)) / 2;

[0035] Step 12: offset compensation;

[0036] The local clock and reference clock of each ESC are inconsistent. The master station calculates the offset between the reference clock and each slave clock and distributes the offset to the ESC. After offset compensation, T (local system time) = local time + offset. The local system time difference between each ESC is also reduced to millisecond level.

[0037] Offset = propagation delay measurement + difference in local clock caused by the order in which each ESC is powered on;

[0038] Step 13: Drift compensation;

[0039] After offset compensation, the clock synchronization accuracy between ESCs at all levels reaches the millisecond level. Due to the difference in clock sources between ESCs at all levels, the clock synchronization accuracy between ESCs at all levels will further decrease over time. Through drift compensation, the clock synchronization accuracy between ESCs at all levels can be reduced to within 100ns and maintained within this range.

[0040] The master sends an EtherCAT frame with an ARMW or FRMW addressing command to access address 0x910;

[0041] The EtherCAT frame reads the local system time T of the reference clock and distributes this time to each slave clock, which calculates the drift ΔT:

[0042] ΔT = (local time + offset - propagation delay) - receiving system time;

[0043] If ΔT>0, it means that the local time is faster than the system time and the local time needs to be slowed down;

[0044] If ΔT<0, it means that the local time is slower than the system time and the local time needs to be adjusted faster;

[0045] By periodically sending synchronization frames from the master station, each level of ESC will continuously correct the local time, thereby maintaining a clock synchronization accuracy within 1us.

[0046] The receiving system time is the local system time T of the reference clock read from the Ethercat frame.

[0047] When an Ethercat frame passes through a reference clock, the time of the reference clock will be uploaded to the frame data, and the slave clock will download this time data to the local for calculation. If the time difference is positive, it means that the time is running fast and needs to be slowed down. It is like the process of checking a watch.

[0048] Beneficial effects: The present invention discloses a clock synchronization method between multiple EtherCAT network segments. The present invention uses MCU to periodically generate LATCH signals, read T1 and write T1 into ESC5; ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, thereby achieving clock synchronization of multiple network segments; through the above scheme, timestamp latching and time adjustment are both achieved by ESC, and MCU software is only responsible for data transmission and does not participate in clock adjustment, so clock errors will not be introduced. The clock synchronization process between network segments is completely achieved by hardware, and the clock synchronization accuracy that has been achieved inside the network segment will not be reduced. Compared with the software solution, the clock synchronization accuracy of the hardware solution is significantly improved. This hardware synchronization solution, when applied to the field of industrial control, can also achieve better control accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 It is a schematic diagram of clock synchronization between EtherCAT network segments of the present invention.

[0050] Figure 2 It is a schematic diagram of the propagation delay measurement of the present invention.

[0051] Figure 3 It is a schematic diagram of drift compensation of the present invention.

[0052] Figure 4 It is a schematic diagram of the drift compensation process of the present invention.

[0053] Figure 5 It is a schematic diagram of the EtherCAT open mode connection of the present invention. DETAILED DESCRIPTION

[0054] This application relates to a clock synchronization method between multiple EtherCAT network segments. Clock synchronization involves the following concepts:

[0055] System time

[0056] System time is the system time used by the distributed clock.

[0057] Reference clock and slave clock

[0058] The clock of the first ESC with DC function connected to the master station is used as the reference clock, and the clocks of the remaining ESCs are called slave clocks.

[0059] The time of the reference clock is distributed to the slave clock, so that the slave clock and the reference clock can achieve clock synchronization. The reference clock can be adjusted to a global clock reference (such as an IEEE1588 master clock), and the reference clock provides system time.

[0060] Local clock

[0061] Each ESC has a local clock, which is independent of the reference clock. The difference between the local clock and the reference clock can be eliminated by offset compensation and drift compensation. Each ESC saves a local system time, which is local system time = local clock + offset.

[0062] Master clock

[0063] The master station clock is usually bound to a global clock reference (such as RTC, PC host or IEEE1588). The EtherCAT master station can directly obtain the master station clock, and the master station can also distribute the master station clock to slave stations at all levels.

[0064] Propagation Delay

[0065] The time it takes for an EtherCAT frame to reach the slave clock from the reference clock is called propagation delay. The propagation delay is composed of the cable between ESCs, ESC frame processing, and PHY data delay.

[0066] Offset

[0067] The skew between the local clock and the reference clock is caused by two reasons:

[0068] 1. Propagation delay between reference clock and slave clock;

[0069] 2. The local clock differences caused by the power-on of each ESC can be compensated by the offset of each ESC. The offset is calculated by the master station and distributed to each level of ESC by the master station.

[0070] drift

[0071] Due to the inconsistency of the crystal oscillator sources of each ESC, the difference in the clock sources results in a slight difference in each cycle, which further leads to the inconsistency of the local timing speed of each ESC. This error will also accumulate over time.

[0072] The following is a detailed explanation through specific implementation manners.

[0073] A clock synchronization method between multiple EtherCAT network segments includes:

[0074] Step 1, synchronize the clocks of multiple slave stations inside each of the multiple EtherCAT network segments;

[0075] Step 2, the MCU generates a pulse signal LATCH;

[0076] Step 3, when ESC1 and ESC5 detect the rising edge of the LATCH signal, latch the local system time, which are T1 and T5 respectively;

[0077] Step 4, the MCU reads the time T1 of the rising edge of the LATCH latched by ESC1 and writes T1 into ESC5;

[0078] Step 5, ESC5 compares T5 and T1. If T5>T1, slow down the local time; if T5<T1, speed up the local time;

[0079] Step 6, the MCU periodically generates the LATCH signal, reads T1 and writes T1 into ESC5;

[0080] Step 7, ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, and further achieve clock synchronization of multiple network segments;

[0081] ESC1 represents the slave station of EtherCAT network segment 1;

[0082] ESC5 represents the slave station of EtherCAT network segment 2;

[0083] The above only illustrates the clock synchronization process between two network segments. This method can be extended to more EtherCAT network segments, and only needs to connect the LATCH signal generated by the MCU to the ESC where the reference clock of different network segments is located.

[0084] In the above solution, timestamp latching and time adjustment are both implemented by ESC. The MCU software is only responsible for data transmission and does not participate in clock adjustment, so it will not introduce clock errors. The clock synchronization process between network segments is completely implemented by hardware and will not reduce the clock synchronization accuracy that has been achieved within the network segment. Compared with the software solution, the clock synchronization accuracy of the hardware solution is significantly improved. This hardware synchronization solution, applied to the field of industrial control, can also achieve better control accuracy.

[0085] The step 1 also includes:

[0086] When synchronizing the clocks within multiple EtherCAT segments, the system time error within each level of ESC is maintained less than 1us. To achieve clock synchronization within the segment, the EtherCAT master and ESC execute:

[0087] Step 11: Propagation delay measurement, as shown in the attached Figure 2 As shown;

[0088] Step 111, the master station sends a broadcast frame and writes register 0x900;

[0089] Step 112: When the ports of each level of ECS receive the SOF of the broadcast frame, the local clock is latched;

[0090] Step 113, the master station reads the port time saved by each ESC, calculates the propagation delay between each level of ESC and the reference clock, and then distributes the propagation delay to each level of ESC;

[0091] When each level of ECS latches the local clock, ESC-A saves T(A0) and T(A1), ESC-B saves T(B0) and T(B1), and ESC-C saves T(C0);

[0092] T(A0): local clock of port 0 of ESC-A executing step 112;

[0093] T(A1): local clock of port 1 of ESC-A executing step 112;

[0094] T(B0): local clock of port 0 of ESC-B executing step 112;

[0095] T(B1): local clock of port 1 of ESC-B executing step 112;

[0096] T(C0): local clock of port 0 of ESC-C executing step 112;

[0097] Assume ESC-A is the reference clock, whose propagation delay is 0, ESC-C and ESC-B represent slave clocks;

[0098] The propagation delay of ESC-C is: T(AC) = (T(A1) - T(A0)) / 2;

[0099] The propagation delay of ESC-B is: T(AB) = (T(A1) - T(A0)) / 2 - (T(B1) - T(B0)) / 2;

[0100] Step 12: Offset compensation, as shown in the attached Figure 3 As shown;

[0101] The local clock and reference clock of each ESC are inconsistent. The master station calculates the offset between the reference clock and each slave clock and distributes the offset to the ESC. After offset compensation, T (local system time) = local time + offset. The local system time difference between each ESC is also reduced to millisecond level.

[0102] Offset = propagation delay measurement + difference in local clock caused by the order in which each ESC is powered on;

[0103] Step 13: Drift compensation, as shown in the attached Figure 4 As shown;

[0104] After offset compensation, the clock synchronization accuracy between ESCs at all levels reaches the millisecond level. Due to the difference in clock sources between ESCs at all levels, the clock synchronization accuracy between ESCs at all levels will further decrease over time. Through drift compensation, the clock synchronization accuracy between ESCs at all levels can be reduced to within 100ns and maintained within this range.

[0105] The master sends an EtherCAT frame with an ARMW or FRMW addressing command to access address 0x910;

[0106] The EtherCAT frame reads the local system time T of the reference clock and distributes this time to each slave clock, which calculates the drift ΔT:

[0107] ΔT = (local time + offset - propagation delay) - receiving system time;

[0108] If ΔT>0, it means that the local time is faster than the system time and the local time needs to be slowed down;

[0109] If ΔT<0, it means that the local time is slower than the system time and the local time needs to be adjusted faster;

[0110] By periodically sending synchronization frames from the master station, each level of ESC will continuously correct the local time, thereby maintaining a clock synchronization accuracy within 1us.

[0111] The receiving system time is the local system time T of the reference clock read from the Ethercat frame.

[0112] When the Ethercat frame passes through the reference clock, the time of the reference clock is uploaded into the frame data. Subsequently, the following slave clocks will download this time data to the local for calculation. If the time difference is positive, it means the time is running fast and needs to be adjusted slower. It's like the process of synchronizing watches.

[0113] As Figure 5 shown, in the open mode, an EtherCAT network segment consists of multiple ESC (EtherCAT slave controller), and multiple EtherCAT network segments can be connected to a standard switch device.

[0114] As Figure 5 shown, master station 1 can control network segment 1, and master station 2 can control network segment 2. In addition, master station 1, master station 2 and general Ethernet devices can also communicate with each other. The open mode is usually applied to relatively complex industrial control systems. To achieve clock synchronization between network segment 1 and network segment 2, the two network segments need to first achieve internal clock synchronization respectively, and then achieve clock synchronization between network segment 1 and network segment 2.

[0115] Principle description:

[0116] Step 1: Synchronize the clocks of multiple slaves within each of the multiple EtherCAT network segments;

[0117] Step 2: The MCU generates a pulse signal LATCH;

[0118] Step 3: When ESC1 and ESC5 detect the rising edge of the LATCH signal, they latch the local system time, which are T1 and T5 respectively;

[0119] Step 4: The MCU reads the time T1 of the rising edge of the LATCH latched by ESC1 and writes T1 into ESC5;

[0120] Step 5: ESC5 compares T5 and T1. If T5 > T1, it slows down the local time; if T5 < T1, it speeds up the local time;

[0121] Step 6: The MCU periodically generates the LATCH signal, reads T1 and writes T1 into ESC5;

[0122] Step 7: ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, and thus achieve clock synchronization of multiple network segments;

[0123] ESC1 represents the slave of EtherCAT network segment 1;

[0124] ESC5 represents the slave of EtherCAT network segment 2;

[0125] The above only describes the clock synchronization process between two network segments. This method can be extended to more EtherCAT network segments. You only need to connect the LATCH signal generated by the MCU to the ESC where the reference clock of different network segments is located.

[0126] The preferred specific embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above specific embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical scheme of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.

Claims

1. A clock synchronization method between multiple EtherCAT network segments, characterized in that: Including: Step 1: Synchronize the clocks of multiple slaves within their respective internal EtherCAT segments; The said Step 1 further includes: When synchronizing the clocks within multiple EtherCAT segments, maintain the system time error within each level of ESC to be less than 1 us. To achieve clock synchronization within the segment, the EtherCAT master station and ESC execute: Step 11: Propagation delay measurement; The said Step 11 includes: Step 111: The master station sends a broadcast frame to write the 0x900 register; Step 112: When the SOF of the broadcast frame is received at the ports of each level of ECS, latch the local clock; Step 113: The master station reads the port time saved in each ESC, calculates the propagation delay between each level of ESC and the reference clock, and then distributes the propagation delay to each level of ESC; When each level of ECS latches the local clock, ESC-A saves T(A0) and T(A1), ESC-B saves T(B0) and T(B1), and ESC-C saves T(C0); Assume ESC-A is the reference clock, with its propagation delay being 0, and ESC-C and ESC-B represent slave clocks; The propagation delay of ESC-C is: T(AC) = (T(A1) - T(A0)) / 2; The propagation delay of ESC-B is: T(AB) = (T(A1) - T(A0)) / 2 - (T(B1) - T(B0)) / 2; Step 2: The MCU generates a pulse signal LATCH; Step 3: When ESC1 and ESC5 detect the rising edge of the LATCH signal, latch the local system time, which are T1 and T5 respectively; Step 4: The MCU reads the time T1 of the rising edge of LATCH latched by ESC1 and writes T1 into ESC5; Step 5: ESC5 compares T5 and T1. If T5 > T1, slow down the local time; if T5 < T1, speed up the local time; Step 6: The MCU periodically generates the LATCH signal, reads T1 and writes T1 into ESC5; Step 7: ESC5 periodically adjusts the local system time to achieve clock synchronization with ESC1, and further achieve clock synchronization of multiple segments; ESC1 represents a slave station in EtherCAT segment 1; ESC5 represents a slave station in EtherCAT segment 2; Step 12: Offset compensation; The said Step 12 includes: The local clocks of each level of ESC are inconsistent with the reference clock. The master station calculates the offset between the reference clock and each slave clock and distributes this offset to the ESC. After offset compensation, T (local system time) = local time + offset, and the difference in local system time between each level of ESC is also reduced to the millisecond level; Offset = propagation delay measurement + difference in local clocks caused by the power-on sequence of each level of ESC; Step 13: Drift compensation, The said Step 13 includes: After offset compensation, the clock synchronization accuracy between ESCs at all levels reaches the millisecond level. Due to the difference in clock sources between ESCs at all levels, the clock synchronization accuracy between ESCs at all levels will further decrease over time. Through drift compensation, the clock synchronization accuracy between ESCs at all levels can be reduced to within 100ns and maintained within this range. The master sends an EtherCAT frame with an ARMW or FRMW addressing command to access address 0x910; The EtherCAT frame reads the local system time T of the reference clock and distributes this time to each slave clock. The slave clock calculates the drift ΔT: ΔT = (local time + offset – propagation delay) – receiving system time; If ΔT>0, it means that the local time is faster than the system time and the local time needs to be slowed down; If ΔT<0, it means that the local time is slower than the system time and the local time needs to be adjusted faster; By periodically sending synchronization frames from the master station, each level of ESC will continuously correct the local time, thereby maintaining a clock synchronization accuracy within 1us.

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