一种基于FPGA的最小二乘法时钟同步精度补偿方法及系统
By implementing least-squares clock synchronization accuracy compensation through FPGA hardware, the problem of excessive network load caused by frequency drift in the IEEE 1588 protocol is solved, achieving high-precision clock synchronization and improving network efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- ZHEJIANG SUPCON RES
- Filing Date
- 2025-06-26
- Publication Date
- 2026-07-17
AI Technical Summary
In the clock synchronization process of the existing IEEE 1588 protocol, frequency drift occurs due to the difference in stability of the crystal oscillators of the master and slave clock devices and the influence of external factors. Traditional methods correct clock deviation by increasing the frequency of synchronization messages, but this leads to excessive network load and affects system performance.
An FPGA-based least squares clock synchronization accuracy compensation method is adopted. By parsing the timestamp data of the master and slave clock devices, the least squares method is used to calculate the fitting curve, and the macro period is limited to compensate for clock deviation, thereby reducing the frequency of synchronization messages and improving synchronization accuracy and network efficiency.
It significantly improves clock synchronization accuracy, reduces network load, avoids network congestion, provides higher computing efficiency and real-time performance, and is scalable and maintainable.
Smart Images
Figure CN120691981B_ABST