A low-frequency time code anti-interference decoding method, system, device and medium

Abstract

The present application belongs to the technical field of radio time signal receiving and processing, and discloses a low-frequency time code anti-interference decoding method, system, device and medium; wherein the low-frequency time code anti-interference decoding method comprises: acquiring a low-frequency time code radio signal and adjusting the shape through an amplitude modulation wave, and outputting a TTL signal stream; inputting the TTL signal stream into an FPGA for decoding to obtain a decoding result; the FPGA comprises: a code element capture module for analyzing a code element capture start time; a code element analysis module for comparing pre-stored ideal code element waveforms of different code element values with code elements to be analyzed according to the TTL signal stream and the code element capture start time, and obtaining a code element analysis result; and a time code analysis module for completing a frame data analysis according to each code element analysis result in a frame, and outputting time code information and a decoding success identifier. The present application can improve the decoding success rate of a low-frequency time code user receiving terminal under a low signal-to-noise ratio condition.

Description

Technical Field

[0001] This invention belongs to the field of radio time signal reception and processing technology, and specifically relates to a low-frequency time code anti-interference decoding method, system, device and medium. Background Technology

[0002] Low-frequency timecode user receiver terminals (e.g., radio-controlled clocks, radio-controlled watches, etc.) are mostly located in urban areas, making them susceptible to various electromagnetic interferences. Reinforced concrete frame structures also shield low-frequency timecode radio signals, leading to a decrease in the signal-to-noise ratio (SNR) of the received signals. Furthermore, excessively long decoding times or failures in decoding by the user receiver terminal reduce user satisfaction. Therefore, the decoding success rate of low-frequency timecode user receiver terminals under low SNR conditions needs further improvement.

[0003] For a specific example, illustratively, patent application number TW093100278 discloses a radio wave decoding method for a radio clock, using the US WWVB time synchronization system as an example. The WWVB data frame period is 60s, the symbol period is 1s, and there are two consecutive interval symbols between two WWVB data frames. The interval symbol has a low level of 800ms and a high level of 200ms. (Illustratively, existing low-frequency time synchronization systems in the world, such as the German DCF77, the British MSF, the US WWVB, the Japanese JJY, and the Chinese BPC, all use pulse width modulation.) The invention application discloses a microcontroller-based technical solution. In the decoding process of two consecutive interval symbols, the level of each interval symbol is not judged in the 0ms~500ms and 800ms~1s intervals. Only the low level statistical judgment is performed in the 500ms~800ms interval. If the interval symbol is a deformed symbol due to interference, and the calculation result in the 500ms~800ms interval just meets the judgment condition, the interval symbol judgment is incomplete, which can easily lead to the interval symbol judgment error. Summary of the Invention

[0004] The purpose of this invention is to provide a low-frequency time code anti-interference decoding method, system, device, and medium to solve one or more of the aforementioned technical problems. Specifically, the technical solution provided by this invention is an anti-interference decoding scheme based on FPGA (Field Programmable Gate Array), which possesses a certain anti-interference decoding capability and can improve the decoding success rate of low-frequency time code user receiving terminals under low signal-to-noise ratio conditions.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides a low-frequency time code anti-interference decoding method, comprising the following steps:

[0007] It acquires low-frequency time-code radio signals, demodulates and shapes them using amplitude modulation, and outputs a TTL signal stream.

[0008] The TTL signal stream is input into the FPGA for decoding to obtain the decoding result;

[0009] The FPGA includes:

[0010] The symbol capture module is used to input a TTL signal stream and parse the start time of the captured symbol parsing from the TTL signal stream;

[0011] The symbol parsing module is used to input TTL signal stream and, based on the TTL signal stream and the start time of symbol parsing, compare the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed to obtain the symbol parsing result.

[0012] The timecode parsing module is used to complete the parsing of a frame of data based on the parsing results of each symbol in a frame, and output the timecode information and decoding success indicator.

[0013] A further improvement of the present invention is that, in the symbol acquisition module, the step of parsing the start time of the captured symbol parsing from the TTL signal stream includes:

[0014] A complete symbol without interference pulses is searched in the TTL signal stream, and the end time of the searched symbol is taken as the start time of parsing the symbol to be parsed.

[0015] A further improvement of the present invention is that, in the symbol parsing module, the step of comparing the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed based on the TTL signal stream and the symbol parsing start time to obtain the symbol parsing result includes:

[0016] Starting from the moment the parsing of the code to be parsed begins, the ideal code waveforms with different code values ​​pre-stored in the FPGA are respectively XORed and accumulated with the code to be parsed. Among them, for each ideal code, after the ideal code and the code to be parsed are calculated, the high and low level calculated values ​​are obtained. The high and low level calculated values ​​are compared with the high and low level pulse width values ​​of the ideal code, and the ideal code closest to the code to be parsed is obtained based on the comparison result. The code value of the code to be parsed is obtained according to the ideal code closest to the code to be parsed.

[0017] A further improvement of the present invention is that, after obtaining the symbol parsing result, the symbol parsing module further includes the following steps:

[0018] After a symbol is successfully parsed, the start time of parsing the next symbol to be parsed is the end time of the current symbol being successfully parsed.

[0019] If code parsing fails, the parsing start time of the next code to be parsed is the parsing start time obtained by the code capture module.

[0020] A further improvement of the present invention is that, in the timecode parsing module, the steps of parsing a frame of data based on the parsing results of each symbol within a frame and outputting timecode information and a decoding success identifier include:

[0021] Step 1: Continuously detect the start marker of a data frame. After detecting the start marker of a data frame, proceed to step 2.

[0022] Step 2: Store symbol values ​​sequentially according to the symbol start identifier, and determine whether a frame of data has been received completely; if a frame of data is successfully received, verify the received frame data. Regardless of whether the verification passes or fails, jump to step 1 to start the time code parsing of the next cycle; if the verification passes, generate a frame data decoding success identifier and the corresponding time code information; if the verification fails, do not generate a frame data decoding success identifier and time code information.

[0023] The start identifier of a data frame, the start identifier of a symbol, and the corresponding code value are all provided by the symbol parsing module, and all identifiers are valid on the rising edge.

[0024] A further improvement of the present invention is that the decoding process of the FPGA includes:

[0025] After the TTL signal stream enters the FPGA, it is split into two paths. One path enters the symbol capture module. When the symbol capture module successfully captures a complete symbol without interference pulses in the TTL signal stream, it generates a symbol capture identifier F1 pulse signal. The other path enters the symbol parsing module. The symbol parsing module parses the symbol value of each symbol based on the F1 pulse signal and the TTL signal stream, generating a frame data start identifier F2 pulse signal and a symbol start identifier F3 pulse signal. The time code parsing module generates a frame data decoding success identifier F4 pulse signal and time code information based on the F2 pulse signal, F3 pulse signal and symbol value. The time code information includes year, month, day, hour, minute, second and day of the week.

[0026] A second aspect of the present invention provides a low-frequency time code anti-interference decoding system, comprising:

[0027] The signal stream acquisition module is used to acquire low-frequency time-code radio signals, demodulate and shape them using amplitude-modulated waves, and output a TTL signal stream.

[0028] The decoding module is used to input the TTL signal stream into the FPGA for decoding and obtain the decoding result;

[0029] The FPGA includes:

[0030] The symbol capture module is used to input a TTL signal stream and parse the start time of the captured symbol parsing from the TTL signal stream;

[0031] The symbol parsing module is used to input TTL signal stream and, based on the TTL signal stream and the start time of symbol parsing, compare the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed to obtain the symbol parsing result.

[0032] The timecode parsing module is used to complete the parsing of a frame of data based on the parsing results of each symbol in a frame, and output the timecode information and decoding success indicator.

[0033] In a third aspect, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the low-frequency time code anti-interference decoding method as described in any one of the first aspects of the present invention.

[0034] In a fourth aspect, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the low-frequency time code anti-interference decoding method as described in any one of the first aspects of the present invention.

[0035] Compared with the prior art, the present invention has the following beneficial effects:

[0036] This invention discloses a low-frequency time-code anti-interference decoding method, specifically an FPGA-based anti-interference decoding method, which can improve the decoding success rate of low-frequency time-code user receiving terminals under low signal-to-noise ratio (SNR) conditions. Specifically, under low SNR conditions, the generated amplitude-modulated wave-shaped TTL signal will produce interference pulses. Existing conventional decoding methods rely on capturing signal edges to determine the start or end time of decoding and acquiring continuous high and low level pulse widths in the signal. The symbol value is determined by judging the high and low level pulse widths of the symbol. This traditional method, when encountering interference pulses, will cause errors in the start or end time of decoding, thus affecting the judgment of high and low level pulse widths, leading to decoding failure or decoding errors. The decoding method disclosed in this invention combines signal edge and symbol feature judgment for decoding, enabling successful decoding even when the signal has interference pulses, thereby improving the decoding success rate under low SNR conditions. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating a low-frequency time code anti-interference decoding method in an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the overall process of the BPC anti-interference decoding method in an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of symbol capture in an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the CEA code symbol parsing process in an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the CEB code element parsing process in an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of a low-frequency time code anti-interference decoding system in an embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0045] Please see Figure 1 In this embodiment of the invention, a low-frequency time code anti-interference decoding method is provided, comprising the following steps:

[0046] Step 1: Obtain the TTL signal stream output by the low-frequency time code amplitude modulated radio signal demodulated and shaped by the low-frequency time code receiving module, referred to as the Sig signal stream; Explain, TTL is the industry-standard way of describing voltage levels; Sig is the name of the signal.

[0047] Step 2: Input the Sig signal stream output in Step 1 into the FPGA for decoding to obtain the decoding result;

[0048] The FPGA includes:

[0049] The symbol capture module is used to input the Sig signal stream and parse the start time of the captured symbol parsing from it;

[0050] The symbol parsing module is used to input the Sig signal stream and, based on the Sig signal stream and the start time of symbol parsing, compare the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed to obtain the symbol parsing result.

[0051] The timecode parsing module is used to complete the parsing of a frame of data based on the parsing results of each symbol in a frame, and output the timecode information and decoding success indicator.

[0052] This invention provides an FPGA-based anti-interference decoding method with certain anti-interference decoding capabilities, which can improve the decoding success rate of low-frequency time-code user receiving terminals under low signal-to-noise ratio (SNR) conditions. Specifically, under low SNR conditions, the generated amplitude-modulated wave-shaped TTL signal will produce interference pulses. Existing conventional decoding methods rely on capturing signal edges to determine the start or end time of decoding and acquiring continuous high and low level pulse widths in the signal. The symbol value is determined by judging the high and low level pulse widths of the symbol. This traditional method, when encountering interference pulses, will cause errors in the start or end time of decoding, thus affecting the judgment of high and low level pulse widths, leading to decoding failure or decoding errors. The decoding method disclosed in this invention combines signal edge and symbol feature judgment for decoding, enabling successful decoding even with interference pulses, thus improving the decoding success rate under low SNR conditions.

[0053] In the specific exemplary technical solution of this invention, in the step of obtaining the Sig signal stream, the low-frequency time code amplitude-modulated radio signal is coupled into the low-frequency time code receiving module through an antenna.

[0054] In a preferred embodiment of the present invention, the step of parsing the start time of the captured symbol parsing in the symbol capture module of the above embodiment specifically includes:

[0055] A complete symbol without interference pulses is searched in the Sig signal stream, and the end time of the searched symbol without interference pulses is taken as the start time of parsing the symbol to be parsed.

[0056] In a preferred embodiment of the present invention, the step of executing ideal symbol waveforms based on pre-stored different symbol values, performing symbol parsing according to the start time of symbol parsing, and obtaining the symbol parsing result in the symbol parsing module of the above embodiment specifically includes:

[0057] Based on the ideal symbol waveforms with different symbol values ​​stored internally by the FPGA, starting from the beginning of the parsing process, the waveforms of the ideal symbol and the symbol to be parsed are simultaneously XORed and accumulated. Each ideal symbol and the symbol to be parsed has calculated high and low level values. If the symbol to be parsed is an ideal symbol, the calculated high and low level values ​​are the same as the pulse width values ​​of the ideal symbol. If the symbol to be parsed is close to the ideal symbol or has a small amount of interference, the calculated high and low level values ​​are near the pulse width values ​​of the ideal symbol. If the symbol to be parsed has a large amount of interference, exceeding the threshold for judging the high and low level values ​​of the ideal symbol, then the parsing fails. A threshold judgment is performed on the high and low level calculation results of each symbol. Based on the high and low level calculation results, the symbol waveform of the symbol to be parsed is determined to be closest to the ideal symbol value, and then the corresponding symbol value is parsed.

[0058] Furthermore, after a symbol parsing is successful, the start time for parsing the next symbol to be parsed does not rely on the start time obtained by the symbol capture module. Instead, the end time of the previous successful symbol parsing is used as the start time of the current symbol to be parsed. This achieves the effect of continuous anti-interference decoding. Explain this by saying that the capture principle of the symbol capture module is to first find the end time of an undisturbed symbol as the start time of the next symbol parsing. If this time is used for every symbol parsing, the effect of continuous anti-interference parsing will not be achieved. If a symbol parsing fails during continuous symbol parsing, the start time provided by the symbol capture module is used when resuming symbol parsing.

[0059] In the technical solution provided by this invention, the symbol parsing module can provide a data frame start identifier, a symbol start identifier, and the corresponding code value, all of which are valid on the rising edge. The time code parsing module cyclically detects the data frame start identifier. Upon detection, it stores the symbol values ​​sequentially according to the symbol start identifier and determines whether a data frame has been completely received. If a data frame is successfully received, it verifies the data frame. Regardless of whether the verification passes or fails, it returns to the step of detecting the data frame start identifier and begins the time code parsing of the next cycle. If the verification passes, a frame data decoding success identifier and the corresponding time code information are generated; if the verification fails, no frame data decoding success identifier and the corresponding time code information are generated.

[0060] Please see Figure 2 In this embodiment of the invention, a low-frequency time code anti-interference decoding system is provided, comprising: a receiving antenna, a low-frequency time code BPC receiving module, and an FPGA; wherein,

[0061] The low-frequency time code radio signal is coupled into the low-frequency time code BPC receiving module through the receiving antenna. After amplitude modulation demodulation and shaping, the output TTL signal Sig enters the FPGA and is decoded by the FPGA.

[0062] Specifically, for example, the demodulation chip of the low-frequency time code BPC receiving module can be CME6005, and the FPGA chip can be Altera's EP3C10E144C8.

[0063] Furthermore, the FPGA includes a symbol acquisition module, a symbol parsing module, and a time-code parsing module; wherein, the specific decoding process may include:

[0064] After the Sig signal stream enters the FPGA, it is divided into two paths. One path enters the symbol capture module. When the module successfully captures a complete symbol without interference in the Sig signal stream, it generates a symbol capture flag F1 pulse signal. The other path enters the symbol parsing module. The module parses the symbol value corresponding to each symbol based on the F1 pulse signal and the Sig signal stream, and generates a data start pulse flag F2 and a symbol start pulse flag F3.

[0065] The time code parsing module generates a frame data decoding success pulse identifier F4 and time code information based on the F2 pulse signal, F3 pulse signal, and symbol value. The time code information includes year, month, day, hour, minute, second, and day of the week.

[0066] In a specific and exemplary embodiment of this invention, my country's low-frequency time code BPC timing system has a transmission carrier frequency of 68.5 kHz, a frame period of 20 s, and a symbol period of 1 s. This invention, taking my country's BPC timing system as an example, specifically and exemplaryly proposes a low-frequency time code anti-interference decoding method.

[0067] Explained, the BPC symbol period is 1 second. The low-level pulse widths of the symbol are 100ms, 200ms, 300ms, and 400ms, representing symbol values ​​0, 1, 2, and 3, respectively. The interval code P0 is low by default, meaning that within one symbol period, the P0 code is always high. The purpose of the P0 code is to identify two frames of data. Thus, there are actually 5 waveforms for the BPC symbol.

[0068] When the low-frequency time code receiver module is interfered with or when the BPC transmission tower stops broadcasting, the output Sig of the low-frequency time code receiver module remains constant at either a low or high level, depending on the selected low-frequency time code receiver module. Searching only for a continuous 1-second high level in the Sig data stream to determine the interval code P0 is not rigorous enough. The correct approach is to first find the symbol preceding P0, and then find the P0 symbol. This method ensures accurate determination. Therefore, finding P0 requires at least two steps. If the symbol preceding P0 and the P0 symbol are considered as a 2-second symbol, the interval between two frames of data can be found in just one step based on the characteristics of this synthesized 2-second symbol. This also facilitates FPGA processing and fully utilizes the parallel computing capabilities of the FPGA. Based on these reasons, the original symbols are divided into two categories.

[0069] To implement the anti-interference decoding method described below, the original code symbols are redefined and divided into two categories. One category consists of code symbols with a period of 1 second, defined as CEA code symbols, such as... Figure 4 As shown, another type is the symbol with a period of 2 seconds, defined as the CEB symbol, such as... Figure 5 As shown, each type of symbol has four code values: 0, 1, 2, and 3. The low-level pulse widths of CEA and CEB symbols are the same: 100ms, 200ms, 300ms, and 400ms, respectively. The high-level pulse widths of CEA symbols are 900ms, 800ms, 700ms, and 600ms, respectively, while those of CEB symbols are 1900ms, 1800ms, 1700ms, and 1600ms, respectively.

[0070] In this embodiment of the invention, the symbol capture module is used to capture complete, interference-free symbols in the Sig signal stream, thus finding the start time for symbol parsing by the symbol parsing module. Specifically, the module detects any falling edge in the Sig signal stream, followed by a rising edge, records the low-level pulse width, and then detects a second falling edge, recording the high-level pulse width. The low-level and high-level pulse widths are then compared to determine if they conform to symbol characteristics. This symbol could be a CEA symbol or a CEB symbol. If it conforms to the symbol characteristics, a symbol capture flag F1 pulse signal is generated at the second falling edge.

[0071] Please see Figure 3 In this embodiment of the invention, there are 3 symbols in the Sig signal stream. The falling edge of symbol 1 is detected at time t0, and the detection of symbol 1 ends at time t1. Time t1 is also the time when the detection of symbol 2 begins. Since symbol 1 is a complete and interference-free symbol, an F1 pulse signal is generated. Since there is an interference pulse in symbol 2, no F1 pulse signal is generated at time t2. Similarly, in the detection of symbol 3, an F1 second pulse signal is generated at time t3.

[0072] In this embodiment of the invention, the symbol parsing module is used to perform symbol parsing on the Sig signal stream. The FPGA locally stores eight symbol waveforms, namely CEA symbols 0-3 and CEB symbols 0-3. These eight symbols are simultaneously XORed and accumulated with the Sig signal stream. If the symbol to be parsed in the Sig signal is a CEA symbol, such as... Figure 4 As shown, the intervals between t0~t1, t1~t2, t2~t3, and t3~t4 are 100ms, and the interval between t5~t6 is Tr. There is one interference pulse during the low level of the symbol and two interference pulses during the high level of the symbol. The rising edge of F1 or the rising edge of F3 is taken as the time t0. If it is the first symbol parsing, the rising edge of F1 is taken as the time t0. If it is not the first time, the rising edge of F3 is taken as the time t0. In this way, as long as the first symbol parsing is successful, the parsing of each subsequent symbol has the anti-interference effect until one of the symbol parsings fails, at which point the rising edge of F1 will be used as the time t0 again. Starting at time t0, CEA symbols 0 through 3 are simultaneously subjected to low-level XOR accumulation with the Sig signal. CEA symbol 0 saves its calculation result as MAL0 at time t1, CEA symbol 1 as MAL1 at time t2, CEA symbol 2 as MAL2 at time t3, and CEA symbol 3 as MAL3 at time t4. After saving the results, high-level XOR accumulation calculations begin. All four CEA symbols complete their calculations at time t5, saving the results as MAH0, MAH1, MAH2, and MAH3 respectively. MAL0 through MAL3 represent the width of the low-level signal within the ideal low-level range of the Sig symbol, while MAH0 through MAH3 represent the width of the high-level signal within the ideal high-level range of the Sig symbol. At time t5, based on MAL0 through MAL3 and MAH0 through MAH3, it is determined which of the four CEA symbols the currently parsed symbol belongs to. If none of the four CEA symbol features are met, symbol parsing fails in that cycle, and symbol capture and parsing begin in the next cycle. If one of the CEA symbol features is met, the falling edge in the Sig signal is detected. If the falling edge is detected and the timeout does not occur, this is counted as time t6. At this time, an F3 pulse marker is generated, the parsed symbol value is output, and then the next symbol parsing begins.

[0073] Assumption Figure 4The Sig signal is free of interference pulses. The code element to be tested in Sig is the ideal CEA code element 3, and Tr is 0. Then, the XOR accumulation result of MAL0 is 100ms, the XOR accumulation result of MAH0 is 600ms, the XOR accumulation result of MAL1 is 200ms, the XOR accumulation result of MAH1 is 600ms, the XOR accumulation result of MAL2 is 300ms, the XOR accumulation result of MAH2 is 600ms, the XOR accumulation result of MAL3 is 400ms, and the XOR accumulation result of MAH3 is 600ms. It can be seen that MAL3 and MAH3 best match the characteristics of CEA code element 3, so the decoded output code value is 3. The code element feature judgment relies on the judgment of MAL0~MAL1 and MAH0~MAH3 within a certain threshold range. If there are a small number of interference pulses in the Sig signal at this time, the calculation result will not change significantly and will not affect the code element value judgment. In reality, the waveform of the symbol to be tested cannot be an ideal waveform. The time t5 is advanced to the time t6 by Tr, which reserves time for detecting the falling edge of Sig. The smaller the value of Tr, the more likely it is to miss the detection of the falling edge. If the value of Tr is too large, it will affect the anti-interference effect.

[0074] Since the CEB and CEA symbols differ only in period, with identical low-level pulse widths, their symbol parsing methods are the same, such as... Figure 5 As shown, an F2 pulse marker is generated at time t6 to indicate the start of a data frame.

[0075] In this embodiment of the invention, the time code parsing module is used to locate the beginning of a frame of data based on the rising edge of F2, and the rising edge of F3 indicates the arrival of a parsing symbol. Based on the rising edge of F3 and its symbol value, the module sequentially obtains the symbol value of each symbol in a frame of data, verifies the frame of data, and after successful verification, extracts and outputs the time code information and generates a decoding success pulse flag F4.

[0076] The following are embodiments of the apparatus of the present invention, which can be used to execute embodiments of the method of the present invention. For details not disclosed in the apparatus embodiments, please refer to the embodiments of the method of the present invention.

[0077] Please see Figure 6 In this embodiment of the invention, a low-frequency time code anti-interference decoding system is provided, comprising:

[0078] The signal stream acquisition module is used to acquire low-frequency time-code radio signals, demodulate and shape them using amplitude-modulated waves, and output a TTL signal stream.

[0079] The decoding module is used to input the TTL signal stream into the FPGA for decoding and obtain the decoding result;

[0080] The FPGA includes:

[0081] The symbol capture module is used to input a TTL signal stream and parse the start time of the captured symbol parsing from the TTL signal stream;

[0082] The symbol parsing module is used to input the TTL signal stream and, based on the TTL signal stream and the start time of symbol parsing, compares the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed to obtain the symbol parsing result.

[0083] The timecode parsing module is used to complete the parsing of a frame of data based on the parsing results of each symbol in a frame, and output the timecode information and decoding success indicator.

[0084] In one embodiment of the present invention, a computer device is provided, comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the computer storage medium. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions from the computer storage medium to achieve a corresponding method flow or corresponding function. The processor described in this embodiment can be used to perform the operation of a low-frequency time code anti-interference decoding method.

[0085] In one embodiment of the present invention, a storage medium is provided, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space that stores the operating system of the terminal. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be a high-speed RAM memory or a non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the low-frequency time code anti-interference decoding method in the above embodiments.

[0086] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0087] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0088] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1The function specified in one or more boxes.

[0089] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0090] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A low-frequency time code anti-interference decoding method, characterized in that, Includes the following steps: It acquires low-frequency time-code radio signals, demodulates and shapes them using amplitude modulation, and outputs a TTL signal stream. The TTL signal stream is input into the FPGA for decoding to obtain the decoding result; The FPGA includes: The symbol capture module is used to input a TTL signal stream and parse the start time of the captured symbol parsing from the TTL signal stream; The symbol parsing module is used to input the TTL signal stream and, based on the TTL signal stream and the start time of symbol parsing, compares the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed to obtain the symbol parsing result. The time code parsing module is used to complete the parsing of a frame of data based on the parsing results of each symbol in a frame, and output the time code information and decoding success identifier; In the symbol parsing module, the steps of comparing the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed based on the TTL signal stream and the symbol parsing start time to obtain the symbol parsing result include: starting from the parsing start time of the symbol to be parsed, performing XOR accumulation calculations on the ideal symbol waveforms of different pre-stored symbol values ​​in the FPGA with the symbol to be parsed; wherein, for each ideal symbol, after the calculation between the ideal symbol and the symbol to be parsed, the high and low level calculated values ​​are obtained; the high and low level calculated values ​​are compared with the high and low level pulse width values ​​of the ideal symbol, and the ideal symbol closest to the symbol to be parsed is obtained based on the comparison result; the symbol value of the symbol to be parsed is obtained based on the ideal symbol closest to the symbol to be parsed.

2. The low-frequency time code anti-interference decoding method according to claim 1, characterized in that, In the symbol capture module, the steps for parsing the start time of captured symbols from the TTL signal stream include: A complete symbol without interference pulses is searched in the TTL signal stream, and the end time of the searched symbol is taken as the start time of parsing the symbol to be parsed.

3. The low-frequency time code anti-interference decoding method according to claim 1, characterized in that, After obtaining the symbol parsing result, the symbol parsing module further includes the following steps: After a symbol is successfully parsed, the start time of parsing the next symbol to be parsed is the end time of the current symbol being successfully parsed. If code parsing fails, the parsing start time of the next code to be parsed is the parsing start time obtained by the code capture module.

4. The low-frequency time code anti-interference decoding method according to claim 1, characterized in that, In the timecode parsing module, the steps of parsing a frame of data based on the parsing results of each symbol in a frame, and outputting timecode information and a decoding success indicator include: Step 1: Continuously detect the start marker of a data frame. After detecting the start marker of a data frame, proceed to step 2. Step 2: Store symbol values ​​sequentially according to the symbol start identifier, and determine whether a frame of data has been received completely; if a frame of data is successfully received, verify the received frame data. Regardless of whether the verification passes or fails, jump to step 1 to start the time code parsing of the next cycle; if the verification passes, generate a frame data decoding success identifier and the corresponding time code information; if the verification fails, do not generate a frame data decoding success identifier and time code information. The start identifier of a data frame, the start identifier of a symbol, and the corresponding code value are all provided by the symbol parsing module, and all identifiers are valid on the rising edge.

5. The low-frequency time code anti-interference decoding method according to claim 1, characterized in that, The decoding process of the FPGA includes: After the TTL signal stream enters the FPGA, it is split into two paths. One path enters the symbol capture module. When the symbol capture module successfully captures a complete symbol without interference pulses in the TTL signal stream, it generates a symbol capture identifier F1 pulse signal. The other path enters the symbol parsing module. The symbol parsing module parses the symbol value of each symbol based on the F1 pulse signal and the TTL signal stream, generating a frame data start identifier F2 pulse signal and a symbol start identifier F3 pulse signal. The time code parsing module generates a frame data decoding success identifier F4 pulse signal and time code information based on the F2 pulse signal, F3 pulse signal and symbol value. The time code information includes year, month, day, hour, minute, second and day of the week.

6. A low-frequency time code anti-interference decoding system, characterized in that, include: The signal stream acquisition module is used to acquire low-frequency time-code radio signals, demodulate and shape them using amplitude-modulated waves, and output a TTL signal stream. The decoding module is used to input the TTL signal stream into the FPGA for decoding and obtain the decoding result; The FPGA includes: The symbol capture module is used to input a TTL signal stream and parse the start time of the captured symbol parsing from the TTL signal stream; The symbol parsing module is used to input the TTL signal stream and, based on the TTL signal stream and the start time of symbol parsing, compares the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed to obtain the symbol parsing result. The time code parsing module is used to complete the parsing of a frame of data based on the parsing results of each symbol in a frame, and output the time code information and decoding success identifier; In the symbol parsing module, the steps of comparing the ideal symbol waveforms of different pre-stored symbol values ​​with the symbol to be parsed based on the TTL signal stream and the symbol parsing start time to obtain the symbol parsing result include: starting from the parsing start time of the symbol to be parsed, performing XOR accumulation calculations on the ideal symbol waveforms of different pre-stored symbol values ​​in the FPGA with the symbol to be parsed; wherein, for each ideal symbol, after the calculation between the ideal symbol and the symbol to be parsed, the high and low level calculated values ​​are obtained; the high and low level calculated values ​​are compared with the high and low level pulse width values ​​of the ideal symbol, and the ideal symbol closest to the symbol to be parsed is obtained based on the comparison result; the symbol value of the symbol to be parsed is obtained based on the ideal symbol closest to the symbol to be parsed.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the low-frequency time code anti-interference decoding method as described in any one of claims 1 to 5.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the low-frequency time code anti-interference decoding method as described in any one of claims 1 to 5.

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