A highly integrated semiconductor chip safety detection system and method

Abstract

The present invention provides a highly integrated semiconductor chip security detection system and method, the system includes a physical security test module, a functional safety test module, a side channel attack test module, a software security analysis module, a security authentication module and a visualization module, by evaluating the physical security of the chip, judging the physical security of the chip based on electromagnetic analysis of sensitive areas, verifying the functional security of the chip, detecting existing vulnerabilities and backdoors, inferring sensitive information inside the device, including keys and data, based on the physical characteristics generated by the chip during operation, evaluating the software related to the chip including detecting existing vulnerabilities, backdoors and malicious codes, performing security authentication and key management on users; outputting an analysis report based on the overall security evaluation of the chip, and the user consulting and analyzing it through a visualization panel, the present invention can effectively reduce the possibility of chip security threats and attacks, and ensure the reliability and credibility of chip operation.

Description

Technical Field

[0001] The invention belongs to the electronic field, and specifically refers to a highly integrated semiconductor chip safety detection system and method. Background Art

[0002] With the development of the economy, the application scope of electronic chips is becoming wider and wider, and it is becoming more and more important. Therefore, the requirements for security are also getting higher and higher. In order to ensure the security of the data inside the chip, the general practice is to check the correctness of the data through various error correction algorithms to ensure the security of the data. This traditional practice is based on the verification of chip data when the chip is not physically damaged. However, when the chip is used in a product, the product often needs to be moved and transported, etc. At this time, it is possible that the chip is physically damaged due to collisions and other reasons. This physical damage may cause various unpredictable errors and failures of the chip. Such unpredictable errors and failures sometimes cannot be confirmed by algorithm verification whether there is a problem with the chip. If such physically damaged chips are used in some relatively dangerous equipment, it will bring unpredictable risks. Summary of the invention

[0003] In order to achieve the above object, the present invention adopts the following technical solution:

[0004] A highly integrated semiconductor chip security detection system, characterized in that it includes: a physical safety test module, a functional safety test module, a side channel attack test module, a software security analysis module, a security authentication module and a visualization module, wherein the output end of the physical safety test module is electrically connected to the input end of the functional safety test module, the output end of the functional safety test module is electrically connected to the input end of the side channel attack test module, the first output end of the side channel attack test module is electrically connected to the input end of the software security analysis module, the side channel attack test module, the second output end of the side channel attack test module is electrically connected to the visualization module, and the output end of the security authentication module is electrically connected to the input end of the visualization module;

[0005] The physical security test module evaluates the physical security of the chip, including the packaging and pin layout of the chip, and determines the physical security of the chip based on electromagnetic analysis of sensitive areas;

[0006] The functional safety test module verifies the functional safety of the chip, including verifying the matching degree between the functions of the chip under normal working conditions and the design requirements, and detecting existing vulnerabilities and backdoors;

[0007] The side channel attack test module infers sensitive information inside the device, including keys and data, based on the physical characteristics generated by the chip during operation, including power consumption, electromagnetic radiation, and timing;

[0008] The software security analysis module detects loopholes, backdoors and malicious codes in software programs running on the chip;

[0009] The security authentication module performs security authentication and key management on the user;

[0010] The visualization module outputs an analysis report based on the overall chip security assessment, and the user can view and analyze it through the visualization panel.

[0011] Furthermore, the physical security test module includes the following submodules:

[0012] Packaging analysis submodule: includes analysis of packaging materials, packaging processes and packaging structures to determine its resistance to physical attacks, with a chip area to package area ratio of 1:1;

[0013] Pin security assessment submodule: assess the chip pin attack situation, including assessing the complexity and physical security of the pin wiring. The method of assessing the complexity of the pin wiring includes the change of the pin shape from long lead straight insertion to short lead or leadless mounting, and then to the ball bump, and assessing the ability to prevent pin attacks; the method of assessing the physical security of the pin wiring includes pin stripping and pin detection. The pad should be located directly below the chip pin and aligned with the pin center. The pad position deviation should be controlled within 0.1mm;

[0014] Physical attack defense assessment submodule: Determine the attack type and the physical attack type against the chip security system, including destruction, tampering, and theft, which involves physical destruction of hardware devices, tampering of firmware or storage media, and theft of sensitive information; according to the physical attack type, establish the chip security protection mechanism and storage media security system, and verify whether the firmware signature and integrity verification mechanism have been tampered with;

[0015] Hardware safety detector test submodule: Evaluate the performance and effectiveness of the hardware safety detectors in the chip, including temperature sensors and voltage monitors, and test and verify the functionality, accuracy and robustness of the hardware safety detectors

[0016] The functional test includes verifying that the voltage monitor can monitor the power supply voltage in real time and trigger corresponding actions when the voltage is lower or higher than the set threshold.

[0017] The accuracy test includes setting different voltage values ​​using a programmable power supply, comparing the difference between the voltage value output by the voltage monitor and the set value, and calculating the error range.

[0018] The robustness test includes simulating power supply voltage fluctuations, noise, interference, etc., to observe whether the voltage monitor can correctly identify and respond to these abnormal conditions;

[0019] Physical isolation evaluation submodule: Evaluates the physical isolation effect between sensitive areas and non-sensitive areas inside the chip, including analysis of the isolation structure, isolation materials and isolation process, as well as testing the destruction or bypass of physical isolation.

[0020] Furthermore, the functional safety test module includes the following submodules:

[0021] Voltage detection submodule: detects the voltage value changes of key circuits or ports inside the chip, obtains the voltage output signal through the voltage detection unit, and generates corresponding status flag signals according to the voltage changes;

[0022] Disassembly detection submodule: This is achieved through the metal windings on the wafer. When the metal windings are cut or short-circuited, a specific detection circuit is used to detect this change, notify the chip core, and verify whether the disassembly detection submodule can accurately detect the disassembly behavior. When disassembly is detected, a corresponding safety response is triggered.

[0023] High and low temperature detection submodule: monitors the temperature of the chip based on the temperature sensor and the adjustable temperature detection circuit, outputs corresponding signals based on the temperature changes, verifies whether the high and low temperature detection submodule can accurately detect temperature changes, and triggers corresponding protection measures when the temperature is abnormal;

[0024] Probe detection submodule: determines whether an external probe is connected by monitoring the changes in electrical signals on the chip pins, verifies whether the probe detection submodule can accurately detect the connection of an external probe, and triggers a corresponding safety response when a probe is detected;

[0025] Signal processing and conversion submodule: Process and convert the input signal according to specific circuits and algorithms to meet the needs of different safety detection modules and verify whether the signal processing and conversion submodule can accurately process and convert the signal.

[0026] Furthermore, the side channel attack test module includes the following submodules:

[0027] The waveform information acquisition submodule is used to acquire waveform information of the component under test when performing encryption operations, wherein the waveform information includes energy waveform information, electromagnetic waveform information, and time waveform information, and the waveform information is captured according to a measuring device, wherein the component under test includes the chip; the measuring device includes a rate analyzer, an electromagnetic radiation measuring instrument, and a time measuring device;

[0028] Feature extraction submodule: pre-processing the waveform information obtained by the waveform information acquisition submodule to extract features related to the side channel attack, and extracting features related to the key secret information through autocorrelation processing;

[0029] Correlation analysis submodule: calculates the correlation between the extracted features and the key secret information of the component to be tested based on a preset correlation analysis mathematical model, determines whether the features in the waveform information are associated with the key secret information, and determines whether there is a side channel attack; the correlation analysis mathematical model includes a first-order CPA analysis mathematical model;

[0030] Detection result output submodule: Based on the result output by the correlation analysis submodule, determine whether the component to be tested has a side channel attack, output the corresponding detection result, and display the analysis result to the user through the visualization module.

[0031] Furthermore, the software security analysis module includes the following submodules:

[0032] Source code audit submodule: reviews the chip source code to identify potential security vulnerabilities and incorrect coding practices, using analysis tools including static code analysis tools and manual code review;

[0033] Binary analysis submodule: When source code is unavailable, the compiled binary code is analyzed to detect security threats.

[0034] Fuzz testing submodule: input a large amount of random or pseudo-random data into the software, trigger anomalies or crashes, and monitor the software's response

[0035] Penetration testing submodule: simulates real attack scenarios, conducts tentative attacks on the software, and evaluates its security in the actual environment. The attacks include exploiting known security vulnerabilities, vulnerability exploit codes, or custom attack strategies;

[0036] Dependency analysis submodule: Analyze the security of libraries, frameworks, and components that the software depends on, using dependency scanning tools to query;

[0037] Encryption and hash algorithm analysis submodule: Checks whether the encryption and hash algorithms used in the software are weakened or bypassed, and analyzes the algorithm selection, key management, encryption and decryption processes;

[0038] Log and monitoring analysis submodule: evaluates the log recording and monitoring of the software, and warns the user through the visualization module when a security incident occurs.

[0039] Furthermore, the security authentication module includes an identity verification submodule and a key management submodule. The identity verification submodule verifies the identity of the user accessing the chip resources based on a password and a biometric authentication mechanism. The verification mechanism includes using a digital certificate or a public key infrastructure (PKI) to verify the identity of the device connected to the chip; the key management submodule stores the key in a storage medium, distributes the key to the entity that needs to use it through a secure communication channel, and revokes and updates the key when the key is leaked or expires.

[0040] Furthermore, the visualization module provides users with the ability to view the number, type and severity of security vulnerabilities found on the chip in the form of charts through a visualization panel, monitors abnormal behavior during chip operation in real time, and informs users on the visualization panel through pop-up windows that the abnormal behavior includes memory leaks and performance degradation; monitors chip performance indicators in real time, and records important events in the chip security detection process for users to view in the form of a timeline.

[0041] The present invention also includes a highly integrated semiconductor chip security detection method, comprising the following steps:

[0042] S1: Evaluate the physical security of the chip, including the packaging and pin layout of the chip, and determine the physical security of the chip based on electromagnetic analysis of sensitive areas;

[0043] S2: Verify the functional safety of the chip, including verifying the matching degree between the chip's functions under normal working conditions and the design requirements, and detecting existing vulnerabilities and backdoors;

[0044] S3: Infer sensitive information inside the device, including keys and data, based on the physical characteristics generated by the chip during operation, including power consumption, electromagnetic radiation, and timing;

[0045] S4: Evaluate the chip-related software including detecting existing vulnerabilities, backdoors and malicious codes;

[0046] S5: Perform security authentication and key management for users;

[0047] S6: Output analysis report based on the overall security assessment of the chip, and users can review and analyze it through the visualization panel.

[0048] A computer storage medium, characterized in that the computer program implements the highly integrated semiconductor chip security detection method of claim 8 when being processed and executed.

[0049] Beneficial effects:

[0050] A highly integrated semiconductor chip security detection system and method provided by the present invention can help discover security holes, backdoors or other potential risks in the chip, thereby helping to reduce the possibility of security threats and attacks and ensure reliability and credibility; the security detection system can ensure the reliability and credibility of the chip and prevent the chip from being damaged, tampered with or manipulated during production, transportation or deployment, thereby ensuring the stability and security of the system. Through the visualization module, the security awareness of chip designers, manufacturers and users is improved, prompting them to pay more attention to security issues and take corresponding measures to prevent and protect them. Early detection and resolution of chip security issues can reduce losses and costs caused by security holes or attacks. Compared with later repairs, the cost of preventing and guarding against security issues is lower and the negative impact caused by security incidents can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 This is a structural diagram of a highly integrated semiconductor chip safety detection system in the first embodiment of the present invention;

[0052] Figure 2 This is a diagram of a physical security test module of a highly integrated semiconductor chip security detection system in the first embodiment of the present invention;

[0053] Figure 3 This is a flow chart of a highly integrated semiconductor chip security detection method in the second embodiment of the present invention. DETAILED DESCRIPTION

[0054] Embodiment 1:

[0055] refer to Figure 1 and Figure 2 , a highly integrated semiconductor chip security detection system, characterized in that it includes: a physical safety test module 1, a functional safety test module 2, a side channel attack test module 3, a software security analysis module 4, a security authentication module 5 and a visualization module 6, the output end of the physical safety test module 1 is electrically connected to the input end of the functional safety test module 2, the output end of the functional safety test module 2 is electrically connected to the input end of the side channel attack test module 3, the first output end of the side channel attack test module 3 is electrically connected to the input end of the software security analysis module 4, the second output end of the side channel attack test module 3 is electrically connected to the visualization module 6, and the output end of the security authentication module 5 is electrically connected to the input end of the visualization module 6;

[0056] The physical security test module 1 evaluates the physical security of the chip, including the packaging and pin layout of the chip, and determines the physical security of the chip based on electromagnetic analysis of sensitive areas;

[0057] The functional safety test module 2 verifies the functional safety of the chip, including verifying the matching degree between the functions of the chip under normal working conditions and the design requirements, and detecting existing vulnerabilities and backdoors;

[0058] The side channel attack test module 3 infers sensitive information inside the device, including keys and data, based on the physical characteristics generated by the chip during operation, including power consumption, electromagnetic radiation, and timing;

[0059] The software security analysis module 4 detects loopholes, backdoors and malicious codes in the software programs running on the chip;

[0060] The security authentication module 5 performs security authentication and key management on the user;

[0061] The visualization module 6 outputs an analysis report based on the overall chip security assessment, and the user can view and analyze it through the visualization panel.

[0062] Furthermore, the physical security test 1 module includes the following submodules:

[0063] Packaging analysis submodule: includes analysis of packaging materials, packaging processes and packaging structures to determine its resistance to physical attacks, with a chip area to package area ratio of 1:1;

[0064] Pin security assessment submodule: assess the chip pin attack situation, including assessing the complexity and physical security of the pin wiring. The method of assessing the complexity of the pin wiring includes the change of the pin shape from long lead straight insertion to short lead or leadless mounting, and then to the ball bump, and assessing the ability to prevent pin attacks; the method of assessing the physical security of the pin wiring includes pin stripping and pin detection. The pad should be located directly below the chip pin and aligned with the pin center. The pad position deviation should be controlled within 0.1mm;

[0065] Physical attack defense assessment submodule: Determine the attack type and the physical attack type against the chip security system, including destruction, tampering, and theft, which involves physical destruction of hardware devices, tampering of firmware or storage media, and theft of sensitive information; according to the physical attack type, establish the chip security protection mechanism and storage media security system, and verify whether the firmware signature and integrity verification mechanism have been tampered with;

[0066] Hardware safety detector test submodule: evaluates the performance and effectiveness of the hardware safety detectors present in the chip, including temperature sensors and voltage monitors, and performs tests and verifications based on the functionality, accuracy and robustness of the hardware safety detectors.

[0067] The functional test includes verifying that the voltage monitor can monitor the power supply voltage in real time and trigger corresponding actions when the voltage is lower or higher than the set threshold.

[0068] The accuracy test includes setting different voltage values ​​using a programmable power supply, comparing the difference between the voltage value output by the voltage monitor and the set value, and calculating the error range.

[0069] The robustness test includes simulating power supply voltage fluctuations, noise, interference, etc., to observe whether the voltage monitor can correctly identify and respond to these abnormal conditions;

[0070] Physical isolation evaluation submodule: Evaluates the physical isolation effect between sensitive areas and non-sensitive areas inside the chip, including analysis of the isolation structure, isolation materials and isolation process, as well as testing the destruction or bypass of physical isolation.

[0071] Furthermore, the functional safety test module 2 includes the following submodules:

[0072] Voltage detection submodule: detects the voltage value changes of key circuits or ports inside the chip, obtains the voltage output signal through the voltage detection unit, and generates corresponding status flag signals according to the voltage changes;

[0073] Disassembly detection submodule: This is achieved through the metal windings on the wafer. When the metal windings are cut or short-circuited, a specific detection circuit is used to detect this change, notify the chip core, and verify whether the disassembly detection submodule can accurately detect the disassembly behavior. When disassembly is detected, a corresponding safety response is triggered.

[0074] High and low temperature detection submodule: monitors the temperature of the chip based on the temperature sensor and the adjustable temperature detection circuit, outputs corresponding signals based on the temperature changes, verifies whether the high and low temperature detection submodule can accurately detect temperature changes, and triggers corresponding protection measures when the temperature is abnormal;

[0075] Probe detection submodule: determines whether an external probe is connected by monitoring the changes in electrical signals on the chip pins, verifies whether the probe detection submodule can accurately detect the connection of an external probe, and triggers a corresponding safety response when a probe is detected;

[0076] Signal processing and conversion submodule: Process and convert the input signal according to specific circuits and algorithms to meet the needs of different safety detection modules and verify whether the signal processing and conversion submodule can accurately process and convert the signal.

[0077] Furthermore, the side channel attack test module 3 includes the following submodules:

[0078] The waveform information acquisition submodule is used to acquire waveform information of the component under test when performing encryption operations, wherein the waveform information includes energy waveform information, electromagnetic waveform information, and time waveform information, and the waveform information is captured according to a measuring device, wherein the component under test includes the chip; the measuring device includes a rate analyzer, an electromagnetic radiation measuring instrument, and a time measuring device;

[0079] Feature extraction submodule: pre-processing the waveform information obtained by the waveform information acquisition submodule to extract features related to the side channel attack, and extracting features related to the key secret information through autocorrelation processing;

[0080] Correlation analysis submodule: calculates the correlation between the extracted features and the key secret information of the component to be tested based on a preset correlation analysis mathematical model, determines whether the features in the waveform information are associated with the key secret information, and determines whether there is a side channel attack; the correlation analysis mathematical model includes a first-order CPA analysis mathematical model;

[0081] Detection result output submodule: Based on the result output by the correlation analysis submodule, determine whether the component to be tested has a side channel attack, and output the corresponding detection result and display the analysis result to the user through the visualization module 6.

[0082] Furthermore, the software security analysis module 4 includes the following submodules:

[0083] Source code audit submodule: reviews the chip source code to identify potential security vulnerabilities and incorrect coding practices, using analysis tools including static code analysis tools and manual code review;

[0084] Binary analysis submodule: When source code is unavailable, the compiled binary code is analyzed to detect security threats.

[0085] Fuzz testing submodule: input a large amount of random or pseudo-random data into the software, trigger anomalies or crashes, and monitor the software's response

[0086] Penetration testing submodule: simulates real attack scenarios, conducts tentative attacks on the software, and evaluates its security in the actual environment. The attacks include exploiting known security vulnerabilities, vulnerability exploit codes, or custom attack strategies;

[0087] Dependency analysis submodule: Analyze the security of libraries, frameworks, and components that the software depends on, using dependency scanning tools to query;

[0088] Encryption and hash algorithm analysis submodule: Checks whether the encryption and hash algorithms used in the software are weakened or bypassed, and analyzes the algorithm selection, key management, encryption and decryption processes;

[0089] Log and monitoring analysis submodule: evaluates the log recording and monitoring of the software, and warns the user through the visualization module 6 when a security incident occurs.

[0090] Furthermore, the security authentication module 5 includes an identity verification submodule and a key management submodule. The identity verification submodule verifies the identity of the user accessing the chip resources based on a password and a biometric authentication mechanism. The verification mechanism includes using a digital certificate or a public key infrastructure (PKI) to verify the identity of the device connected to the chip; the key management submodule stores the key in a storage medium, distributes the key to the entity that needs to use it through a secure communication channel, and revokes and updates the key when the key is leaked or expires.

[0091] Furthermore, the visualization module 6 provides users with the ability to view the number, type and severity of security vulnerabilities found on the chip in the form of charts through a visualization panel, monitors abnormal behaviors during chip operation in real time, and informs users on the visualization panel through pop-up windows, wherein the abnormal behaviors include memory leaks and performance degradation; it monitors chip performance indicators in real time, and records important events in the chip security detection process for users to view in the form of a timeline.

[0092] Embodiment 2

[0093] refer to Figure 3 The present invention also includes a highly integrated semiconductor chip security detection method, comprising the following steps:

[0094] S1: Evaluate the physical security of the chip, including the packaging and pin layout of the chip, and determine the physical security of the chip based on electromagnetic analysis of sensitive areas;

[0095] S2: Verify the functional safety of the chip, including verifying the matching degree between the chip's functions under normal working conditions and the design requirements, and detecting existing vulnerabilities and backdoors;

[0096] S3: Infer sensitive information inside the device, including keys and data, based on the physical characteristics generated by the chip during operation, including power consumption, electromagnetic radiation, and timing;

[0097] S4: Evaluate the chip-related software including detecting existing vulnerabilities, backdoors and malicious codes;

[0098] S5: Perform security authentication and key management for users;

[0099] S6: Output analysis report based on the overall security assessment of the chip, and users can review and analyze it through the visualization panel.

[0100] A computer storage medium, characterized in that the computer program implements the highly integrated semiconductor chip security detection method of claim 8 when being processed and executed.

[0101] The present invention and its embodiments are described above, which is not restrictive. What is shown in the accompanying drawings is only one of the embodiments of the present invention, and the actual content is not limited to this. In short, if ordinary technicians in this field are inspired by it and do not deviate from the purpose of the invention, they can creatively design structural methods and embodiments similar to the technical scheme, which should all fall within the scope of protection of the present invention.

Claims

1. A highly integrated semiconductor chip security detection system, characterized in that: include: A physical safety test module (1), a functional safety test module (2), a side channel attack test module (3), a software safety analysis module (4), a security authentication module (5) and a visualization module (6), wherein an output end of the physical safety test module (1) is electrically connected to an input end of the functional safety test module (2), an output end of the functional safety test module (2) is electrically connected to an input end of the side channel attack test module (3), a first output end of the side channel attack test module (3) is electrically connected to an input end of the software safety analysis module (4), a second output end of the side channel attack test module (3) is electrically connected to the visualization module (6), and an output end of the security authentication module (5) is electrically connected to an input end of the visualization module (6); The physical security test module (1) evaluates the physical security of the chip, including the packaging and pin layout of the chip, and determines the physical security of the chip based on electromagnetic analysis of sensitive areas; The functional safety test module (2) verifies the functional safety of the chip, including verifying the matching degree between the functions of the chip under normal working conditions and the design requirements, and detecting existing vulnerabilities and backdoors; The side channel attack test module (3) infers sensitive information inside the device, including keys and data, based on the physical characteristics of the chip generated during operation, including power consumption, electromagnetic radiation, and timing; The software security analysis module (4) detects loopholes, backdoors and malicious codes in the software programs running on the chip; The security authentication module (5) performs security authentication and key management on the user; The visualization module (6) outputs an analysis report based on the overall chip security assessment, and the user can view and analyze it through the visualization panel; The physical security test module (1) comprises a packaging analysis submodule (11), a pin security assessment submodule (12), a physical attack defense assessment submodule (13), a hardware security detector test submodule (14) and a physical isolation assessment submodule (15); Packaging analysis submodule (11): includes analysis of packaging materials, packaging processes and packaging structures to determine its resistance to physical attacks, with a chip area to package area ratio of 1:1; Pin security assessment submodule (12): assesses chip pin attack situations, including assessing the complexity and physical security of pin wiring. The assessment of the complexity of pin wiring includes changes in pin shape from long lead direct insertion to short lead or leadless mounting, and then to ball bumps, and assesses the ability to prevent pin attacks. The assessment of the physical security of pin wiring includes pin stripping and pin detection. The pad should be located directly below the chip pin and aligned with the pin center. The pad position deviation should be controlled within 0.1 mm. Physical attack defense assessment submodule (13): Determine the attack type and the physical attack type against the chip security system, including destruction, tampering, and theft, which involves physical destruction of hardware devices, tampering of firmware or storage media, and theft of sensitive information. According to the physical attack type, establish the chip security protection mechanism and storage media security system, and verify whether the firmware signature and integrity verification mechanism have been tampered with; Hardware safety detector test submodule (14): evaluates the performance and effectiveness of the hardware safety detectors present in the chip, including temperature sensors and voltage monitors, and performs tests and verifications based on the functionality, accuracy and robustness of the hardware safety detectors; Functional testing includes verifying that the voltage monitor can monitor the power supply voltage in real time and trigger corresponding actions when the voltage is below or above the set threshold; The accuracy test includes setting different voltage values ​​using a programmable power supply, comparing the difference between the voltage value output by the voltage monitor and the set value, and calculating the error range; Robustness testing involves simulating supply voltage fluctuations, noise, and interference to see if the voltage monitor can correctly identify and respond to these abnormal conditions; Physical isolation assessment submodule (15): Assess the physical isolation effect between sensitive areas and non-sensitive areas inside the chip, including analysis of the isolation structure, isolation materials and isolation process, as well as testing the destruction or bypass of physical isolation.

2. A highly integrated semiconductor chip security detection system according to claim 1, characterized in that: The functional safety test module (2) comprises the following submodules: Voltage detection submodule (21): detects voltage value changes of key circuits or ports inside the chip, obtains voltage output signals through voltage detection units, and generates corresponding status flag signals according to voltage changes; Disassembly detection submodule (22): This is achieved by detecting the metal windings on the wafer. When the metal windings are cut or short-circuited, the change is detected based on a specific detection circuit, and the chip core is notified of the security event. This verifies whether the disassembly detection submodule can accurately detect the disassembly behavior, and triggers a corresponding security response when disassembly is detected. High and low temperature detection submodule (23): monitors the temperature of the chip based on the temperature sensor and the adjustable temperature detection circuit, outputs a corresponding signal based on the temperature change, verifies whether the high and low temperature detection submodule can accurately detect the temperature change, and triggers corresponding protection measures when the temperature is abnormal; Probe detection submodule (24): determines whether an external probe is connected by monitoring the change of the electrical signal on the chip pin, verifies whether the probe detection submodule can accurately detect the connection of the external probe, and triggers a corresponding safety response when the probe is detected; Signal processing and conversion submodule (25): processes and converts the input signal according to specific circuits and algorithms to meet the requirements of different safety detection modules and verify whether the signal processing and conversion submodule can accurately process and convert the signal.

3. The highly integrated semiconductor chip security detection system according to claim 1, characterized in that: The side channel attack test module (3) includes the following submodules: A waveform information acquisition submodule (31): acquiring waveform information of the component under test when performing an encryption operation, wherein the waveform information includes energy waveform information, electromagnetic waveform information, and time waveform information, and the waveform information is captured according to a measuring device, wherein the component under test includes the chip; the measuring device includes a rate analyzer, an electromagnetic radiation measuring instrument, and a time measuring device; Feature extraction submodule (32): pre-processing the waveform information obtained by the waveform information acquisition submodule (31) to extract features related to the side channel attack, thereby extracting features related to the key secret information through autocorrelation processing; Correlation analysis submodule (33): based on a preset correlation analysis mathematical model, the correlation between the extracted features and the key secret information of the component to be tested is calculated to determine whether the features in the waveform information are associated with the key secret information, and whether there is a side channel attack; the correlation analysis mathematical model includes a first-order CPA analysis mathematical model; Detection result output submodule: Based on the result output by the correlation analysis submodule (33), it is determined whether the component to be tested has a side channel attack, and the corresponding detection result is output and the analysis result is displayed to the user through the visualization module (6).

4. The highly integrated semiconductor chip safety detection system according to claim 1, characterized in that: The software safety analysis module (4) includes the following submodules: Source code audit submodule (41): reviews the chip source code to identify potential security vulnerabilities and incorrect coding practices, using analysis tools including static code analysis tools and manual code review; Binary analysis submodule (42): when the source code is unavailable, the compiled binary code is analyzed to detect the security threats. Fuzz testing submodule (43): inputs a large amount of random or pseudo-random data into the software, triggers anomalies or crashes, and monitors the response of the software; Penetration testing submodule (44): simulating real attack scenarios, conducting trial attacks on the software, and evaluating its security in the actual environment. The attacks include exploiting known security vulnerabilities, vulnerability exploit codes, or custom attack strategies; Dependency analysis submodule (45): Analyzes the security of libraries, frameworks, and components that the software depends on, using dependency scanning tools to query; Encryption and hash algorithm analysis submodule (46): Checks whether the encryption and hash algorithms used in the software are weakened or bypassed, and analyzes the algorithm selection, key management, encryption and decryption processes; Log and monitoring analysis submodule (47): evaluates the logging and monitoring mechanism of the software and warns the user through the visualization module when a security incident occurs.

5. The highly integrated semiconductor chip security detection system according to claim 1, characterized in that: The security authentication module (5) comprises an identity authentication submodule (51) and a key management submodule (52), wherein the identity authentication submodule (51) verifies the identity of a user accessing chip resources based on a password and a biometric authentication mechanism, wherein the authentication mechanism comprises using a digital certificate or a public key infrastructure to verify the identity of a device connected to the chip; and the key management submodule (52) stores keys in a storage medium, distributes the keys to entities that need to use the keys through a secure communication channel, and revokes and updates the keys when the keys are leaked or expired.

6. The highly integrated semiconductor chip security detection system according to claim 1, characterized in that: The visualization module (6) provides users with the number, type and severity of security vulnerabilities found on the chip in the form of charts through a visualization panel, monitors abnormal behavior during chip operation in real time, and informs users in the form of pop-up windows on the visualization panel, wherein the abnormal behavior includes memory leakage and performance degradation; monitors chip performance indicators in real time, and records important events in the chip security detection process for users to view in the form of a timeline.

7. A highly integrated semiconductor chip security detection method, used to implement a highly integrated semiconductor chip security detection system as claimed in any one of claims 1 to 6, characterized in that: The following steps are involved: S1: Evaluate the physical security of the chip, including the packaging and pin layout of the chip, and determine the physical security of the chip based on electromagnetic analysis of sensitive areas; S2: Verify the functional safety of the chip, including verifying the matching degree between the chip's functions under normal working conditions and the design requirements, and detecting existing vulnerabilities and backdoors; S3: Infer sensitive information inside the device, including keys and data, based on the physical characteristics generated by the chip during operation, including power consumption, electromagnetic radiation, and timing; S4: Evaluate chip-related software including detecting existing vulnerabilities, backdoors, and malicious code; S5: Perform security authentication and key management for users; S6: Output analysis report based on the overall security assessment of the chip, and users can review and analyze it through the visualization panel.

8. A computer storage medium, characterized in that: The computer program implements the highly integrated semiconductor chip security detection method of claim 7 when being processed and executed.

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